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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63 static void r700SetRenderTarget(context_t *context, int id);
64 static void r700SetDepthTarget(context_t *context);
65
66 void r700SetDefaultStates(context_t *context) //--------------------
67 {
68
69 }
70
71 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
72 {
73 context_t *context = R700_CONTEXT(ctx);
74
75 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
76 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
77 int i;
78
79 if (ctx->FragmentProgram._Current) {
80 struct r700_fragment_program *fp = (struct r700_fragment_program *)
81 (ctx->FragmentProgram._Current);
82 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
83 {
84 fp->r700AsmCode.bR6xx = 1;
85 }
86
87 if(GL_FALSE == fp->translated)
88 {
89 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
90 {
91 //return GL_TRUE;
92 }
93 }
94 }
95
96 if (context->radeon.NewGLState)
97 {
98 struct r700_vertex_program *vp;
99 context->radeon.NewGLState = 0;
100
101 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
102 {
103 /* mat states from state var not array for sw */
104 dummy_attrib[i].stride = 0;
105
106 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
107 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
108 }
109
110 _tnl_UpdateFixedFunctionProgram(ctx);
111
112 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
113 {
114 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
115 }
116
117 r700SelectVertexShader(ctx);
118 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
119
120 if (vp->translated == GL_FALSE)
121 {
122 // TODO
123 //fprintf(stderr, "Failing back to sw-tcl\n");
124 //hw_tcl_on = future_hw_tcl_on = 0;
125 //r300ResetHwState(rmesa);
126 //
127 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
128 return;
129 }
130 }
131
132 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
133 }
134
135 /*
136 * To correctly position primitives:
137 */
138 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
139 {
140 context_t *context = R700_CONTEXT(ctx);
141 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
142 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
143 GLfloat xoffset = (GLfloat) dPriv->x;
144 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
145 const GLfloat *v = ctx->Viewport._WindowMap.m;
146 int id = 0;
147
148 GLfloat tx = v[MAT_TX] + xoffset;
149 GLfloat ty = (-v[MAT_TY]) + yoffset;
150
151 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
152 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
153
154 radeonUpdateScissor(ctx);
155 }
156
157 /**
158 * Tell the card where to render (offset, pitch).
159 * Effected by glDrawBuffer, etc
160 */
161 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
162 {
163 context_t *context = R700_CONTEXT(ctx);
164
165 r700SetRenderTarget(context, 0);
166 r700SetDepthTarget(context);
167 }
168
169 static void r700FetchStateParameter(GLcontext * ctx,
170 const gl_state_index state[STATE_LENGTH],
171 GLfloat * value)
172 {
173 /* TODO */
174 }
175
176 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
177 {
178 struct r700_fragment_program *fp;
179 struct gl_program_parameter_list *paramList;
180 GLuint i;
181
182 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
183 return;
184
185 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
186 if (!fp)
187 {
188 return;
189 }
190
191 paramList = fp->mesa_program.Base.Parameters;
192
193 if (!paramList)
194 {
195 return;
196 }
197
198 for (i = 0; i < paramList->NumParameters; i++)
199 {
200 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
201 {
202 r700FetchStateParameter(ctx,
203 paramList->Parameters[i].
204 StateIndexes,
205 paramList->ParameterValues[i]);
206 }
207 }
208 }
209
210 /**
211 * Called by Mesa after an internal state update.
212 */
213 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
214 {
215 context_t *context = R700_CONTEXT(ctx);
216
217 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
218
219 _swrast_InvalidateState(ctx, new_state);
220 _swsetup_InvalidateState(ctx, new_state);
221 _vbo_InvalidateState(ctx, new_state);
222 _tnl_InvalidateState(ctx, new_state);
223 _ae_invalidate_state(ctx, new_state);
224
225 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
226 {
227 _mesa_update_framebuffer(ctx);
228 /* this updates the DrawBuffer's Width/Height if it's a FBO */
229 _mesa_update_draw_buffer_bounds(ctx);
230
231 r700UpdateDrawBuffer(ctx);
232 }
233
234 r700UpdateStateParameters(ctx, new_state);
235
236 if(GL_TRUE == r700->bEnablePerspective)
237 {
238 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
239 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
240 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
241
242 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
243
244 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
245 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
246 }
247 else
248 {
249 /* For orthogonal case. */
250 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
251 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
252
253 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
254
255 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
256 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
257 }
258
259 context->radeon.NewGLState |= new_state;
260 }
261
262 static void r700SetDepthState(GLcontext * ctx)
263 {
264 context_t *context = R700_CONTEXT(ctx);
265
266 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
267
268 if (ctx->Depth.Test)
269 {
270 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
271 if (ctx->Depth.Mask)
272 {
273 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
274 }
275 else
276 {
277 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
278 }
279
280 switch (ctx->Depth.Func)
281 {
282 case GL_NEVER:
283 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
284 ZFUNC_shift, ZFUNC_mask);
285 break;
286 case GL_LESS:
287 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
288 ZFUNC_shift, ZFUNC_mask);
289 break;
290 case GL_EQUAL:
291 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
292 ZFUNC_shift, ZFUNC_mask);
293 break;
294 case GL_LEQUAL:
295 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
296 ZFUNC_shift, ZFUNC_mask);
297 break;
298 case GL_GREATER:
299 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
300 ZFUNC_shift, ZFUNC_mask);
301 break;
302 case GL_NOTEQUAL:
303 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
304 ZFUNC_shift, ZFUNC_mask);
305 break;
306 case GL_GEQUAL:
307 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
308 ZFUNC_shift, ZFUNC_mask);
309 break;
310 case GL_ALWAYS:
311 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
312 ZFUNC_shift, ZFUNC_mask);
313 break;
314 default:
315 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
316 ZFUNC_shift, ZFUNC_mask);
317 break;
318 }
319 }
320 else
321 {
322 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
323 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
324 }
325 }
326
327 static void r700SetAlphaState(GLcontext * ctx)
328 {
329 context_t *context = R700_CONTEXT(ctx);
330 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
331 uint32_t alpha_func = REF_ALWAYS;
332 GLboolean really_enabled = ctx->Color.AlphaEnabled;
333
334 switch (ctx->Color.AlphaFunc) {
335 case GL_NEVER:
336 alpha_func = REF_NEVER;
337 break;
338 case GL_LESS:
339 alpha_func = REF_LESS;
340 break;
341 case GL_EQUAL:
342 alpha_func = REF_EQUAL;
343 break;
344 case GL_LEQUAL:
345 alpha_func = REF_LEQUAL;
346 break;
347 case GL_GREATER:
348 alpha_func = REF_GREATER;
349 break;
350 case GL_NOTEQUAL:
351 alpha_func = REF_NOTEQUAL;
352 break;
353 case GL_GEQUAL:
354 alpha_func = REF_GEQUAL;
355 break;
356 case GL_ALWAYS:
357 /*alpha_func = REF_ALWAYS; */
358 really_enabled = GL_FALSE;
359 break;
360 }
361
362 if (really_enabled) {
363 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
364 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
365 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
366 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
367 } else {
368 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
369 }
370
371 }
372
373 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
374 {
375 (void)func;
376 (void)ref;
377 r700SetAlphaState(ctx);
378 }
379
380
381 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
382 {
383 context_t *context = R700_CONTEXT(ctx);
384 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
385
386 r700->CB_BLEND_RED.f32All = cf[0];
387 r700->CB_BLEND_GREEN.f32All = cf[1];
388 r700->CB_BLEND_BLUE.f32All = cf[2];
389 r700->CB_BLEND_ALPHA.f32All = cf[3];
390 }
391
392 static int blend_factor(GLenum factor, GLboolean is_src)
393 {
394 switch (factor) {
395 case GL_ZERO:
396 return BLEND_ZERO;
397 break;
398 case GL_ONE:
399 return BLEND_ONE;
400 break;
401 case GL_DST_COLOR:
402 return BLEND_DST_COLOR;
403 break;
404 case GL_ONE_MINUS_DST_COLOR:
405 return BLEND_ONE_MINUS_DST_COLOR;
406 break;
407 case GL_SRC_COLOR:
408 return BLEND_SRC_COLOR;
409 break;
410 case GL_ONE_MINUS_SRC_COLOR:
411 return BLEND_ONE_MINUS_SRC_COLOR;
412 break;
413 case GL_SRC_ALPHA:
414 return BLEND_SRC_ALPHA;
415 break;
416 case GL_ONE_MINUS_SRC_ALPHA:
417 return BLEND_ONE_MINUS_SRC_ALPHA;
418 break;
419 case GL_DST_ALPHA:
420 return BLEND_DST_ALPHA;
421 break;
422 case GL_ONE_MINUS_DST_ALPHA:
423 return BLEND_ONE_MINUS_DST_ALPHA;
424 break;
425 case GL_SRC_ALPHA_SATURATE:
426 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
427 break;
428 case GL_CONSTANT_COLOR:
429 return BLEND_CONSTANT_COLOR;
430 break;
431 case GL_ONE_MINUS_CONSTANT_COLOR:
432 return BLEND_ONE_MINUS_CONSTANT_COLOR;
433 break;
434 case GL_CONSTANT_ALPHA:
435 return BLEND_CONSTANT_ALPHA;
436 break;
437 case GL_ONE_MINUS_CONSTANT_ALPHA:
438 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
439 break;
440 default:
441 fprintf(stderr, "unknown blend factor %x\n", factor);
442 return (is_src) ? BLEND_ONE : BLEND_ZERO;
443 break;
444 }
445 }
446
447 static void r700SetBlendState(GLcontext * ctx)
448 {
449 context_t *context = R700_CONTEXT(ctx);
450 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
451 int id = 0;
452 uint32_t blend_reg = 0, eqn, eqnA;
453
454 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
455 SETfield(blend_reg,
456 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
457 SETfield(blend_reg,
458 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
459 SETfield(blend_reg,
460 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
461 SETfield(blend_reg,
462 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
463 SETfield(blend_reg,
464 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
465 SETfield(blend_reg,
466 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
467 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
468 r700->CB_BLEND_CONTROL.u32All = blend_reg;
469 else
470 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
471 return;
472 }
473
474 SETfield(blend_reg,
475 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
476 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
479 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480
481 switch (ctx->Color.BlendEquationRGB) {
482 case GL_FUNC_ADD:
483 eqn = COMB_DST_PLUS_SRC;
484 break;
485 case GL_FUNC_SUBTRACT:
486 eqn = COMB_SRC_MINUS_DST;
487 break;
488 case GL_FUNC_REVERSE_SUBTRACT:
489 eqn = COMB_DST_MINUS_SRC;
490 break;
491 case GL_MIN:
492 eqn = COMB_MIN_DST_SRC;
493 SETfield(blend_reg,
494 BLEND_ONE,
495 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
496 SETfield(blend_reg,
497 BLEND_ONE,
498 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
499 break;
500 case GL_MAX:
501 eqn = COMB_MAX_DST_SRC;
502 SETfield(blend_reg,
503 BLEND_ONE,
504 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
505 SETfield(blend_reg,
506 BLEND_ONE,
507 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
508 break;
509
510 default:
511 fprintf(stderr,
512 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
513 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
514 return;
515 }
516 SETfield(blend_reg,
517 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
518
519 SETfield(blend_reg,
520 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
521 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
522 SETfield(blend_reg,
523 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
524 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
525
526 switch (ctx->Color.BlendEquationA) {
527 case GL_FUNC_ADD:
528 eqnA = COMB_DST_PLUS_SRC;
529 break;
530 case GL_FUNC_SUBTRACT:
531 eqnA = COMB_SRC_MINUS_DST;
532 break;
533 case GL_FUNC_REVERSE_SUBTRACT:
534 eqnA = COMB_DST_MINUS_SRC;
535 break;
536 case GL_MIN:
537 eqnA = COMB_MIN_DST_SRC;
538 SETfield(blend_reg,
539 BLEND_ONE,
540 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
541 SETfield(blend_reg,
542 BLEND_ONE,
543 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
544 break;
545 case GL_MAX:
546 eqnA = COMB_MAX_DST_SRC;
547 SETfield(blend_reg,
548 BLEND_ONE,
549 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
550 SETfield(blend_reg,
551 BLEND_ONE,
552 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
553 break;
554 default:
555 fprintf(stderr,
556 "[%s:%u] Invalid A blend equation (0x%04x).\n",
557 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
558 return;
559 }
560
561 SETfield(blend_reg,
562 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
563
564 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
565
566 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
567 r700->CB_BLEND_CONTROL.u32All = blend_reg;
568 else {
569 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
570 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
571 }
572 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
573 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
574
575 }
576
577 static void r700BlendEquationSeparate(GLcontext * ctx,
578 GLenum modeRGB, GLenum modeA) //-----------------
579 {
580 r700SetBlendState(ctx);
581 }
582
583 static void r700BlendFuncSeparate(GLcontext * ctx,
584 GLenum sfactorRGB, GLenum dfactorRGB,
585 GLenum sfactorA, GLenum dfactorA) //------------------------
586 {
587 r700SetBlendState(ctx);
588 }
589
590 /**
591 * Translate LogicOp enums into hardware representation.
592 */
593 static GLuint translate_logicop(GLenum logicop)
594 {
595 switch (logicop) {
596 case GL_CLEAR:
597 return 0x00;
598 case GL_SET:
599 return 0xff;
600 case GL_COPY:
601 return 0xcc;
602 case GL_COPY_INVERTED:
603 return 0x33;
604 case GL_NOOP:
605 return 0xaa;
606 case GL_INVERT:
607 return 0x55;
608 case GL_AND:
609 return 0x88;
610 case GL_NAND:
611 return 0x77;
612 case GL_OR:
613 return 0xee;
614 case GL_NOR:
615 return 0x11;
616 case GL_XOR:
617 return 0x66;
618 case GL_EQUIV:
619 return 0xaa;
620 case GL_AND_REVERSE:
621 return 0x44;
622 case GL_AND_INVERTED:
623 return 0x22;
624 case GL_OR_REVERSE:
625 return 0xdd;
626 case GL_OR_INVERTED:
627 return 0xbb;
628 default:
629 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
630 return 0xcc;
631 }
632 }
633
634 /**
635 * Used internally to update the r300->hw hardware state to match the
636 * current OpenGL state.
637 */
638 static void r700SetLogicOpState(GLcontext *ctx)
639 {
640 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
641
642 if (RGBA_LOGICOP_ENABLED(ctx))
643 SETfield(r700->CB_COLOR_CONTROL.u32All,
644 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
645 else
646 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
647 }
648
649 /**
650 * Called by Mesa when an application program changes the LogicOp state
651 * via glLogicOp.
652 */
653 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
654 {
655 if (RGBA_LOGICOP_ENABLED(ctx))
656 r700SetLogicOpState(ctx);
657 }
658
659 static void r700UpdateCulling(GLcontext * ctx)
660 {
661 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
662
663 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
664 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
665 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
666
667 if (ctx->Polygon.CullFlag)
668 {
669 switch (ctx->Polygon.CullFaceMode)
670 {
671 case GL_FRONT:
672 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
673 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
674 break;
675 case GL_BACK:
676 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
677 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
678 break;
679 case GL_FRONT_AND_BACK:
680 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
681 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
682 break;
683 default:
684 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
685 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
686 break;
687 }
688 }
689
690 switch (ctx->Polygon.FrontFace)
691 {
692 case GL_CW:
693 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
694 break;
695 case GL_CCW:
696 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
697 break;
698 default:
699 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
700 break;
701 }
702 }
703
704 static void r700UpdateLineStipple(GLcontext * ctx)
705 {
706 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
707 if (ctx->Line.StippleFlag)
708 {
709 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
710 }
711 else
712 {
713 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
714 }
715 }
716
717 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
718 {
719 context_t *context = R700_CONTEXT(ctx);
720
721 switch (cap) {
722 case GL_TEXTURE_1D:
723 case GL_TEXTURE_2D:
724 case GL_TEXTURE_3D:
725 /* empty */
726 break;
727 case GL_FOG:
728 /* empty */
729 break;
730 case GL_ALPHA_TEST:
731 r700SetAlphaState(ctx);
732 break;
733 case GL_COLOR_LOGIC_OP:
734 r700SetLogicOpState(ctx);
735 /* fall-through, because logic op overrides blending */
736 case GL_BLEND:
737 r700SetBlendState(ctx);
738 break;
739 case GL_CLIP_PLANE0:
740 case GL_CLIP_PLANE1:
741 case GL_CLIP_PLANE2:
742 case GL_CLIP_PLANE3:
743 case GL_CLIP_PLANE4:
744 case GL_CLIP_PLANE5:
745 r700SetClipPlaneState(ctx, cap, state);
746 break;
747 case GL_DEPTH_TEST:
748 r700SetDepthState(ctx);
749 break;
750 case GL_STENCIL_TEST:
751 r700SetStencilState(ctx, state);
752 break;
753 case GL_CULL_FACE:
754 r700UpdateCulling(ctx);
755 break;
756 case GL_POLYGON_OFFSET_POINT:
757 case GL_POLYGON_OFFSET_LINE:
758 case GL_POLYGON_OFFSET_FILL:
759 r700SetPolygonOffsetState(ctx, state);
760 break;
761 case GL_SCISSOR_TEST:
762 radeon_firevertices(&context->radeon);
763 context->radeon.state.scissor.enabled = state;
764 radeonUpdateScissor(ctx);
765 break;
766 case GL_LINE_STIPPLE:
767 r700UpdateLineStipple(ctx);
768 break;
769 default:
770 break;
771 }
772
773 }
774
775 /**
776 * Handle glColorMask()
777 */
778 static void r700ColorMask(GLcontext * ctx,
779 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
780 {
781 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
782 unsigned int mask = ((r ? 1 : 0) |
783 (g ? 2 : 0) |
784 (b ? 4 : 0) |
785 (a ? 8 : 0));
786
787 if (mask != r700->CB_SHADER_MASK.u32All)
788 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
789 }
790
791 /**
792 * Change the depth testing function.
793 *
794 * \note Mesa already filters redundant calls to this function.
795 */
796 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
797 {
798 r700SetDepthState(ctx);
799 }
800
801 /**
802 * Enable/Disable depth writing.
803 *
804 * \note Mesa already filters redundant calls to this function.
805 */
806 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
807 {
808 r700SetDepthState(ctx);
809 }
810
811 /**
812 * Change the culling mode.
813 *
814 * \note Mesa already filters redundant calls to this function.
815 */
816 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
817 {
818 r700UpdateCulling(ctx);
819 }
820
821 /* =============================================================
822 * Fog
823 */
824 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
825 {
826 }
827
828 /**
829 * Change the polygon orientation.
830 *
831 * \note Mesa already filters redundant calls to this function.
832 */
833 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
834 {
835 r700UpdateCulling(ctx);
836 r700UpdatePolygonMode(ctx);
837 }
838
839 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
840 {
841 context_t *context = R700_CONTEXT(ctx);
842 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
843
844 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
845 switch (mode) {
846 case GL_FLAT:
847 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
848 break;
849 case GL_SMOOTH:
850 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
851 break;
852 default:
853 return;
854 }
855 }
856
857 /* =============================================================
858 * Point state
859 */
860 static void r700PointSize(GLcontext * ctx, GLfloat size)
861 {
862 context_t *context = R700_CONTEXT(ctx);
863 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
864
865 /* We need to clamp to user defined range here, because
866 * the HW clamping happens only for per vertex point size. */
867 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
868
869 /* same size limits for AA, non-AA points */
870 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
871
872 /* format is 12.4 fixed point */
873 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
874 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
875 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
876 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
877
878 }
879
880 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
881 {
882 context_t *context = R700_CONTEXT(ctx);
883 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
884
885 /* format is 12.4 fixed point */
886 switch (pname) {
887 case GL_POINT_SIZE_MIN:
888 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
889 MIN_SIZE_shift, MIN_SIZE_mask);
890 break;
891 case GL_POINT_SIZE_MAX:
892 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
893 MAX_SIZE_shift, MAX_SIZE_mask);
894 break;
895 case GL_POINT_DISTANCE_ATTENUATION:
896 break;
897 case GL_POINT_FADE_THRESHOLD_SIZE:
898 break;
899 default:
900 break;
901 }
902 }
903
904 static int translate_stencil_func(int func)
905 {
906 switch (func) {
907 case GL_NEVER:
908 return REF_NEVER;
909 case GL_LESS:
910 return REF_LESS;
911 case GL_EQUAL:
912 return REF_EQUAL;
913 case GL_LEQUAL:
914 return REF_LEQUAL;
915 case GL_GREATER:
916 return REF_GREATER;
917 case GL_NOTEQUAL:
918 return REF_NOTEQUAL;
919 case GL_GEQUAL:
920 return REF_GEQUAL;
921 case GL_ALWAYS:
922 return REF_ALWAYS;
923 }
924 return 0;
925 }
926
927 static int translate_stencil_op(int op)
928 {
929 switch (op) {
930 case GL_KEEP:
931 return STENCIL_KEEP;
932 case GL_ZERO:
933 return STENCIL_ZERO;
934 case GL_REPLACE:
935 return STENCIL_REPLACE;
936 case GL_INCR:
937 return STENCIL_INCR_CLAMP;
938 case GL_DECR:
939 return STENCIL_DECR_CLAMP;
940 case GL_INCR_WRAP_EXT:
941 return STENCIL_INCR_WRAP;
942 case GL_DECR_WRAP_EXT:
943 return STENCIL_DECR_WRAP;
944 case GL_INVERT:
945 return STENCIL_INVERT;
946 default:
947 WARN_ONCE("Do not know how to translate stencil op");
948 return STENCIL_KEEP;
949 }
950 return 0;
951 }
952
953 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
954 {
955 context_t *context = R700_CONTEXT(ctx);
956 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
957 GLboolean hw_stencil = GL_FALSE;
958
959 //fixme
960 //r300CatchStencilFallback(ctx);
961
962 if (ctx->DrawBuffer) {
963 struct radeon_renderbuffer *rrbStencil
964 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
965 hw_stencil = (rrbStencil && rrbStencil->bo);
966 }
967
968 if (hw_stencil) {
969 if (state)
970 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
971 else
972 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
973 }
974 }
975
976 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
977 GLenum func, GLint ref, GLuint mask) //---------------------
978 {
979 context_t *context = R700_CONTEXT(ctx);
980 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
981 const unsigned back = ctx->Stencil._BackFace;
982
983 //fixme
984 //r300CatchStencilFallback(ctx);
985
986 //front
987 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
988 STENCILREF_shift, STENCILREF_mask);
989 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
990 STENCILMASK_shift, STENCILMASK_mask);
991
992 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
993 STENCILFUNC_shift, STENCILFUNC_mask);
994
995 //back
996 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
997 STENCILREF_BF_shift, STENCILREF_BF_mask);
998 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
999 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1000
1001 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1002 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1003
1004 }
1005
1006 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1007 {
1008 context_t *context = R700_CONTEXT(ctx);
1009 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1010 const unsigned back = ctx->Stencil._BackFace;
1011
1012 //fixme
1013 //r300CatchStencilFallback(ctx);
1014
1015 // front
1016 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1017 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1018
1019 // back
1020 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1021 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1022
1023 }
1024
1025 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1026 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1027 {
1028 context_t *context = R700_CONTEXT(ctx);
1029 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1030 const unsigned back = ctx->Stencil._BackFace;
1031
1032 //fixme
1033 //r300CatchStencilFallback(ctx);
1034
1035 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1036 STENCILFAIL_shift, STENCILFAIL_mask);
1037 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1038 STENCILZFAIL_shift, STENCILZFAIL_mask);
1039 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1040 STENCILZPASS_shift, STENCILZPASS_mask);
1041
1042 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1043 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1044 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1045 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1046 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1047 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1048 }
1049
1050 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1051 {
1052 context_t *context = R700_CONTEXT(ctx);
1053 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1054 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1055 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1056 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1057 const GLfloat *v = ctx->Viewport._WindowMap.m;
1058 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1059 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1060 GLfloat y_scale, y_bias;
1061
1062 if (render_to_fbo) {
1063 y_scale = 1.0;
1064 y_bias = 0;
1065 } else {
1066 y_scale = -1.0;
1067 y_bias = yoffset;
1068 }
1069
1070 GLfloat sx = v[MAT_SX];
1071 GLfloat tx = v[MAT_TX] + xoffset;
1072 GLfloat sy = v[MAT_SY] * y_scale;
1073 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1074 GLfloat sz = v[MAT_SZ] * depthScale;
1075 GLfloat tz = v[MAT_TZ] * depthScale;
1076
1077 /* TODO : Need DMA flush as well. */
1078
1079 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1080 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1081
1082 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1083 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1084
1085 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1086 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1087
1088 r700->viewport[id].enabled = GL_TRUE;
1089
1090 r700SetScissor(context);
1091 }
1092
1093
1094 static void r700Viewport(GLcontext * ctx,
1095 GLint x,
1096 GLint y,
1097 GLsizei width,
1098 GLsizei height) //--------------------
1099 {
1100 r700UpdateWindow(ctx, 0);
1101
1102 radeon_viewport(ctx, x, y, width, height);
1103 }
1104
1105 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1106 {
1107 r700UpdateWindow(ctx, 0);
1108 }
1109
1110 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1111 {
1112 context_t *context = R700_CONTEXT(ctx);
1113 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1114 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1115 if (lineWidth > 0xFFFF)
1116 lineWidth = 0xFFFF;
1117 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1118 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1119 }
1120
1121 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1122 {
1123 context_t *context = R700_CONTEXT(ctx);
1124 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1125
1126 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1127 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1128 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1129 }
1130
1131 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1132 {
1133 context_t *context = R700_CONTEXT(ctx);
1134 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1135
1136 if (state) {
1137 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1138 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1139 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1140 } else {
1141 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1142 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1143 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1144 }
1145 }
1146
1147 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1148 {
1149 context_t *context = R700_CONTEXT(ctx);
1150 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1151 GLfloat constant = units;
1152
1153 switch (ctx->Visual.depthBits) {
1154 case 16:
1155 constant *= 4.0;
1156 break;
1157 case 24:
1158 constant *= 2.0;
1159 break;
1160 }
1161
1162 factor *= 12.0;
1163
1164 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1165 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1166 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1167 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1168 }
1169
1170 static void r700UpdatePolygonMode(GLcontext * ctx)
1171 {
1172 context_t *context = R700_CONTEXT(ctx);
1173 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1174
1175 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1176
1177 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1178 if (ctx->Polygon.FrontMode != GL_FILL ||
1179 ctx->Polygon.BackMode != GL_FILL) {
1180 GLenum f, b;
1181
1182 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1183 * correctly by selecting the correct front and back face
1184 */
1185 if (ctx->Polygon.FrontFace == GL_CCW) {
1186 f = ctx->Polygon.FrontMode;
1187 b = ctx->Polygon.BackMode;
1188 } else {
1189 f = ctx->Polygon.BackMode;
1190 b = ctx->Polygon.FrontMode;
1191 }
1192
1193 /* Enable polygon mode */
1194 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1195
1196 switch (f) {
1197 case GL_LINE:
1198 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1199 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1200 break;
1201 case GL_POINT:
1202 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1203 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1204 break;
1205 case GL_FILL:
1206 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1207 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1208 break;
1209 }
1210
1211 switch (b) {
1212 case GL_LINE:
1213 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1214 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1215 break;
1216 case GL_POINT:
1217 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1218 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1219 break;
1220 case GL_FILL:
1221 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1222 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1223 break;
1224 }
1225 }
1226 }
1227
1228 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1229 {
1230 (void)face;
1231 (void)mode;
1232
1233 r700UpdatePolygonMode(ctx);
1234 }
1235
1236 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1237 {
1238 }
1239
1240 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1241 {
1242 context_t *context = R700_CONTEXT(ctx);
1243 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1244 GLint p;
1245 GLint *ip;
1246
1247 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1248 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1249
1250 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1251 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1252 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1253 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1254 }
1255
1256 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1257 {
1258 context_t *context = R700_CONTEXT(ctx);
1259 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1260 GLuint p;
1261
1262 p = cap - GL_CLIP_PLANE0;
1263 if (state) {
1264 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1265 r700->ucp[p].enabled = GL_TRUE;
1266 r700ClipPlane(ctx, cap, NULL);
1267 } else {
1268 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1269 r700->ucp[p].enabled = GL_FALSE;
1270 }
1271 }
1272
1273 void r700SetScissor(context_t *context) //---------------
1274 {
1275 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1276 unsigned x1, y1, x2, y2;
1277 int id = 0;
1278 struct radeon_renderbuffer *rrb;
1279
1280 rrb = radeon_get_colorbuffer(&context->radeon);
1281 if (!rrb || !rrb->bo) {
1282 return;
1283 }
1284 if (context->radeon.state.scissor.enabled) {
1285 x1 = context->radeon.state.scissor.rect.x1;
1286 y1 = context->radeon.state.scissor.rect.y1;
1287 x2 = context->radeon.state.scissor.rect.x2 - 1;
1288 y2 = context->radeon.state.scissor.rect.y2 - 1;
1289 } else {
1290 x1 = rrb->dPriv->x;
1291 y1 = rrb->dPriv->y;
1292 x2 = rrb->dPriv->x + rrb->dPriv->w;
1293 y2 = rrb->dPriv->y + rrb->dPriv->h;
1294 }
1295
1296 /* window */
1297 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1298 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1299 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1300 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1301 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1302
1303 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1304 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1305 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1306 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1307
1308
1309 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1310 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1311 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1312 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1313 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1314 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1315 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1316 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1317
1318 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1319 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1320 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1321 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1322 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1323 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1324
1325 /* more....2d clip */
1326 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1327 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1328 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1329 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1330 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1331 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1332 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1333 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1334 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1335
1336 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1337 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1338 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1339 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1340 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1341 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1342 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1343 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1344 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1345
1346 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1347 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1348 r700->viewport[id].enabled = GL_TRUE;
1349 }
1350
1351 static void r700SetRenderTarget(context_t *context, int id)
1352 {
1353 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1354
1355 struct radeon_renderbuffer *rrb;
1356 unsigned int nPitchInPixel;
1357
1358 rrb = radeon_get_colorbuffer(&context->radeon);
1359 if (!rrb || !rrb->bo) {
1360 fprintf(stderr, "no rrb\n");
1361 return;
1362 }
1363
1364 /* screen/window/view */
1365 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1366
1367 /* color buffer */
1368 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1369
1370 nPitchInPixel = rrb->pitch/rrb->cpp;
1371 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1372 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1373 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1374 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1375 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1376 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1377 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1378 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1379 if(4 == rrb->cpp)
1380 {
1381 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1382 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1383 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1384 }
1385 else
1386 {
1387 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1388 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1389 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1390 COMP_SWAP_shift, COMP_SWAP_mask);
1391 }
1392 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1393 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1394 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1395
1396 r700->render_target[id].enabled = GL_TRUE;
1397 }
1398
1399 static void r700SetDepthTarget(context_t *context)
1400 {
1401 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1402
1403 struct radeon_renderbuffer *rrb;
1404 unsigned int nPitchInPixel;
1405
1406 rrb = radeon_get_depthbuffer(&context->radeon);
1407 if (!rrb)
1408 return;
1409
1410 /* depth buf */
1411 r700->DB_DEPTH_SIZE.u32All = 0;
1412 r700->DB_DEPTH_BASE.u32All = 0;
1413 r700->DB_DEPTH_INFO.u32All = 0;
1414 r700->DB_DEPTH_VIEW.u32All = 0;
1415
1416 nPitchInPixel = rrb->pitch/rrb->cpp;
1417
1418 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1419 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1420 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1421 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1422
1423 if(4 == rrb->cpp)
1424 {
1425 switch (GL_CONTEXT(context)->Visual.depthBits)
1426 {
1427 case 16:
1428 case 24:
1429 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1430 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1431 break;
1432 default:
1433 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1434 GL_CONTEXT(context)->Visual.depthBits);
1435 _mesa_exit(-1);
1436 }
1437 }
1438 else
1439 {
1440 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1441 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1442 }
1443 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1444 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1445 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1446 }
1447
1448 static void r700InitSQConfig(GLcontext * ctx)
1449 {
1450 context_t *context = R700_CONTEXT(ctx);
1451 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1452 int ps_prio;
1453 int vs_prio;
1454 int gs_prio;
1455 int es_prio;
1456 int num_ps_gprs;
1457 int num_vs_gprs;
1458 int num_gs_gprs;
1459 int num_es_gprs;
1460 int num_temp_gprs;
1461 int num_ps_threads;
1462 int num_vs_threads;
1463 int num_gs_threads;
1464 int num_es_threads;
1465 int num_ps_stack_entries;
1466 int num_vs_stack_entries;
1467 int num_gs_stack_entries;
1468 int num_es_stack_entries;
1469
1470 // SQ
1471 ps_prio = 0;
1472 vs_prio = 1;
1473 gs_prio = 2;
1474 es_prio = 3;
1475 switch (context->radeon.radeonScreen->chip_family) {
1476 case CHIP_FAMILY_R600:
1477 num_ps_gprs = 192;
1478 num_vs_gprs = 56;
1479 num_temp_gprs = 4;
1480 num_gs_gprs = 0;
1481 num_es_gprs = 0;
1482 num_ps_threads = 136;
1483 num_vs_threads = 48;
1484 num_gs_threads = 4;
1485 num_es_threads = 4;
1486 num_ps_stack_entries = 128;
1487 num_vs_stack_entries = 128;
1488 num_gs_stack_entries = 0;
1489 num_es_stack_entries = 0;
1490 break;
1491 case CHIP_FAMILY_RV630:
1492 case CHIP_FAMILY_RV635:
1493 num_ps_gprs = 84;
1494 num_vs_gprs = 36;
1495 num_temp_gprs = 4;
1496 num_gs_gprs = 0;
1497 num_es_gprs = 0;
1498 num_ps_threads = 144;
1499 num_vs_threads = 40;
1500 num_gs_threads = 4;
1501 num_es_threads = 4;
1502 num_ps_stack_entries = 40;
1503 num_vs_stack_entries = 40;
1504 num_gs_stack_entries = 32;
1505 num_es_stack_entries = 16;
1506 break;
1507 case CHIP_FAMILY_RV610:
1508 case CHIP_FAMILY_RV620:
1509 case CHIP_FAMILY_RS780:
1510 default:
1511 num_ps_gprs = 84;
1512 num_vs_gprs = 36;
1513 num_temp_gprs = 4;
1514 num_gs_gprs = 0;
1515 num_es_gprs = 0;
1516 num_ps_threads = 136;
1517 num_vs_threads = 48;
1518 num_gs_threads = 4;
1519 num_es_threads = 4;
1520 num_ps_stack_entries = 40;
1521 num_vs_stack_entries = 40;
1522 num_gs_stack_entries = 32;
1523 num_es_stack_entries = 16;
1524 break;
1525 case CHIP_FAMILY_RV670:
1526 num_ps_gprs = 144;
1527 num_vs_gprs = 40;
1528 num_temp_gprs = 4;
1529 num_gs_gprs = 0;
1530 num_es_gprs = 0;
1531 num_ps_threads = 136;
1532 num_vs_threads = 48;
1533 num_gs_threads = 4;
1534 num_es_threads = 4;
1535 num_ps_stack_entries = 40;
1536 num_vs_stack_entries = 40;
1537 num_gs_stack_entries = 32;
1538 num_es_stack_entries = 16;
1539 break;
1540 case CHIP_FAMILY_RV770:
1541 num_ps_gprs = 192;
1542 num_vs_gprs = 56;
1543 num_temp_gprs = 4;
1544 num_gs_gprs = 0;
1545 num_es_gprs = 0;
1546 num_ps_threads = 188;
1547 num_vs_threads = 60;
1548 num_gs_threads = 0;
1549 num_es_threads = 0;
1550 num_ps_stack_entries = 256;
1551 num_vs_stack_entries = 256;
1552 num_gs_stack_entries = 0;
1553 num_es_stack_entries = 0;
1554 break;
1555 case CHIP_FAMILY_RV730:
1556 case CHIP_FAMILY_RV740:
1557 num_ps_gprs = 84;
1558 num_vs_gprs = 36;
1559 num_temp_gprs = 4;
1560 num_gs_gprs = 0;
1561 num_es_gprs = 0;
1562 num_ps_threads = 188;
1563 num_vs_threads = 60;
1564 num_gs_threads = 0;
1565 num_es_threads = 0;
1566 num_ps_stack_entries = 128;
1567 num_vs_stack_entries = 128;
1568 num_gs_stack_entries = 0;
1569 num_es_stack_entries = 0;
1570 break;
1571 case CHIP_FAMILY_RV710:
1572 num_ps_gprs = 192;
1573 num_vs_gprs = 56;
1574 num_temp_gprs = 4;
1575 num_gs_gprs = 0;
1576 num_es_gprs = 0;
1577 num_ps_threads = 144;
1578 num_vs_threads = 48;
1579 num_gs_threads = 0;
1580 num_es_threads = 0;
1581 num_ps_stack_entries = 128;
1582 num_vs_stack_entries = 128;
1583 num_gs_stack_entries = 0;
1584 num_es_stack_entries = 0;
1585 break;
1586 }
1587
1588 r700->sq_config.SQ_CONFIG.u32All = 0;
1589 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1590 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1591 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1592 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1593 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1594 else
1595 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1596 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1597 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1598 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1599 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1600 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1601 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1602
1603 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1604 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1605 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1606 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1607 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1608
1609 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1610 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1611 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1612
1613 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1614 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1615 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1616 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1617 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1618 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1619 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1620 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1621 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1622
1623 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1624 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1625 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1626 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1627 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1628
1629 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1630 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1631 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1632 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1633 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1634
1635 }
1636
1637 /**
1638 * Calculate initial hardware state and register state functions.
1639 * Assumes that the command buffer and state atoms have been
1640 * initialized already.
1641 */
1642 void r700InitState(GLcontext * ctx) //-------------------
1643 {
1644 context_t *context = R700_CONTEXT(ctx);
1645 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1646
1647 radeon_firevertices(&context->radeon);
1648
1649 r700->TA_CNTL_AUX.u32All = 0;
1650 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1651 r700->VC_ENHANCE.u32All = 0;
1652 r700->DB_WATERMARKS.u32All = 0;
1653 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1654 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1655 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1656 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1657 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1658 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1659 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1660 r700->DB_DEBUG.u32All = 0x82000000;
1661 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1662 } else {
1663 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1664 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1665 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1666 }
1667
1668 /* Turn off vgt reuse */
1669 r700->VGT_REUSE_OFF.u32All = 0;
1670 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1671
1672 /* Specify offsetting and clamp values for vertices */
1673 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1674 r700->VGT_MIN_VTX_INDX.u32All = 0;
1675 r700->VGT_INDX_OFFSET.u32All = 0;
1676
1677 /* default shader connections. */
1678 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1679 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1680
1681 r700->SPI_THREAD_GROUPING.u32All = 0;
1682 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1683 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1684
1685 /* screen */
1686 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1687
1688 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1689 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1690 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1691 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1692 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1693 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1694
1695 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1696 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1697 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1698
1699 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1700 r700->PA_SC_EDGERULE.u32All = 0;
1701 else
1702 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1703
1704 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1705 r700->PA_SC_MODE_CNTL.u32All = 0;
1706 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1707 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1708 } else {
1709 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1710 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1711 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1712 }
1713
1714 /* Do scale XY and Z by 1/W0. */
1715 r700->bEnablePerspective = GL_TRUE;
1716 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1717 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1718 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1719
1720 /* Enable viewport scaling for all three axis */
1721 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1722 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1723 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1724 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1725 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1726 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1727
1728 /* GL uses last vtx for flat shading components */
1729 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1730
1731 /* Set up vertex control */
1732 r700->PA_SU_VTX_CNTL.u32All = 0;
1733 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1734 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1735 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1736 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1737
1738 /* to 1.0 = no guard band */
1739 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1740 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1741 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1742 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1743
1744 /* Enable all samples for multi-sample anti-aliasing */
1745 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1746 /* Turn off AA */
1747 r700->PA_SC_AA_CONFIG.u32All = 0;
1748
1749 r700->SX_MISC.u32All = 0;
1750
1751 r700InitSQConfig(ctx);
1752
1753 r700ColorMask(ctx,
1754 ctx->Color.ColorMask[RCOMP],
1755 ctx->Color.ColorMask[GCOMP],
1756 ctx->Color.ColorMask[BCOMP],
1757 ctx->Color.ColorMask[ACOMP]);
1758
1759 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1760 r700DepthMask(ctx, ctx->Depth.Mask);
1761 r700DepthFunc(ctx, ctx->Depth.Func);
1762 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1763
1764 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1765
1766 r700->DB_RENDER_CONTROL.u32All = 0;
1767 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1768 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1769 r700->DB_RENDER_OVERRIDE.u32All = 0;
1770 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1771 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1772 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1773 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1774 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1775
1776 r700->DB_ALPHA_TO_MASK.u32All = 0;
1777 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1778 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1779 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1780 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1781
1782 /* stencil */
1783 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1784 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1785 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1786 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1787 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1788 ctx->Stencil.ZFailFunc[0],
1789 ctx->Stencil.ZPassFunc[0]);
1790
1791 r700UpdateCulling(ctx);
1792
1793 r700SetBlendState(ctx);
1794 r700SetLogicOpState(ctx);
1795
1796 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1797 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1798
1799 r700PointSize(ctx, 1.0);
1800
1801 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1802 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1803
1804 r700LineWidth(ctx, 1.0);
1805
1806 r700->PA_SC_LINE_CNTL.u32All = 0;
1807 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1808 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1809
1810 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1811 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1812 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1813 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1814 ctx->Polygon.OffsetUnits);
1815 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1816 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1817 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1818
1819 /* CB */
1820 r700BlendColor(ctx, ctx->Color.BlendColor);
1821
1822 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1823 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1824 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1825 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1826 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1827 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1828 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1829
1830 /* Disable color compares */
1831 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1832 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1833 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1834 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1835 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1836 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1837
1838 /* Zero out source */
1839 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1840
1841 /* Put a compare color in for error checking */
1842 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1843
1844 /* Set up color compare mask */
1845 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1846
1847 context->radeon.hw.all_dirty = GL_TRUE;
1848
1849 }
1850
1851 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1852 {
1853 functions->UpdateState = r700InvalidateState;
1854 functions->AlphaFunc = r700AlphaFunc;
1855 functions->BlendColor = r700BlendColor;
1856 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1857 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1858 functions->Enable = r700Enable;
1859 functions->ColorMask = r700ColorMask;
1860 functions->DepthFunc = r700DepthFunc;
1861 functions->DepthMask = r700DepthMask;
1862 functions->CullFace = r700CullFace;
1863 functions->Fogfv = r700Fogfv;
1864 functions->FrontFace = r700FrontFace;
1865 functions->ShadeModel = r700ShadeModel;
1866 functions->LogicOpcode = r700LogicOpcode;
1867
1868 /* ARB_point_parameters */
1869 functions->PointParameterfv = r700PointParameter;
1870
1871 /* Stencil related */
1872 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1873 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1874 functions->StencilOpSeparate = r700StencilOpSeparate;
1875
1876 /* Viewport related */
1877 functions->Viewport = r700Viewport;
1878 functions->DepthRange = r700DepthRange;
1879 functions->PointSize = r700PointSize;
1880 functions->LineWidth = r700LineWidth;
1881 functions->LineStipple = r700LineStipple;
1882
1883 functions->PolygonOffset = r700PolygonOffset;
1884 functions->PolygonMode = r700PolygonMode;
1885
1886 functions->RenderMode = r700RenderMode;
1887
1888 functions->ClipPlane = r700ClipPlane;
1889
1890 functions->Scissor = radeonScissor;
1891
1892 functions->DrawBuffer = radeonDrawBuffer;
1893 functions->ReadBuffer = radeonReadBuffer;
1894
1895 }
1896