2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
63 static void r700SetRenderTarget(context_t
*context
, int id
);
64 static void r700SetDepthTarget(context_t
*context
);
66 void r700SetDefaultStates(context_t
*context
) //--------------------
71 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
73 context_t
*context
= R700_CONTEXT(ctx
);
74 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
75 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
78 /* should only happenen once, just after context is created */
79 /* TODO: shouldn't we fallback to sw here? */
80 if (!ctx
->FragmentProgram
._Current
) {
81 _mesa_fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
85 r700SelectFragmentShader(ctx
);
87 if (context
->radeon
.NewGLState
) {
88 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
89 /* mat states from state var not array for sw */
90 dummy_attrib
[i
].stride
= 0;
91 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
92 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
95 _tnl_UpdateFixedFunctionProgram(ctx
);
97 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
98 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
102 r700SelectVertexShader(ctx
);
103 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
104 context
->radeon
.NewGLState
= 0;
108 * To correctly position primitives:
110 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
112 context_t
*context
= R700_CONTEXT(ctx
);
113 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
114 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
115 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
116 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
117 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
120 GLfloat tx
= v
[MAT_TX
] + xoffset
;
121 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
123 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
124 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
125 /* Note: this should also modify whatever data the context reset
128 R600_STATECHANGE(context
, vpt
);
129 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
130 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
133 radeonUpdateScissor(ctx
);
137 * Tell the card where to render (offset, pitch).
138 * Effected by glDrawBuffer, etc
140 void r700UpdateDrawBuffer(GLcontext
* ctx
) /* TODO */ //---------------------
142 context_t
*context
= R700_CONTEXT(ctx
);
144 R600_STATECHANGE(context
, cb_target
);
145 R600_STATECHANGE(context
, db_target
);
147 r700SetRenderTarget(context
, 0);
148 r700SetDepthTarget(context
);
151 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
153 struct r700_fragment_program
*fp
=
154 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
155 struct gl_program_parameter_list
*paramList
;
157 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
160 if (!ctx
->FragmentProgram
._Current
|| !fp
)
163 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
168 _mesa_load_state_parameters(ctx
, paramList
);
173 * Called by Mesa after an internal state update.
175 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
177 context_t
*context
= R700_CONTEXT(ctx
);
179 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
181 _swrast_InvalidateState(ctx
, new_state
);
182 _swsetup_InvalidateState(ctx
, new_state
);
183 _vbo_InvalidateState(ctx
, new_state
);
184 _tnl_InvalidateState(ctx
, new_state
);
185 _ae_invalidate_state(ctx
, new_state
);
187 if (new_state
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
))
189 _mesa_update_framebuffer(ctx
);
190 /* this updates the DrawBuffer's Width/Height if it's a FBO */
191 _mesa_update_draw_buffer_bounds(ctx
);
193 r700UpdateDrawBuffer(ctx
);
196 r700UpdateStateParameters(ctx
, new_state
);
198 R600_STATECHANGE(context
, cl
);
199 R600_STATECHANGE(context
, spi
);
201 if(GL_TRUE
== r700
->bEnablePerspective
)
203 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
204 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
205 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
207 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
209 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
210 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
214 /* For orthogonal case. */
215 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
216 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
218 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
220 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
221 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
224 context
->radeon
.NewGLState
|= new_state
;
227 static void r700SetDepthState(GLcontext
* ctx
)
229 context_t
*context
= R700_CONTEXT(ctx
);
230 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
232 R600_STATECHANGE(context
, db
);
236 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
239 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
243 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
246 switch (ctx
->Depth
.Func
)
249 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
250 ZFUNC_shift
, ZFUNC_mask
);
253 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
254 ZFUNC_shift
, ZFUNC_mask
);
257 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
258 ZFUNC_shift
, ZFUNC_mask
);
261 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
262 ZFUNC_shift
, ZFUNC_mask
);
265 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
266 ZFUNC_shift
, ZFUNC_mask
);
269 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
270 ZFUNC_shift
, ZFUNC_mask
);
273 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
274 ZFUNC_shift
, ZFUNC_mask
);
277 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
278 ZFUNC_shift
, ZFUNC_mask
);
281 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
282 ZFUNC_shift
, ZFUNC_mask
);
288 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
289 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
293 static void r700SetAlphaState(GLcontext
* ctx
)
295 context_t
*context
= R700_CONTEXT(ctx
);
296 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
297 uint32_t alpha_func
= REF_ALWAYS
;
298 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
300 R600_STATECHANGE(context
, sx
);
302 switch (ctx
->Color
.AlphaFunc
) {
304 alpha_func
= REF_NEVER
;
307 alpha_func
= REF_LESS
;
310 alpha_func
= REF_EQUAL
;
313 alpha_func
= REF_LEQUAL
;
316 alpha_func
= REF_GREATER
;
319 alpha_func
= REF_NOTEQUAL
;
322 alpha_func
= REF_GEQUAL
;
325 /*alpha_func = REF_ALWAYS; */
326 really_enabled
= GL_FALSE
;
330 if (really_enabled
) {
331 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
332 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
333 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
334 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
336 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
341 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
345 r700SetAlphaState(ctx
);
349 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
351 context_t
*context
= R700_CONTEXT(ctx
);
352 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
354 R600_STATECHANGE(context
, blnd_clr
);
356 r700
->CB_BLEND_RED
.f32All
= cf
[0];
357 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
358 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
359 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
362 static int blend_factor(GLenum factor
, GLboolean is_src
)
372 return BLEND_DST_COLOR
;
374 case GL_ONE_MINUS_DST_COLOR
:
375 return BLEND_ONE_MINUS_DST_COLOR
;
378 return BLEND_SRC_COLOR
;
380 case GL_ONE_MINUS_SRC_COLOR
:
381 return BLEND_ONE_MINUS_SRC_COLOR
;
384 return BLEND_SRC_ALPHA
;
386 case GL_ONE_MINUS_SRC_ALPHA
:
387 return BLEND_ONE_MINUS_SRC_ALPHA
;
390 return BLEND_DST_ALPHA
;
392 case GL_ONE_MINUS_DST_ALPHA
:
393 return BLEND_ONE_MINUS_DST_ALPHA
;
395 case GL_SRC_ALPHA_SATURATE
:
396 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
398 case GL_CONSTANT_COLOR
:
399 return BLEND_CONSTANT_COLOR
;
401 case GL_ONE_MINUS_CONSTANT_COLOR
:
402 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
404 case GL_CONSTANT_ALPHA
:
405 return BLEND_CONSTANT_ALPHA
;
407 case GL_ONE_MINUS_CONSTANT_ALPHA
:
408 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
411 fprintf(stderr
, "unknown blend factor %x\n", factor
);
412 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
417 static void r700SetBlendState(GLcontext
* ctx
)
419 context_t
*context
= R700_CONTEXT(ctx
);
420 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
422 uint32_t blend_reg
= 0, eqn
, eqnA
;
424 R600_STATECHANGE(context
, blnd
);
426 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
428 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
430 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
432 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
434 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
436 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
438 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
439 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
440 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
442 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
447 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
448 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
450 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
451 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
453 switch (ctx
->Color
.BlendEquationRGB
) {
455 eqn
= COMB_DST_PLUS_SRC
;
457 case GL_FUNC_SUBTRACT
:
458 eqn
= COMB_SRC_MINUS_DST
;
460 case GL_FUNC_REVERSE_SUBTRACT
:
461 eqn
= COMB_DST_MINUS_SRC
;
464 eqn
= COMB_MIN_DST_SRC
;
467 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
470 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
473 eqn
= COMB_MAX_DST_SRC
;
476 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
479 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
484 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
485 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
489 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
492 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
493 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
495 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
496 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
498 switch (ctx
->Color
.BlendEquationA
) {
500 eqnA
= COMB_DST_PLUS_SRC
;
502 case GL_FUNC_SUBTRACT
:
503 eqnA
= COMB_SRC_MINUS_DST
;
505 case GL_FUNC_REVERSE_SUBTRACT
:
506 eqnA
= COMB_DST_MINUS_SRC
;
509 eqnA
= COMB_MIN_DST_SRC
;
512 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
515 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
518 eqnA
= COMB_MAX_DST_SRC
;
521 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
524 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
528 "[%s:%u] Invalid A blend equation (0x%04x).\n",
529 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
534 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
536 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
538 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
539 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
541 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
542 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
544 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
545 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
549 static void r700BlendEquationSeparate(GLcontext
* ctx
,
550 GLenum modeRGB
, GLenum modeA
) //-----------------
552 r700SetBlendState(ctx
);
555 static void r700BlendFuncSeparate(GLcontext
* ctx
,
556 GLenum sfactorRGB
, GLenum dfactorRGB
,
557 GLenum sfactorA
, GLenum dfactorA
) //------------------------
559 r700SetBlendState(ctx
);
563 * Translate LogicOp enums into hardware representation.
565 static GLuint
translate_logicop(GLenum logicop
)
574 case GL_COPY_INVERTED
:
594 case GL_AND_INVERTED
:
601 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
607 * Used internally to update the r300->hw hardware state to match the
608 * current OpenGL state.
610 static void r700SetLogicOpState(GLcontext
*ctx
)
612 context_t
*context
= R700_CONTEXT(ctx
);
613 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
615 R600_STATECHANGE(context
, blnd
);
617 if (RGBA_LOGICOP_ENABLED(ctx
))
618 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
619 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
621 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
625 * Called by Mesa when an application program changes the LogicOp state
628 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
630 if (RGBA_LOGICOP_ENABLED(ctx
))
631 r700SetLogicOpState(ctx
);
634 static void r700UpdateCulling(GLcontext
* ctx
)
636 context_t
*context
= R700_CONTEXT(ctx
);
637 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
639 R600_STATECHANGE(context
, su
);
641 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
642 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
643 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
645 if (ctx
->Polygon
.CullFlag
)
647 switch (ctx
->Polygon
.CullFaceMode
)
650 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
651 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
654 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
655 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
657 case GL_FRONT_AND_BACK
:
658 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
659 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
662 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
663 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
668 switch (ctx
->Polygon
.FrontFace
)
671 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
674 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
677 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
682 static void r700UpdateLineStipple(GLcontext
* ctx
)
684 context_t
*context
= R700_CONTEXT(ctx
);
685 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
687 R600_STATECHANGE(context
, sc
);
689 if (ctx
->Line
.StippleFlag
)
691 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
695 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
699 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
701 context_t
*context
= R700_CONTEXT(ctx
);
713 r700SetAlphaState(ctx
);
715 case GL_COLOR_LOGIC_OP
:
716 r700SetLogicOpState(ctx
);
717 /* fall-through, because logic op overrides blending */
719 r700SetBlendState(ctx
);
727 r700SetClipPlaneState(ctx
, cap
, state
);
730 r700SetDepthState(ctx
);
732 case GL_STENCIL_TEST
:
733 r700SetStencilState(ctx
, state
);
736 r700UpdateCulling(ctx
);
738 case GL_POLYGON_OFFSET_POINT
:
739 case GL_POLYGON_OFFSET_LINE
:
740 case GL_POLYGON_OFFSET_FILL
:
741 r700SetPolygonOffsetState(ctx
, state
);
743 case GL_SCISSOR_TEST
:
744 radeon_firevertices(&context
->radeon
);
745 context
->radeon
.state
.scissor
.enabled
= state
;
746 radeonUpdateScissor(ctx
);
748 case GL_LINE_STIPPLE
:
749 r700UpdateLineStipple(ctx
);
758 * Handle glColorMask()
760 static void r700ColorMask(GLcontext
* ctx
,
761 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
763 context_t
*context
= R700_CONTEXT(ctx
);
764 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
765 unsigned int mask
= ((r
? 1 : 0) |
770 if (mask
!= r700
->CB_SHADER_MASK
.u32All
) {
771 R600_STATECHANGE(context
, cb
);
772 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
777 * Change the depth testing function.
779 * \note Mesa already filters redundant calls to this function.
781 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
783 r700SetDepthState(ctx
);
787 * Enable/Disable depth writing.
789 * \note Mesa already filters redundant calls to this function.
791 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
793 r700SetDepthState(ctx
);
797 * Change the culling mode.
799 * \note Mesa already filters redundant calls to this function.
801 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
803 r700UpdateCulling(ctx
);
806 /* =============================================================
809 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
814 * Change the polygon orientation.
816 * \note Mesa already filters redundant calls to this function.
818 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
820 r700UpdateCulling(ctx
);
821 r700UpdatePolygonMode(ctx
);
824 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
826 context_t
*context
= R700_CONTEXT(ctx
);
827 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
829 R600_STATECHANGE(context
, spi
);
831 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
834 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
837 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
844 /* =============================================================
847 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
849 context_t
*context
= R700_CONTEXT(ctx
);
850 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
852 R600_STATECHANGE(context
, su
);
854 /* We need to clamp to user defined range here, because
855 * the HW clamping happens only for per vertex point size. */
856 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
858 /* same size limits for AA, non-AA points */
859 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
861 /* format is 12.4 fixed point */
862 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
863 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
864 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
865 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
869 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
871 context_t
*context
= R700_CONTEXT(ctx
);
872 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
874 R600_STATECHANGE(context
, su
);
876 /* format is 12.4 fixed point */
878 case GL_POINT_SIZE_MIN
:
879 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 16.0),
880 MIN_SIZE_shift
, MIN_SIZE_mask
);
882 case GL_POINT_SIZE_MAX
:
883 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 16.0),
884 MAX_SIZE_shift
, MAX_SIZE_mask
);
886 case GL_POINT_DISTANCE_ATTENUATION
:
888 case GL_POINT_FADE_THRESHOLD_SIZE
:
895 static int translate_stencil_func(int func
)
918 static int translate_stencil_op(int op
)
926 return STENCIL_REPLACE
;
928 return STENCIL_INCR_CLAMP
;
930 return STENCIL_DECR_CLAMP
;
931 case GL_INCR_WRAP_EXT
:
932 return STENCIL_INCR_WRAP
;
933 case GL_DECR_WRAP_EXT
:
934 return STENCIL_DECR_WRAP
;
936 return STENCIL_INVERT
;
938 WARN_ONCE("Do not know how to translate stencil op");
944 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
946 context_t
*context
= R700_CONTEXT(ctx
);
947 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
948 GLboolean hw_stencil
= GL_FALSE
;
950 if (ctx
->DrawBuffer
) {
951 struct radeon_renderbuffer
*rrbStencil
952 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
953 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
957 R600_STATECHANGE(context
, db
);
959 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
960 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
962 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
966 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
967 GLenum func
, GLint ref
, GLuint mask
) //---------------------
969 context_t
*context
= R700_CONTEXT(ctx
);
970 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
971 const unsigned back
= ctx
->Stencil
._BackFace
;
973 R600_STATECHANGE(context
, stencil
);
974 R600_STATECHANGE(context
, db
);
977 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
978 STENCILREF_shift
, STENCILREF_mask
);
979 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
980 STENCILMASK_shift
, STENCILMASK_mask
);
982 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
983 STENCILFUNC_shift
, STENCILFUNC_mask
);
986 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
987 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
988 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
989 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
991 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
992 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
996 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
998 context_t
*context
= R700_CONTEXT(ctx
);
999 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1000 const unsigned back
= ctx
->Stencil
._BackFace
;
1002 R600_STATECHANGE(context
, stencil
);
1005 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1006 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1009 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1010 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1014 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
1015 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1017 context_t
*context
= R700_CONTEXT(ctx
);
1018 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1019 const unsigned back
= ctx
->Stencil
._BackFace
;
1021 R600_STATECHANGE(context
, db
);
1023 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1024 STENCILFAIL_shift
, STENCILFAIL_mask
);
1025 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1026 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1027 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1028 STENCILZPASS_shift
, STENCILZPASS_mask
);
1030 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1031 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1032 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1033 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1034 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1035 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1038 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1040 context_t
*context
= R700_CONTEXT(ctx
);
1041 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1042 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1043 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1044 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1045 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1046 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1047 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1048 GLfloat y_scale
, y_bias
;
1050 if (render_to_fbo
) {
1058 GLfloat sx
= v
[MAT_SX
];
1059 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1060 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1061 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1062 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1063 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1065 R600_STATECHANGE(context
, vpt
);
1067 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1068 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1070 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1071 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1073 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1074 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1076 r700
->viewport
[id
].enabled
= GL_TRUE
;
1078 r700SetScissor(context
);
1082 static void r700Viewport(GLcontext
* ctx
,
1086 GLsizei height
) //--------------------
1088 r700UpdateWindow(ctx
, 0);
1090 radeon_viewport(ctx
, x
, y
, width
, height
);
1093 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1095 r700UpdateWindow(ctx
, 0);
1098 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1100 context_t
*context
= R700_CONTEXT(ctx
);
1101 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1102 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1104 R600_STATECHANGE(context
, su
);
1106 if (lineWidth
> 0xFFFF)
1108 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1109 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1112 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1114 context_t
*context
= R700_CONTEXT(ctx
);
1115 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1117 R600_STATECHANGE(context
, sc
);
1119 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1120 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1121 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1124 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1126 context_t
*context
= R700_CONTEXT(ctx
);
1127 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1129 R600_STATECHANGE(context
, su
);
1132 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1133 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1134 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1136 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1137 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1138 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1142 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1144 context_t
*context
= R700_CONTEXT(ctx
);
1145 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1146 GLfloat constant
= units
;
1148 switch (ctx
->Visual
.depthBits
) {
1159 R600_STATECHANGE(context
, poly
);
1161 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1162 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1163 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1164 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1167 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1169 context_t
*context
= R700_CONTEXT(ctx
);
1170 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1172 R600_STATECHANGE(context
, su
);
1174 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1176 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1177 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1178 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1181 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1182 * correctly by selecting the correct front and back face
1184 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1185 f
= ctx
->Polygon
.FrontMode
;
1186 b
= ctx
->Polygon
.BackMode
;
1188 f
= ctx
->Polygon
.BackMode
;
1189 b
= ctx
->Polygon
.FrontMode
;
1192 /* Enable polygon mode */
1193 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1197 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1198 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1201 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1202 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1205 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1206 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1212 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1213 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1216 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1217 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1220 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1221 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1227 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1232 r700UpdatePolygonMode(ctx
);
1235 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1239 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1241 context_t
*context
= R700_CONTEXT(ctx
);
1242 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1246 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1247 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1249 R600_STATECHANGE(context
, ucp
);
1251 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1252 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1253 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1254 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1257 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1259 context_t
*context
= R700_CONTEXT(ctx
);
1260 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1263 p
= cap
- GL_CLIP_PLANE0
;
1265 R600_STATECHANGE(context
, cl
);
1268 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1269 r700
->ucp
[p
].enabled
= GL_TRUE
;
1270 r700ClipPlane(ctx
, cap
, NULL
);
1272 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1273 r700
->ucp
[p
].enabled
= GL_FALSE
;
1277 void r700SetScissor(context_t
*context
) //---------------
1279 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1280 unsigned x1
, y1
, x2
, y2
;
1282 struct radeon_renderbuffer
*rrb
;
1284 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1285 if (!rrb
|| !rrb
->bo
) {
1288 if (context
->radeon
.state
.scissor
.enabled
) {
1289 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1290 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1291 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
1292 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
1294 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1297 x2
= rrb
->base
.Width
- 1;
1298 y2
= rrb
->base
.Height
- 1;
1302 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1303 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1307 R600_STATECHANGE(context
, scissor
);
1310 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1311 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1312 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1313 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1314 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1316 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1317 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1318 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1319 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1322 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1323 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1324 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1325 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1326 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1328 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1329 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1330 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1331 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1334 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1335 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1336 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1337 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1338 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1339 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1340 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1341 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1343 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1344 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1345 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1346 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1347 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1348 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1350 /* more....2d clip */
1351 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1352 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1353 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1354 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1355 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1356 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1357 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1358 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1359 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1361 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1362 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1363 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1364 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1365 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1366 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1367 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1368 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1369 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1371 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1372 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1373 r700
->viewport
[id
].enabled
= GL_TRUE
;
1376 static void r700SetRenderTarget(context_t
*context
, int id
)
1378 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1380 struct radeon_renderbuffer
*rrb
;
1381 unsigned int nPitchInPixel
;
1383 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1384 if (!rrb
|| !rrb
->bo
) {
1388 R600_STATECHANGE(context
, cb_target
);
1389 R600_STATECHANGE(context
, cb
);
1391 /* screen/window/view */
1392 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
1395 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
;
1397 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1398 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1399 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1400 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1401 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
1402 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= 0;
1403 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
1404 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
1405 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
1408 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
1409 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1410 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
1414 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
1415 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1416 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
1417 COMP_SWAP_shift
, COMP_SWAP_mask
);
1419 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
1420 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
1421 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
1423 r700
->render_target
[id
].enabled
= GL_TRUE
;
1426 static void r700SetDepthTarget(context_t
*context
)
1428 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1430 struct radeon_renderbuffer
*rrb
;
1431 unsigned int nPitchInPixel
;
1433 rrb
= radeon_get_depthbuffer(&context
->radeon
);
1437 R600_STATECHANGE(context
, db_target
);
1440 r700
->DB_DEPTH_SIZE
.u32All
= 0;
1441 r700
->DB_DEPTH_BASE
.u32All
= 0;
1442 r700
->DB_DEPTH_INFO
.u32All
= 0;
1443 r700
->DB_DEPTH_VIEW
.u32All
= 0;
1445 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1447 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1448 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1449 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1450 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
1454 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
1455 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1459 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
1460 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1462 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_2D_TILED_THIN1
,
1463 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
1464 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1467 static void r700InitSQConfig(GLcontext
* ctx
)
1469 context_t
*context
= R700_CONTEXT(ctx
);
1470 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1484 int num_ps_stack_entries
;
1485 int num_vs_stack_entries
;
1486 int num_gs_stack_entries
;
1487 int num_es_stack_entries
;
1489 R600_STATECHANGE(context
, sq
);
1496 switch (context
->radeon
.radeonScreen
->chip_family
) {
1497 case CHIP_FAMILY_R600
:
1503 num_ps_threads
= 136;
1504 num_vs_threads
= 48;
1507 num_ps_stack_entries
= 128;
1508 num_vs_stack_entries
= 128;
1509 num_gs_stack_entries
= 0;
1510 num_es_stack_entries
= 0;
1512 case CHIP_FAMILY_RV630
:
1513 case CHIP_FAMILY_RV635
:
1519 num_ps_threads
= 144;
1520 num_vs_threads
= 40;
1523 num_ps_stack_entries
= 40;
1524 num_vs_stack_entries
= 40;
1525 num_gs_stack_entries
= 32;
1526 num_es_stack_entries
= 16;
1528 case CHIP_FAMILY_RV610
:
1529 case CHIP_FAMILY_RV620
:
1530 case CHIP_FAMILY_RS780
:
1531 case CHIP_FAMILY_RS880
:
1538 num_ps_threads
= 136;
1539 num_vs_threads
= 48;
1542 num_ps_stack_entries
= 40;
1543 num_vs_stack_entries
= 40;
1544 num_gs_stack_entries
= 32;
1545 num_es_stack_entries
= 16;
1547 case CHIP_FAMILY_RV670
:
1553 num_ps_threads
= 136;
1554 num_vs_threads
= 48;
1557 num_ps_stack_entries
= 40;
1558 num_vs_stack_entries
= 40;
1559 num_gs_stack_entries
= 32;
1560 num_es_stack_entries
= 16;
1562 case CHIP_FAMILY_RV770
:
1568 num_ps_threads
= 188;
1569 num_vs_threads
= 60;
1572 num_ps_stack_entries
= 256;
1573 num_vs_stack_entries
= 256;
1574 num_gs_stack_entries
= 0;
1575 num_es_stack_entries
= 0;
1577 case CHIP_FAMILY_RV730
:
1578 case CHIP_FAMILY_RV740
:
1584 num_ps_threads
= 188;
1585 num_vs_threads
= 60;
1588 num_ps_stack_entries
= 128;
1589 num_vs_stack_entries
= 128;
1590 num_gs_stack_entries
= 0;
1591 num_es_stack_entries
= 0;
1593 case CHIP_FAMILY_RV710
:
1599 num_ps_threads
= 144;
1600 num_vs_threads
= 48;
1603 num_ps_stack_entries
= 128;
1604 num_vs_stack_entries
= 128;
1605 num_gs_stack_entries
= 0;
1606 num_es_stack_entries
= 0;
1610 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1611 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1612 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1613 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1614 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1615 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1616 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1618 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1619 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1620 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1621 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1622 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1623 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1624 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1626 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1627 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1628 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1629 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1630 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1632 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1633 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1634 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1636 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1637 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1638 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1639 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1640 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1641 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1642 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1643 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1644 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1646 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1647 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1648 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1649 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1650 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1652 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1653 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1654 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1655 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1656 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1661 * Calculate initial hardware state and register state functions.
1662 * Assumes that the command buffer and state atoms have been
1663 * initialized already.
1665 void r700InitState(GLcontext
* ctx
) //-------------------
1667 context_t
*context
= R700_CONTEXT(ctx
);
1668 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1670 radeon_firevertices(&context
->radeon
);
1672 r700
->TA_CNTL_AUX
.u32All
= 0;
1673 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1674 r700
->VC_ENHANCE
.u32All
= 0;
1675 r700
->DB_WATERMARKS
.u32All
= 0;
1676 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1677 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1678 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1679 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1680 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1681 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1682 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1683 r700
->DB_DEBUG
.u32All
= 0x82000000;
1684 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1686 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1687 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1688 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1691 /* Turn off vgt reuse */
1692 r700
->VGT_REUSE_OFF
.u32All
= 0;
1693 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1695 /* Specify offsetting and clamp values for vertices */
1696 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1697 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1698 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1700 /* default shader connections. */
1701 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1702 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1703 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1704 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1706 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1707 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1708 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1710 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1711 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1712 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1714 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1715 r700
->PA_SC_EDGERULE
.u32All
= 0;
1717 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1719 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1720 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1721 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1722 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1724 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1725 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1726 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1729 /* Do scale XY and Z by 1/W0. */
1730 r700
->bEnablePerspective
= GL_TRUE
;
1731 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1732 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1733 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1735 /* Enable viewport scaling for all three axis */
1736 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1737 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1738 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1739 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1740 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1741 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1743 /* GL uses last vtx for flat shading components */
1744 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1746 /* Set up vertex control */
1747 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1748 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1749 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1750 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1751 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1753 /* to 1.0 = no guard band */
1754 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1755 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1756 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1757 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1759 /* Enable all samples for multi-sample anti-aliasing */
1760 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1762 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1764 r700
->SX_MISC
.u32All
= 0;
1766 r700InitSQConfig(ctx
);
1769 ctx
->Color
.ColorMask
[RCOMP
],
1770 ctx
->Color
.ColorMask
[GCOMP
],
1771 ctx
->Color
.ColorMask
[BCOMP
],
1772 ctx
->Color
.ColorMask
[ACOMP
]);
1774 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1775 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1776 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1777 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1779 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1781 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1782 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1783 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1784 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1785 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1786 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1787 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1788 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1789 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1791 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1792 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1793 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1794 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1795 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1798 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1799 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1800 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1801 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1802 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1803 ctx
->Stencil
.ZFailFunc
[0],
1804 ctx
->Stencil
.ZPassFunc
[0]);
1806 r700UpdateCulling(ctx
);
1808 r700SetBlendState(ctx
);
1809 r700SetLogicOpState(ctx
);
1811 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1812 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1814 r700PointSize(ctx
, 1.0);
1816 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1817 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1819 r700LineWidth(ctx
, 1.0);
1821 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1822 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1823 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1825 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1826 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1827 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1828 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1829 ctx
->Polygon
.OffsetUnits
);
1830 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1831 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1832 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1835 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1837 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1838 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1839 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1840 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1841 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1842 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1843 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1845 /* Disable color compares */
1846 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1847 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1848 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1849 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1850 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1851 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1853 /* Zero out source */
1854 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1856 /* Put a compare color in for error checking */
1857 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1859 /* Set up color compare mask */
1860 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1862 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1866 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1868 functions
->UpdateState
= r700InvalidateState
;
1869 functions
->AlphaFunc
= r700AlphaFunc
;
1870 functions
->BlendColor
= r700BlendColor
;
1871 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1872 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1873 functions
->Enable
= r700Enable
;
1874 functions
->ColorMask
= r700ColorMask
;
1875 functions
->DepthFunc
= r700DepthFunc
;
1876 functions
->DepthMask
= r700DepthMask
;
1877 functions
->CullFace
= r700CullFace
;
1878 functions
->Fogfv
= r700Fogfv
;
1879 functions
->FrontFace
= r700FrontFace
;
1880 functions
->ShadeModel
= r700ShadeModel
;
1881 functions
->LogicOpcode
= r700LogicOpcode
;
1883 /* ARB_point_parameters */
1884 functions
->PointParameterfv
= r700PointParameter
;
1886 /* Stencil related */
1887 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1888 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1889 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1891 /* Viewport related */
1892 functions
->Viewport
= r700Viewport
;
1893 functions
->DepthRange
= r700DepthRange
;
1894 functions
->PointSize
= r700PointSize
;
1895 functions
->LineWidth
= r700LineWidth
;
1896 functions
->LineStipple
= r700LineStipple
;
1898 functions
->PolygonOffset
= r700PolygonOffset
;
1899 functions
->PolygonMode
= r700PolygonMode
;
1901 functions
->RenderMode
= r700RenderMode
;
1903 functions
->ClipPlane
= r700ClipPlane
;
1905 functions
->Scissor
= radeonScissor
;
1907 functions
->DrawBuffer
= radeonDrawBuffer
;
1908 functions
->ReadBuffer
= radeonReadBuffer
;