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r600: add logicop support
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 void r700SetDefaultStates(context_t *context) //--------------------
60 {
61
62 }
63
64 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
65 {
66 context_t *context = R700_CONTEXT(ctx);
67
68 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
69 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
70
71 struct r700_vertex_program *vp;
72 int i;
73
74 if (context->radeon.NewGLState)
75 {
76 context->radeon.NewGLState = 0;
77
78 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
79 {
80 /* mat states from state var not array for sw */
81 dummy_attrib[i].stride = 0;
82
83 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
84 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
85 }
86
87 _tnl_UpdateFixedFunctionProgram(ctx);
88
89 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
90 {
91 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
92 }
93
94 r700SelectVertexShader(ctx);
95 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
96
97 if (vp->translated == GL_FALSE)
98 {
99 // TODO
100 //fprintf(stderr, "Failing back to sw-tcl\n");
101 //hw_tcl_on = future_hw_tcl_on = 0;
102 //r300ResetHwState(rmesa);
103 //
104 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
105 return;
106 }
107 }
108
109 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
110 }
111
112 /*
113 * To correctly position primitives:
114 */
115 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
116 {
117
118 //radeonUpdateScissor(ctx);
119
120 return;
121 }
122
123 /**
124 * Tell the card where to render (offset, pitch).
125 * Effected by glDrawBuffer, etc
126 */
127 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
128 {
129 #if 0 /* to be enabled */
130 context_t *context = R700_CONTEXT(ctx);
131
132 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
133 {
134 case BUFFER_FRONT_LEFT:
135 context->target.rt = context->screen->frontBuffer;
136 break;
137 case BUFFER_BACK_LEFT:
138 context->target.rt = context->screen->backBuffer;
139 break;
140 default:
141 memset (&context->target.rt, sizeof(context->target.rt), 0);
142 }
143 #endif /* to be enabled */
144 }
145
146 static void r700FetchStateParameter(GLcontext * ctx,
147 const gl_state_index state[STATE_LENGTH],
148 GLfloat * value)
149 {
150 context_t *context = R700_CONTEXT(ctx);
151
152 /* TODO */
153 }
154
155 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
156 {
157 struct r700_fragment_program *fp;
158 struct gl_program_parameter_list *paramList;
159 GLuint i;
160
161 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
162 return;
163
164 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
165 if (!fp)
166 {
167 return;
168 }
169
170 paramList = fp->mesa_program.Base.Parameters;
171
172 if (!paramList)
173 {
174 return;
175 }
176
177 for (i = 0; i < paramList->NumParameters; i++)
178 {
179 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
180 {
181 r700FetchStateParameter(ctx,
182 paramList->Parameters[i].
183 StateIndexes,
184 paramList->ParameterValues[i]);
185 }
186 }
187 }
188
189 /**
190 * Called by Mesa after an internal state update.
191 */
192 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
193 {
194 context_t *context = R700_CONTEXT(ctx);
195
196 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
197
198 _swrast_InvalidateState(ctx, new_state);
199 _swsetup_InvalidateState(ctx, new_state);
200 _vbo_InvalidateState(ctx, new_state);
201 _tnl_InvalidateState(ctx, new_state);
202 _ae_invalidate_state(ctx, new_state);
203
204 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
205 {
206 _mesa_update_framebuffer(ctx);
207 /* this updates the DrawBuffer's Width/Height if it's a FBO */
208 _mesa_update_draw_buffer_bounds(ctx);
209
210 r700UpdateDrawBuffer(ctx);
211 }
212
213 r700UpdateStateParameters(ctx, new_state);
214
215 if(GL_TRUE == r700->bEnablePerspective)
216 {
217 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
218 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
219 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
220
221 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
222
223 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
224 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
225 }
226 else
227 {
228 /* For orthogonal case. */
229 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
230 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
231
232 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
233
234 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
235 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
236 }
237
238 context->radeon.NewGLState |= new_state;
239 }
240
241 static void r700SetDepthState(GLcontext * ctx)
242 {
243 context_t *context = R700_CONTEXT(ctx);
244
245 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
246
247 if (ctx->Depth.Test)
248 {
249 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
250 if (ctx->Depth.Mask)
251 {
252 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
253 }
254 else
255 {
256 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
257 }
258
259 switch (ctx->Depth.Func)
260 {
261 case GL_NEVER:
262 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
263 ZFUNC_shift, ZFUNC_mask);
264 break;
265 case GL_LESS:
266 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
267 ZFUNC_shift, ZFUNC_mask);
268 break;
269 case GL_EQUAL:
270 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
271 ZFUNC_shift, ZFUNC_mask);
272 break;
273 case GL_LEQUAL:
274 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
275 ZFUNC_shift, ZFUNC_mask);
276 break;
277 case GL_GREATER:
278 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
279 ZFUNC_shift, ZFUNC_mask);
280 break;
281 case GL_NOTEQUAL:
282 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
283 ZFUNC_shift, ZFUNC_mask);
284 break;
285 case GL_GEQUAL:
286 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
287 ZFUNC_shift, ZFUNC_mask);
288 break;
289 case GL_ALWAYS:
290 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
291 ZFUNC_shift, ZFUNC_mask);
292 break;
293 default:
294 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
295 ZFUNC_shift, ZFUNC_mask);
296 break;
297 }
298 }
299 else
300 {
301 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
302 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
303 }
304 }
305
306 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
307 {
308 }
309
310
311 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
312 {
313 }
314
315 static void r700BlendEquationSeparate(GLcontext * ctx,
316 GLenum modeRGB, GLenum modeA) //-----------------
317 {
318 }
319
320 static void r700BlendFuncSeparate(GLcontext * ctx,
321 GLenum sfactorRGB, GLenum dfactorRGB,
322 GLenum sfactorA, GLenum dfactorA) //------------------------
323 {
324 }
325
326 /**
327 * Translate LogicOp enums into hardware representation.
328 * Both use a very logical bit-wise layout, but unfortunately the order
329 * of bits is reversed.
330 */
331 static GLuint translate_logicop(GLenum logicop)
332 {
333 GLuint bits = logicop - GL_CLEAR;
334 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
335 return bits;
336 }
337
338 /**
339 * Used internally to update the r300->hw hardware state to match the
340 * current OpenGL state.
341 */
342 static void r700SetLogicOpState(GLcontext *ctx)
343 {
344 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
345
346 if (RGBA_LOGICOP_ENABLED(ctx))
347 SETfield(r700->CB_COLOR_CONTROL.u32All,
348 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
349 else
350 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
351 }
352
353 /**
354 * Called by Mesa when an application program changes the LogicOp state
355 * via glLogicOp.
356 */
357 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
358 {
359 if (RGBA_LOGICOP_ENABLED(ctx))
360 r700SetLogicOpState(ctx);
361 }
362
363 static void r700UpdateCulling(GLcontext * ctx)
364 {
365 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
366
367 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
368 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
369 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
370
371 if (ctx->Polygon.CullFlag)
372 {
373 switch (ctx->Polygon.CullFaceMode)
374 {
375 case GL_FRONT:
376 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
377 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
378 break;
379 case GL_BACK:
380 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
381 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
382 break;
383 case GL_FRONT_AND_BACK:
384 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
385 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
386 break;
387 default:
388 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
389 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
390 break;
391 }
392 }
393
394 switch (ctx->Polygon.FrontFace)
395 {
396 case GL_CW:
397 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
398 break;
399 case GL_CCW:
400 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
401 break;
402 default:
403 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
404 break;
405 }
406 }
407
408 static void r700UpdateLineStipple(GLcontext * ctx)
409 {
410 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
411 if (ctx->Line.StippleFlag)
412 {
413 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
414 }
415 else
416 {
417 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
418 }
419 }
420
421 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
422 {
423 context_t *context = R700_CONTEXT(ctx);
424
425 switch (cap) {
426 case GL_TEXTURE_1D:
427 case GL_TEXTURE_2D:
428 case GL_TEXTURE_3D:
429 /* empty */
430 break;
431 case GL_FOG:
432 /* empty */
433 break;
434 case GL_ALPHA_TEST:
435 //r700SetAlphaState(ctx);
436 break;
437 case GL_COLOR_LOGIC_OP:
438 r700SetLogicOpState(ctx);
439 /* fall-through, because logic op overrides blending */
440 case GL_BLEND:
441 //r700SetBlendState(ctx);
442 break;
443 case GL_CLIP_PLANE0:
444 case GL_CLIP_PLANE1:
445 case GL_CLIP_PLANE2:
446 case GL_CLIP_PLANE3:
447 case GL_CLIP_PLANE4:
448 case GL_CLIP_PLANE5:
449 //r700SetClipPlaneState(ctx, cap, state);
450 break;
451 case GL_DEPTH_TEST:
452 r700SetDepthState(ctx);
453 break;
454 case GL_STENCIL_TEST:
455 //r700SetStencilState(ctx, state);
456 break;
457 case GL_CULL_FACE:
458 r700UpdateCulling(ctx);
459 break;
460 case GL_POLYGON_OFFSET_POINT:
461 case GL_POLYGON_OFFSET_LINE:
462 case GL_POLYGON_OFFSET_FILL:
463 //r700SetPolygonOffsetState(ctx, state);
464 break;
465 case GL_SCISSOR_TEST:
466 radeon_firevertices(&context->radeon);
467 context->radeon.state.scissor.enabled = state;
468 radeonUpdateScissor(ctx);
469 break;
470 case GL_LINE_STIPPLE:
471 r700UpdateLineStipple(ctx);
472 break;
473 default:
474 break;
475 }
476
477 }
478
479 /**
480 * Handle glColorMask()
481 */
482 static void r700ColorMask(GLcontext * ctx,
483 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
484 {
485 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
486 unsigned int mask = ((r ? 1 : 0) |
487 (g ? 2 : 0) |
488 (b ? 4 : 0) |
489 (a ? 8 : 0));
490
491 if (mask != r700->CB_SHADER_MASK.u32All)
492 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
493 }
494
495 /**
496 * Change the depth testing function.
497 *
498 * \note Mesa already filters redundant calls to this function.
499 */
500 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
501 {
502 r700SetDepthState(ctx);
503 }
504
505 /**
506 * Enable/Disable depth writing.
507 *
508 * \note Mesa already filters redundant calls to this function.
509 */
510 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
511 {
512 r700SetDepthState(ctx);
513 }
514
515 /**
516 * Change the culling mode.
517 *
518 * \note Mesa already filters redundant calls to this function.
519 */
520 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
521 {
522 r700UpdateCulling(ctx);
523 }
524
525 /* =============================================================
526 * Fog
527 */
528 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
529 {
530 }
531
532 /**
533 * Change the polygon orientation.
534 *
535 * \note Mesa already filters redundant calls to this function.
536 */
537 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
538 {
539 r700UpdateCulling(ctx);
540 }
541
542 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
543 {
544 context_t *context = R700_CONTEXT(ctx);
545 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
546
547 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
548 switch (mode) {
549 case GL_FLAT:
550 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
551 break;
552 case GL_SMOOTH:
553 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
554 break;
555 default:
556 return;
557 }
558 }
559
560 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
561 {
562 }
563
564 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
565 GLenum func, GLint ref, GLuint mask) //---------------------
566 {
567 }
568
569
570 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
571 {
572 }
573
574 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
575 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
576 {
577 }
578
579 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
580 {
581
582 context_t *context = R700_CONTEXT(ctx);
583 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
584 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
585 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
586 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
587 const GLfloat *v = ctx->Viewport._WindowMap.m;
588 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
589 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
590 GLfloat y_scale, y_bias;
591
592 if (render_to_fbo) {
593 y_scale = 1.0;
594 y_bias = 0;
595 } else {
596 y_scale = -1.0;
597 y_bias = yoffset;
598 }
599
600 GLfloat sx = v[MAT_SX];
601 GLfloat tx = v[MAT_TX] + xoffset;
602 GLfloat sy = v[MAT_SY] * y_scale;
603 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
604 GLfloat sz = v[MAT_SZ] * depthScale;
605 GLfloat tz = v[MAT_TZ] * depthScale;
606
607 /* TODO : Need DMA flush as well. */
608
609 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
610 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
611
612 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
613 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
614
615 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
616 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
617
618 r700->viewport[id].enabled = GL_TRUE;
619
620 r700SetScissor(context);
621 }
622
623
624 static void r700Viewport(GLcontext * ctx,
625 GLint x,
626 GLint y,
627 GLsizei width,
628 GLsizei height) //--------------------
629 {
630 r700UpdateWindow(ctx, 0);
631
632 radeon_viewport(ctx, x, y, width, height);
633 }
634
635 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
636 {
637 r700UpdateWindow(ctx, 0);
638 }
639
640 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
641 {
642 }
643
644 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
645 {
646 context_t *context = R700_CONTEXT(ctx);
647 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
648 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
649 if (lineWidth > 0xFFFF)
650 lineWidth = 0xFFFF;
651 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
652 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
653 }
654
655 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
656 {
657 context_t *context = R700_CONTEXT(ctx);
658 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
659
660 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
661 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
662 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
663 }
664
665 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
666 {
667 }
668
669
670 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
671 {
672 }
673
674 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
675 {
676 }
677
678 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
679 {
680 }
681
682 void r700SetScissor(context_t *context) //---------------
683 {
684 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
685 unsigned x1, y1, x2, y2;
686 int id = 0;
687 struct radeon_renderbuffer *rrb;
688
689 rrb = radeon_get_colorbuffer(&context->radeon);
690 if (!rrb || !rrb->bo) {
691 return;
692 }
693 if (context->radeon.state.scissor.enabled) {
694 x1 = context->radeon.state.scissor.rect.x1;
695 y1 = context->radeon.state.scissor.rect.y1;
696 x2 = context->radeon.state.scissor.rect.x2 - 1;
697 y2 = context->radeon.state.scissor.rect.y2 - 1;
698 } else {
699 x1 = rrb->dPriv->x;
700 y1 = rrb->dPriv->y;
701 x2 = rrb->dPriv->x + rrb->dPriv->w;
702 y2 = rrb->dPriv->y + rrb->dPriv->h;
703 }
704
705 /* window */
706 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
707 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
708 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
709 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
710 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
711
712 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
713 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
714 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
715 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
716
717
718 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
719 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
720 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
721 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
722 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
723 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
724 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
725 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
726
727 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
728 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
729 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
730 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
731 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
732 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
733
734 /* more....2d clip */
735 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
736 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
737 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
738 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
739 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
740 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
741 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
742 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
743 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
744
745 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
746 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
747 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
748 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
749 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
750 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
751 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
752 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
753 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
754
755 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
756 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
757 r700->viewport[id].enabled = GL_TRUE;
758 }
759
760 void r700SetRenderTarget(context_t *context, int id)
761 {
762 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
763
764 struct radeon_renderbuffer *rrb;
765 unsigned int nPitchInPixel;
766
767 /* screen/window/view */
768 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
769
770 rrb = radeon_get_colorbuffer(&context->radeon);
771 if (!rrb || !rrb->bo) {
772 fprintf(stderr, "no rrb\n");
773 return;
774 }
775
776 /* color buffer */
777 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
778
779 nPitchInPixel = rrb->pitch/rrb->cpp;
780 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
781 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
782 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
783 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
784 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
785 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
786 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
787 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
788 if(4 == rrb->cpp)
789 {
790 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
791 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
792 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
793 }
794 else
795 {
796 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
797 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
798 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
799 COMP_SWAP_shift, COMP_SWAP_mask);
800 }
801 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
802 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
803 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
804
805 CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
806 CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
807
808 r700->render_target[id].enabled = GL_TRUE;
809 }
810
811 void r700SetDepthTarget(context_t *context)
812 {
813 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
814
815 struct radeon_renderbuffer *rrb;
816 unsigned int nPitchInPixel;
817
818 /* depth buf */
819 r700->DB_DEPTH_SIZE.u32All = 0;
820 r700->DB_DEPTH_BASE.u32All = 0;
821 r700->DB_DEPTH_INFO.u32All = 0;
822
823 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
824 r700->DB_DEPTH_VIEW.u32All = 0;
825 r700->DB_RENDER_CONTROL.u32All = 0;
826 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
827 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
828 r700->DB_RENDER_OVERRIDE.u32All = 0;
829 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
830 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
831 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
832 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
833 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
834
835 r700->DB_ALPHA_TO_MASK.u32All = 0;
836 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
837 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
838 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
839 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
840
841 rrb = radeon_get_depthbuffer(&context->radeon);
842 if (!rrb)
843 return;
844
845 nPitchInPixel = rrb->pitch/rrb->cpp;
846
847 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
848 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
849 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
850 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
851
852 if(4 == rrb->cpp)
853 {
854 switch (GL_CONTEXT(context)->Visual.depthBits)
855 {
856 case 16:
857 case 24:
858 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
859 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
860 break;
861 default:
862 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
863 GL_CONTEXT(context)->Visual.depthBits);
864 _mesa_exit(-1);
865 }
866 }
867 else
868 {
869 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
870 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
871 }
872 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
873 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
874 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
875 }
876
877 static void r700InitSQConfig(GLcontext * ctx)
878 {
879 context_t *context = R700_CONTEXT(ctx);
880 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
881 int ps_prio;
882 int vs_prio;
883 int gs_prio;
884 int es_prio;
885 int num_ps_gprs;
886 int num_vs_gprs;
887 int num_gs_gprs;
888 int num_es_gprs;
889 int num_temp_gprs;
890 int num_ps_threads;
891 int num_vs_threads;
892 int num_gs_threads;
893 int num_es_threads;
894 int num_ps_stack_entries;
895 int num_vs_stack_entries;
896 int num_gs_stack_entries;
897 int num_es_stack_entries;
898
899 // SQ
900 ps_prio = 0;
901 vs_prio = 1;
902 gs_prio = 2;
903 es_prio = 3;
904 switch (context->radeon.radeonScreen->chip_family) {
905 case CHIP_FAMILY_R600:
906 num_ps_gprs = 192;
907 num_vs_gprs = 56;
908 num_temp_gprs = 4;
909 num_gs_gprs = 0;
910 num_es_gprs = 0;
911 num_ps_threads = 136;
912 num_vs_threads = 48;
913 num_gs_threads = 4;
914 num_es_threads = 4;
915 num_ps_stack_entries = 128;
916 num_vs_stack_entries = 128;
917 num_gs_stack_entries = 0;
918 num_es_stack_entries = 0;
919 break;
920 case CHIP_FAMILY_RV630:
921 case CHIP_FAMILY_RV635:
922 num_ps_gprs = 84;
923 num_vs_gprs = 36;
924 num_temp_gprs = 4;
925 num_gs_gprs = 0;
926 num_es_gprs = 0;
927 num_ps_threads = 144;
928 num_vs_threads = 40;
929 num_gs_threads = 4;
930 num_es_threads = 4;
931 num_ps_stack_entries = 40;
932 num_vs_stack_entries = 40;
933 num_gs_stack_entries = 32;
934 num_es_stack_entries = 16;
935 break;
936 case CHIP_FAMILY_RV610:
937 case CHIP_FAMILY_RV620:
938 case CHIP_FAMILY_RS780:
939 default:
940 num_ps_gprs = 84;
941 num_vs_gprs = 36;
942 num_temp_gprs = 4;
943 num_gs_gprs = 0;
944 num_es_gprs = 0;
945 num_ps_threads = 136;
946 num_vs_threads = 48;
947 num_gs_threads = 4;
948 num_es_threads = 4;
949 num_ps_stack_entries = 40;
950 num_vs_stack_entries = 40;
951 num_gs_stack_entries = 32;
952 num_es_stack_entries = 16;
953 break;
954 case CHIP_FAMILY_RV670:
955 num_ps_gprs = 144;
956 num_vs_gprs = 40;
957 num_temp_gprs = 4;
958 num_gs_gprs = 0;
959 num_es_gprs = 0;
960 num_ps_threads = 136;
961 num_vs_threads = 48;
962 num_gs_threads = 4;
963 num_es_threads = 4;
964 num_ps_stack_entries = 40;
965 num_vs_stack_entries = 40;
966 num_gs_stack_entries = 32;
967 num_es_stack_entries = 16;
968 break;
969 case CHIP_FAMILY_RV770:
970 num_ps_gprs = 192;
971 num_vs_gprs = 56;
972 num_temp_gprs = 4;
973 num_gs_gprs = 0;
974 num_es_gprs = 0;
975 num_ps_threads = 188;
976 num_vs_threads = 60;
977 num_gs_threads = 0;
978 num_es_threads = 0;
979 num_ps_stack_entries = 256;
980 num_vs_stack_entries = 256;
981 num_gs_stack_entries = 0;
982 num_es_stack_entries = 0;
983 break;
984 case CHIP_FAMILY_RV730:
985 case CHIP_FAMILY_RV740:
986 num_ps_gprs = 84;
987 num_vs_gprs = 36;
988 num_temp_gprs = 4;
989 num_gs_gprs = 0;
990 num_es_gprs = 0;
991 num_ps_threads = 188;
992 num_vs_threads = 60;
993 num_gs_threads = 0;
994 num_es_threads = 0;
995 num_ps_stack_entries = 128;
996 num_vs_stack_entries = 128;
997 num_gs_stack_entries = 0;
998 num_es_stack_entries = 0;
999 break;
1000 case CHIP_FAMILY_RV710:
1001 num_ps_gprs = 192;
1002 num_vs_gprs = 56;
1003 num_temp_gprs = 4;
1004 num_gs_gprs = 0;
1005 num_es_gprs = 0;
1006 num_ps_threads = 144;
1007 num_vs_threads = 48;
1008 num_gs_threads = 0;
1009 num_es_threads = 0;
1010 num_ps_stack_entries = 128;
1011 num_vs_stack_entries = 128;
1012 num_gs_stack_entries = 0;
1013 num_es_stack_entries = 0;
1014 break;
1015 }
1016
1017 r700->sq_config.SQ_CONFIG.u32All = 0;
1018 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1019 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1020 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1021 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1022 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1023 else
1024 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1025 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1026 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1027 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1028 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1029 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1030 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1031
1032 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1033 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1034 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1035 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1036 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1037
1038 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1039 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1040 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1041
1042 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1043 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1044 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1045 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1046 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1047 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1048 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1049 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1050 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1051
1052 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1053 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1054 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1055 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1056 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1057
1058 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1059 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1060 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1061 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1062 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1063
1064 }
1065
1066 /**
1067 * Calculate initial hardware state and register state functions.
1068 * Assumes that the command buffer and state atoms have been
1069 * initialized already.
1070 */
1071 void r700InitState(GLcontext * ctx) //-------------------
1072 {
1073 context_t *context = R700_CONTEXT(ctx);
1074
1075 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1076
1077 r700->TA_CNTL_AUX.u32All = 0;
1078 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1079 r700->VC_ENHANCE.u32All = 0;
1080 r700->DB_WATERMARKS.u32All = 0;
1081 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1082 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1083 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1084 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1085 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1086 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1087 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1088 r700->DB_DEBUG.u32All = 0x82000000;
1089 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1090 } else {
1091 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1092 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1093 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1094 }
1095
1096 /* Turn off vgt reuse */
1097 r700->VGT_REUSE_OFF.u32All = 0;
1098 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1099
1100 /* Specify offsetting and clamp values for vertices */
1101 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1102 r700->VGT_MIN_VTX_INDX.u32All = 0;
1103 r700->VGT_INDX_OFFSET.u32All = 0;
1104
1105 /* Specify the number of instances */
1106 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
1107
1108 /* not alpha blend */
1109 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
1110 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
1111
1112 /* default shader connections. */
1113 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1114 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1115
1116 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1117 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1118 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1119
1120 r700->SPI_THREAD_GROUPING.u32All = 0;
1121 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1122 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1123
1124 r700SetLogicOpState(ctx);
1125 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
1126
1127 r700->DB_SHADER_CONTROL.u32All = 0;
1128 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1129
1130 /* Set up the culling control register */
1131 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1132 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1133 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1134 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1135
1136 /* screen */
1137 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1138
1139 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1140 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1141 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1142 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1143 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1144 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1145
1146 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1147 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1148 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1149
1150 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1151 r700->PA_SC_EDGERULE.u32All = 0;
1152 else
1153 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1154
1155 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1156 r700->PA_SC_MODE_CNTL.u32All = 0;
1157 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1158 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1159 } else {
1160 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1161 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1162 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1163 }
1164
1165 /* Do scale XY and Z by 1/W0. */
1166 r700->bEnablePerspective = GL_TRUE;
1167 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1168 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1169 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1170
1171 /* Enable viewport scaling for all three axis */
1172 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1173 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1174 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1175 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1176 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1177 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1178
1179 /* Set up point sizes and min/max values */
1180 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1181 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
1182 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1183 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
1184 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1185 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1186
1187 /* Set up line control */
1188 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
1189 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1190
1191 r700->PA_SC_LINE_CNTL.u32All = 0;
1192 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1193 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1194
1195 /* Set up vertex control */
1196 r700->PA_SU_VTX_CNTL.u32All = 0;
1197 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1198 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1199 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1200 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1201
1202 /* to 1.0 = no guard band */
1203 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1204 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1205 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1206 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1207
1208 /* CB */
1209 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1210 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1211 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1212 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1213 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1214 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1215 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1216
1217 r700->CB_BLEND_RED.u32All = 0;
1218 r700->CB_BLEND_GREEN.u32All = 0;
1219 r700->CB_BLEND_BLUE.u32All = 0;
1220 r700->CB_BLEND_ALPHA.u32All = 0;
1221
1222 r700->CB_BLEND_CONTROL.u32All = 0;
1223
1224 /* Disable color compares */
1225 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1226 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1227 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1228 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1229 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1230 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1231
1232 /* Zero out source */
1233 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1234
1235 /* Put a compare color in for error checking */
1236 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1237
1238 /* Set up color compare mask */
1239 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1240
1241 /* default color mask */
1242 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
1243
1244 /* Enable all samples for multi-sample anti-aliasing */
1245 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1246 /* Turn off AA */
1247 r700->PA_SC_AA_CONFIG.u32All = 0;
1248
1249 r700->SX_MISC.u32All = 0;
1250
1251 r700InitSQConfig(ctx);
1252 }
1253
1254 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1255 {
1256 functions->UpdateState = r700InvalidateState;
1257 functions->AlphaFunc = r700AlphaFunc;
1258 functions->BlendColor = r700BlendColor;
1259 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1260 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1261 functions->Enable = r700Enable;
1262 functions->ColorMask = r700ColorMask;
1263 functions->DepthFunc = r700DepthFunc;
1264 functions->DepthMask = r700DepthMask;
1265 functions->CullFace = r700CullFace;
1266 functions->Fogfv = r700Fogfv;
1267 functions->FrontFace = r700FrontFace;
1268 functions->ShadeModel = r700ShadeModel;
1269 functions->LogicOpcode = r700LogicOpcode;
1270
1271 /* ARB_point_parameters */
1272 functions->PointParameterfv = r700PointParameter;
1273
1274 /* Stencil related */
1275 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1276 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1277 functions->StencilOpSeparate = r700StencilOpSeparate;
1278
1279 /* Viewport related */
1280 functions->Viewport = r700Viewport;
1281 functions->DepthRange = r700DepthRange;
1282 functions->PointSize = r700PointSize;
1283 functions->LineWidth = r700LineWidth;
1284 functions->LineStipple = r700LineStipple;
1285
1286 functions->PolygonOffset = r700PolygonOffset;
1287 functions->PolygonMode = r700PolygonMode;
1288
1289 functions->RenderMode = r700RenderMode;
1290
1291 functions->ClipPlane = r700ClipPlane;
1292
1293 functions->Scissor = radeonScissor;
1294
1295 functions->DrawBuffer = radeonDrawBuffer;
1296 functions->ReadBuffer = radeonReadBuffer;
1297
1298 }
1299