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r600: handle state emit better
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700SetDefaultStates(context_t *context) //--------------------
65 {
66
67 }
68
69 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
70 {
71 context_t *context = R700_CONTEXT(ctx);
72
73 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
74 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
75 int i;
76
77 if (ctx->FragmentProgram._Current) {
78 struct r700_fragment_program *fp = (struct r700_fragment_program *)
79 (ctx->FragmentProgram._Current);
80 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
81 {
82 fp->r700AsmCode.bR6xx = 1;
83 }
84
85 if(GL_FALSE == fp->translated)
86 {
87 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
88 {
89 //return GL_TRUE;
90 }
91 }
92 }
93
94 if (context->radeon.NewGLState)
95 {
96 struct r700_vertex_program *vp;
97 context->radeon.NewGLState = 0;
98
99 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
100 {
101 /* mat states from state var not array for sw */
102 dummy_attrib[i].stride = 0;
103
104 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
105 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
106 }
107
108 _tnl_UpdateFixedFunctionProgram(ctx);
109
110 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
111 {
112 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
113 }
114
115 r700SelectVertexShader(ctx);
116 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
117
118 if (vp->translated == GL_FALSE)
119 {
120 // TODO
121 //fprintf(stderr, "Failing back to sw-tcl\n");
122 //hw_tcl_on = future_hw_tcl_on = 0;
123 //r300ResetHwState(rmesa);
124 //
125 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
126 return;
127 }
128 }
129
130 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
131 }
132
133 /*
134 * To correctly position primitives:
135 */
136 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
137 {
138 context_t *context = R700_CONTEXT(ctx);
139 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
140 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
141 GLfloat xoffset = (GLfloat) dPriv->x;
142 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
143 const GLfloat *v = ctx->Viewport._WindowMap.m;
144 int id = 0;
145
146 GLfloat tx = v[MAT_TX] + xoffset;
147 GLfloat ty = (-v[MAT_TY]) + yoffset;
148
149 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
150 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
151
152 radeonUpdateScissor(ctx);
153 }
154
155 /**
156 * Tell the card where to render (offset, pitch).
157 * Effected by glDrawBuffer, etc
158 */
159 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
160 {
161 #if 0 /* to be enabled */
162 context_t *context = R700_CONTEXT(ctx);
163
164 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
165 {
166 case BUFFER_FRONT_LEFT:
167 context->target.rt = context->screen->frontBuffer;
168 break;
169 case BUFFER_BACK_LEFT:
170 context->target.rt = context->screen->backBuffer;
171 break;
172 default:
173 memset (&context->target.rt, sizeof(context->target.rt), 0);
174 }
175 #endif /* to be enabled */
176 }
177
178 static void r700FetchStateParameter(GLcontext * ctx,
179 const gl_state_index state[STATE_LENGTH],
180 GLfloat * value)
181 {
182 context_t *context = R700_CONTEXT(ctx);
183
184 /* TODO */
185 }
186
187 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
188 {
189 struct r700_fragment_program *fp;
190 struct gl_program_parameter_list *paramList;
191 GLuint i;
192
193 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
194 return;
195
196 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
197 if (!fp)
198 {
199 return;
200 }
201
202 paramList = fp->mesa_program.Base.Parameters;
203
204 if (!paramList)
205 {
206 return;
207 }
208
209 for (i = 0; i < paramList->NumParameters; i++)
210 {
211 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
212 {
213 r700FetchStateParameter(ctx,
214 paramList->Parameters[i].
215 StateIndexes,
216 paramList->ParameterValues[i]);
217 }
218 }
219 }
220
221 /**
222 * Called by Mesa after an internal state update.
223 */
224 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
225 {
226 context_t *context = R700_CONTEXT(ctx);
227
228 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
229
230 _swrast_InvalidateState(ctx, new_state);
231 _swsetup_InvalidateState(ctx, new_state);
232 _vbo_InvalidateState(ctx, new_state);
233 _tnl_InvalidateState(ctx, new_state);
234 _ae_invalidate_state(ctx, new_state);
235
236 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
237 {
238 _mesa_update_framebuffer(ctx);
239 /* this updates the DrawBuffer's Width/Height if it's a FBO */
240 _mesa_update_draw_buffer_bounds(ctx);
241
242 r700UpdateDrawBuffer(ctx);
243 }
244
245 r700UpdateStateParameters(ctx, new_state);
246
247 if(GL_TRUE == r700->bEnablePerspective)
248 {
249 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
250 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
251 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
252
253 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
254
255 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
256 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
257 }
258 else
259 {
260 /* For orthogonal case. */
261 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
262 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
263
264 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
265
266 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
267 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
268 }
269
270 context->radeon.NewGLState |= new_state;
271 }
272
273 static void r700SetDepthState(GLcontext * ctx)
274 {
275 context_t *context = R700_CONTEXT(ctx);
276
277 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
278
279 if (ctx->Depth.Test)
280 {
281 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
282 if (ctx->Depth.Mask)
283 {
284 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
285 }
286 else
287 {
288 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
289 }
290
291 switch (ctx->Depth.Func)
292 {
293 case GL_NEVER:
294 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
295 ZFUNC_shift, ZFUNC_mask);
296 break;
297 case GL_LESS:
298 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
299 ZFUNC_shift, ZFUNC_mask);
300 break;
301 case GL_EQUAL:
302 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
303 ZFUNC_shift, ZFUNC_mask);
304 break;
305 case GL_LEQUAL:
306 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
307 ZFUNC_shift, ZFUNC_mask);
308 break;
309 case GL_GREATER:
310 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
311 ZFUNC_shift, ZFUNC_mask);
312 break;
313 case GL_NOTEQUAL:
314 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
315 ZFUNC_shift, ZFUNC_mask);
316 break;
317 case GL_GEQUAL:
318 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
319 ZFUNC_shift, ZFUNC_mask);
320 break;
321 case GL_ALWAYS:
322 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
323 ZFUNC_shift, ZFUNC_mask);
324 break;
325 default:
326 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
327 ZFUNC_shift, ZFUNC_mask);
328 break;
329 }
330 }
331 else
332 {
333 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
334 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
335 }
336 }
337
338 static void r700SetAlphaState(GLcontext * ctx)
339 {
340 context_t *context = R700_CONTEXT(ctx);
341 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
342 uint32_t alpha_func = REF_ALWAYS;
343 GLboolean really_enabled = ctx->Color.AlphaEnabled;
344
345 switch (ctx->Color.AlphaFunc) {
346 case GL_NEVER:
347 alpha_func = REF_NEVER;
348 break;
349 case GL_LESS:
350 alpha_func = REF_LESS;
351 break;
352 case GL_EQUAL:
353 alpha_func = REF_EQUAL;
354 break;
355 case GL_LEQUAL:
356 alpha_func = REF_LEQUAL;
357 break;
358 case GL_GREATER:
359 alpha_func = REF_GREATER;
360 break;
361 case GL_NOTEQUAL:
362 alpha_func = REF_NOTEQUAL;
363 break;
364 case GL_GEQUAL:
365 alpha_func = REF_GEQUAL;
366 break;
367 case GL_ALWAYS:
368 /*alpha_func = REF_ALWAYS; */
369 really_enabled = GL_FALSE;
370 break;
371 }
372
373 if (really_enabled) {
374 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
375 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
376 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
377 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
378 } else {
379 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
380 }
381
382 }
383
384 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
385 {
386 (void)func;
387 (void)ref;
388 r700SetAlphaState(ctx);
389 }
390
391
392 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
393 {
394 context_t *context = R700_CONTEXT(ctx);
395 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
396
397 r700->CB_BLEND_RED.f32All = cf[0];
398 r700->CB_BLEND_GREEN.f32All = cf[1];
399 r700->CB_BLEND_BLUE.f32All = cf[2];
400 r700->CB_BLEND_ALPHA.f32All = cf[3];
401 }
402
403 static int blend_factor(GLenum factor, GLboolean is_src)
404 {
405 switch (factor) {
406 case GL_ZERO:
407 return BLEND_ZERO;
408 break;
409 case GL_ONE:
410 return BLEND_ONE;
411 break;
412 case GL_DST_COLOR:
413 return BLEND_DST_COLOR;
414 break;
415 case GL_ONE_MINUS_DST_COLOR:
416 return BLEND_ONE_MINUS_DST_COLOR;
417 break;
418 case GL_SRC_COLOR:
419 return BLEND_SRC_COLOR;
420 break;
421 case GL_ONE_MINUS_SRC_COLOR:
422 return BLEND_ONE_MINUS_SRC_COLOR;
423 break;
424 case GL_SRC_ALPHA:
425 return BLEND_SRC_ALPHA;
426 break;
427 case GL_ONE_MINUS_SRC_ALPHA:
428 return BLEND_ONE_MINUS_SRC_ALPHA;
429 break;
430 case GL_DST_ALPHA:
431 return BLEND_DST_ALPHA;
432 break;
433 case GL_ONE_MINUS_DST_ALPHA:
434 return BLEND_ONE_MINUS_DST_ALPHA;
435 break;
436 case GL_SRC_ALPHA_SATURATE:
437 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
438 break;
439 case GL_CONSTANT_COLOR:
440 return BLEND_CONSTANT_COLOR;
441 break;
442 case GL_ONE_MINUS_CONSTANT_COLOR:
443 return BLEND_ONE_MINUS_CONSTANT_COLOR;
444 break;
445 case GL_CONSTANT_ALPHA:
446 return BLEND_CONSTANT_ALPHA;
447 break;
448 case GL_ONE_MINUS_CONSTANT_ALPHA:
449 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
450 break;
451 default:
452 fprintf(stderr, "unknown blend factor %x\n", factor);
453 return (is_src) ? BLEND_ONE : BLEND_ZERO;
454 break;
455 }
456 }
457
458 static void r700SetBlendState(GLcontext * ctx)
459 {
460 context_t *context = R700_CONTEXT(ctx);
461 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
462 int id = 0;
463 uint32_t blend_reg = 0, eqn, eqnA;
464
465 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
466 SETfield(blend_reg,
467 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
468 SETfield(blend_reg,
469 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
470 SETfield(blend_reg,
471 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
472 SETfield(blend_reg,
473 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
474 SETfield(blend_reg,
475 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
476 SETfield(blend_reg,
477 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
478 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
479 r700->CB_BLEND_CONTROL.u32All = blend_reg;
480 else
481 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
482 return;
483 }
484
485 SETfield(blend_reg,
486 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
487 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
488 SETfield(blend_reg,
489 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
490 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
491
492 switch (ctx->Color.BlendEquationRGB) {
493 case GL_FUNC_ADD:
494 eqn = COMB_DST_PLUS_SRC;
495 break;
496 case GL_FUNC_SUBTRACT:
497 eqn = COMB_SRC_MINUS_DST;
498 break;
499 case GL_FUNC_REVERSE_SUBTRACT:
500 eqn = COMB_DST_MINUS_SRC;
501 break;
502 case GL_MIN:
503 eqn = COMB_MIN_DST_SRC;
504 SETfield(blend_reg,
505 BLEND_ONE,
506 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
507 SETfield(blend_reg,
508 BLEND_ONE,
509 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
510 break;
511 case GL_MAX:
512 eqn = COMB_MAX_DST_SRC;
513 SETfield(blend_reg,
514 BLEND_ONE,
515 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
516 SETfield(blend_reg,
517 BLEND_ONE,
518 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
519 break;
520
521 default:
522 fprintf(stderr,
523 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
524 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
525 return;
526 }
527 SETfield(blend_reg,
528 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
529
530 SETfield(blend_reg,
531 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
532 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
533 SETfield(blend_reg,
534 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
535 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
536
537 switch (ctx->Color.BlendEquationA) {
538 case GL_FUNC_ADD:
539 eqnA = COMB_DST_PLUS_SRC;
540 break;
541 case GL_FUNC_SUBTRACT:
542 eqnA = COMB_SRC_MINUS_DST;
543 break;
544 case GL_FUNC_REVERSE_SUBTRACT:
545 eqnA = COMB_DST_MINUS_SRC;
546 break;
547 case GL_MIN:
548 eqnA = COMB_MIN_DST_SRC;
549 SETfield(blend_reg,
550 BLEND_ONE,
551 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
552 SETfield(blend_reg,
553 BLEND_ONE,
554 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
555 break;
556 case GL_MAX:
557 eqnA = COMB_MAX_DST_SRC;
558 SETfield(blend_reg,
559 BLEND_ONE,
560 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
561 SETfield(blend_reg,
562 BLEND_ONE,
563 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
564 break;
565 default:
566 fprintf(stderr,
567 "[%s:%u] Invalid A blend equation (0x%04x).\n",
568 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
569 return;
570 }
571
572 SETfield(blend_reg,
573 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
574
575 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
576
577 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
578 r700->CB_BLEND_CONTROL.u32All = blend_reg;
579 else {
580 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
581 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
582 }
583 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
584 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
585
586 }
587
588 static void r700BlendEquationSeparate(GLcontext * ctx,
589 GLenum modeRGB, GLenum modeA) //-----------------
590 {
591 r700SetBlendState(ctx);
592 }
593
594 static void r700BlendFuncSeparate(GLcontext * ctx,
595 GLenum sfactorRGB, GLenum dfactorRGB,
596 GLenum sfactorA, GLenum dfactorA) //------------------------
597 {
598 r700SetBlendState(ctx);
599 }
600
601 /**
602 * Translate LogicOp enums into hardware representation.
603 */
604 static GLuint translate_logicop(GLenum logicop)
605 {
606 switch (logicop) {
607 case GL_CLEAR:
608 return 0x00;
609 case GL_SET:
610 return 0xff;
611 case GL_COPY:
612 return 0xcc;
613 case GL_COPY_INVERTED:
614 return 0x33;
615 case GL_NOOP:
616 return 0xaa;
617 case GL_INVERT:
618 return 0x55;
619 case GL_AND:
620 return 0x88;
621 case GL_NAND:
622 return 0x77;
623 case GL_OR:
624 return 0xee;
625 case GL_NOR:
626 return 0x11;
627 case GL_XOR:
628 return 0x66;
629 case GL_EQUIV:
630 return 0xaa;
631 case GL_AND_REVERSE:
632 return 0x44;
633 case GL_AND_INVERTED:
634 return 0x22;
635 case GL_OR_REVERSE:
636 return 0xdd;
637 case GL_OR_INVERTED:
638 return 0xbb;
639 default:
640 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
641 return 0xcc;
642 }
643 }
644
645 /**
646 * Used internally to update the r300->hw hardware state to match the
647 * current OpenGL state.
648 */
649 static void r700SetLogicOpState(GLcontext *ctx)
650 {
651 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
652
653 if (RGBA_LOGICOP_ENABLED(ctx))
654 SETfield(r700->CB_COLOR_CONTROL.u32All,
655 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
656 else
657 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
658 }
659
660 /**
661 * Called by Mesa when an application program changes the LogicOp state
662 * via glLogicOp.
663 */
664 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
665 {
666 if (RGBA_LOGICOP_ENABLED(ctx))
667 r700SetLogicOpState(ctx);
668 }
669
670 static void r700UpdateCulling(GLcontext * ctx)
671 {
672 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
673
674 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
675 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
676 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
677
678 if (ctx->Polygon.CullFlag)
679 {
680 switch (ctx->Polygon.CullFaceMode)
681 {
682 case GL_FRONT:
683 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
684 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
685 break;
686 case GL_BACK:
687 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
688 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
689 break;
690 case GL_FRONT_AND_BACK:
691 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
692 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
693 break;
694 default:
695 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
696 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
697 break;
698 }
699 }
700
701 switch (ctx->Polygon.FrontFace)
702 {
703 case GL_CW:
704 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
705 break;
706 case GL_CCW:
707 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
708 break;
709 default:
710 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
711 break;
712 }
713 }
714
715 static void r700UpdateLineStipple(GLcontext * ctx)
716 {
717 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
718 if (ctx->Line.StippleFlag)
719 {
720 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
721 }
722 else
723 {
724 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
725 }
726 }
727
728 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
729 {
730 context_t *context = R700_CONTEXT(ctx);
731
732 switch (cap) {
733 case GL_TEXTURE_1D:
734 case GL_TEXTURE_2D:
735 case GL_TEXTURE_3D:
736 /* empty */
737 break;
738 case GL_FOG:
739 /* empty */
740 break;
741 case GL_ALPHA_TEST:
742 r700SetAlphaState(ctx);
743 break;
744 case GL_COLOR_LOGIC_OP:
745 r700SetLogicOpState(ctx);
746 /* fall-through, because logic op overrides blending */
747 case GL_BLEND:
748 r700SetBlendState(ctx);
749 break;
750 case GL_CLIP_PLANE0:
751 case GL_CLIP_PLANE1:
752 case GL_CLIP_PLANE2:
753 case GL_CLIP_PLANE3:
754 case GL_CLIP_PLANE4:
755 case GL_CLIP_PLANE5:
756 r700SetClipPlaneState(ctx, cap, state);
757 break;
758 case GL_DEPTH_TEST:
759 r700SetDepthState(ctx);
760 break;
761 case GL_STENCIL_TEST:
762 r700SetStencilState(ctx, state);
763 break;
764 case GL_CULL_FACE:
765 r700UpdateCulling(ctx);
766 break;
767 case GL_POLYGON_OFFSET_POINT:
768 case GL_POLYGON_OFFSET_LINE:
769 case GL_POLYGON_OFFSET_FILL:
770 r700SetPolygonOffsetState(ctx, state);
771 break;
772 case GL_SCISSOR_TEST:
773 radeon_firevertices(&context->radeon);
774 context->radeon.state.scissor.enabled = state;
775 radeonUpdateScissor(ctx);
776 break;
777 case GL_LINE_STIPPLE:
778 r700UpdateLineStipple(ctx);
779 break;
780 default:
781 break;
782 }
783
784 }
785
786 /**
787 * Handle glColorMask()
788 */
789 static void r700ColorMask(GLcontext * ctx,
790 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
791 {
792 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
793 unsigned int mask = ((r ? 1 : 0) |
794 (g ? 2 : 0) |
795 (b ? 4 : 0) |
796 (a ? 8 : 0));
797
798 if (mask != r700->CB_SHADER_MASK.u32All)
799 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
800 }
801
802 /**
803 * Change the depth testing function.
804 *
805 * \note Mesa already filters redundant calls to this function.
806 */
807 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
808 {
809 r700SetDepthState(ctx);
810 }
811
812 /**
813 * Enable/Disable depth writing.
814 *
815 * \note Mesa already filters redundant calls to this function.
816 */
817 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
818 {
819 r700SetDepthState(ctx);
820 }
821
822 /**
823 * Change the culling mode.
824 *
825 * \note Mesa already filters redundant calls to this function.
826 */
827 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
828 {
829 r700UpdateCulling(ctx);
830 }
831
832 /* =============================================================
833 * Fog
834 */
835 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
836 {
837 }
838
839 /**
840 * Change the polygon orientation.
841 *
842 * \note Mesa already filters redundant calls to this function.
843 */
844 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
845 {
846 r700UpdateCulling(ctx);
847 r700UpdatePolygonMode(ctx);
848 }
849
850 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
851 {
852 context_t *context = R700_CONTEXT(ctx);
853 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
854
855 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
856 switch (mode) {
857 case GL_FLAT:
858 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
859 break;
860 case GL_SMOOTH:
861 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
862 break;
863 default:
864 return;
865 }
866 }
867
868 /* =============================================================
869 * Point state
870 */
871 static void r700PointSize(GLcontext * ctx, GLfloat size)
872 {
873 context_t *context = R700_CONTEXT(ctx);
874 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
875
876 /* We need to clamp to user defined range here, because
877 * the HW clamping happens only for per vertex point size. */
878 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
879
880 /* same size limits for AA, non-AA points */
881 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
882
883 /* format is 12.4 fixed point */
884 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
885 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
886 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
887 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
888
889 }
890
891 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
892 {
893 context_t *context = R700_CONTEXT(ctx);
894 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
895
896 /* format is 12.4 fixed point */
897 switch (pname) {
898 case GL_POINT_SIZE_MIN:
899 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
900 MIN_SIZE_shift, MIN_SIZE_mask);
901 break;
902 case GL_POINT_SIZE_MAX:
903 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
904 MAX_SIZE_shift, MAX_SIZE_mask);
905 break;
906 case GL_POINT_DISTANCE_ATTENUATION:
907 break;
908 case GL_POINT_FADE_THRESHOLD_SIZE:
909 break;
910 default:
911 break;
912 }
913 }
914
915 static int translate_stencil_func(int func)
916 {
917 switch (func) {
918 case GL_NEVER:
919 return REF_NEVER;
920 case GL_LESS:
921 return REF_LESS;
922 case GL_EQUAL:
923 return REF_EQUAL;
924 case GL_LEQUAL:
925 return REF_LEQUAL;
926 case GL_GREATER:
927 return REF_GREATER;
928 case GL_NOTEQUAL:
929 return REF_NOTEQUAL;
930 case GL_GEQUAL:
931 return REF_GEQUAL;
932 case GL_ALWAYS:
933 return REF_ALWAYS;
934 }
935 return 0;
936 }
937
938 static int translate_stencil_op(int op)
939 {
940 switch (op) {
941 case GL_KEEP:
942 return STENCIL_KEEP;
943 case GL_ZERO:
944 return STENCIL_ZERO;
945 case GL_REPLACE:
946 return STENCIL_REPLACE;
947 case GL_INCR:
948 return STENCIL_INCR_CLAMP;
949 case GL_DECR:
950 return STENCIL_DECR_CLAMP;
951 case GL_INCR_WRAP_EXT:
952 return STENCIL_INCR_WRAP;
953 case GL_DECR_WRAP_EXT:
954 return STENCIL_DECR_WRAP;
955 case GL_INVERT:
956 return STENCIL_INVERT;
957 default:
958 WARN_ONCE("Do not know how to translate stencil op");
959 return STENCIL_KEEP;
960 }
961 return 0;
962 }
963
964 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
965 {
966 context_t *context = R700_CONTEXT(ctx);
967 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
968 GLboolean hw_stencil = GL_FALSE;
969
970 //fixme
971 //r300CatchStencilFallback(ctx);
972
973 if (ctx->DrawBuffer) {
974 struct radeon_renderbuffer *rrbStencil
975 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
976 hw_stencil = (rrbStencil && rrbStencil->bo);
977 }
978
979 if (hw_stencil) {
980 if (state)
981 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
982 else
983 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
984 }
985 }
986
987 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
988 GLenum func, GLint ref, GLuint mask) //---------------------
989 {
990 context_t *context = R700_CONTEXT(ctx);
991 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
992 const unsigned back = ctx->Stencil._BackFace;
993
994 //fixme
995 //r300CatchStencilFallback(ctx);
996
997 //front
998 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
999 STENCILREF_shift, STENCILREF_mask);
1000 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1001 STENCILMASK_shift, STENCILMASK_mask);
1002
1003 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1004 STENCILFUNC_shift, STENCILFUNC_mask);
1005
1006 //back
1007 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1008 STENCILREF_BF_shift, STENCILREF_BF_mask);
1009 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1010 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1011
1012 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1013 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1014
1015 }
1016
1017 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1018 {
1019 context_t *context = R700_CONTEXT(ctx);
1020 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1021 const unsigned back = ctx->Stencil._BackFace;
1022
1023 //fixme
1024 //r300CatchStencilFallback(ctx);
1025
1026 // front
1027 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1028 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1029
1030 // back
1031 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1032 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1033
1034 }
1035
1036 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1037 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1038 {
1039 context_t *context = R700_CONTEXT(ctx);
1040 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1041 const unsigned back = ctx->Stencil._BackFace;
1042
1043 //fixme
1044 //r300CatchStencilFallback(ctx);
1045
1046 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1047 STENCILFAIL_shift, STENCILFAIL_mask);
1048 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1049 STENCILZFAIL_shift, STENCILZFAIL_mask);
1050 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1051 STENCILZPASS_shift, STENCILZPASS_mask);
1052
1053 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1054 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1055 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1056 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1057 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1058 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1059 }
1060
1061 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1062 {
1063 context_t *context = R700_CONTEXT(ctx);
1064 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1065 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1066 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1067 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1068 const GLfloat *v = ctx->Viewport._WindowMap.m;
1069 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1070 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1071 GLfloat y_scale, y_bias;
1072
1073 if (render_to_fbo) {
1074 y_scale = 1.0;
1075 y_bias = 0;
1076 } else {
1077 y_scale = -1.0;
1078 y_bias = yoffset;
1079 }
1080
1081 GLfloat sx = v[MAT_SX];
1082 GLfloat tx = v[MAT_TX] + xoffset;
1083 GLfloat sy = v[MAT_SY] * y_scale;
1084 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1085 GLfloat sz = v[MAT_SZ] * depthScale;
1086 GLfloat tz = v[MAT_TZ] * depthScale;
1087
1088 /* TODO : Need DMA flush as well. */
1089
1090 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1091 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1092
1093 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1094 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1095
1096 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1097 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1098
1099 r700->viewport[id].enabled = GL_TRUE;
1100
1101 r700SetScissor(context);
1102 }
1103
1104
1105 static void r700Viewport(GLcontext * ctx,
1106 GLint x,
1107 GLint y,
1108 GLsizei width,
1109 GLsizei height) //--------------------
1110 {
1111 r700UpdateWindow(ctx, 0);
1112
1113 radeon_viewport(ctx, x, y, width, height);
1114 }
1115
1116 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1117 {
1118 r700UpdateWindow(ctx, 0);
1119 }
1120
1121 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1122 {
1123 context_t *context = R700_CONTEXT(ctx);
1124 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1125 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1126 if (lineWidth > 0xFFFF)
1127 lineWidth = 0xFFFF;
1128 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1129 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1130 }
1131
1132 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1133 {
1134 context_t *context = R700_CONTEXT(ctx);
1135 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1136
1137 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1138 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1139 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1140 }
1141
1142 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1143 {
1144 context_t *context = R700_CONTEXT(ctx);
1145 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1146
1147 if (state) {
1148 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1149 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1150 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1151 } else {
1152 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1153 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1154 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1155 }
1156 }
1157
1158 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1159 {
1160 context_t *context = R700_CONTEXT(ctx);
1161 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1162 GLfloat constant = units;
1163
1164 switch (ctx->Visual.depthBits) {
1165 case 16:
1166 constant *= 4.0;
1167 break;
1168 case 24:
1169 constant *= 2.0;
1170 break;
1171 }
1172
1173 factor *= 12.0;
1174
1175 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1176 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1177 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1178 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1179 }
1180
1181 static void r700UpdatePolygonMode(GLcontext * ctx)
1182 {
1183 context_t *context = R700_CONTEXT(ctx);
1184 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1185
1186 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1187
1188 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1189 if (ctx->Polygon.FrontMode != GL_FILL ||
1190 ctx->Polygon.BackMode != GL_FILL) {
1191 GLenum f, b;
1192
1193 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1194 * correctly by selecting the correct front and back face
1195 */
1196 if (ctx->Polygon.FrontFace == GL_CCW) {
1197 f = ctx->Polygon.FrontMode;
1198 b = ctx->Polygon.BackMode;
1199 } else {
1200 f = ctx->Polygon.BackMode;
1201 b = ctx->Polygon.FrontMode;
1202 }
1203
1204 /* Enable polygon mode */
1205 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1206
1207 switch (f) {
1208 case GL_LINE:
1209 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1210 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1211 break;
1212 case GL_POINT:
1213 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1214 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1215 break;
1216 case GL_FILL:
1217 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1218 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1219 break;
1220 }
1221
1222 switch (b) {
1223 case GL_LINE:
1224 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1225 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1226 break;
1227 case GL_POINT:
1228 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1229 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1230 break;
1231 case GL_FILL:
1232 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1233 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1234 break;
1235 }
1236 }
1237 }
1238
1239 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1240 {
1241 (void)face;
1242 (void)mode;
1243
1244 r700UpdatePolygonMode(ctx);
1245 }
1246
1247 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1248 {
1249 }
1250
1251 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1252 {
1253 context_t *context = R700_CONTEXT(ctx);
1254 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1255 GLint p;
1256 GLint *ip;
1257
1258 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1259 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1260
1261 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1262 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1263 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1264 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1265 }
1266
1267 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1268 {
1269 context_t *context = R700_CONTEXT(ctx);
1270 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1271 GLuint p;
1272
1273 p = cap - GL_CLIP_PLANE0;
1274 if (state) {
1275 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1276 r700->ucp[p].enabled = GL_TRUE;
1277 r700ClipPlane(ctx, cap, NULL);
1278 } else {
1279 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1280 r700->ucp[p].enabled = GL_FALSE;
1281 }
1282 }
1283
1284 void r700SetScissor(context_t *context) //---------------
1285 {
1286 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1287 unsigned x1, y1, x2, y2;
1288 int id = 0;
1289 struct radeon_renderbuffer *rrb;
1290
1291 rrb = radeon_get_colorbuffer(&context->radeon);
1292 if (!rrb || !rrb->bo) {
1293 return;
1294 }
1295 if (context->radeon.state.scissor.enabled) {
1296 x1 = context->radeon.state.scissor.rect.x1;
1297 y1 = context->radeon.state.scissor.rect.y1;
1298 x2 = context->radeon.state.scissor.rect.x2 - 1;
1299 y2 = context->radeon.state.scissor.rect.y2 - 1;
1300 } else {
1301 x1 = rrb->dPriv->x;
1302 y1 = rrb->dPriv->y;
1303 x2 = rrb->dPriv->x + rrb->dPriv->w;
1304 y2 = rrb->dPriv->y + rrb->dPriv->h;
1305 }
1306
1307 /* window */
1308 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1309 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1310 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1311 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1312 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1313
1314 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1315 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1316 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1317 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1318
1319
1320 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1321 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1322 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1323 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1324 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1325 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1326 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1327 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1328
1329 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1330 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1331 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1332 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1333 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1334 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1335
1336 /* more....2d clip */
1337 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1338 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1339 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1340 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1341 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1342 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1343 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1344 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1345 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1346
1347 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1348 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1349 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1350 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1351 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1352 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1353 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1354 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1355 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1356
1357 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1358 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1359 r700->viewport[id].enabled = GL_TRUE;
1360 }
1361
1362 void r700SetRenderTarget(context_t *context, int id)
1363 {
1364 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1365
1366 struct radeon_renderbuffer *rrb;
1367 unsigned int nPitchInPixel;
1368
1369 /* screen/window/view */
1370 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1371
1372 rrb = radeon_get_colorbuffer(&context->radeon);
1373 if (!rrb || !rrb->bo) {
1374 fprintf(stderr, "no rrb\n");
1375 return;
1376 }
1377
1378 /* color buffer */
1379 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1380
1381 nPitchInPixel = rrb->pitch/rrb->cpp;
1382 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1383 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1384 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1385 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1386 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1387 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1388 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1389 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1390 if(4 == rrb->cpp)
1391 {
1392 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1393 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1394 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1395 }
1396 else
1397 {
1398 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1399 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1400 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1401 COMP_SWAP_shift, COMP_SWAP_mask);
1402 }
1403 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1404 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1405 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1406
1407 r700->render_target[id].enabled = GL_TRUE;
1408 }
1409
1410 void r700SetDepthTarget(context_t *context)
1411 {
1412 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1413
1414 struct radeon_renderbuffer *rrb;
1415 unsigned int nPitchInPixel;
1416
1417 /* depth buf */
1418 r700->DB_DEPTH_SIZE.u32All = 0;
1419 r700->DB_DEPTH_BASE.u32All = 0;
1420 r700->DB_DEPTH_INFO.u32All = 0;
1421
1422 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1423 r700->DB_DEPTH_VIEW.u32All = 0;
1424 r700->DB_RENDER_CONTROL.u32All = 0;
1425 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1426 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1427 r700->DB_RENDER_OVERRIDE.u32All = 0;
1428 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1429 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1430 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1431 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1432 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1433
1434 r700->DB_ALPHA_TO_MASK.u32All = 0;
1435 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1436 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1437 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1438 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1439
1440 rrb = radeon_get_depthbuffer(&context->radeon);
1441 if (!rrb)
1442 return;
1443
1444 nPitchInPixel = rrb->pitch/rrb->cpp;
1445
1446 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1447 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1448 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1449 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1450
1451 if(4 == rrb->cpp)
1452 {
1453 switch (GL_CONTEXT(context)->Visual.depthBits)
1454 {
1455 case 16:
1456 case 24:
1457 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1458 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1459 break;
1460 default:
1461 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1462 GL_CONTEXT(context)->Visual.depthBits);
1463 _mesa_exit(-1);
1464 }
1465 }
1466 else
1467 {
1468 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1469 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1470 }
1471 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1472 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1473 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1474 }
1475
1476 static void r700InitSQConfig(GLcontext * ctx)
1477 {
1478 context_t *context = R700_CONTEXT(ctx);
1479 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1480 int ps_prio;
1481 int vs_prio;
1482 int gs_prio;
1483 int es_prio;
1484 int num_ps_gprs;
1485 int num_vs_gprs;
1486 int num_gs_gprs;
1487 int num_es_gprs;
1488 int num_temp_gprs;
1489 int num_ps_threads;
1490 int num_vs_threads;
1491 int num_gs_threads;
1492 int num_es_threads;
1493 int num_ps_stack_entries;
1494 int num_vs_stack_entries;
1495 int num_gs_stack_entries;
1496 int num_es_stack_entries;
1497
1498 // SQ
1499 ps_prio = 0;
1500 vs_prio = 1;
1501 gs_prio = 2;
1502 es_prio = 3;
1503 switch (context->radeon.radeonScreen->chip_family) {
1504 case CHIP_FAMILY_R600:
1505 num_ps_gprs = 192;
1506 num_vs_gprs = 56;
1507 num_temp_gprs = 4;
1508 num_gs_gprs = 0;
1509 num_es_gprs = 0;
1510 num_ps_threads = 136;
1511 num_vs_threads = 48;
1512 num_gs_threads = 4;
1513 num_es_threads = 4;
1514 num_ps_stack_entries = 128;
1515 num_vs_stack_entries = 128;
1516 num_gs_stack_entries = 0;
1517 num_es_stack_entries = 0;
1518 break;
1519 case CHIP_FAMILY_RV630:
1520 case CHIP_FAMILY_RV635:
1521 num_ps_gprs = 84;
1522 num_vs_gprs = 36;
1523 num_temp_gprs = 4;
1524 num_gs_gprs = 0;
1525 num_es_gprs = 0;
1526 num_ps_threads = 144;
1527 num_vs_threads = 40;
1528 num_gs_threads = 4;
1529 num_es_threads = 4;
1530 num_ps_stack_entries = 40;
1531 num_vs_stack_entries = 40;
1532 num_gs_stack_entries = 32;
1533 num_es_stack_entries = 16;
1534 break;
1535 case CHIP_FAMILY_RV610:
1536 case CHIP_FAMILY_RV620:
1537 case CHIP_FAMILY_RS780:
1538 default:
1539 num_ps_gprs = 84;
1540 num_vs_gprs = 36;
1541 num_temp_gprs = 4;
1542 num_gs_gprs = 0;
1543 num_es_gprs = 0;
1544 num_ps_threads = 136;
1545 num_vs_threads = 48;
1546 num_gs_threads = 4;
1547 num_es_threads = 4;
1548 num_ps_stack_entries = 40;
1549 num_vs_stack_entries = 40;
1550 num_gs_stack_entries = 32;
1551 num_es_stack_entries = 16;
1552 break;
1553 case CHIP_FAMILY_RV670:
1554 num_ps_gprs = 144;
1555 num_vs_gprs = 40;
1556 num_temp_gprs = 4;
1557 num_gs_gprs = 0;
1558 num_es_gprs = 0;
1559 num_ps_threads = 136;
1560 num_vs_threads = 48;
1561 num_gs_threads = 4;
1562 num_es_threads = 4;
1563 num_ps_stack_entries = 40;
1564 num_vs_stack_entries = 40;
1565 num_gs_stack_entries = 32;
1566 num_es_stack_entries = 16;
1567 break;
1568 case CHIP_FAMILY_RV770:
1569 num_ps_gprs = 192;
1570 num_vs_gprs = 56;
1571 num_temp_gprs = 4;
1572 num_gs_gprs = 0;
1573 num_es_gprs = 0;
1574 num_ps_threads = 188;
1575 num_vs_threads = 60;
1576 num_gs_threads = 0;
1577 num_es_threads = 0;
1578 num_ps_stack_entries = 256;
1579 num_vs_stack_entries = 256;
1580 num_gs_stack_entries = 0;
1581 num_es_stack_entries = 0;
1582 break;
1583 case CHIP_FAMILY_RV730:
1584 case CHIP_FAMILY_RV740:
1585 num_ps_gprs = 84;
1586 num_vs_gprs = 36;
1587 num_temp_gprs = 4;
1588 num_gs_gprs = 0;
1589 num_es_gprs = 0;
1590 num_ps_threads = 188;
1591 num_vs_threads = 60;
1592 num_gs_threads = 0;
1593 num_es_threads = 0;
1594 num_ps_stack_entries = 128;
1595 num_vs_stack_entries = 128;
1596 num_gs_stack_entries = 0;
1597 num_es_stack_entries = 0;
1598 break;
1599 case CHIP_FAMILY_RV710:
1600 num_ps_gprs = 192;
1601 num_vs_gprs = 56;
1602 num_temp_gprs = 4;
1603 num_gs_gprs = 0;
1604 num_es_gprs = 0;
1605 num_ps_threads = 144;
1606 num_vs_threads = 48;
1607 num_gs_threads = 0;
1608 num_es_threads = 0;
1609 num_ps_stack_entries = 128;
1610 num_vs_stack_entries = 128;
1611 num_gs_stack_entries = 0;
1612 num_es_stack_entries = 0;
1613 break;
1614 }
1615
1616 r700->sq_config.SQ_CONFIG.u32All = 0;
1617 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1618 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1619 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1620 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1621 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1622 else
1623 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1624 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1625 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1626 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1627 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1628 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1629 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1630
1631 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1632 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1633 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1634 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1635 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1636
1637 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1638 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1639 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1640
1641 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1642 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1643 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1644 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1645 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1646 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1647 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1648 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1649 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1650
1651 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1652 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1653 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1654 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1655 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1656
1657 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1658 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1659 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1660 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1661 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1662
1663 }
1664
1665 /**
1666 * Calculate initial hardware state and register state functions.
1667 * Assumes that the command buffer and state atoms have been
1668 * initialized already.
1669 */
1670 void r700InitState(GLcontext * ctx) //-------------------
1671 {
1672 context_t *context = R700_CONTEXT(ctx);
1673 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1674
1675 radeon_firevertices(&context->radeon);
1676
1677 r700->TA_CNTL_AUX.u32All = 0;
1678 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1679 r700->VC_ENHANCE.u32All = 0;
1680 r700->DB_WATERMARKS.u32All = 0;
1681 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1682 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1683 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1684 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1685 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1686 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1687 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1688 r700->DB_DEBUG.u32All = 0x82000000;
1689 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1690 } else {
1691 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1692 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1693 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1694 }
1695
1696 /* Turn off vgt reuse */
1697 r700->VGT_REUSE_OFF.u32All = 0;
1698 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1699
1700 /* Specify offsetting and clamp values for vertices */
1701 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1702 r700->VGT_MIN_VTX_INDX.u32All = 0;
1703 r700->VGT_INDX_OFFSET.u32All = 0;
1704
1705 /* default shader connections. */
1706 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1707 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1708
1709 r700->SPI_THREAD_GROUPING.u32All = 0;
1710 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1711 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1712
1713 /* screen */
1714 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1715
1716 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1717 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1718 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1719 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1720 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1721 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1722
1723 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1724 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1725 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1726
1727 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1728 r700->PA_SC_EDGERULE.u32All = 0;
1729 else
1730 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1731
1732 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1733 r700->PA_SC_MODE_CNTL.u32All = 0;
1734 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1735 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1736 } else {
1737 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1738 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1739 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1740 }
1741
1742 /* Do scale XY and Z by 1/W0. */
1743 r700->bEnablePerspective = GL_TRUE;
1744 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1745 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1746 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1747
1748 /* Enable viewport scaling for all three axis */
1749 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1750 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1751 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1752 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1753 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1754 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1755
1756 /* GL uses last vtx for flat shading components */
1757 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1758
1759 /* Set up vertex control */
1760 r700->PA_SU_VTX_CNTL.u32All = 0;
1761 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1762 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1763 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1764 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1765
1766 /* to 1.0 = no guard band */
1767 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1768 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1769 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1770 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1771
1772 /* Enable all samples for multi-sample anti-aliasing */
1773 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1774 /* Turn off AA */
1775 r700->PA_SC_AA_CONFIG.u32All = 0;
1776
1777 r700->SX_MISC.u32All = 0;
1778
1779 r700InitSQConfig(ctx);
1780
1781 r700ColorMask(ctx,
1782 ctx->Color.ColorMask[RCOMP],
1783 ctx->Color.ColorMask[GCOMP],
1784 ctx->Color.ColorMask[BCOMP],
1785 ctx->Color.ColorMask[ACOMP]);
1786
1787 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1788 r700DepthMask(ctx, ctx->Depth.Mask);
1789 r700DepthFunc(ctx, ctx->Depth.Func);
1790 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1791
1792 /* stencil */
1793 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1794 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1795 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1796 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1797 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1798 ctx->Stencil.ZFailFunc[0],
1799 ctx->Stencil.ZPassFunc[0]);
1800
1801 r700UpdateCulling(ctx);
1802
1803 r700SetBlendState(ctx);
1804 r700SetLogicOpState(ctx);
1805
1806 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1807 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1808
1809 r700PointSize(ctx, 1.0);
1810
1811 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1812 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1813
1814 r700LineWidth(ctx, 1.0);
1815
1816 r700->PA_SC_LINE_CNTL.u32All = 0;
1817 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1818 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1819
1820 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1821 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1822 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1823 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1824 ctx->Polygon.OffsetUnits);
1825 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1826 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1827 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1828
1829 /* CB */
1830 r700BlendColor(ctx, ctx->Color.BlendColor);
1831
1832 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1833 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1834 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1835 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1836 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1837 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1838 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1839
1840 /* Disable color compares */
1841 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1842 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1843 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1844 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1845 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1846 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1847
1848 /* Zero out source */
1849 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1850
1851 /* Put a compare color in for error checking */
1852 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1853
1854 /* Set up color compare mask */
1855 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1856
1857 context->radeon.hw.all_dirty = GL_TRUE;
1858
1859 }
1860
1861 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1862 {
1863 functions->UpdateState = r700InvalidateState;
1864 functions->AlphaFunc = r700AlphaFunc;
1865 functions->BlendColor = r700BlendColor;
1866 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1867 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1868 functions->Enable = r700Enable;
1869 functions->ColorMask = r700ColorMask;
1870 functions->DepthFunc = r700DepthFunc;
1871 functions->DepthMask = r700DepthMask;
1872 functions->CullFace = r700CullFace;
1873 functions->Fogfv = r700Fogfv;
1874 functions->FrontFace = r700FrontFace;
1875 functions->ShadeModel = r700ShadeModel;
1876 functions->LogicOpcode = r700LogicOpcode;
1877
1878 /* ARB_point_parameters */
1879 functions->PointParameterfv = r700PointParameter;
1880
1881 /* Stencil related */
1882 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1883 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1884 functions->StencilOpSeparate = r700StencilOpSeparate;
1885
1886 /* Viewport related */
1887 functions->Viewport = r700Viewport;
1888 functions->DepthRange = r700DepthRange;
1889 functions->PointSize = r700PointSize;
1890 functions->LineWidth = r700LineWidth;
1891 functions->LineStipple = r700LineStipple;
1892
1893 functions->PolygonOffset = r700PolygonOffset;
1894 functions->PolygonMode = r700PolygonMode;
1895
1896 functions->RenderMode = r700RenderMode;
1897
1898 functions->ClipPlane = r700ClipPlane;
1899
1900 functions->Scissor = radeonScissor;
1901
1902 functions->DrawBuffer = radeonDrawBuffer;
1903 functions->ReadBuffer = radeonReadBuffer;
1904
1905 }
1906