src/mesa/drivers/dri/radeon/radeon_blit.c

   1 /*
   2  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "radeon_context.h"
  30 #include "radeon_blit.h"
  31
  32 static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
  33                                   int reg, int count)
  34 {
  35     if (count)
  36             return CP_PACKET0(reg, count - 1);
  37     return CP_PACKET2;
  38 }
  39
  40 /* common formats supported as both textures and render targets */
  41 static unsigned is_blit_supported(gl_format mesa_format)
  42 {
  43     /* XXX others?  BE/LE? */
  44     switch (mesa_format) {
  45     case MESA_FORMAT_ARGB8888:
  46     case MESA_FORMAT_XRGB8888:
  47     case MESA_FORMAT_RGB565:
  48     case MESA_FORMAT_ARGB4444:
  49     case MESA_FORMAT_ARGB1555:
  50     case MESA_FORMAT_A8:
  51             break;
  52     default:
  53             return 0;
  54     }
  55
  56     /* ??? */
  57     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  58             return 0;
  59
  60     return 1;
  61 }
  62
  63 static inline void emit_vtx_state(struct r100_context *r100)
  64 {
  65     BATCH_LOCALS(&r100->radeon);
  66
  67     BEGIN_BATCH(8);
  68     if (r100->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
  69             OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0);
  70     } else {
  71             OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
  72
  73     }
  74     OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
  75                                            RADEON_TEX1_W_ROUTING_USE_W0));
  76     OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0);
  77     OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
  78                                       RADEON_BFACE_SOLID |
  79                                       RADEON_FFACE_SOLID |
  80                                       RADEON_VTX_PIX_CENTER_OGL |
  81                                       RADEON_ROUND_MODE_ROUND |
  82                                       RADEON_ROUND_PREC_4TH_PIX));
  83     END_BATCH();
  84 }
  85
  86 static void inline emit_tx_setup(struct r100_context *r100,
  87                                  gl_format mesa_format,
  88                                  struct radeon_bo *bo,
  89                                  intptr_t offset,
  90                                  unsigned width,
  91                                  unsigned height,
  92                                  unsigned pitch)
  93 {
  94     uint32_t txformat = RADEON_TXFORMAT_NON_POWER2;
  95     BATCH_LOCALS(&r100->radeon);
  96
  97     assert(width <= 2047);
  98     assert(height <= 2047);
  99     assert(offset % 32 == 0);
 100
 101     /* XXX others?  BE/LE? */
 102     switch (mesa_format) {
 103     case MESA_FORMAT_ARGB8888:
 104             txformat |= RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 105             break;
 106     case MESA_FORMAT_XRGB8888:
 107             txformat |= RADEON_TXFORMAT_ARGB8888;
 108             break;
 109     case MESA_FORMAT_RGB565:
 110             txformat |= RADEON_TXFORMAT_RGB565;
 111             break;
 112     case MESA_FORMAT_ARGB4444:
 113             txformat |= RADEON_TXFORMAT_ARGB4444 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 114             break;
 115     case MESA_FORMAT_ARGB1555:
 116             txformat |= RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 117             break;
 118     case MESA_FORMAT_A8:
 119             txformat |= RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
 120             break;
 121     default:
 122             break;
 123     }
 124
 125     BEGIN_BATCH(18);
 126     OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
 127     OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO |
 128                                             RADEON_COLOR_ARG_B_ZERO |
 129                                             RADEON_COLOR_ARG_C_T0_COLOR |
 130                                             RADEON_BLEND_CTL_ADD |
 131                                             RADEON_CLAMP_TX));
 132     OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO |
 133                                             RADEON_ALPHA_ARG_B_ZERO |
 134                                             RADEON_ALPHA_ARG_C_T0_ALPHA |
 135                                             RADEON_BLEND_CTL_ADD |
 136                                             RADEON_CLAMP_TX));
 137     OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST |
 138                                             RADEON_CLAMP_T_CLAMP_LAST |
 139                                             RADEON_MAG_FILTER_NEAREST |
 140                                             RADEON_MIN_FILTER_NEAREST));
 141     OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat);
 142     OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
 143                                             ((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
 144     OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
 145
 146     OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1);
 147     OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 148
 149     END_BATCH();
 150 }
 151
 152 static inline void emit_cb_setup(struct r100_context *r100,
 153                                  struct radeon_bo *bo,
 154                                  intptr_t offset,
 155                                  gl_format mesa_format,
 156                                  unsigned pitch,
 157                                  unsigned width,
 158                                  unsigned height)
 159 {
 160     uint32_t dst_pitch = pitch;
 161     uint32_t dst_format = 0;
 162     BATCH_LOCALS(&r100->radeon);
 163
 164     /* XXX others?  BE/LE? */
 165     switch (mesa_format) {
 166     case MESA_FORMAT_ARGB8888:
 167     case MESA_FORMAT_XRGB8888:
 168             dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 169             break;
 170     case MESA_FORMAT_RGB565:
 171             dst_format = RADEON_COLOR_FORMAT_RGB565;
 172             break;
 173     case MESA_FORMAT_ARGB4444:
 174             dst_format = RADEON_COLOR_FORMAT_ARGB4444;
 175             break;
 176     case MESA_FORMAT_ARGB1555:
 177             dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 178             break;
 179     case MESA_FORMAT_A8:
 180             dst_format = RADEON_COLOR_FORMAT_RGB8;
 181             break;
 182     default:
 183             break;
 184     }
 185
 186     BEGIN_BATCH_NO_AUTOSTATE(18);
 187     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
 188     OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
 189                                               (height << RADEON_RE_HEIGHT_SHIFT)));
 190     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
 191     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
 192     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 193
 194     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
 195     OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 196     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
 197     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 198
 199     END_BATCH();
 200 }
 201
 202 static GLboolean validate_buffers(struct r100_context *r100,
 203                                   struct radeon_bo *src_bo,
 204                                   struct radeon_bo *dst_bo)
 205 {
 206     int ret;
 207     radeon_cs_space_add_persistent_bo(r100->radeon.cmdbuf.cs,
 208                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 209
 210     radeon_cs_space_add_persistent_bo(r100->radeon.cmdbuf.cs,
 211                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 212
 213     ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs,
 214                                         first_elem(&r100->radeon.dma.reserved)->bo,
 215                                         RADEON_GEM_DOMAIN_GTT, 0);
 216     if (ret)
 217         return GL_FALSE;
 218
 219     return GL_TRUE;
 220 }
 221
 222 /**
 223  * Calculate texcoords for given image region.
 224  * Output values are [minx, maxx, miny, maxy]
 225  */
 226 static inline void calc_tex_coords(float img_width, float img_height,
 227                                    float x, float y,
 228                                    float reg_width, float reg_height,
 229                                    unsigned flip_y, float *buf)
 230 {
 231     buf[0] = x / img_width;
 232     buf[1] = buf[0] + reg_width / img_width;
 233     buf[2] = y / img_height;
 234     buf[3] = buf[2] + reg_height / img_height;
 235     if (flip_y)
 236     {
 237         buf[2] = 1.0 - buf[2];
 238         buf[3] = 1.0 - buf[3];
 239     }
 240 }
 241
 242 static inline void emit_draw_packet(struct r100_context *r100,
 243                                     unsigned src_width, unsigned src_height,
 244                                     unsigned src_x_offset, unsigned src_y_offset,
 245                                     unsigned dst_x_offset, unsigned dst_y_offset,
 246                                     unsigned reg_width, unsigned reg_height,
 247                                     unsigned flip_y)
 248 {
 249     float texcoords[4];
 250     float verts[12];
 251     BATCH_LOCALS(&r100->radeon);
 252
 253     calc_tex_coords(src_width, src_height,
 254                     src_x_offset, src_y_offset,
 255                     reg_width, reg_height,
 256                     flip_y, texcoords);
 257
 258     verts[0] = dst_x_offset;
 259     verts[1] = dst_y_offset + reg_height;
 260     verts[2] = texcoords[0];
 261     verts[3] = texcoords[3];
 262
 263     verts[4] = dst_x_offset + reg_width;
 264     verts[5] = dst_y_offset + reg_height;
 265     verts[6] = texcoords[1];
 266     verts[7] = texcoords[3];
 267
 268     verts[8] = dst_x_offset + reg_width;
 269     verts[9] = dst_y_offset;
 270     verts[10] = texcoords[1];
 271     verts[11] = texcoords[2];
 272
 273     BEGIN_BATCH(15);
 274     OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD | (13 << 16));
 275     OUT_BATCH(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0);
 276     OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 277               RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
 278               RADEON_CP_VC_CNTL_MAOS_ENABLE |
 279               RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 280               (3 << 16));
 281     OUT_BATCH_TABLE(verts, 12);
 282     END_BATCH();
 283 }
 284
 285 /**
 286  * Copy a region of [@a width x @a height] pixels from source buffer
 287  * to destination buffer.
 288  * @param[in] r100 r100 context
 289  * @param[in] src_bo source radeon buffer object
 290  * @param[in] src_offset offset of the source image in the @a src_bo
 291  * @param[in] src_mesaformat source image format
 292  * @param[in] src_pitch aligned source image width
 293  * @param[in] src_width source image width
 294  * @param[in] src_height source image height
 295  * @param[in] src_x_offset x offset in the source image
 296  * @param[in] src_y_offset y offset in the source image
 297  * @param[in] dst_bo destination radeon buffer object
 298  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 299  * @param[in] dst_mesaformat destination image format
 300  * @param[in] dst_pitch aligned destination image width
 301  * @param[in] dst_width destination image width
 302  * @param[in] dst_height destination image height
 303  * @param[in] dst_x_offset x offset in the destination image
 304  * @param[in] dst_y_offset y offset in the destination image
 305  * @param[in] width region width
 306  * @param[in] height region height
 307  * @param[in] flip_y set if y coords of the source image need to be flipped
 308  */
 309 unsigned r100_blit(GLcontext *ctx,
 310                    struct radeon_bo *src_bo,
 311                    intptr_t src_offset,
 312                    gl_format src_mesaformat,
 313                    unsigned src_pitch,
 314                    unsigned src_width,
 315                    unsigned src_height,
 316                    unsigned src_x_offset,
 317                    unsigned src_y_offset,
 318                    struct radeon_bo *dst_bo,
 319                    intptr_t dst_offset,
 320                    gl_format dst_mesaformat,
 321                    unsigned dst_pitch,
 322                    unsigned dst_width,
 323                    unsigned dst_height,
 324                    unsigned dst_x_offset,
 325                    unsigned dst_y_offset,
 326                    unsigned reg_width,
 327                    unsigned reg_height,
 328                    unsigned flip_y)
 329 {
 330     struct r100_context *r100 = R100_CONTEXT(ctx);
 331
 332     if (!is_blit_supported(dst_mesaformat))
 333         return GL_FALSE;
 334
 335     /* Make sure that colorbuffer has even width - hw limitation */
 336     if (dst_pitch % 2 > 0)
 337         ++dst_pitch;
 338
 339     /* Rendering to small buffer doesn't work.
 340      * Looks like a hw limitation.
 341      */
 342     if (dst_pitch < 32)
 343         return GL_FALSE;
 344
 345     /* Need to clamp the region size to make sure
 346      * we don't read outside of the source buffer
 347      * or write outside of the destination buffer.
 348      */
 349     if (reg_width + src_x_offset > src_width)
 350         reg_width = src_width - src_x_offset;
 351     if (reg_height + src_y_offset > src_height)
 352         reg_height = src_height - src_y_offset;
 353     if (reg_width + dst_x_offset > dst_width)
 354         reg_width = dst_width - dst_x_offset;
 355     if (reg_height + dst_y_offset > dst_height)
 356         reg_height = dst_height - dst_y_offset;
 357
 358     if (src_bo == dst_bo) {
 359         return GL_FALSE;
 360     }
 361
 362     if (src_offset % 32 || dst_offset % 32) {
 363         return GL_FALSE;
 364     }
 365
 366     if (0) {
 367         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 368                 "offset [%d x %d], format %s, bo %p\n",
 369                 src_width, src_height, src_pitch,
 370                 src_x_offset, src_y_offset,
 371                 _mesa_get_format_name(src_mesaformat),
 372                 src_bo);
 373         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 374                 dst_pitch, dst_x_offset, dst_y_offset,
 375                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 376         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 377     }
 378
 379     /* Flush is needed to make sure that source buffer has correct data */
 380     radeonFlush(ctx);
 381
 382     rcommonEnsureCmdBufSpace(&r100->radeon, 59, __FUNCTION__);
 383
 384     if (!validate_buffers(r100, src_bo, dst_bo))
 385         return GL_FALSE;
 386
 387     /* 8 */
 388     emit_vtx_state(r100);
 389     /* 18 */
 390     emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 391     /* 18 */
 392     emit_cb_setup(r100, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 393     /* 15 */
 394     emit_draw_packet(r100, src_width, src_height,
 395                      src_x_offset, src_y_offset,
 396                      dst_x_offset, dst_y_offset,
 397                      reg_width, reg_height,
 398                      flip_y);
 399
 400     radeonFlush(ctx);
 401
 402     return GL_TRUE;
 403 }