src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_debug.h"
  12 #include "radeon_screen.h"
  13 #include "radeon_drm.h"
  14 #include "dri_util.h"
  15 #include "tnl/t_vertex.h"
  16
  17 #include "dri_metaops.h"
  18 struct radeon_context;
  19
  20 #include "radeon_bocs_wrapper.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct gl_renderbuffer base;
  84         struct radeon_bo *bo;
  85         unsigned int cpp;
  86         /* unsigned int offset; */
  87         unsigned int pitch;
  88
  89         uint32_t draw_offset; /* FBO */
  90         /* boo Xorg 6.8.2 compat */
  91         int has_surface;
  92
  93         GLuint pf_pending;  /**< sequence number of pending flip */
  94         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  95         __DRIdrawable *dPriv;
  96
  97         /* r6xx+ tiling */
  98         GLuint tile_config;
  99         GLint group_bytes;
 100         GLint num_channels;
 101         GLint num_banks;
 102         GLint r7xx_bank_op;
 103 };
 104
 105 struct radeon_framebuffer
 106 {
 107         struct gl_framebuffer base;
 108
 109         struct radeon_renderbuffer *color_rb[2];
 110
 111         GLuint vbl_waited;
 112
 113         /* buffer swap */
 114         int64_t swap_ust;
 115         int64_t swap_missed_ust;
 116
 117         GLuint swap_count;
 118         GLuint swap_missed_count;
 119
 120         /* Drawable page flipping state */
 121         GLboolean pf_active;
 122         GLint pf_current_page;
 123         GLint pf_num_pages;
 124
 125 };
 126
 127
 128 struct radeon_colorbuffer_state {
 129         GLuint clear;
 130         int roundEnable;
 131         struct gl_renderbuffer *rb;
 132         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 133 };
 134
 135 struct radeon_depthbuffer_state {
 136         GLuint clear;
 137         struct gl_renderbuffer *rb;
 138 };
 139
 140 struct radeon_scissor_state {
 141         drm_clip_rect_t rect;
 142         GLboolean enabled;
 143
 144         GLuint numClipRects;    /* Cliprects active */
 145         GLuint numAllocedClipRects;     /* Cliprects available */
 146         drm_clip_rect_t *pClipRects;
 147 };
 148
 149 struct radeon_stencilbuffer_state {
 150         GLuint clear;           /* rb3d_stencilrefmask value */
 151 };
 152
 153 struct radeon_state_atom {
 154         struct radeon_state_atom *next, *prev;
 155         const char *name;       /* for debug */
 156         int cmd_size;           /* size in bytes */
 157         GLuint idx;
 158         GLuint is_tcl;
 159         GLuint *cmd;            /* one or more cmd's */
 160         GLuint *lastcmd;                /* one or more cmd's */
 161         GLboolean dirty;        /* dirty-mark in emit_state_list */
 162         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 163         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 164 };
 165
 166 struct radeon_hw_state {
 167         /* Head of the linked list of state atoms. */
 168         struct radeon_state_atom atomlist;
 169         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 170         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 171         GLboolean is_dirty, all_dirty;
 172 };
 173
 174
 175 /* Texture related */
 176 typedef struct _radeon_texture_image radeon_texture_image;
 177
 178 struct _radeon_texture_image {
 179         struct gl_texture_image base;
 180
 181         /**
 182          * If mt != 0, the image is stored in hardware format in the
 183          * given mipmap tree. In this case, base.Data may point into the
 184          * mapping of the buffer object that contains the mipmap tree.
 185          *
 186          * If mt == 0, the image is stored in normal memory pointed to
 187          * by base.Data.
 188          */
 189         struct _radeon_mipmap_tree *mt;
 190         struct radeon_bo *bo;
 191
 192         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 193         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 194 };
 195
 196
 197 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 198 {
 199         return (radeon_texture_image*)image;
 200 }
 201
 202
 203 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 204
 205 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 206
 207 /* Texture object in locally shared texture space.
 208  */
 209 struct radeon_tex_obj {
 210         struct gl_texture_object base;
 211         struct _radeon_mipmap_tree *mt;
 212
 213         /**
 214          * This is true if we've verified that the mipmap tree above is complete
 215          * and so on.
 216          */
 217         GLboolean validated;
 218         /* Minimum LOD to be used during rendering */
 219         unsigned minLod;
 220         /* Miximum LOD to be used during rendering */
 221         unsigned maxLod;
 222
 223         GLuint override_offset;
 224         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 225         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 226         struct radeon_bo *bo;
 227
 228         GLuint pp_txfilter;     /* hardware register values */
 229         GLuint pp_txformat;
 230         GLuint pp_txformat_x;
 231         GLuint pp_txsize;       /* npot only */
 232         GLuint pp_txpitch;      /* npot only */
 233         GLuint pp_border_color;
 234         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 235
 236         GLuint pp_txfilter_1;   /*  r300 */
 237
 238         /* r700 texture states */
 239         GLuint SQ_TEX_RESOURCE0;
 240         GLuint SQ_TEX_RESOURCE1;
 241         GLuint SQ_TEX_RESOURCE2;
 242         GLuint SQ_TEX_RESOURCE3;
 243         GLuint SQ_TEX_RESOURCE4;
 244         GLuint SQ_TEX_RESOURCE5;
 245         GLuint SQ_TEX_RESOURCE6;
 246
 247     GLuint SQ_TEX_RESOURCE7;
 248
 249         GLuint SQ_TEX_SAMPLER0;
 250         GLuint SQ_TEX_SAMPLER1;
 251         GLuint SQ_TEX_SAMPLER2;
 252
 253         GLuint TD_PS_SAMPLER0_BORDER_RED;
 254         GLuint TD_PS_SAMPLER0_BORDER_GREEN;
 255         GLuint TD_PS_SAMPLER0_BORDER_BLUE;
 256         GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
 257
 258         GLboolean border_fallback;
 259
 260
 261 };
 262
 263 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 264 {
 265         return (radeonTexObj*)texObj;
 266 }
 267
 268 /* occlusion query */
 269 struct radeon_query_object {
 270         struct gl_query_object Base;
 271         struct radeon_bo *bo;
 272         int curr_offset;
 273         GLboolean emitted_begin;
 274
 275         /* Double linked list of not flushed query objects */
 276         struct radeon_query_object *prev, *next;
 277 };
 278
 279 /* Need refcounting on dma buffers:
 280  */
 281 struct radeon_dma_buffer {
 282         int refcount;           /* the number of retained regions in buf */
 283         drmBufPtr buf;
 284 };
 285
 286 struct radeon_aos {
 287         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 288         int offset; /** Offset into buffer object, in bytes */
 289         int components; /** Number of components per vertex */
 290         int stride; /** Stride in dwords (may be 0 for repeating) */
 291         int count; /** Number of vertices */
 292 };
 293
 294 #define DMA_BO_FREE_TIME 100
 295
 296 struct radeon_dma_bo {
 297   struct radeon_dma_bo *next, *prev;
 298   struct radeon_bo *bo;
 299   int expire_counter;
 300 };
 301
 302 struct radeon_dma {
 303         /* Active dma region.  Allocations for vertices and retained
 304          * regions come from here.  Also used for emitting random vertices,
 305          * these may be flushed by calling flush_current();
 306          */
 307         struct radeon_dma_bo free;
 308         struct radeon_dma_bo wait;
 309         struct radeon_dma_bo reserved;
 310         size_t current_used; /** Number of bytes allocated and forgotten about */
 311         size_t current_vertexptr; /** End of active vertex region */
 312         size_t minimum_size;
 313
 314         /**
 315          * If current_vertexptr != current_used then flush must be non-zero.
 316          * flush must be called before non-active vertex allocations can be
 317          * performed.
 318          */
 319         void (*flush) (GLcontext *);
 320 };
 321
 322 /* radeon_swtcl.c
 323  */
 324 struct radeon_swtcl_info {
 325
 326         GLuint RenderIndex;
 327         GLuint vertex_size;
 328         GLubyte *verts;
 329
 330         /* Fallback rasterization functions
 331          */
 332         GLuint hw_primitive;
 333         GLenum render_primitive;
 334         GLuint numverts;
 335
 336         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 337         GLuint vertex_attr_count;
 338
 339         GLuint emit_prediction;
 340         struct radeon_bo *bo;
 341 };
 342
 343 #define RADEON_MAX_AOS_ARRAYS           16
 344 struct radeon_tcl_info {
 345         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 346         GLuint aos_count;
 347         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 348         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 349 };
 350
 351 struct radeon_ioctl {
 352         GLuint vertex_offset;
 353         GLuint vertex_max;
 354         struct radeon_bo *bo;
 355         GLuint vertex_size;
 356 };
 357
 358 #define RADEON_MAX_PRIMS 64
 359
 360 struct radeon_prim {
 361         GLuint start;
 362         GLuint end;
 363         GLuint prim;
 364 };
 365
 366 static INLINE GLuint radeonPackColor(GLuint cpp,
 367                                      GLubyte r, GLubyte g,
 368                                      GLubyte b, GLubyte a)
 369 {
 370         switch (cpp) {
 371         case 2:
 372                 return PACK_COLOR_565(r, g, b);
 373         case 4:
 374                 return PACK_COLOR_8888(a, r, g, b);
 375         default:
 376                 return 0;
 377         }
 378 }
 379
 380 #define MAX_CMD_BUF_SZ (16*1024)
 381
 382 #define MAX_DMA_BUF_SZ (64*1024)
 383
 384 struct radeon_store {
 385         GLuint statenr;
 386         GLuint primnr;
 387         char cmd_buf[MAX_CMD_BUF_SZ];
 388         int cmd_used;
 389         int elts_start;
 390 };
 391
 392 struct radeon_dri_mirror {
 393         __DRIcontext *context;  /* DRI context */
 394         __DRIscreen *screen;    /* DRI screen */
 395
 396         drm_context_t hwContext;
 397         drm_hw_lock_t *hwLock;
 398         int hwLockCount;
 399         int fd;
 400         int drmMinor;
 401 };
 402
 403 typedef void (*radeon_tri_func) (radeonContextPtr,
 404                                  radeonVertex *,
 405                                  radeonVertex *, radeonVertex *);
 406
 407 typedef void (*radeon_line_func) (radeonContextPtr,
 408                                   radeonVertex *, radeonVertex *);
 409
 410 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 411
 412 #define RADEON_MAX_BOS 32
 413 struct radeon_state {
 414         struct radeon_colorbuffer_state color;
 415         struct radeon_depthbuffer_state depth;
 416         struct radeon_scissor_state scissor;
 417         struct radeon_stencilbuffer_state stencil;
 418 };
 419
 420 /**
 421  * This structure holds the command buffer while it is being constructed.
 422  *
 423  * The first batch of commands in the buffer is always the state that needs
 424  * to be re-emitted when the context is lost. This batch can be skipped
 425  * otherwise.
 426  */
 427 struct radeon_cmdbuf {
 428         struct radeon_cs_manager    *csm;
 429         struct radeon_cs            *cs;
 430         int size; /** # of dwords total */
 431         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 432 };
 433
 434 struct radeon_context {
 435    GLcontext *glCtx;
 436    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 437
 438    /* Texture object bookkeeping
 439     */
 440    int                   texture_depth;
 441    float                 initialMaxAnisotropy;
 442    uint32_t              texture_row_align;
 443    uint32_t              texture_rect_row_align;
 444    uint32_t              texture_compressed_row_align;
 445
 446   struct radeon_dma dma;
 447   struct radeon_hw_state hw;
 448    /* Rasterization and vertex state:
 449     */
 450    GLuint TclFallback;
 451    GLuint Fallback;
 452    GLuint NewGLState;
 453    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 454
 455    /* Drawable, cliprect and scissor information */
 456    GLuint numClipRects; /* Cliprects for the draw buffer */
 457    drm_clip_rect_t *pClipRects;
 458    unsigned int lastStamp;
 459    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 460
 461    /* Mirrors of some DRI state */
 462    struct radeon_dri_mirror dri;
 463
 464    /* Busy waiting */
 465    GLuint do_usleeps;
 466    GLuint do_irqs;
 467    GLuint irqsEmitted;
 468    drm_radeon_irq_wait_t iw;
 469
 470    /* Derived state - for r300 only */
 471    struct radeon_state state;
 472
 473    struct radeon_swtcl_info swtcl;
 474    struct radeon_tcl_info tcl;
 475    /* Configuration cache
 476     */
 477    driOptionCache optionCache;
 478
 479    struct radeon_cmdbuf cmdbuf;
 480
 481    struct radeon_debug debug;
 482
 483   drm_clip_rect_t fboRect;
 484   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 485   GLboolean front_cliprects;
 486
 487    /**
 488     * Set if rendering has occured to the drawable's front buffer.
 489     *
 490     * This is used in the DRI2 case to detect that glFlush should also copy
 491     * the contents of the fake front buffer to the real front buffer.
 492     */
 493    GLboolean front_buffer_dirty;
 494
 495    /**
 496     * Track whether front-buffer rendering is currently enabled
 497     *
 498     * A separate flag is used to track this in order to support MRT more
 499     * easily.
 500     */
 501    GLboolean is_front_buffer_rendering;
 502
 503    /**
 504     * Track whether front-buffer is the current read target.
 505     *
 506     * This is closely associated with is_front_buffer_rendering, but may
 507     * be set separately.  The DRI2 fake front buffer must be referenced
 508     * either way.
 509     */
 510    GLboolean is_front_buffer_reading;
 511
 512    struct dri_metaops meta;
 513
 514    struct {
 515         struct radeon_query_object *current;
 516         struct radeon_state_atom queryobj;
 517    } query;
 518
 519    struct {
 520            void (*get_lock)(radeonContextPtr radeon);
 521            void (*update_viewport_offset)(GLcontext *ctx);
 522            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 523            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 524            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 525            void (*pre_emit_state)(radeonContextPtr rmesa);
 526            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 527            void (*free_context)(GLcontext *ctx);
 528            void (*emit_query_finish)(radeonContextPtr radeon);
 529            void (*update_scissor)(GLcontext *ctx);
 530            unsigned (*check_blit)(gl_format mesa_format);
 531            unsigned (*blit)(GLcontext *ctx,
 532                         struct radeon_bo *src_bo,
 533                         intptr_t src_offset,
 534                         gl_format src_mesaformat,
 535                         unsigned src_pitch,
 536                         unsigned src_width,
 537                         unsigned src_height,
 538                         unsigned src_x_offset,
 539                         unsigned src_y_offset,
 540                         struct radeon_bo *dst_bo,
 541                         intptr_t dst_offset,
 542                         gl_format dst_mesaformat,
 543                         unsigned dst_pitch,
 544                         unsigned dst_width,
 545                         unsigned dst_height,
 546                         unsigned dst_x_offset,
 547                         unsigned dst_y_offset,
 548                         unsigned reg_width,
 549                         unsigned reg_height,
 550                         unsigned flip_y);
 551            unsigned (*is_format_renderable)(gl_format mesa_format);
 552    } vtbl;
 553 };
 554
 555 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 556
 557 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 558 {
 559         return radeon->dri.context->driDrawablePriv;
 560 }
 561
 562 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 563 {
 564         return radeon->dri.context->driReadablePriv;
 565 }
 566
 567 /**
 568  * This function takes a float and packs it into a uint32_t
 569  */
 570 static INLINE uint32_t radeonPackFloat32(float fl)
 571 {
 572         union {
 573                 float fl;
 574                 uint32_t u;
 575         } u;
 576
 577         u.fl = fl;
 578         return u.u;
 579 }
 580
 581 /* This is probably wrong for some values, I need to test this
 582  * some more.  Range checking would be a good idea also..
 583  *
 584  * But it works for most things.  I'll fix it later if someone
 585  * else with a better clue doesn't
 586  */
 587 static INLINE uint32_t radeonPackFloat24(float f)
 588 {
 589         float mantissa;
 590         int exponent;
 591         uint32_t float24 = 0;
 592
 593         if (f == 0.0)
 594                 return 0;
 595
 596         mantissa = frexpf(f, &exponent);
 597
 598         /* Handle -ve */
 599         if (mantissa < 0) {
 600                 float24 |= (1 << 23);
 601                 mantissa = mantissa * -1.0;
 602         }
 603         /* Handle exponent, bias of 63 */
 604         exponent += 62;
 605         float24 |= (exponent << 16);
 606         /* Kill 7 LSB of mantissa */
 607         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 608
 609         return float24;
 610 }
 611
 612 GLboolean radeonInitContext(radeonContextPtr radeon,
 613                             struct dd_function_table* functions,
 614                             const __GLcontextModes * glVisual,
 615                             __DRIcontext * driContextPriv,
 616                             void *sharedContextPrivate);
 617
 618 void radeonCleanupContext(radeonContextPtr radeon);
 619 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 620 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 621                                  GLboolean front_only);
 622 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 623                             __DRIdrawable * driDrawPriv,
 624                             __DRIdrawable * driReadPriv);
 625 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 626 void radeon_prepare_render(radeonContextPtr radeon);
 627
 628 #endif