src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 #include "dri_metaops.h"
  17 struct radeon_context;
  18
  19 #include "radeon_bocs_wrapper.h"
  20
  21 /* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html .
  22    I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble
  23    with other compilers ... GLUE!
  24 */
  25 #define WARN_ONCE(a, ...)       { \
  26         static int warn##__LINE__=1; \
  27         if(warn##__LINE__){ \
  28                 fprintf(stderr, "*********************************WARN_ONCE*********************************\n"); \
  29                 fprintf(stderr, "File %s function %s line %d\n", \
  30                         __FILE__, __FUNCTION__, __LINE__); \
  31                 fprintf(stderr,  a, ## __VA_ARGS__);\
  32                 fprintf(stderr, "***************************************************************************\n"); \
  33                 warn##__LINE__=0;\
  34                 } \
  35         }
  36
  37 /* This union is used to avoid warnings/miscompilation
  38    with float to uint32_t casts due to strict-aliasing */
  39 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  40
  41 struct radeon_context;
  42 typedef struct radeon_context radeonContextRec;
  43 typedef struct radeon_context *radeonContextPtr;
  44
  45
  46 #define TEX_0   0x1
  47 #define TEX_1   0x2
  48 #define TEX_2   0x4
  49 #define TEX_3   0x8
  50 #define TEX_4   0x10
  51 #define TEX_5   0x20
  52
  53 /* Rasterizing fallbacks */
  54 /* See correponding strings in r200_swtcl.c */
  55 #define RADEON_FALLBACK_TEXTURE         0x0001
  56 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  57 #define RADEON_FALLBACK_STENCIL         0x0004
  58 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  59 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  60 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  61 #define RADEON_FALLBACK_DISABLE         0x0040
  62 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  63 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  64 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  65
  66 #define R200_FALLBACK_TEXTURE           0x01
  67 #define R200_FALLBACK_DRAW_BUFFER       0x02
  68 #define R200_FALLBACK_STENCIL           0x04
  69 #define R200_FALLBACK_RENDER_MODE       0x08
  70 #define R200_FALLBACK_DISABLE           0x10
  71 #define R200_FALLBACK_BORDER_MODE       0x20
  72
  73 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  74 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  75 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  76 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  77 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  78 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  79 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  80 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  81 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  82
  83 /* The blit width for texture uploads
  84  */
  85 #define BLIT_WIDTH_BYTES 1024
  86
  87 /* Use the templated vertex format:
  88  */
  89 #define COLOR_IS_RGBA
  90 #define TAG(x) radeon##x
  91 #include "tnl_dd/t_dd_vertex.h"
  92 #undef TAG
  93
  94 #define RADEON_RB_CLASS 0xdeadbeef
  95
  96 struct radeon_renderbuffer
  97 {
  98         struct gl_renderbuffer base;
  99         struct radeon_bo *bo;
 100         unsigned int cpp;
 101         /* unsigned int offset; */
 102         unsigned int pitch;
 103
 104         uint32_t draw_offset; /* FBO */
 105         /* boo Xorg 6.8.2 compat */
 106         int has_surface;
 107
 108         GLuint pf_pending;  /**< sequence number of pending flip */
 109         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
 110         __DRIdrawablePrivate *dPriv;
 111 };
 112
 113 struct radeon_framebuffer
 114 {
 115         struct gl_framebuffer base;
 116
 117         struct radeon_renderbuffer *color_rb[2];
 118
 119         GLuint vbl_waited;
 120
 121         /* buffer swap */
 122         int64_t swap_ust;
 123         int64_t swap_missed_ust;
 124
 125         GLuint swap_count;
 126         GLuint swap_missed_count;
 127
 128         /* Drawable page flipping state */
 129         GLboolean pf_active;
 130         GLint pf_current_page;
 131         GLint pf_num_pages;
 132
 133 };
 134
 135
 136 struct radeon_colorbuffer_state {
 137         GLuint clear;
 138         int roundEnable;
 139         struct gl_renderbuffer *rb;
 140         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 141 };
 142
 143 struct radeon_depthbuffer_state {
 144         GLuint clear;
 145         struct gl_renderbuffer *rb;
 146 };
 147
 148 struct radeon_scissor_state {
 149         drm_clip_rect_t rect;
 150         GLboolean enabled;
 151
 152         GLuint numClipRects;    /* Cliprects active */
 153         GLuint numAllocedClipRects;     /* Cliprects available */
 154         drm_clip_rect_t *pClipRects;
 155 };
 156
 157 struct radeon_stencilbuffer_state {
 158         GLuint clear;           /* rb3d_stencilrefmask value */
 159 };
 160
 161 struct radeon_stipple_state {
 162         GLuint mask[32];
 163 };
 164
 165 struct radeon_state_atom {
 166         struct radeon_state_atom *next, *prev;
 167         const char *name;       /* for debug */
 168         int cmd_size;           /* size in bytes */
 169         GLuint idx;
 170         GLuint is_tcl;
 171         GLuint *cmd;            /* one or more cmd's */
 172         GLuint *lastcmd;                /* one or more cmd's */
 173         GLboolean dirty;        /* dirty-mark in emit_state_list */
 174         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 175         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 176 };
 177
 178 struct radeon_hw_state {
 179         /* Head of the linked list of state atoms. */
 180         struct radeon_state_atom atomlist;
 181         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 182         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 183         GLboolean is_dirty, all_dirty;
 184 };
 185
 186
 187 /* Texture related */
 188 typedef struct _radeon_texture_image radeon_texture_image;
 189
 190 struct _radeon_texture_image {
 191         struct gl_texture_image base;
 192
 193         /**
 194          * If mt != 0, the image is stored in hardware format in the
 195          * given mipmap tree. In this case, base.Data may point into the
 196          * mapping of the buffer object that contains the mipmap tree.
 197          *
 198          * If mt == 0, the image is stored in normal memory pointed to
 199          * by base.Data.
 200          */
 201         struct _radeon_mipmap_tree *mt;
 202         struct radeon_bo *bo;
 203
 204         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 205         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 206 };
 207
 208
 209 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 210 {
 211         return (radeon_texture_image*)image;
 212 }
 213
 214
 215 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 216
 217 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 218
 219 /* Texture object in locally shared texture space.
 220  */
 221 struct radeon_tex_obj {
 222         struct gl_texture_object base;
 223         struct _radeon_mipmap_tree *mt;
 224
 225         /**
 226          * This is true if we've verified that the mipmap tree above is complete
 227          * and so on.
 228          */
 229         GLboolean validated;
 230
 231         GLuint override_offset;
 232         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 233         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 234         struct radeon_bo *bo;
 235
 236         GLuint pp_txfilter;     /* hardware register values */
 237         GLuint pp_txformat;
 238         GLuint pp_txformat_x;
 239         GLuint pp_txsize;       /* npot only */
 240         GLuint pp_txpitch;      /* npot only */
 241         GLuint pp_border_color;
 242         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 243
 244         GLuint pp_txfilter_1;   /*  r300 */
 245
 246         /* r700 texture states */
 247         GLuint SQ_TEX_RESOURCE0;
 248         GLuint SQ_TEX_RESOURCE1;
 249         GLuint SQ_TEX_RESOURCE2;
 250         GLuint SQ_TEX_RESOURCE3;
 251         GLuint SQ_TEX_RESOURCE4;
 252         GLuint SQ_TEX_RESOURCE5;
 253         GLuint SQ_TEX_RESOURCE6;
 254
 255         GLuint SQ_TEX_SAMPLER0;
 256         GLuint SQ_TEX_SAMPLER1;
 257         GLuint SQ_TEX_SAMPLER2;
 258
 259         GLuint TD_PS_SAMPLER0_BORDER_RED;
 260         GLuint TD_PS_SAMPLER0_BORDER_GREEN;
 261         GLuint TD_PS_SAMPLER0_BORDER_BLUE;
 262         GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
 263
 264         GLboolean border_fallback;
 265
 266
 267 };
 268
 269 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 270 {
 271         return (radeonTexObj*)texObj;
 272 }
 273
 274 /* occlusion query */
 275 struct radeon_query_object {
 276         struct gl_query_object Base;
 277         struct radeon_bo *bo;
 278         int curr_offset;
 279         GLboolean emitted_begin;
 280
 281         /* Double linked list of not flushed query objects */
 282         struct radeon_query_object *prev, *next;
 283 };
 284
 285 /* Need refcounting on dma buffers:
 286  */
 287 struct radeon_dma_buffer {
 288         int refcount;           /* the number of retained regions in buf */
 289         drmBufPtr buf;
 290 };
 291
 292 struct radeon_aos {
 293         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 294         int offset; /** Offset into buffer object, in bytes */
 295         int components; /** Number of components per vertex */
 296         int stride; /** Stride in dwords (may be 0 for repeating) */
 297         int count; /** Number of vertices */
 298 };
 299
 300 #define DMA_BO_FREE_TIME 100
 301
 302 struct radeon_dma_bo {
 303   struct radeon_dma_bo *next, *prev;
 304   struct radeon_bo *bo;
 305   int expire_counter;
 306 };
 307
 308 struct radeon_dma {
 309         /* Active dma region.  Allocations for vertices and retained
 310          * regions come from here.  Also used for emitting random vertices,
 311          * these may be flushed by calling flush_current();
 312          */
 313         struct radeon_dma_bo free;
 314         struct radeon_dma_bo wait;
 315         struct radeon_dma_bo reserved;
 316         size_t current_used; /** Number of bytes allocated and forgotten about */
 317         size_t current_vertexptr; /** End of active vertex region */
 318         size_t minimum_size;
 319
 320         /**
 321          * If current_vertexptr != current_used then flush must be non-zero.
 322          * flush must be called before non-active vertex allocations can be
 323          * performed.
 324          */
 325         void (*flush) (GLcontext *);
 326 };
 327
 328 /* radeon_swtcl.c
 329  */
 330 struct radeon_swtcl_info {
 331
 332         GLuint RenderIndex;
 333         GLuint vertex_size;
 334         GLubyte *verts;
 335
 336         /* Fallback rasterization functions
 337          */
 338         GLuint hw_primitive;
 339         GLenum render_primitive;
 340         GLuint numverts;
 341
 342         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 343         GLuint vertex_attr_count;
 344
 345 };
 346
 347 #define RADEON_MAX_AOS_ARRAYS           16
 348 struct radeon_tcl_info {
 349         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 350         GLuint aos_count;
 351         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 352         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 353 };
 354
 355 struct radeon_ioctl {
 356         GLuint vertex_offset;
 357         struct radeon_bo *bo;
 358         GLuint vertex_size;
 359 };
 360
 361 #define RADEON_MAX_PRIMS 64
 362
 363 struct radeon_prim {
 364         GLuint start;
 365         GLuint end;
 366         GLuint prim;
 367 };
 368
 369 static INLINE GLuint radeonPackColor(GLuint cpp,
 370                                      GLubyte r, GLubyte g,
 371                                      GLubyte b, GLubyte a)
 372 {
 373         switch (cpp) {
 374         case 2:
 375                 return PACK_COLOR_565(r, g, b);
 376         case 4:
 377                 return PACK_COLOR_8888(a, r, g, b);
 378         default:
 379                 return 0;
 380         }
 381 }
 382
 383 #define MAX_CMD_BUF_SZ (16*1024)
 384
 385 #define MAX_DMA_BUF_SZ (64*1024)
 386
 387 struct radeon_store {
 388         GLuint statenr;
 389         GLuint primnr;
 390         char cmd_buf[MAX_CMD_BUF_SZ];
 391         int cmd_used;
 392         int elts_start;
 393 };
 394
 395 struct radeon_dri_mirror {
 396         __DRIcontextPrivate *context;   /* DRI context */
 397         __DRIscreenPrivate *screen;     /* DRI screen */
 398
 399         drm_context_t hwContext;
 400         drm_hw_lock_t *hwLock;
 401         int hwLockCount;
 402         int fd;
 403         int drmMinor;
 404 };
 405
 406 #define DEBUG_TEXTURE   0x001
 407 #define DEBUG_STATE     0x002
 408 #define DEBUG_IOCTL     0x004
 409 #define DEBUG_PRIMS     0x008
 410 #define DEBUG_VERTS     0x010
 411 #define DEBUG_FALLBACKS 0x020
 412 #define DEBUG_VFMT      0x040
 413 #define DEBUG_CODEGEN   0x080
 414 #define DEBUG_VERBOSE   0x100
 415 #define DEBUG_DRI       0x200
 416 #define DEBUG_DMA       0x400
 417 #define DEBUG_SANITY    0x800
 418 #define DEBUG_SYNC      0x1000
 419 #define DEBUG_PIXEL     0x2000
 420 #define DEBUG_MEMORY    0x4000
 421
 422
 423 typedef void (*radeon_tri_func) (radeonContextPtr,
 424                                  radeonVertex *,
 425                                  radeonVertex *, radeonVertex *);
 426
 427 typedef void (*radeon_line_func) (radeonContextPtr,
 428                                   radeonVertex *, radeonVertex *);
 429
 430 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 431
 432 #define RADEON_MAX_BOS 32
 433 struct radeon_state {
 434         struct radeon_colorbuffer_state color;
 435         struct radeon_depthbuffer_state depth;
 436         struct radeon_scissor_state scissor;
 437         struct radeon_stencilbuffer_state stencil;
 438
 439         struct radeon_cs_space_check bos[RADEON_MAX_BOS];
 440         int validated_bo_count;
 441 };
 442
 443 /**
 444  * This structure holds the command buffer while it is being constructed.
 445  *
 446  * The first batch of commands in the buffer is always the state that needs
 447  * to be re-emitted when the context is lost. This batch can be skipped
 448  * otherwise.
 449  */
 450 struct radeon_cmdbuf {
 451         struct radeon_cs_manager    *csm;
 452         struct radeon_cs            *cs;
 453         int size; /** # of dwords total */
 454         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 455 };
 456
 457 struct radeon_context {
 458    GLcontext *glCtx;
 459    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 460
 461    /* Texture object bookkeeping
 462     */
 463    int                   texture_depth;
 464    float                 initialMaxAnisotropy;
 465    uint32_t              texture_row_align;
 466    uint32_t              texture_rect_row_align;
 467    uint32_t              texture_compressed_row_align;
 468
 469   struct radeon_dma dma;
 470   struct radeon_hw_state hw;
 471    /* Rasterization and vertex state:
 472     */
 473    GLuint TclFallback;
 474    GLuint Fallback;
 475    GLuint NewGLState;
 476    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 477
 478    /* Drawable, cliprect and scissor information */
 479    GLuint numClipRects; /* Cliprects for the draw buffer */
 480    drm_clip_rect_t *pClipRects;
 481    unsigned int lastStamp;
 482    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 483
 484    /* Mirrors of some DRI state */
 485    struct radeon_dri_mirror dri;
 486
 487    /* Busy waiting */
 488    GLuint do_usleeps;
 489    GLuint do_irqs;
 490    GLuint irqsEmitted;
 491    drm_radeon_irq_wait_t iw;
 492
 493    /* Derived state - for r300 only */
 494    struct radeon_state state;
 495
 496    struct radeon_swtcl_info swtcl;
 497    struct radeon_tcl_info tcl;
 498    /* Configuration cache
 499     */
 500    driOptionCache optionCache;
 501
 502    struct radeon_cmdbuf cmdbuf;
 503
 504   drm_clip_rect_t fboRect;
 505   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 506   GLboolean front_cliprects;
 507
 508    /**
 509     * Set if rendering has occured to the drawable's front buffer.
 510     *
 511     * This is used in the DRI2 case to detect that glFlush should also copy
 512     * the contents of the fake front buffer to the real front buffer.
 513     */
 514    GLboolean front_buffer_dirty;
 515
 516    /**
 517     * Track whether front-buffer rendering is currently enabled
 518     *
 519     * A separate flag is used to track this in order to support MRT more
 520     * easily.
 521     */
 522    GLboolean is_front_buffer_rendering;
 523
 524    /**
 525     * Track whether front-buffer is the current read target.
 526     *
 527     * This is closely associated with is_front_buffer_rendering, but may
 528     * be set separately.  The DRI2 fake front buffer must be referenced
 529     * either way.
 530     */
 531    GLboolean is_front_buffer_reading;
 532
 533    struct dri_metaops meta;
 534
 535    struct {
 536         struct radeon_query_object *current;
 537         struct radeon_query_object not_flushed_head;
 538         struct radeon_state_atom queryobj;
 539    } query;
 540
 541    struct {
 542            void (*get_lock)(radeonContextPtr radeon);
 543            void (*update_viewport_offset)(GLcontext *ctx);
 544            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 545            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 546            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 547            void (*pre_emit_state)(radeonContextPtr rmesa);
 548            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 549            void (*free_context)(GLcontext *ctx);
 550            void (*emit_query_finish)(radeonContextPtr radeon);
 551            void (*update_scissor)(GLcontext *ctx);
 552    } vtbl;
 553 };
 554
 555 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 556
 557 static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon)
 558 {
 559         return radeon->dri.context->driDrawablePriv;
 560 }
 561
 562 static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon)
 563 {
 564         return radeon->dri.context->driReadablePriv;
 565 }
 566
 567 /**
 568  * This function takes a float and packs it into a uint32_t
 569  */
 570 static INLINE uint32_t radeonPackFloat32(float fl)
 571 {
 572         union {
 573                 float fl;
 574                 uint32_t u;
 575         } u;
 576
 577         u.fl = fl;
 578         return u.u;
 579 }
 580
 581 /* This is probably wrong for some values, I need to test this
 582  * some more.  Range checking would be a good idea also..
 583  *
 584  * But it works for most things.  I'll fix it later if someone
 585  * else with a better clue doesn't
 586  */
 587 static INLINE uint32_t radeonPackFloat24(float f)
 588 {
 589         float mantissa;
 590         int exponent;
 591         uint32_t float24 = 0;
 592
 593         if (f == 0.0)
 594                 return 0;
 595
 596         mantissa = frexpf(f, &exponent);
 597
 598         /* Handle -ve */
 599         if (mantissa < 0) {
 600                 float24 |= (1 << 23);
 601                 mantissa = mantissa * -1.0;
 602         }
 603         /* Handle exponent, bias of 63 */
 604         exponent += 62;
 605         float24 |= (exponent << 16);
 606         /* Kill 7 LSB of mantissa */
 607         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 608
 609         return float24;
 610 }
 611
 612 GLboolean radeonInitContext(radeonContextPtr radeon,
 613                             struct dd_function_table* functions,
 614                             const __GLcontextModes * glVisual,
 615                             __DRIcontextPrivate * driContextPriv,
 616                             void *sharedContextPrivate);
 617
 618 void radeonCleanupContext(radeonContextPtr radeon);
 619 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 620 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 621 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 622                             __DRIdrawablePrivate * driDrawPriv,
 623                             __DRIdrawablePrivate * driReadPriv);
 624 extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
 625
 626 /* ================================================================
 627  * Debugging:
 628  */
 629 #define DO_DEBUG                1
 630
 631 #if DO_DEBUG
 632 extern int RADEON_DEBUG;
 633 #else
 634 #define RADEON_DEBUG            0
 635 #endif
 636
 637 #endif