src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/matrix.h"
  43 #include "main/extensions.h"
  44 #include "main/framebuffer.h"
  45 #include "main/state.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55
  56 #include "radeon_common.h"
  57 #include "radeon_context.h"
  58 #include "radeon_ioctl.h"
  59 #include "radeon_state.h"
  60 #include "radeon_span.h"
  61 #include "radeon_tex.h"
  62 #include "radeon_swtcl.h"
  63 #include "radeon_tcl.h"
  64 #include "radeon_maos.h"
  65
  66 #define need_GL_EXT_blend_minmax
  67 #define need_GL_EXT_fog_coord
  68 #define need_GL_EXT_secondary_color
  69 #include "extension_helper.h"
  70
  71 #define DRIVER_DATE     "20061018"
  72
  73 #include "vblank.h"
  74 #include "utils.h"
  75 #include "xmlpool.h" /* for symbolic values of enum-type options */
  76
  77 /* Extension strings exported by the R100 driver.
  78  */
  79 const struct dri_extension card_extensions[] =
  80 {
  81     { "GL_ARB_multitexture",               NULL },
  82     { "GL_ARB_texture_border_clamp",       NULL },
  83     { "GL_ARB_texture_env_add",            NULL },
  84     { "GL_ARB_texture_env_combine",        NULL },
  85     { "GL_ARB_texture_env_crossbar",       NULL },
  86     { "GL_ARB_texture_env_dot3",           NULL },
  87     { "GL_ARB_texture_mirrored_repeat",    NULL },
  88     { "GL_EXT_blend_logic_op",             NULL },
  89     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  90     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  91     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  92     { "GL_EXT_stencil_wrap",               NULL },
  93     { "GL_EXT_texture_edge_clamp",         NULL },
  94     { "GL_EXT_texture_env_combine",        NULL },
  95     { "GL_EXT_texture_env_dot3",           NULL },
  96     { "GL_EXT_texture_filter_anisotropic", NULL },
  97     { "GL_EXT_texture_lod_bias",           NULL },
  98     { "GL_EXT_texture_mirror_clamp",       NULL },
  99     { "GL_ATI_texture_env_combine3",       NULL },
 100     { "GL_ATI_texture_mirror_once",        NULL },
 101     { "GL_MESA_ycbcr_texture",             NULL },
 102     { "GL_NV_blend_square",                NULL },
 103     { "GL_SGIS_generate_mipmap",           NULL },
 104     { NULL,                                NULL }
 105 };
 106
 107 extern const struct tnl_pipeline_stage _radeon_render_stage;
 108 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 109
 110 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 111
 112    /* Try and go straight to t&l
 113     */
 114    &_radeon_tcl_stage,
 115
 116    /* Catch any t&l fallbacks
 117     */
 118    &_tnl_vertex_transform_stage,
 119    &_tnl_normal_transform_stage,
 120    &_tnl_lighting_stage,
 121    &_tnl_fog_coordinate_stage,
 122    &_tnl_texgen_stage,
 123    &_tnl_texture_transform_stage,
 124
 125    &_radeon_render_stage,
 126    &_tnl_render_stage,          /* FALLBACK:  */
 127    NULL,
 128 };
 129
 130 static const struct dri_debug_control debug_control[] =
 131 {
 132     { "fall",  DEBUG_FALLBACKS },
 133     { "tex",   DEBUG_TEXTURE },
 134     { "ioctl", DEBUG_IOCTL },
 135     { "prim",  DEBUG_PRIMS },
 136     { "vert",  DEBUG_VERTS },
 137     { "state", DEBUG_STATE },
 138     { "code",  DEBUG_CODEGEN },
 139     { "vfmt",  DEBUG_VFMT },
 140     { "vtxf",  DEBUG_VFMT },
 141     { "verb",  DEBUG_VERBOSE },
 142     { "dri",   DEBUG_DRI },
 143     { "dma",   DEBUG_DMA },
 144     { "san",   DEBUG_SANITY },
 145     { "sync",  DEBUG_SYNC },
 146     { NULL,    0 }
 147 };
 148
 149 static void r100_get_lock(radeonContextPtr radeon)
 150 {
 151    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 152    drm_radeon_sarea_t *sarea = radeon->sarea;
 153
 154    RADEON_STATECHANGE(rmesa, ctx);
 155    if (rmesa->radeon.sarea->tiling_enabled) {
 156       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 157          RADEON_COLOR_TILE_ENABLE;
 158    } else {
 159       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 160          ~RADEON_COLOR_TILE_ENABLE;
 161    }
 162
 163    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 164       int i;
 165       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 166
 167       for (i = 0; i < rmesa->radeon.nr_heaps; i++) {
 168          DRI_AGE_TEXTURES(rmesa->radeon.texture_heaps[i]);
 169       }
 170    }
 171 }
 172
 173 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 174 {
 175 }
 176
 177 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 178 {
 179    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 180
 181    /* r100 always needs to emit ZBS to avoid TCL lockups */
 182    rmesa->hw.zbs.dirty = 1;
 183    radeon->hw.is_dirty = 1;
 184 }
 185
 186
 187 static void r100_init_vtbl(radeonContextPtr radeon)
 188 {
 189    radeon->vtbl.get_lock = r100_get_lock;
 190    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 191    radeon->vtbl.update_draw_buffer = radeonUpdateDrawBuffer;
 192    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 193    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 194    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 195 }
 196
 197 /* Create the device specific context.
 198  */
 199 GLboolean
 200 radeonCreateContext( const __GLcontextModes *glVisual,
 201                      __DRIcontextPrivate *driContextPriv,
 202                      void *sharedContextPrivate)
 203 {
 204    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 205    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 206    struct dd_function_table functions;
 207    r100ContextPtr rmesa;
 208    GLcontext *ctx;
 209    int i;
 210    int tcl_mode, fthrottle_mode;
 211
 212    assert(glVisual);
 213    assert(driContextPriv);
 214    assert(screen);
 215
 216    /* Allocate the Radeon context */
 217    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 218    if ( !rmesa )
 219       return GL_FALSE;
 220
 221    r100_init_vtbl(&rmesa->radeon);
 222
 223    /* init exp fog table data */
 224    radeonInitStaticFogData();
 225
 226    /* Parse configuration files.
 227     * Do this here so that initialMaxAnisotropy is set before we create
 228     * the default textures.
 229     */
 230    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 231                         screen->driScreen->myNum, "radeon");
 232    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 233                                                  "def_max_anisotropy");
 234
 235    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 236       if ( sPriv->drm_version.minor < 13 )
 237          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 238                           "disabling.\n", sPriv->drm_version.minor );
 239       else
 240          rmesa->using_hyperz = GL_TRUE;
 241    }
 242
 243    if ( sPriv->drm_version.minor >= 15 )
 244       rmesa->texmicrotile = GL_TRUE;
 245
 246    /* Init default driver functions then plug in our Radeon-specific functions
 247     * (the texture functions are especially important)
 248     */
 249    _mesa_init_driver_functions( &functions );
 250    radeonInitTextureFuncs( &functions );
 251
 252    if (!radeonInitContext(&rmesa->radeon, &functions,
 253                           glVisual, driContextPriv,
 254                           sharedContextPrivate)) {
 255      FREE(rmesa);
 256      return GL_FALSE;
 257    }
 258
 259    (void) memset( rmesa->radeon.texture_heaps, 0, sizeof( rmesa->radeon.texture_heaps ) );
 260    make_empty_list( & rmesa->radeon.swapped );
 261
 262 #if 0
 263    rmesa->radeon.nr_heaps = screen->numTexHeaps;
 264    for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
 265       rmesa->radeon.texture_heaps[i] = driCreateTextureHeap( i, rmesa,
 266             screen->texSize[i],
 267             12,
 268             RADEON_NR_TEX_REGIONS,
 269             (drmTextureRegionPtr)rmesa->radeon.sarea->tex_list[i],
 270             & rmesa->radeon.sarea->tex_age[i],
 271             & rmesa->radeon.swapped,
 272             sizeof( radeonTexObj ),
 273             (destroy_texture_object_t *) radeonDestroyTexObj );
 274
 275       driSetTextureSwapCounterLocation( rmesa->radeon.texture_heaps[i],
 276                                         & rmesa->c_textureSwaps );
 277    }
 278 #endif
 279    rmesa->radeon.texture_depth = driQueryOptioni (&rmesa->radeon.optionCache,
 280                                            "texture_depth");
 281    if (rmesa->radeon.texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
 282       rmesa->radeon.texture_depth = ( screen->cpp == 4 ) ?
 283          DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 284
 285    rmesa->radeon.swtcl.RenderIndex = ~0;
 286    rmesa->radeon.hw.all_dirty = GL_TRUE;
 287
 288    /* Set the maximum texture size small enough that we can guarentee that
 289     * all texture units can bind a maximal texture and have all of them in
 290     * texturable memory at once. Depending on the allow_large_textures driconf
 291     * setting allow larger textures.
 292     */
 293
 294    ctx = rmesa->radeon.glCtx;
 295    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 296                                                  "texture_units");
 297    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 298    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 299
 300    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 301
 302    driCalculateMaxTextureLevels( rmesa->radeon.texture_heaps,
 303                                  rmesa->radeon.nr_heaps,
 304                                  & ctx->Const,
 305                                  4,
 306                                  11, /* max 2D texture size is 2048x2048 */
 307                                  8,  /* 256^3 */
 308                                  9,  /* \todo: max cube texture size seems to be 512x512(x6) */
 309                                  11, /* max rect texture size is 2048x2048. */
 310                                  12,
 311                                  GL_FALSE,
 312                                  i );
 313
 314
 315    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 316
 317    /* No wide points.
 318     */
 319    ctx->Const.MinPointSize = 1.0;
 320    ctx->Const.MinPointSizeAA = 1.0;
 321    ctx->Const.MaxPointSize = 1.0;
 322    ctx->Const.MaxPointSizeAA = 1.0;
 323
 324    ctx->Const.MinLineWidth = 1.0;
 325    ctx->Const.MinLineWidthAA = 1.0;
 326    ctx->Const.MaxLineWidth = 10.0;
 327    ctx->Const.MaxLineWidthAA = 10.0;
 328    ctx->Const.LineWidthGranularity = 0.0625;
 329
 330    /* Set maxlocksize (and hence vb size) small enough to avoid
 331     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 332     * fit in a single dma buffer for indexed rendering of quad strips,
 333     * etc.
 334     */
 335    ctx->Const.MaxArrayLockSize =
 336       MIN2( ctx->Const.MaxArrayLockSize,
 337             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 338
 339    rmesa->boxes = 0;
 340
 341    ctx->Const.MaxDrawBuffers = 1;
 342
 343    /* Initialize the software rasterizer and helper modules.
 344     */
 345    _swrast_CreateContext( ctx );
 346    _vbo_CreateContext( ctx );
 347    _tnl_CreateContext( ctx );
 348    _swsetup_CreateContext( ctx );
 349    _ae_create_context( ctx );
 350
 351    /* Install the customized pipeline:
 352     */
 353    _tnl_destroy_pipeline( ctx );
 354    _tnl_install_pipeline( ctx, radeon_pipeline );
 355
 356    /* Try and keep materials and vertices separate:
 357     */
 358 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 359
 360    /* Configure swrast and T&L to match hardware characteristics:
 361     */
 362    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 363    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 364    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 365    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 366
 367
 368    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 369       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 370       _math_matrix_ctr( &rmesa->tmpmat[i] );
 371       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 372       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 373    }
 374
 375    driInitExtensions( ctx, card_extensions, GL_TRUE );
 376    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 377       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 378    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 379       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 380       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 381    }
 382    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 383       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 384    }
 385
 386    if (rmesa->radeon.dri.drmMinor >= 9)
 387       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 388
 389    /* XXX these should really go right after _mesa_init_driver_functions() */
 390    radeonInitSpanFuncs( ctx );
 391    radeonInitIoctlFuncs( ctx );
 392    radeonInitStateFuncs( ctx );
 393    radeonInitState( rmesa );
 394    radeonInitSwtcl( ctx );
 395
 396    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 397                          ctx->Const.MaxArrayLockSize, 32 );
 398
 399    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 400    rmesa->radeon.iw.irq_seq = -1;
 401    rmesa->radeon.irqsEmitted = 0;
 402    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 403                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 404
 405    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 406
 407    (*sPriv->systemTime->getUST)( & rmesa->radeon.swap_ust );
 408
 409
 410 #if DO_DEBUG
 411    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 412                                        debug_control );
 413 #endif
 414
 415    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 416    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 417       fprintf(stderr, "disabling 3D acceleration\n");
 418       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 419    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 420               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 421       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 422          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 423          fprintf(stderr, "Disabling HW TCL support\n");
 424       }
 425       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 426    }
 427
 428    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 429 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 430    }
 431    return GL_TRUE;
 432 }
 433
 434
 435 /* Destroy the device specific context.
 436  */
 437 /* Destroy the Mesa and driver specific context data.
 438  */
 439 void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
 440 {
 441    GET_CURRENT_CONTEXT(ctx);
 442    r100ContextPtr rmesa = (r100ContextPtr) driContextPriv->driverPrivate;
 443    r100ContextPtr current = ctx ? R100_CONTEXT(ctx) : NULL;
 444
 445    /* check if we're deleting the currently bound context */
 446    if (rmesa == current) {
 447       radeon_firevertices(&rmesa->radeon);
 448       _mesa_make_current(NULL, NULL, NULL);
 449    }
 450
 451    /* Free radeon context resources */
 452    assert(rmesa); /* should never be null */
 453    if ( rmesa ) {
 454       GLboolean   release_texture_heaps;
 455
 456
 457       release_texture_heaps = (rmesa->radeon.glCtx->Shared->RefCount == 1);
 458       _swsetup_DestroyContext( rmesa->radeon.glCtx );
 459       _tnl_DestroyContext( rmesa->radeon.glCtx );
 460       _vbo_DestroyContext( rmesa->radeon.glCtx );
 461       _swrast_DestroyContext( rmesa->radeon.glCtx );
 462
 463       radeonDestroySwtcl( rmesa->radeon.glCtx );
 464       radeonReleaseArrays( rmesa->radeon.glCtx, ~0 );
 465       if (rmesa->radeon.dma.current) {
 466          radeonReleaseDmaRegion( &rmesa->radeon );
 467          rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
 468       }
 469
 470       _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 471
 472       if (rmesa->radeon.state.scissor.pClipRects) {
 473          FREE(rmesa->radeon.state.scissor.pClipRects);
 474          rmesa->radeon.state.scissor.pClipRects = NULL;
 475       }
 476
 477       if ( release_texture_heaps ) {
 478          /* This share group is about to go away, free our private
 479           * texture object data.
 480           */
 481          int i;
 482
 483          for ( i = 0 ; i < rmesa->radeon.nr_heaps ; i++ ) {
 484             driDestroyTextureHeap( rmesa->radeon.texture_heaps[ i ] );
 485             rmesa->radeon.texture_heaps[ i ] = NULL;
 486          }
 487
 488          assert( is_empty_list( & rmesa->radeon.swapped ) );
 489       }
 490
 491       radeonCleanupContext(&rmesa->radeon);
 492
 493       FREE( rmesa );
 494    }
 495 }
 496