src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/matrix.h"
  43 #include "main/extensions.h"
  44 #include "main/framebuffer.h"
  45 #include "main/state.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55
  56 #include "radeon_common.h"
  57 #include "radeon_context.h"
  58 #include "radeon_ioctl.h"
  59 #include "radeon_state.h"
  60 #include "radeon_span.h"
  61 #include "radeon_tex.h"
  62 #include "radeon_swtcl.h"
  63 #include "radeon_tcl.h"
  64 #include "radeon_maos.h"
  65
  66 #define need_GL_EXT_blend_minmax
  67 #define need_GL_EXT_fog_coord
  68 #define need_GL_EXT_secondary_color
  69 #define need_GL_EXT_framebuffer_object
  70 #include "extension_helper.h"
  71
  72 #define DRIVER_DATE     "20061018"
  73
  74 #include "vblank.h"
  75 #include "utils.h"
  76 #include "xmlpool.h" /* for symbolic values of enum-type options */
  77
  78 /* Extension strings exported by the R100 driver.
  79  */
  80 const struct dri_extension card_extensions[] =
  81 {
  82     { "GL_ARB_multitexture",               NULL },
  83     { "GL_ARB_texture_border_clamp",       NULL },
  84     { "GL_ARB_texture_env_add",            NULL },
  85     { "GL_ARB_texture_env_combine",        NULL },
  86     { "GL_ARB_texture_env_crossbar",       NULL },
  87     { "GL_ARB_texture_env_dot3",           NULL },
  88     { "GL_ARB_texture_mirrored_repeat",    NULL },
  89     { "GL_EXT_blend_logic_op",             NULL },
  90     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  91     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  92     { "GL_EXT_packed_depth_stencil",       NULL},
  93     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  94     { "GL_EXT_stencil_wrap",               NULL },
  95     { "GL_EXT_texture_edge_clamp",         NULL },
  96     { "GL_EXT_texture_env_combine",        NULL },
  97     { "GL_EXT_texture_env_dot3",           NULL },
  98     { "GL_EXT_texture_filter_anisotropic", NULL },
  99     { "GL_EXT_texture_lod_bias",           NULL },
 100     { "GL_EXT_texture_mirror_clamp",       NULL },
 101     { "GL_ATI_texture_env_combine3",       NULL },
 102     { "GL_ATI_texture_mirror_once",        NULL },
 103     { "GL_MESA_ycbcr_texture",             NULL },
 104     { "GL_NV_blend_square",                NULL },
 105     { "GL_SGIS_generate_mipmap",           NULL },
 106     { NULL,                                NULL }
 107 };
 108
 109 const struct dri_extension mm_extensions[] = {
 110   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 111   { NULL, NULL }
 112 };
 113
 114 extern const struct tnl_pipeline_stage _radeon_render_stage;
 115 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 116
 117 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 118
 119    /* Try and go straight to t&l
 120     */
 121    &_radeon_tcl_stage,
 122
 123    /* Catch any t&l fallbacks
 124     */
 125    &_tnl_vertex_transform_stage,
 126    &_tnl_normal_transform_stage,
 127    &_tnl_lighting_stage,
 128    &_tnl_fog_coordinate_stage,
 129    &_tnl_texgen_stage,
 130    &_tnl_texture_transform_stage,
 131
 132    &_radeon_render_stage,
 133    &_tnl_render_stage,          /* FALLBACK:  */
 134    NULL,
 135 };
 136
 137 static const struct dri_debug_control debug_control[] =
 138 {
 139     { "fall",  DEBUG_FALLBACKS },
 140     { "tex",   DEBUG_TEXTURE },
 141     { "ioctl", DEBUG_IOCTL },
 142     { "prim",  DEBUG_PRIMS },
 143     { "vert",  DEBUG_VERTS },
 144     { "state", DEBUG_STATE },
 145     { "code",  DEBUG_CODEGEN },
 146     { "vfmt",  DEBUG_VFMT },
 147     { "vtxf",  DEBUG_VFMT },
 148     { "verb",  DEBUG_VERBOSE },
 149     { "dri",   DEBUG_DRI },
 150     { "dma",   DEBUG_DMA },
 151     { "san",   DEBUG_SANITY },
 152     { "sync",  DEBUG_SYNC },
 153     { NULL,    0 }
 154 };
 155
 156 static void r100_get_lock(radeonContextPtr radeon)
 157 {
 158    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 159    drm_radeon_sarea_t *sarea = radeon->sarea;
 160
 161    RADEON_STATECHANGE(rmesa, ctx);
 162    if (rmesa->radeon.sarea->tiling_enabled) {
 163       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 164          RADEON_COLOR_TILE_ENABLE;
 165    } else {
 166       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 167          ~RADEON_COLOR_TILE_ENABLE;
 168    }
 169
 170    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 171       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 172
 173       if (!radeon->radeonScreen->kernel_mm)
 174          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 175    }
 176 }
 177
 178 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 179 {
 180 }
 181
 182 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 183 {
 184    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 185
 186    /* r100 always needs to emit ZBS to avoid TCL lockups */
 187    rmesa->hw.zbs.dirty = 1;
 188    radeon->hw.is_dirty = 1;
 189 }
 190
 191 static void r100_vtbl_free_context(GLcontext *ctx)
 192 {
 193    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 194    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 195 }
 196
 197 static void r100_init_vtbl(radeonContextPtr radeon)
 198 {
 199    radeon->vtbl.get_lock = r100_get_lock;
 200    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 201    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 202    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 203    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 204    radeon->vtbl.fallback = radeonFallback;
 205 }
 206
 207 /* Create the device specific context.
 208  */
 209 GLboolean
 210 r100CreateContext( const __GLcontextModes *glVisual,
 211                      __DRIcontextPrivate *driContextPriv,
 212                      void *sharedContextPrivate)
 213 {
 214    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 215    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 216    struct dd_function_table functions;
 217    r100ContextPtr rmesa;
 218    GLcontext *ctx;
 219    int i;
 220    int tcl_mode, fthrottle_mode;
 221
 222    assert(glVisual);
 223    assert(driContextPriv);
 224    assert(screen);
 225
 226    /* Allocate the Radeon context */
 227    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 228    if ( !rmesa )
 229       return GL_FALSE;
 230
 231    r100_init_vtbl(&rmesa->radeon);
 232
 233    /* init exp fog table data */
 234    radeonInitStaticFogData();
 235
 236    /* Parse configuration files.
 237     * Do this here so that initialMaxAnisotropy is set before we create
 238     * the default textures.
 239     */
 240    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 241                         screen->driScreen->myNum, "radeon");
 242    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 243                                                  "def_max_anisotropy");
 244
 245    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 246       if ( sPriv->drm_version.minor < 13 )
 247          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 248                           "disabling.\n", sPriv->drm_version.minor );
 249       else
 250          rmesa->using_hyperz = GL_TRUE;
 251    }
 252
 253    if ( sPriv->drm_version.minor >= 15 )
 254       rmesa->texmicrotile = GL_TRUE;
 255
 256    /* Init default driver functions then plug in our Radeon-specific functions
 257     * (the texture functions are especially important)
 258     */
 259    _mesa_init_driver_functions( &functions );
 260    radeonInitTextureFuncs( &functions );
 261
 262    if (!radeonInitContext(&rmesa->radeon, &functions,
 263                           glVisual, driContextPriv,
 264                           sharedContextPrivate)) {
 265      FREE(rmesa);
 266      return GL_FALSE;
 267    }
 268
 269    rmesa->radeon.swtcl.RenderIndex = ~0;
 270    rmesa->radeon.hw.all_dirty = GL_TRUE;
 271
 272    /* Set the maximum texture size small enough that we can guarentee that
 273     * all texture units can bind a maximal texture and have all of them in
 274     * texturable memory at once. Depending on the allow_large_textures driconf
 275     * setting allow larger textures.
 276     */
 277
 278    ctx = rmesa->radeon.glCtx;
 279    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 280                                                  "texture_units");
 281    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 282    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 283
 284    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 285
 286    /* FIXME: When no memory manager is available we should set this
 287     * to some reasonable value based on texture memory pool size */
 288    ctx->Const.MaxTextureLevels = 12;
 289    ctx->Const.Max3DTextureLevels = 9;
 290    ctx->Const.MaxCubeTextureLevels = 12;
 291    ctx->Const.MaxTextureRectSize = 2048;
 292
 293    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 294
 295    /* No wide points.
 296     */
 297    ctx->Const.MinPointSize = 1.0;
 298    ctx->Const.MinPointSizeAA = 1.0;
 299    ctx->Const.MaxPointSize = 1.0;
 300    ctx->Const.MaxPointSizeAA = 1.0;
 301
 302    ctx->Const.MinLineWidth = 1.0;
 303    ctx->Const.MinLineWidthAA = 1.0;
 304    ctx->Const.MaxLineWidth = 10.0;
 305    ctx->Const.MaxLineWidthAA = 10.0;
 306    ctx->Const.LineWidthGranularity = 0.0625;
 307
 308    /* Set maxlocksize (and hence vb size) small enough to avoid
 309     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 310     * fit in a single dma buffer for indexed rendering of quad strips,
 311     * etc.
 312     */
 313    ctx->Const.MaxArrayLockSize =
 314       MIN2( ctx->Const.MaxArrayLockSize,
 315             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 316
 317    rmesa->boxes = 0;
 318
 319    ctx->Const.MaxDrawBuffers = 1;
 320
 321    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 322
 323    /* Initialize the software rasterizer and helper modules.
 324     */
 325    _swrast_CreateContext( ctx );
 326    _vbo_CreateContext( ctx );
 327    _tnl_CreateContext( ctx );
 328    _swsetup_CreateContext( ctx );
 329    _ae_create_context( ctx );
 330
 331    /* Install the customized pipeline:
 332     */
 333    _tnl_destroy_pipeline( ctx );
 334    _tnl_install_pipeline( ctx, radeon_pipeline );
 335
 336    /* Try and keep materials and vertices separate:
 337     */
 338 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 339
 340    /* Configure swrast and T&L to match hardware characteristics:
 341     */
 342    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 343    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 344    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 345    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 346
 347
 348    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 349       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 350       _math_matrix_ctr( &rmesa->tmpmat[i] );
 351       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 352       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 353    }
 354
 355    driInitExtensions( ctx, card_extensions, GL_TRUE );
 356    if (rmesa->radeon.radeonScreen->kernel_mm)
 357      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 358    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 359       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 360    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 361       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 362       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 363    }
 364    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 365       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 366    }
 367
 368    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 369       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 370
 371    /* XXX these should really go right after _mesa_init_driver_functions() */
 372    radeon_fbo_init(&rmesa->radeon);
 373    radeonInitSpanFuncs( ctx );
 374    radeonInitIoctlFuncs( ctx );
 375    radeonInitStateFuncs( ctx );
 376    radeonInitState( rmesa );
 377    radeonInitSwtcl( ctx );
 378
 379    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 380                          ctx->Const.MaxArrayLockSize, 32 );
 381
 382    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 383    rmesa->radeon.iw.irq_seq = -1;
 384    rmesa->radeon.irqsEmitted = 0;
 385    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 386                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 387
 388    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 389
 390
 391 #if DO_DEBUG
 392    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 393                                        debug_control );
 394 #endif
 395
 396    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 397    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 398       fprintf(stderr, "disabling 3D acceleration\n");
 399       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 400    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 401               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 402       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 403          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 404          fprintf(stderr, "Disabling HW TCL support\n");
 405       }
 406       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 407    }
 408
 409    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 410 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 411    }
 412    return GL_TRUE;
 413 }