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[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #endif
63
64 #include "utils.h"
65 #include "vblank.h"
66 #include "drirenderbuffer.h"
67
68 #include "radeon_bocs_wrapper.h"
69
70 #include "GL/internal/dri_interface.h"
71
72 /* Radeon configuration
73 */
74 #include "xmlpool.h"
75
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
80 DRI_CONF_OPT_END
81
82 #if !RADEON_COMMON /* R100 */
83 PUBLIC const char __driConfigOptions[] =
84 DRI_CONF_BEGIN
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
92 DRI_CONF_SECTION_END
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
102 DRI_CONF_SECTION_END
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
105 DRI_CONF_SECTION_END
106 DRI_CONF_END;
107 static const GLuint __driNConfigOptions = 15;
108
109 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
110
111 PUBLIC const char __driConfigOptions[] =
112 DRI_CONF_BEGIN
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
120 DRI_CONF_SECTION_END
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
131 DRI_CONF_SECTION_END
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_END;
139 static const GLuint __driNConfigOptions = 17;
140
141 extern const struct dri_extension blend_extensions[];
142 extern const struct dri_extension ARB_vp_extension[];
143 extern const struct dri_extension NV_vp_extension[];
144 extern const struct dri_extension ATI_fs_extension[];
145 extern const struct dri_extension point_extensions[];
146
147 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
148
149 /* TODO: integrate these into xmlpool.h! */
150 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
151 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
152 DRI_CONF_DESC(en,"Number of texture image units") \
153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
154 DRI_CONF_OPT_END
155
156 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture coordinate units") \
159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
160 DRI_CONF_OPT_END
161
162
163
164 #define DRI_CONF_DISABLE_S3TC(def) \
165 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
166 DRI_CONF_DESC(en,"Disable S3TC compression") \
167 DRI_CONF_OPT_END
168
169 #define DRI_CONF_DISABLE_FALLBACK(def) \
170 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
172 DRI_CONF_OPT_END
173
174 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
175 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
177 DRI_CONF_OPT_END
178
179 #define DRI_CONF_FP_OPTIMIZATION(def) \
180 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
182 DRI_CONF_ENUM(0,"Optimize for Speed") \
183 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 DRI_CONF_DESC_END \
185 DRI_CONF_OPT_END
186
187 PUBLIC const char __driConfigOptions[] =
188 DRI_CONF_BEGIN
189 DRI_CONF_SECTION_PERFORMANCE
190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
196 DRI_CONF_DISABLE_FALLBACK(true)
197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
198 DRI_CONF_SECTION_END
199 DRI_CONF_SECTION_QUALITY
200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
202 DRI_CONF_FORCE_S3TC_ENABLE(false)
203 DRI_CONF_DISABLE_S3TC(false)
204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
208 DRI_CONF_SECTION_END
209 DRI_CONF_SECTION_DEBUG
210 DRI_CONF_NO_RAST(false)
211 DRI_CONF_SECTION_END
212 DRI_CONF_END;
213 static const GLuint __driNConfigOptions = 17;
214
215 #ifndef RADEON_DEBUG
216
217 static const struct dri_debug_control debug_control[] = {
218 {"fall", DEBUG_FALLBACKS},
219 {"tex", DEBUG_TEXTURE},
220 {"ioctl", DEBUG_IOCTL},
221 {"prim", DEBUG_PRIMS},
222 {"vert", DEBUG_VERTS},
223 {"state", DEBUG_STATE},
224 {"code", DEBUG_CODEGEN},
225 {"vfmt", DEBUG_VFMT},
226 {"vtxf", DEBUG_VFMT},
227 {"verb", DEBUG_VERBOSE},
228 {"dri", DEBUG_DRI},
229 {"dma", DEBUG_DMA},
230 {"san", DEBUG_SANITY},
231 {"sync", DEBUG_SYNC},
232 {"pix", DEBUG_PIXEL},
233 {"mem", DEBUG_MEMORY},
234 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
235 {NULL, 0}
236 };
237 #endif /* RADEON_DEBUG */
238
239 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
240
241 extern const struct dri_extension card_extensions[];
242
243 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
244
245 static int
246 radeonGetParam(int fd, int param, void *value)
247 {
248 int ret;
249 drm_radeon_getparam_t gp;
250
251 gp.param = param;
252 gp.value = value;
253
254 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
255 return ret;
256 }
257
258 static const __DRIconfig **
259 radeonFillInModes( __DRIscreenPrivate *psp,
260 unsigned pixel_bits, unsigned depth_bits,
261 unsigned stencil_bits, GLboolean have_back_buffer )
262 {
263 __DRIconfig **configs;
264 __GLcontextModes *m;
265 unsigned depth_buffer_factor;
266 unsigned back_buffer_factor;
267 GLenum fb_format;
268 GLenum fb_type;
269 int i;
270
271 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
272 * enough to add support. Basically, if a context is created with an
273 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
274 * will never be used.
275 */
276 static const GLenum back_buffer_modes[] = {
277 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
278 };
279
280 uint8_t depth_bits_array[2];
281 uint8_t stencil_bits_array[2];
282
283
284 depth_bits_array[0] = depth_bits;
285 depth_bits_array[1] = depth_bits;
286
287 /* Just like with the accumulation buffer, always provide some modes
288 * with a stencil buffer. It will be a sw fallback, but some apps won't
289 * care about that.
290 */
291 stencil_bits_array[0] = 0;
292 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
293
294 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
295 back_buffer_factor = (have_back_buffer) ? 2 : 1;
296
297 if ( pixel_bits == 16 ) {
298 fb_format = GL_RGB;
299 fb_type = GL_UNSIGNED_SHORT_5_6_5;
300 }
301 else {
302 fb_format = GL_BGRA;
303 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
304 }
305
306 configs = driCreateConfigs(fb_format, fb_type,
307 depth_bits_array, stencil_bits_array,
308 depth_buffer_factor,
309 back_buffer_modes, back_buffer_factor);
310 if (configs == NULL) {
311 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
312 __func__, __LINE__ );
313 return NULL;
314 }
315
316 /* Mark the visual as slow if there are "fake" stencil bits.
317 */
318 for (i = 0; configs[i]; i++) {
319 m = &configs[i]->modes;
320 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
321 m->visualRating = GLX_SLOW_CONFIG;
322 }
323 }
324
325 return (const __DRIconfig **) configs;
326 }
327
328 #if !RADEON_COMMON
329 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
330 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
331 radeonSetTexOffset,
332 };
333 #endif
334
335 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
336 static const __DRIallocateExtension r200AllocateExtension = {
337 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
338 r200AllocateMemoryMESA,
339 r200FreeMemoryMESA,
340 r200GetMemoryOffsetMESA
341 };
342
343 static const __DRItexOffsetExtension r200texOffsetExtension = {
344 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
345 r200SetTexOffset,
346 };
347 #endif
348
349 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
350 static const __DRItexOffsetExtension r300texOffsetExtension = {
351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352 r300SetTexOffset,
353 };
354
355 void r300SetTexBuffer(__DRIcontext *pDRICtx,
356 GLint target,
357 __DRIdrawable *dPriv);
358 static const __DRItexBufferExtension r300TexBufferExtension = {
359 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
360 r300SetTexBuffer,
361 };
362 #endif
363
364 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
365 {
366 screen->chip_flags = 0;
367 switch ( device_id ) {
368 case PCI_CHIP_RADEON_LY:
369 case PCI_CHIP_RADEON_LZ:
370 case PCI_CHIP_RADEON_QY:
371 case PCI_CHIP_RADEON_QZ:
372 case PCI_CHIP_RN50_515E:
373 case PCI_CHIP_RN50_5969:
374 screen->chip_family = CHIP_FAMILY_RV100;
375 break;
376
377 case PCI_CHIP_RS100_4136:
378 case PCI_CHIP_RS100_4336:
379 screen->chip_family = CHIP_FAMILY_RS100;
380 break;
381
382 case PCI_CHIP_RS200_4137:
383 case PCI_CHIP_RS200_4337:
384 case PCI_CHIP_RS250_4237:
385 case PCI_CHIP_RS250_4437:
386 screen->chip_family = CHIP_FAMILY_RS200;
387 break;
388
389 case PCI_CHIP_RADEON_QD:
390 case PCI_CHIP_RADEON_QE:
391 case PCI_CHIP_RADEON_QF:
392 case PCI_CHIP_RADEON_QG:
393 /* all original radeons (7200) presumably have a stencil op bug */
394 screen->chip_family = CHIP_FAMILY_R100;
395 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
396 break;
397
398 case PCI_CHIP_RV200_QW:
399 case PCI_CHIP_RV200_QX:
400 case PCI_CHIP_RADEON_LW:
401 case PCI_CHIP_RADEON_LX:
402 screen->chip_family = CHIP_FAMILY_RV200;
403 screen->chip_flags = RADEON_CHIPSET_TCL;
404 break;
405
406 case PCI_CHIP_R200_BB:
407 case PCI_CHIP_R200_BC:
408 case PCI_CHIP_R200_QH:
409 case PCI_CHIP_R200_QL:
410 case PCI_CHIP_R200_QM:
411 screen->chip_family = CHIP_FAMILY_R200;
412 screen->chip_flags = RADEON_CHIPSET_TCL;
413 break;
414
415 case PCI_CHIP_RV250_If:
416 case PCI_CHIP_RV250_Ig:
417 case PCI_CHIP_RV250_Ld:
418 case PCI_CHIP_RV250_Lf:
419 case PCI_CHIP_RV250_Lg:
420 screen->chip_family = CHIP_FAMILY_RV250;
421 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
422 break;
423
424 case PCI_CHIP_RV280_5960:
425 case PCI_CHIP_RV280_5961:
426 case PCI_CHIP_RV280_5962:
427 case PCI_CHIP_RV280_5964:
428 case PCI_CHIP_RV280_5965:
429 case PCI_CHIP_RV280_5C61:
430 case PCI_CHIP_RV280_5C63:
431 screen->chip_family = CHIP_FAMILY_RV280;
432 screen->chip_flags = RADEON_CHIPSET_TCL;
433 break;
434
435 case PCI_CHIP_RS300_5834:
436 case PCI_CHIP_RS300_5835:
437 case PCI_CHIP_RS350_7834:
438 case PCI_CHIP_RS350_7835:
439 screen->chip_family = CHIP_FAMILY_RS300;
440 break;
441
442 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
443 case PCI_CHIP_R300_AD:
444 screen->chip_family = CHIP_FAMILY_RV350;
445 screen->chip_flags = RADEON_CHIPSET_TCL;
446 break;
447 case PCI_CHIP_R300_AE:
448 case PCI_CHIP_R300_AF:
449 case PCI_CHIP_R300_AG:
450 case PCI_CHIP_R300_ND:
451 case PCI_CHIP_R300_NE:
452 case PCI_CHIP_R300_NF:
453 case PCI_CHIP_R300_NG:
454 screen->chip_family = CHIP_FAMILY_R300;
455 screen->chip_flags = RADEON_CHIPSET_TCL;
456 break;
457
458 case PCI_CHIP_RV350_AP:
459 case PCI_CHIP_RV350_AQ:
460 case PCI_CHIP_RV350_AR:
461 case PCI_CHIP_RV350_AS:
462 case PCI_CHIP_RV350_AT:
463 case PCI_CHIP_RV350_AV:
464 case PCI_CHIP_RV350_AU:
465 case PCI_CHIP_RV350_NP:
466 case PCI_CHIP_RV350_NQ:
467 case PCI_CHIP_RV350_NR:
468 case PCI_CHIP_RV350_NS:
469 case PCI_CHIP_RV350_NT:
470 case PCI_CHIP_RV350_NV:
471 screen->chip_family = CHIP_FAMILY_RV350;
472 screen->chip_flags = RADEON_CHIPSET_TCL;
473 break;
474
475 case PCI_CHIP_R350_AH:
476 case PCI_CHIP_R350_AI:
477 case PCI_CHIP_R350_AJ:
478 case PCI_CHIP_R350_AK:
479 case PCI_CHIP_R350_NH:
480 case PCI_CHIP_R350_NI:
481 case PCI_CHIP_R360_NJ:
482 case PCI_CHIP_R350_NK:
483 screen->chip_family = CHIP_FAMILY_R350;
484 screen->chip_flags = RADEON_CHIPSET_TCL;
485 break;
486
487 case PCI_CHIP_RV370_5460:
488 case PCI_CHIP_RV370_5462:
489 case PCI_CHIP_RV370_5464:
490 case PCI_CHIP_RV370_5B60:
491 case PCI_CHIP_RV370_5B62:
492 case PCI_CHIP_RV370_5B63:
493 case PCI_CHIP_RV370_5B64:
494 case PCI_CHIP_RV370_5B65:
495 case PCI_CHIP_RV380_3150:
496 case PCI_CHIP_RV380_3152:
497 case PCI_CHIP_RV380_3154:
498 case PCI_CHIP_RV380_3E50:
499 case PCI_CHIP_RV380_3E54:
500 screen->chip_family = CHIP_FAMILY_RV380;
501 screen->chip_flags = RADEON_CHIPSET_TCL;
502 break;
503
504 case PCI_CHIP_R420_JN:
505 case PCI_CHIP_R420_JH:
506 case PCI_CHIP_R420_JI:
507 case PCI_CHIP_R420_JJ:
508 case PCI_CHIP_R420_JK:
509 case PCI_CHIP_R420_JL:
510 case PCI_CHIP_R420_JM:
511 case PCI_CHIP_R420_JO:
512 case PCI_CHIP_R420_JP:
513 case PCI_CHIP_R420_JT:
514 case PCI_CHIP_R481_4B49:
515 case PCI_CHIP_R481_4B4A:
516 case PCI_CHIP_R481_4B4B:
517 case PCI_CHIP_R481_4B4C:
518 case PCI_CHIP_R423_UH:
519 case PCI_CHIP_R423_UI:
520 case PCI_CHIP_R423_UJ:
521 case PCI_CHIP_R423_UK:
522 case PCI_CHIP_R430_554C:
523 case PCI_CHIP_R430_554D:
524 case PCI_CHIP_R430_554E:
525 case PCI_CHIP_R430_554F:
526 case PCI_CHIP_R423_5550:
527 case PCI_CHIP_R423_UQ:
528 case PCI_CHIP_R423_UR:
529 case PCI_CHIP_R423_UT:
530 case PCI_CHIP_R430_5D48:
531 case PCI_CHIP_R430_5D49:
532 case PCI_CHIP_R430_5D4A:
533 case PCI_CHIP_R480_5D4C:
534 case PCI_CHIP_R480_5D4D:
535 case PCI_CHIP_R480_5D4E:
536 case PCI_CHIP_R480_5D4F:
537 case PCI_CHIP_R480_5D50:
538 case PCI_CHIP_R480_5D52:
539 case PCI_CHIP_R423_5D57:
540 screen->chip_family = CHIP_FAMILY_R420;
541 screen->chip_flags = RADEON_CHIPSET_TCL;
542 break;
543
544 case PCI_CHIP_RV410_5E4C:
545 case PCI_CHIP_RV410_5E4F:
546 case PCI_CHIP_RV410_564A:
547 case PCI_CHIP_RV410_564B:
548 case PCI_CHIP_RV410_564F:
549 case PCI_CHIP_RV410_5652:
550 case PCI_CHIP_RV410_5653:
551 case PCI_CHIP_RV410_5657:
552 case PCI_CHIP_RV410_5E48:
553 case PCI_CHIP_RV410_5E4A:
554 case PCI_CHIP_RV410_5E4B:
555 case PCI_CHIP_RV410_5E4D:
556 screen->chip_family = CHIP_FAMILY_RV410;
557 screen->chip_flags = RADEON_CHIPSET_TCL;
558 break;
559
560 case PCI_CHIP_RS480_5954:
561 case PCI_CHIP_RS480_5955:
562 case PCI_CHIP_RS482_5974:
563 case PCI_CHIP_RS482_5975:
564 case PCI_CHIP_RS400_5A41:
565 case PCI_CHIP_RS400_5A42:
566 case PCI_CHIP_RC410_5A61:
567 case PCI_CHIP_RC410_5A62:
568 screen->chip_family = CHIP_FAMILY_RS400;
569 break;
570
571 case PCI_CHIP_RS690_791E:
572 case PCI_CHIP_RS690_791F:
573 screen->chip_family = CHIP_FAMILY_RS690;
574 break;
575 case PCI_CHIP_RS740_796C:
576 case PCI_CHIP_RS740_796D:
577 case PCI_CHIP_RS740_796E:
578 case PCI_CHIP_RS740_796F:
579 screen->chip_family = CHIP_FAMILY_RS740;
580 break;
581
582 case PCI_CHIP_R520_7100:
583 case PCI_CHIP_R520_7101:
584 case PCI_CHIP_R520_7102:
585 case PCI_CHIP_R520_7103:
586 case PCI_CHIP_R520_7104:
587 case PCI_CHIP_R520_7105:
588 case PCI_CHIP_R520_7106:
589 case PCI_CHIP_R520_7108:
590 case PCI_CHIP_R520_7109:
591 case PCI_CHIP_R520_710A:
592 case PCI_CHIP_R520_710B:
593 case PCI_CHIP_R520_710C:
594 case PCI_CHIP_R520_710E:
595 case PCI_CHIP_R520_710F:
596 screen->chip_family = CHIP_FAMILY_R520;
597 screen->chip_flags = RADEON_CHIPSET_TCL;
598 break;
599
600 case PCI_CHIP_RV515_7140:
601 case PCI_CHIP_RV515_7141:
602 case PCI_CHIP_RV515_7142:
603 case PCI_CHIP_RV515_7143:
604 case PCI_CHIP_RV515_7144:
605 case PCI_CHIP_RV515_7145:
606 case PCI_CHIP_RV515_7146:
607 case PCI_CHIP_RV515_7147:
608 case PCI_CHIP_RV515_7149:
609 case PCI_CHIP_RV515_714A:
610 case PCI_CHIP_RV515_714B:
611 case PCI_CHIP_RV515_714C:
612 case PCI_CHIP_RV515_714D:
613 case PCI_CHIP_RV515_714E:
614 case PCI_CHIP_RV515_714F:
615 case PCI_CHIP_RV515_7151:
616 case PCI_CHIP_RV515_7152:
617 case PCI_CHIP_RV515_7153:
618 case PCI_CHIP_RV515_715E:
619 case PCI_CHIP_RV515_715F:
620 case PCI_CHIP_RV515_7180:
621 case PCI_CHIP_RV515_7181:
622 case PCI_CHIP_RV515_7183:
623 case PCI_CHIP_RV515_7186:
624 case PCI_CHIP_RV515_7187:
625 case PCI_CHIP_RV515_7188:
626 case PCI_CHIP_RV515_718A:
627 case PCI_CHIP_RV515_718B:
628 case PCI_CHIP_RV515_718C:
629 case PCI_CHIP_RV515_718D:
630 case PCI_CHIP_RV515_718F:
631 case PCI_CHIP_RV515_7193:
632 case PCI_CHIP_RV515_7196:
633 case PCI_CHIP_RV515_719B:
634 case PCI_CHIP_RV515_719F:
635 case PCI_CHIP_RV515_7200:
636 case PCI_CHIP_RV515_7210:
637 case PCI_CHIP_RV515_7211:
638 screen->chip_family = CHIP_FAMILY_RV515;
639 screen->chip_flags = RADEON_CHIPSET_TCL;
640 break;
641
642 case PCI_CHIP_RV530_71C0:
643 case PCI_CHIP_RV530_71C1:
644 case PCI_CHIP_RV530_71C2:
645 case PCI_CHIP_RV530_71C3:
646 case PCI_CHIP_RV530_71C4:
647 case PCI_CHIP_RV530_71C5:
648 case PCI_CHIP_RV530_71C6:
649 case PCI_CHIP_RV530_71C7:
650 case PCI_CHIP_RV530_71CD:
651 case PCI_CHIP_RV530_71CE:
652 case PCI_CHIP_RV530_71D2:
653 case PCI_CHIP_RV530_71D4:
654 case PCI_CHIP_RV530_71D5:
655 case PCI_CHIP_RV530_71D6:
656 case PCI_CHIP_RV530_71DA:
657 case PCI_CHIP_RV530_71DE:
658 screen->chip_family = CHIP_FAMILY_RV530;
659 screen->chip_flags = RADEON_CHIPSET_TCL;
660 break;
661
662 case PCI_CHIP_R580_7240:
663 case PCI_CHIP_R580_7243:
664 case PCI_CHIP_R580_7244:
665 case PCI_CHIP_R580_7245:
666 case PCI_CHIP_R580_7246:
667 case PCI_CHIP_R580_7247:
668 case PCI_CHIP_R580_7248:
669 case PCI_CHIP_R580_7249:
670 case PCI_CHIP_R580_724A:
671 case PCI_CHIP_R580_724B:
672 case PCI_CHIP_R580_724C:
673 case PCI_CHIP_R580_724D:
674 case PCI_CHIP_R580_724E:
675 case PCI_CHIP_R580_724F:
676 case PCI_CHIP_R580_7284:
677 screen->chip_family = CHIP_FAMILY_R580;
678 screen->chip_flags = RADEON_CHIPSET_TCL;
679 break;
680
681 case PCI_CHIP_RV570_7280:
682 case PCI_CHIP_RV560_7281:
683 case PCI_CHIP_RV560_7283:
684 case PCI_CHIP_RV560_7287:
685 case PCI_CHIP_RV570_7288:
686 case PCI_CHIP_RV570_7289:
687 case PCI_CHIP_RV570_728B:
688 case PCI_CHIP_RV570_728C:
689 case PCI_CHIP_RV560_7290:
690 case PCI_CHIP_RV560_7291:
691 case PCI_CHIP_RV560_7293:
692 case PCI_CHIP_RV560_7297:
693 screen->chip_family = CHIP_FAMILY_RV560;
694 screen->chip_flags = RADEON_CHIPSET_TCL;
695 break;
696
697 default:
698 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
699 device_id);
700 return -1;
701 }
702
703 return 0;
704 }
705
706
707 /* Create the device specific screen private data struct.
708 */
709 static radeonScreenPtr
710 radeonCreateScreen( __DRIscreenPrivate *sPriv )
711 {
712 radeonScreenPtr screen;
713 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
714 unsigned char *RADEONMMIO = NULL;
715 int i;
716 int ret;
717 uint32_t temp;
718
719 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
720 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
721 return GL_FALSE;
722 }
723
724 /* Allocate the private area */
725 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
726 if ( !screen ) {
727 __driUtilMessage("%s: Could not allocate memory for screen structure",
728 __FUNCTION__);
729 return NULL;
730 }
731
732 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
733 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
734 #endif
735
736 /* parse information in __driConfigOptions */
737 driParseOptionInfo (&screen->optionCache,
738 __driConfigOptions, __driNConfigOptions);
739
740 /* This is first since which regions we map depends on whether or
741 * not we are using a PCI card.
742 */
743 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
744 {
745 int ret;
746
747 #ifdef RADEON_PARAM_KERNEL_MM
748 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
749 &screen->kernel_mm);
750
751 if (ret && ret != -EINVAL) {
752 FREE( screen );
753 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
754 return NULL;
755 }
756
757 if (ret == -EINVAL)
758 screen->kernel_mm = 0;
759 #endif
760
761 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
762 &screen->gart_buffer_offset);
763
764 if (ret) {
765 FREE( screen );
766 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
767 return NULL;
768 }
769
770 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
771 &screen->gart_base);
772 if (ret) {
773 FREE( screen );
774 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
775 return NULL;
776 }
777
778 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
779 &screen->irq);
780 if (ret) {
781 FREE( screen );
782 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
783 return NULL;
784 }
785 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
786 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
787 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
788 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
789 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
790 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
791 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
792 }
793
794 if (!screen->kernel_mm) {
795 screen->mmio.handle = dri_priv->registerHandle;
796 screen->mmio.size = dri_priv->registerSize;
797 if ( drmMap( sPriv->fd,
798 screen->mmio.handle,
799 screen->mmio.size,
800 &screen->mmio.map ) ) {
801 FREE( screen );
802 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
803 return NULL;
804 }
805
806 RADEONMMIO = screen->mmio.map;
807
808 screen->status.handle = dri_priv->statusHandle;
809 screen->status.size = dri_priv->statusSize;
810 if ( drmMap( sPriv->fd,
811 screen->status.handle,
812 screen->status.size,
813 &screen->status.map ) ) {
814 drmUnmap( screen->mmio.map, screen->mmio.size );
815 FREE( screen );
816 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
817 return NULL;
818 }
819 screen->scratch = (__volatile__ uint32_t *)
820 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
821
822 screen->buffers = drmMapBufs( sPriv->fd );
823 if ( !screen->buffers ) {
824 drmUnmap( screen->status.map, screen->status.size );
825 drmUnmap( screen->mmio.map, screen->mmio.size );
826 FREE( screen );
827 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
828 return NULL;
829 }
830
831 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
832 screen->gartTextures.handle = dri_priv->gartTexHandle;
833 screen->gartTextures.size = dri_priv->gartTexMapSize;
834 if ( drmMap( sPriv->fd,
835 screen->gartTextures.handle,
836 screen->gartTextures.size,
837 (drmAddressPtr)&screen->gartTextures.map ) ) {
838 drmUnmapBufs( screen->buffers );
839 drmUnmap( screen->status.map, screen->status.size );
840 drmUnmap( screen->mmio.map, screen->mmio.size );
841 FREE( screen );
842 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
843 return NULL;
844 }
845
846 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
847 }
848 }
849
850
851 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
852 if (ret == -1)
853 return NULL;
854
855 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
856 sPriv->ddx_version.minor < 2) {
857 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
858 return NULL;
859 }
860
861 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
862 fprintf(stderr, "R500 support requires a newer drm.\n");
863 return NULL;
864 }
865
866 if (getenv("R300_NO_TCL"))
867 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
868
869 if (screen->chip_family <= CHIP_FAMILY_RS200)
870 screen->chip_flags |= RADEON_CLASS_R100;
871 else if (screen->chip_family <= CHIP_FAMILY_RV280)
872 screen->chip_flags |= RADEON_CLASS_R200;
873 else
874 screen->chip_flags |= RADEON_CLASS_R300;
875
876 screen->cpp = dri_priv->bpp / 8;
877 screen->AGPMode = dri_priv->AGPMode;
878
879 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
880 &temp);
881 if (ret) {
882 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm)
883 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
884 else {
885 FREE( screen );
886 fprintf(stderr, "Unable to get fb location need newer drm\n");
887 return NULL;
888 }
889 } else {
890 screen->fbLocation = (temp & 0xffff) << 16;
891 }
892
893 if (screen->chip_family >= CHIP_FAMILY_RV515) {
894 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
895 &temp);
896 if (ret) {
897 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
898 switch (screen->chip_family) {
899 case CHIP_FAMILY_R300:
900 case CHIP_FAMILY_R350:
901 screen->num_gb_pipes = 2;
902 break;
903 case CHIP_FAMILY_R420:
904 case CHIP_FAMILY_R520:
905 case CHIP_FAMILY_R580:
906 case CHIP_FAMILY_RV560:
907 case CHIP_FAMILY_RV570:
908 screen->num_gb_pipes = 4;
909 break;
910 case CHIP_FAMILY_RV350:
911 case CHIP_FAMILY_RV515:
912 case CHIP_FAMILY_RV530:
913 case CHIP_FAMILY_RV410:
914 default:
915 screen->num_gb_pipes = 1;
916 break;
917 }
918 } else {
919 screen->num_gb_pipes = temp;
920 }
921 }
922
923 if ( sPriv->drm_version.minor >= 10 ) {
924 drm_radeon_setparam_t sp;
925
926 sp.param = RADEON_SETPARAM_FB_LOCATION;
927 sp.value = screen->fbLocation;
928
929 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
930 &sp, sizeof( sp ) );
931 }
932
933 screen->frontOffset = dri_priv->frontOffset;
934 screen->frontPitch = dri_priv->frontPitch;
935 screen->backOffset = dri_priv->backOffset;
936 screen->backPitch = dri_priv->backPitch;
937 screen->depthOffset = dri_priv->depthOffset;
938 screen->depthPitch = dri_priv->depthPitch;
939
940 /* Check if ddx has set up a surface reg to cover depth buffer */
941 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
942 /* these chips don't use tiled z without hyperz. So always pretend
943 we have set up a surface which will cause linear reads/writes */
944 (IS_R100_CLASS(screen) &&
945 !(screen->chip_flags & RADEON_CHIPSET_TCL));
946
947 if ( dri_priv->textureSize == 0 ) {
948 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
949 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
950 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
951 dri_priv->log2GARTTexGran;
952 } else {
953 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
954 + screen->fbLocation;
955 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
956 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
957 dri_priv->log2TexGran;
958 }
959
960 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
961 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
962 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
963 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
964 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
965 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
966 } else {
967 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
968 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
969 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
970 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
971 dri_priv->log2GARTTexGran;
972 }
973
974 i = 0;
975 screen->extensions[i++] = &driCopySubBufferExtension.base;
976 screen->extensions[i++] = &driFrameTrackingExtension.base;
977 screen->extensions[i++] = &driReadDrawableExtension;
978
979 if ( screen->irq != 0 ) {
980 screen->extensions[i++] = &driSwapControlExtension.base;
981 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
982 }
983
984 #if !RADEON_COMMON
985 screen->extensions[i++] = &radeonTexOffsetExtension.base;
986 #endif
987
988 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
989 if (IS_R200_CLASS(screen))
990 screen->extensions[i++] = &r200AllocateExtension.base;
991
992 screen->extensions[i++] = &r200texOffsetExtension.base;
993 #endif
994
995 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
996 //screen->extensions[i++] = &r300texOffsetExtension.base;
997 #endif
998
999 screen->extensions[i++] = NULL;
1000 sPriv->extensions = screen->extensions;
1001
1002 screen->driScreen = sPriv;
1003 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1004 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1005 screen->sarea_priv_offset);
1006
1007 if (screen->kernel_mm)
1008 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1009 else
1010 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1011 if (screen->bom == NULL) {
1012 free(screen);
1013 return NULL;
1014 }
1015
1016 return screen;
1017 }
1018
1019 static radeonScreenPtr
1020 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1021 {
1022 radeonScreenPtr screen;
1023 int i;
1024 int ret;
1025 uint32_t device_id;
1026
1027 /* Allocate the private area */
1028 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1029 if ( !screen ) {
1030 __driUtilMessage("%s: Could not allocate memory for screen structure",
1031 __FUNCTION__);
1032 fprintf(stderr, "leaving here\n");
1033 return NULL;
1034 }
1035
1036 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1037 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1038 #endif
1039
1040 /* parse information in __driConfigOptions */
1041 driParseOptionInfo (&screen->optionCache,
1042 __driConfigOptions, __driNConfigOptions);
1043
1044 screen->kernel_mm = 1;
1045 screen->chip_flags = 0;
1046
1047 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
1048 &screen->irq);
1049
1050 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
1051 &device_id);
1052 if (ret) {
1053 FREE( screen );
1054 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1055 return NULL;
1056 }
1057
1058 ret = radeon_set_screen_flags(screen, device_id);
1059 if (ret == -1)
1060 return NULL;
1061
1062 if (screen->chip_family <= CHIP_FAMILY_RS200)
1063 screen->chip_flags |= RADEON_CLASS_R100;
1064 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1065 screen->chip_flags |= RADEON_CLASS_R200;
1066 else
1067 screen->chip_flags |= RADEON_CLASS_R300;
1068
1069 i = 0;
1070 screen->extensions[i++] = &driCopySubBufferExtension.base;
1071 screen->extensions[i++] = &driFrameTrackingExtension.base;
1072 screen->extensions[i++] = &driReadDrawableExtension;
1073
1074 if ( screen->irq != 0 ) {
1075 screen->extensions[i++] = &driSwapControlExtension.base;
1076 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1077 }
1078
1079 #if !RADEON_COMMON
1080 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1081 #endif
1082
1083 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1084 if (IS_R200_CLASS(screen))
1085 screen->extensions[i++] = &r200AllocateExtension.base;
1086
1087 screen->extensions[i++] = &r200texOffsetExtension.base;
1088 #endif
1089
1090 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1091 screen->extensions[i++] = &r300texOffsetExtension.base;
1092 screen->extensions[i++] = &r300TexBufferExtension.base;
1093 #endif
1094
1095 screen->extensions[i++] = NULL;
1096 sPriv->extensions = screen->extensions;
1097
1098 screen->driScreen = sPriv;
1099 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1100 if (screen->bom == NULL) {
1101 free(screen);
1102 return NULL;
1103 }
1104 return screen;
1105 }
1106
1107 /* Destroy the device specific screen private data struct.
1108 */
1109 static void
1110 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1111 {
1112 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1113
1114 if (!screen)
1115 return;
1116
1117 if (screen->kernel_mm) {
1118 #ifdef RADEON_BO_TRACK
1119 radeon_tracker_print(&screen->bom->tracker, stderr);
1120 #endif
1121 radeon_bo_manager_gem_dtor(screen->bom);
1122 } else {
1123 radeon_bo_manager_legacy_dtor(screen->bom);
1124
1125 if ( screen->gartTextures.map ) {
1126 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1127 }
1128 drmUnmapBufs( screen->buffers );
1129 drmUnmap( screen->status.map, screen->status.size );
1130 drmUnmap( screen->mmio.map, screen->mmio.size );
1131 }
1132
1133 /* free all option information */
1134 driDestroyOptionInfo (&screen->optionCache);
1135
1136 FREE( screen );
1137 sPriv->private = NULL;
1138 }
1139
1140
1141 /* Initialize the driver specific screen private data.
1142 */
1143 static GLboolean
1144 radeonInitDriver( __DRIscreenPrivate *sPriv )
1145 {
1146 if (sPriv->dri2.enabled) {
1147 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1148 } else {
1149 sPriv->private = (void *) radeonCreateScreen( sPriv );
1150 }
1151 if ( !sPriv->private ) {
1152 radeonDestroyScreen( sPriv );
1153 return GL_FALSE;
1154 }
1155
1156 return GL_TRUE;
1157 }
1158
1159 static GLboolean
1160 radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1161 GLenum intFormat, GLuint w, GLuint h)
1162 {
1163 rb->Width = w;
1164 rb->Height = h;
1165 rb->_ActualFormat = intFormat;
1166
1167 return GL_TRUE;
1168 }
1169
1170
1171 static struct radeon_renderbuffer *
1172 radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1173 {
1174 struct radeon_renderbuffer *ret;
1175
1176 ret = CALLOC_STRUCT(radeon_renderbuffer);
1177 if (!ret)
1178 return NULL;
1179
1180 _mesa_init_renderbuffer(&ret->base, 0);
1181
1182 /* XXX format junk */
1183 switch (format) {
1184 case GL_RGB5:
1185 ret->base._ActualFormat = GL_RGB5;
1186 ret->base._BaseFormat = GL_RGBA;
1187 ret->base.RedBits = 5;
1188 ret->base.GreenBits = 6;
1189 ret->base.BlueBits = 5;
1190 ret->base.DataType = GL_UNSIGNED_BYTE;
1191 break;
1192 case GL_RGBA8:
1193 ret->base._ActualFormat = GL_RGBA8;
1194 ret->base._BaseFormat = GL_RGBA;
1195 ret->base.RedBits = 8;
1196 ret->base.GreenBits = 8;
1197 ret->base.BlueBits = 8;
1198 ret->base.AlphaBits = 8;
1199 ret->base.DataType = GL_UNSIGNED_BYTE;
1200 break;
1201 case GL_STENCIL_INDEX8_EXT:
1202 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1203 ret->base._BaseFormat = GL_STENCIL_INDEX;
1204 ret->base.StencilBits = 8;
1205 ret->base.DataType = GL_UNSIGNED_BYTE;
1206 break;
1207 case GL_DEPTH_COMPONENT16:
1208 ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1209 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1210 ret->base.DepthBits = 16;
1211 ret->base.DataType = GL_UNSIGNED_SHORT;
1212 break;
1213 case GL_DEPTH_COMPONENT24:
1214 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1215 ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1216 ret->base.DepthBits = 24;
1217 ret->base.DataType = GL_UNSIGNED_INT;
1218 break;
1219 case GL_DEPTH24_STENCIL8_EXT:
1220 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1221 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1222 ret->base.DepthBits = 24;
1223 ret->base.StencilBits = 8;
1224 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1225 break;
1226 default:
1227 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1228 _mesa_delete_renderbuffer(&ret->base);
1229 return NULL;
1230 }
1231
1232 ret->dPriv = driDrawPriv;
1233 ret->base.InternalFormat = format;
1234
1235 ret->base.AllocStorage = radeon_alloc_window_storage;
1236
1237 radeonSetSpanFunctions(ret);
1238
1239 ret->bo = NULL;
1240 return ret;
1241 }
1242
1243 /**
1244 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1245 *
1246 * \todo This function (and its interface) will need to be updated to support
1247 * pbuffers.
1248 */
1249 static GLboolean
1250 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1251 __DRIdrawablePrivate *driDrawPriv,
1252 const __GLcontextModes *mesaVis,
1253 GLboolean isPixmap )
1254 {
1255 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1256
1257 const GLboolean swDepth = GL_FALSE;
1258 const GLboolean swAlpha = GL_FALSE;
1259 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1260 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1261 mesaVis->depthBits != 24;
1262 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1263 GLenum depthFormat = GL_NONE;
1264 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1265
1266 if (mesaVis->depthBits == 16)
1267 depthFormat = GL_DEPTH_COMPONENT16;
1268 else if (mesaVis->depthBits == 24)
1269 depthFormat = GL_DEPTH_COMPONENT24;
1270
1271 /* front color renderbuffer */
1272 {
1273 struct radeon_renderbuffer *front =
1274 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1275 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
1276 front->has_surface = 1;
1277 }
1278
1279 /* back color renderbuffer */
1280 if (mesaVis->doubleBufferMode) {
1281 struct radeon_renderbuffer *back =
1282 radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1283 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
1284 back->has_surface = 1;
1285 }
1286
1287 /* depth renderbuffer */
1288 if (depthFormat != GL_NONE) {
1289 struct radeon_renderbuffer *depth =
1290 radeon_create_renderbuffer(depthFormat, driDrawPriv);
1291 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
1292 depth->has_surface = screen->depthHasSurface;
1293 }
1294
1295 /* stencil renderbuffer */
1296 if (mesaVis->stencilBits > 0 && !swStencil) {
1297 struct radeon_renderbuffer *stencil =
1298 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1299 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
1300 stencil->has_surface = screen->depthHasSurface;
1301 }
1302
1303 _mesa_add_soft_renderbuffers(fb,
1304 GL_FALSE, /* color */
1305 swDepth,
1306 swStencil,
1307 swAccum,
1308 swAlpha,
1309 GL_FALSE /* aux */);
1310 driDrawPriv->driverPrivate = (void *) fb;
1311
1312 return (driDrawPriv->driverPrivate != NULL);
1313 }
1314
1315 static void
1316 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1317 {
1318 struct radeon_renderbuffer *rb;
1319 GLframebuffer *fb;
1320
1321 fb = (void*)driDrawPriv->driverPrivate;
1322 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1323 if (rb && rb->bo) {
1324 radeon_bo_unref(rb->bo);
1325 rb->bo = NULL;
1326 }
1327 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1328 if (rb && rb->bo) {
1329 radeon_bo_unref(rb->bo);
1330 rb->bo = NULL;
1331 }
1332 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1333 if (rb && rb->bo) {
1334 radeon_bo_unref(rb->bo);
1335 rb->bo = NULL;
1336 }
1337 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1338 }
1339
1340 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1341 /**
1342 * Choose the appropriate CreateContext function based on the chipset.
1343 * Eventually, all drivers will go through this process.
1344 */
1345 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1346 __DRIcontextPrivate * driContextPriv,
1347 void *sharedContextPriv)
1348 {
1349 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1350 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1351
1352 if (IS_R300_CLASS(screen))
1353 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1354 return GL_FALSE;
1355 }
1356
1357 /**
1358 * Choose the appropriate DestroyContext function based on the chipset.
1359 */
1360 static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1361 {
1362 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1363
1364 if (IS_R300_CLASS(radeon->radeonScreen))
1365 return r300DestroyContext(driContextPriv);
1366 }
1367
1368
1369 #endif
1370
1371 /**
1372 * This is the driver specific part of the createNewScreen entry point.
1373 *
1374 * \todo maybe fold this into intelInitDriver
1375 *
1376 * \return the __GLcontextModes supported by this driver
1377 */
1378 static const __DRIconfig **
1379 radeonInitScreen(__DRIscreenPrivate *psp)
1380 {
1381 #if !RADEON_COMMON
1382 static const char *driver_name = "Radeon";
1383 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1384 static const __DRIversion dri_expected = { 4, 0, 0 };
1385 static const __DRIversion drm_expected = { 1, 6, 0 };
1386 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1387 static const char *driver_name = "R200";
1388 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1389 static const __DRIversion dri_expected = { 4, 0, 0 };
1390 static const __DRIversion drm_expected = { 1, 6, 0 };
1391 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1392 static const char *driver_name = "R300";
1393 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1394 static const __DRIversion dri_expected = { 4, 0, 0 };
1395 static const __DRIversion drm_expected = { 1, 24, 0 };
1396 #endif
1397 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1398
1399 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1400 &psp->dri_version, & dri_expected,
1401 &psp->ddx_version, & ddx_expected,
1402 &psp->drm_version, & drm_expected ) ) {
1403 return NULL;
1404 }
1405
1406 /* Calling driInitExtensions here, with a NULL context pointer,
1407 * does not actually enable the extensions. It just makes sure
1408 * that all the dispatch offsets for all the extensions that
1409 * *might* be enables are known. This is needed because the
1410 * dispatch offsets need to be known when _mesa_context_create
1411 * is called, but we can't enable the extensions until we have a
1412 * context pointer.
1413 *
1414 * Hello chicken. Hello egg. How are you two today?
1415 */
1416 driInitExtensions( NULL, card_extensions, GL_FALSE );
1417 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1418 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1419 driInitSingleExtension( NULL, ARB_vp_extension );
1420 driInitSingleExtension( NULL, NV_vp_extension );
1421 driInitSingleExtension( NULL, ATI_fs_extension );
1422 driInitExtensions( NULL, point_extensions, GL_FALSE );
1423 #endif
1424
1425 if (!radeonInitDriver(psp))
1426 return NULL;
1427
1428 /* for now fill in all modes */
1429 return radeonFillInModes( psp,
1430 dri_priv->bpp,
1431 (dri_priv->bpp == 16) ? 16 : 24,
1432 (dri_priv->bpp == 16) ? 0 : 8, 1);
1433 }
1434
1435 /**
1436 * This is the driver specific part of the createNewScreen entry point.
1437 * Called when using DRI2.
1438 *
1439 * \return the __GLcontextModes supported by this driver
1440 */
1441 static const
1442 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1443 {
1444 /* Calling driInitExtensions here, with a NULL context pointer,
1445 * does not actually enable the extensions. It just makes sure
1446 * that all the dispatch offsets for all the extensions that
1447 * *might* be enables are known. This is needed because the
1448 * dispatch offsets need to be known when _mesa_context_create
1449 * is called, but we can't enable the extensions until we have a
1450 * context pointer.
1451 *
1452 * Hello chicken. Hello egg. How are you two today?
1453 */
1454 driInitExtensions( NULL, card_extensions, GL_FALSE );
1455 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1456 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1457 driInitSingleExtension( NULL, ARB_vp_extension );
1458 driInitSingleExtension( NULL, NV_vp_extension );
1459 driInitSingleExtension( NULL, ATI_fs_extension );
1460 driInitExtensions( NULL, point_extensions, GL_FALSE );
1461 #endif
1462
1463 if (!radeonInitDriver(psp)) {
1464 return NULL;
1465 }
1466
1467 /* for now fill in all modes */
1468 return radeonFillInModes( psp, 24, 24, 8, 1);
1469 }
1470
1471 /**
1472 * Get information about previous buffer swaps.
1473 */
1474 static int
1475 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1476 {
1477 radeonContextPtr rmesa;
1478
1479 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1480 || (dPriv->driContextPriv->driverPrivate == NULL)
1481 || (sInfo == NULL) ) {
1482 return -1;
1483 }
1484
1485 rmesa = dPriv->driContextPriv->driverPrivate;
1486 sInfo->swap_count = rmesa->swap_count;
1487 sInfo->swap_ust = rmesa->swap_ust;
1488 sInfo->swap_missed_count = rmesa->swap_missed_count;
1489
1490 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1491 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1492 : 0.0;
1493
1494 return 0;
1495 }
1496
1497 #if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1498 const struct __DriverAPIRec driDriverAPI = {
1499 .InitScreen = radeonInitScreen,
1500 .DestroyScreen = radeonDestroyScreen,
1501 .CreateContext = radeonCreateContext,
1502 .DestroyContext = radeonDestroyContext,
1503 .CreateBuffer = radeonCreateBuffer,
1504 .DestroyBuffer = radeonDestroyBuffer,
1505 .SwapBuffers = radeonSwapBuffers,
1506 .MakeCurrent = radeonMakeCurrent,
1507 .UnbindContext = radeonUnbindContext,
1508 .GetSwapInfo = getSwapInfo,
1509 .GetDrawableMSC = driDrawableGetMSC32,
1510 .WaitForMSC = driWaitForMSC32,
1511 .WaitForSBC = NULL,
1512 .SwapBuffersMSC = NULL,
1513 .CopySubBuffer = radeonCopySubBuffer,
1514 /* DRI2 */
1515 .InitScreen2 = radeonInitScreen2,
1516 };
1517 #else
1518 const struct __DriverAPIRec driDriverAPI = {
1519 .InitScreen = radeonInitScreen,
1520 .DestroyScreen = radeonDestroyScreen,
1521 .CreateContext = r200CreateContext,
1522 .DestroyContext = r200DestroyContext,
1523 .CreateBuffer = radeonCreateBuffer,
1524 .DestroyBuffer = radeonDestroyBuffer,
1525 .SwapBuffers = radeonSwapBuffers,
1526 .MakeCurrent = radeonMakeCurrent,
1527 .UnbindContext = radeonUnbindContext,
1528 .GetSwapInfo = getSwapInfo,
1529 .GetDrawableMSC = driDrawableGetMSC32,
1530 .WaitForMSC = driWaitForMSC32,
1531 .WaitForSBC = NULL,
1532 .SwapBuffersMSC = NULL,
1533 .CopySubBuffer = radeonCopySubBuffer,
1534 };
1535 #endif
1536