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Initial pull of code from r6xx-r7xx-support branch
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_fragprog.h"
61 #include "r300_tex.h"
62 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
63 #include "r600_context.h"
64 #include "r700_fragprog.h"
65 #include "r700_tex.h"
66 #endif
67
68 #include "utils.h"
69 #include "vblank.h"
70 #include "drirenderbuffer.h"
71
72 #include "radeon_bocs_wrapper.h"
73
74 #include "GL/internal/dri_interface.h"
75
76 /* Radeon configuration
77 */
78 #include "xmlpool.h"
79
80 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
81 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
82 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
83 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
84 DRI_CONF_OPT_END
85
86 #if !RADEON_COMMON /* R100 */
87 PUBLIC const char __driConfigOptions[] =
88 DRI_CONF_BEGIN
89 DRI_CONF_SECTION_PERFORMANCE
90 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
91 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
92 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
93 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
94 DRI_CONF_HYPERZ(false)
95 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
96 DRI_CONF_SECTION_END
97 DRI_CONF_SECTION_QUALITY
98 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
99 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
100 DRI_CONF_NO_NEG_LOD_BIAS(false)
101 DRI_CONF_FORCE_S3TC_ENABLE(false)
102 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
103 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
104 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
105 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
106 DRI_CONF_SECTION_END
107 DRI_CONF_SECTION_DEBUG
108 DRI_CONF_NO_RAST(false)
109 DRI_CONF_SECTION_END
110 DRI_CONF_END;
111 static const GLuint __driNConfigOptions = 15;
112
113 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
114
115 PUBLIC const char __driConfigOptions[] =
116 DRI_CONF_BEGIN
117 DRI_CONF_SECTION_PERFORMANCE
118 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
119 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
120 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
121 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
122 DRI_CONF_HYPERZ(false)
123 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
124 DRI_CONF_SECTION_END
125 DRI_CONF_SECTION_QUALITY
126 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
127 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
128 DRI_CONF_NO_NEG_LOD_BIAS(false)
129 DRI_CONF_FORCE_S3TC_ENABLE(false)
130 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
131 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
132 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
133 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
134 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
135 DRI_CONF_SECTION_END
136 DRI_CONF_SECTION_DEBUG
137 DRI_CONF_NO_RAST(false)
138 DRI_CONF_SECTION_END
139 DRI_CONF_SECTION_SOFTWARE
140 DRI_CONF_NV_VERTEX_PROGRAM(false)
141 DRI_CONF_SECTION_END
142 DRI_CONF_END;
143 static const GLuint __driNConfigOptions = 17;
144
145 extern const struct dri_extension blend_extensions[];
146 extern const struct dri_extension ARB_vp_extension[];
147 extern const struct dri_extension NV_vp_extension[];
148 extern const struct dri_extension ATI_fs_extension[];
149 extern const struct dri_extension point_extensions[];
150
151 #elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
152
153 /* TODO: integrate these into xmlpool.h! */
154 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
155 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
156 DRI_CONF_DESC(en,"Number of texture image units") \
157 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
158 DRI_CONF_OPT_END
159
160 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
161 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
162 DRI_CONF_DESC(en,"Number of texture coordinate units") \
163 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
164 DRI_CONF_OPT_END
165
166
167
168 #define DRI_CONF_DISABLE_S3TC(def) \
169 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
170 DRI_CONF_DESC(en,"Disable S3TC compression") \
171 DRI_CONF_OPT_END
172
173 #define DRI_CONF_DISABLE_FALLBACK(def) \
174 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
175 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
176 DRI_CONF_OPT_END
177
178 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
179 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
180 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
181 DRI_CONF_OPT_END
182
183 #define DRI_CONF_FP_OPTIMIZATION(def) \
184 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
185 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
186 DRI_CONF_ENUM(0,"Optimize for Speed") \
187 DRI_CONF_ENUM(1,"Optimize for Quality") \
188 DRI_CONF_DESC_END \
189 DRI_CONF_OPT_END
190
191 PUBLIC const char __driConfigOptions[] =
192 DRI_CONF_BEGIN
193 DRI_CONF_SECTION_PERFORMANCE
194 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
195 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
196 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
197 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
198 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
199 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
200 DRI_CONF_DISABLE_FALLBACK(true)
201 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
202 DRI_CONF_SECTION_END
203 DRI_CONF_SECTION_QUALITY
204 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
205 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
206 DRI_CONF_FORCE_S3TC_ENABLE(false)
207 DRI_CONF_DISABLE_S3TC(false)
208 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
209 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
210 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
211 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
212 DRI_CONF_SECTION_END
213 DRI_CONF_SECTION_DEBUG
214 DRI_CONF_NO_RAST(false)
215 DRI_CONF_SECTION_END
216 DRI_CONF_END;
217 static const GLuint __driNConfigOptions = 17;
218
219 extern const struct dri_extension gl_20_extension[];
220
221 #ifndef RADEON_DEBUG
222
223 static const struct dri_debug_control debug_control[] = {
224 {"fall", DEBUG_FALLBACKS},
225 {"tex", DEBUG_TEXTURE},
226 {"ioctl", DEBUG_IOCTL},
227 {"prim", DEBUG_PRIMS},
228 {"vert", DEBUG_VERTS},
229 {"state", DEBUG_STATE},
230 {"code", DEBUG_CODEGEN},
231 {"vfmt", DEBUG_VFMT},
232 {"vtxf", DEBUG_VFMT},
233 {"verb", DEBUG_VERBOSE},
234 {"dri", DEBUG_DRI},
235 {"dma", DEBUG_DMA},
236 {"san", DEBUG_SANITY},
237 {"sync", DEBUG_SYNC},
238 {"pix", DEBUG_PIXEL},
239 {"mem", DEBUG_MEMORY},
240 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
241 {NULL, 0}
242 };
243 #endif /* RADEON_DEBUG */
244
245 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
246
247 extern const struct dri_extension card_extensions[];
248 extern const struct dri_extension mm_extensions[];
249
250 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
251
252 static int
253 radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)
254 {
255 int ret;
256 drm_radeon_getparam_t gp;
257 struct drm_radeon_info info;
258
259 if (sPriv->drm_version.major >= 2) {
260 info.value = (uint64_t)value;
261 switch (param) {
262 case RADEON_PARAM_DEVICE_ID:
263 info.request = RADEON_INFO_DEVICE_ID;
264 break;
265 case RADEON_PARAM_NUM_GB_PIPES:
266 info.request = RADEON_INFO_NUM_GB_PIPES;
267 break;
268 default:
269 return -EINVAL;
270 }
271 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
272 } else {
273 gp.param = param;
274 gp.value = value;
275
276 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
277 }
278 return ret;
279 }
280
281 static const __DRIconfig **
282 radeonFillInModes( __DRIscreenPrivate *psp,
283 unsigned pixel_bits, unsigned depth_bits,
284 unsigned stencil_bits, GLboolean have_back_buffer )
285 {
286 __DRIconfig **configs;
287 __GLcontextModes *m;
288 unsigned depth_buffer_factor;
289 unsigned back_buffer_factor;
290 int i;
291
292 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
293 * enough to add support. Basically, if a context is created with an
294 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
295 * will never be used.
296 */
297 static const GLenum back_buffer_modes[] = {
298 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
299 };
300
301 uint8_t depth_bits_array[2];
302 uint8_t stencil_bits_array[2];
303 uint8_t msaa_samples_array[1];
304
305 depth_bits_array[0] = depth_bits;
306 depth_bits_array[1] = depth_bits;
307
308 /* Just like with the accumulation buffer, always provide some modes
309 * with a stencil buffer. It will be a sw fallback, but some apps won't
310 * care about that.
311 */
312 stencil_bits_array[0] = 0;
313 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
314
315 msaa_samples_array[0] = 0;
316
317 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
318 back_buffer_factor = (have_back_buffer) ? 2 : 1;
319
320 if (pixel_bits == 16) {
321 __DRIconfig **configs_a8r8g8b8;
322 __DRIconfig **configs_r5g6b5;
323
324 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
325 depth_bits_array, stencil_bits_array,
326 depth_buffer_factor, back_buffer_modes,
327 back_buffer_factor, msaa_samples_array,
328 1);
329 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
330 depth_bits_array, stencil_bits_array,
331 1, back_buffer_modes, 1,
332 msaa_samples_array, 1);
333 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
334 } else
335 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
336 depth_bits_array, stencil_bits_array,
337 depth_buffer_factor,
338 back_buffer_modes, back_buffer_factor,
339 msaa_samples_array, 1);
340
341 if (configs == NULL) {
342 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
343 __func__, __LINE__ );
344 return NULL;
345 }
346
347 /* Mark the visual as slow if there are "fake" stencil bits.
348 */
349 for (i = 0; configs[i]; i++) {
350 m = &configs[i]->modes;
351 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
352 m->visualRating = GLX_SLOW_CONFIG;
353 }
354 }
355
356 return (const __DRIconfig **) configs;
357 }
358
359 #if !RADEON_COMMON
360 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
361 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
362 radeonSetTexOffset,
363 };
364
365 static const __DRItexBufferExtension radeonTexBufferExtension = {
366 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
367 radeonSetTexBuffer,
368 radeonSetTexBuffer2,
369 };
370 #endif
371
372 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
373 static const __DRIallocateExtension r200AllocateExtension = {
374 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
375 r200AllocateMemoryMESA,
376 r200FreeMemoryMESA,
377 r200GetMemoryOffsetMESA
378 };
379
380 static const __DRItexOffsetExtension r200texOffsetExtension = {
381 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
382 r200SetTexOffset,
383 };
384
385 static const __DRItexBufferExtension r200TexBufferExtension = {
386 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
387 r200SetTexBuffer,
388 r200SetTexBuffer2,
389 };
390 #endif
391
392 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
393 static const __DRItexOffsetExtension r300texOffsetExtension = {
394 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
395 r300SetTexOffset,
396 };
397
398 static const __DRItexBufferExtension r300TexBufferExtension = {
399 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
400 r300SetTexBuffer,
401 r300SetTexBuffer2,
402 };
403 #endif
404
405 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
406 static const __DRItexOffsetExtension r600texOffsetExtension = {
407 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
408 r700SetTexOffset,
409 };
410
411 static const __DRItexBufferExtension r600TexBufferExtension = {
412 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
413 r700SetTexBuffer,
414 r700SetTexBuffer2,
415 };
416 #endif
417
418 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
419 {
420 screen->chip_flags = 0;
421 switch ( device_id ) {
422 case PCI_CHIP_RADEON_LY:
423 case PCI_CHIP_RADEON_LZ:
424 case PCI_CHIP_RADEON_QY:
425 case PCI_CHIP_RADEON_QZ:
426 case PCI_CHIP_RN50_515E:
427 case PCI_CHIP_RN50_5969:
428 screen->chip_family = CHIP_FAMILY_RV100;
429 break;
430
431 case PCI_CHIP_RS100_4136:
432 case PCI_CHIP_RS100_4336:
433 screen->chip_family = CHIP_FAMILY_RS100;
434 break;
435
436 case PCI_CHIP_RS200_4137:
437 case PCI_CHIP_RS200_4337:
438 case PCI_CHIP_RS250_4237:
439 case PCI_CHIP_RS250_4437:
440 screen->chip_family = CHIP_FAMILY_RS200;
441 break;
442
443 case PCI_CHIP_RADEON_QD:
444 case PCI_CHIP_RADEON_QE:
445 case PCI_CHIP_RADEON_QF:
446 case PCI_CHIP_RADEON_QG:
447 /* all original radeons (7200) presumably have a stencil op bug */
448 screen->chip_family = CHIP_FAMILY_R100;
449 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
450 break;
451
452 case PCI_CHIP_RV200_QW:
453 case PCI_CHIP_RV200_QX:
454 case PCI_CHIP_RADEON_LW:
455 case PCI_CHIP_RADEON_LX:
456 screen->chip_family = CHIP_FAMILY_RV200;
457 screen->chip_flags = RADEON_CHIPSET_TCL;
458 break;
459
460 case PCI_CHIP_R200_BB:
461 case PCI_CHIP_R200_BC:
462 case PCI_CHIP_R200_QH:
463 case PCI_CHIP_R200_QL:
464 case PCI_CHIP_R200_QM:
465 screen->chip_family = CHIP_FAMILY_R200;
466 screen->chip_flags = RADEON_CHIPSET_TCL;
467 break;
468
469 case PCI_CHIP_RV250_If:
470 case PCI_CHIP_RV250_Ig:
471 case PCI_CHIP_RV250_Ld:
472 case PCI_CHIP_RV250_Lf:
473 case PCI_CHIP_RV250_Lg:
474 screen->chip_family = CHIP_FAMILY_RV250;
475 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
476 break;
477
478 case PCI_CHIP_RV280_5960:
479 case PCI_CHIP_RV280_5961:
480 case PCI_CHIP_RV280_5962:
481 case PCI_CHIP_RV280_5964:
482 case PCI_CHIP_RV280_5965:
483 case PCI_CHIP_RV280_5C61:
484 case PCI_CHIP_RV280_5C63:
485 screen->chip_family = CHIP_FAMILY_RV280;
486 screen->chip_flags = RADEON_CHIPSET_TCL;
487 break;
488
489 case PCI_CHIP_RS300_5834:
490 case PCI_CHIP_RS300_5835:
491 case PCI_CHIP_RS350_7834:
492 case PCI_CHIP_RS350_7835:
493 screen->chip_family = CHIP_FAMILY_RS300;
494 break;
495
496 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
497 case PCI_CHIP_R300_AD:
498 screen->chip_family = CHIP_FAMILY_RV350;
499 screen->chip_flags = RADEON_CHIPSET_TCL;
500 break;
501 case PCI_CHIP_R300_AE:
502 case PCI_CHIP_R300_AF:
503 case PCI_CHIP_R300_AG:
504 case PCI_CHIP_R300_ND:
505 case PCI_CHIP_R300_NE:
506 case PCI_CHIP_R300_NF:
507 case PCI_CHIP_R300_NG:
508 screen->chip_family = CHIP_FAMILY_R300;
509 screen->chip_flags = RADEON_CHIPSET_TCL;
510 break;
511
512 case PCI_CHIP_RV350_AP:
513 case PCI_CHIP_RV350_AQ:
514 case PCI_CHIP_RV350_AR:
515 case PCI_CHIP_RV350_AS:
516 case PCI_CHIP_RV350_AT:
517 case PCI_CHIP_RV350_AV:
518 case PCI_CHIP_RV350_AU:
519 case PCI_CHIP_RV350_NP:
520 case PCI_CHIP_RV350_NQ:
521 case PCI_CHIP_RV350_NR:
522 case PCI_CHIP_RV350_NS:
523 case PCI_CHIP_RV350_NT:
524 case PCI_CHIP_RV350_NV:
525 screen->chip_family = CHIP_FAMILY_RV350;
526 screen->chip_flags = RADEON_CHIPSET_TCL;
527 break;
528
529 case PCI_CHIP_R350_AH:
530 case PCI_CHIP_R350_AI:
531 case PCI_CHIP_R350_AJ:
532 case PCI_CHIP_R350_AK:
533 case PCI_CHIP_R350_NH:
534 case PCI_CHIP_R350_NI:
535 case PCI_CHIP_R360_NJ:
536 case PCI_CHIP_R350_NK:
537 screen->chip_family = CHIP_FAMILY_R350;
538 screen->chip_flags = RADEON_CHIPSET_TCL;
539 break;
540
541 case PCI_CHIP_RV370_5460:
542 case PCI_CHIP_RV370_5462:
543 case PCI_CHIP_RV370_5464:
544 case PCI_CHIP_RV370_5B60:
545 case PCI_CHIP_RV370_5B62:
546 case PCI_CHIP_RV370_5B63:
547 case PCI_CHIP_RV370_5B64:
548 case PCI_CHIP_RV370_5B65:
549 case PCI_CHIP_RV380_3150:
550 case PCI_CHIP_RV380_3152:
551 case PCI_CHIP_RV380_3154:
552 case PCI_CHIP_RV380_3E50:
553 case PCI_CHIP_RV380_3E54:
554 screen->chip_family = CHIP_FAMILY_RV380;
555 screen->chip_flags = RADEON_CHIPSET_TCL;
556 break;
557
558 case PCI_CHIP_R420_JN:
559 case PCI_CHIP_R420_JH:
560 case PCI_CHIP_R420_JI:
561 case PCI_CHIP_R420_JJ:
562 case PCI_CHIP_R420_JK:
563 case PCI_CHIP_R420_JL:
564 case PCI_CHIP_R420_JM:
565 case PCI_CHIP_R420_JO:
566 case PCI_CHIP_R420_JP:
567 case PCI_CHIP_R420_JT:
568 case PCI_CHIP_R481_4B49:
569 case PCI_CHIP_R481_4B4A:
570 case PCI_CHIP_R481_4B4B:
571 case PCI_CHIP_R481_4B4C:
572 case PCI_CHIP_R423_UH:
573 case PCI_CHIP_R423_UI:
574 case PCI_CHIP_R423_UJ:
575 case PCI_CHIP_R423_UK:
576 case PCI_CHIP_R430_554C:
577 case PCI_CHIP_R430_554D:
578 case PCI_CHIP_R430_554E:
579 case PCI_CHIP_R430_554F:
580 case PCI_CHIP_R423_5550:
581 case PCI_CHIP_R423_UQ:
582 case PCI_CHIP_R423_UR:
583 case PCI_CHIP_R423_UT:
584 case PCI_CHIP_R430_5D48:
585 case PCI_CHIP_R430_5D49:
586 case PCI_CHIP_R430_5D4A:
587 case PCI_CHIP_R480_5D4C:
588 case PCI_CHIP_R480_5D4D:
589 case PCI_CHIP_R480_5D4E:
590 case PCI_CHIP_R480_5D4F:
591 case PCI_CHIP_R480_5D50:
592 case PCI_CHIP_R480_5D52:
593 case PCI_CHIP_R423_5D57:
594 screen->chip_family = CHIP_FAMILY_R420;
595 screen->chip_flags = RADEON_CHIPSET_TCL;
596 break;
597
598 case PCI_CHIP_RV410_5E4C:
599 case PCI_CHIP_RV410_5E4F:
600 case PCI_CHIP_RV410_564A:
601 case PCI_CHIP_RV410_564B:
602 case PCI_CHIP_RV410_564F:
603 case PCI_CHIP_RV410_5652:
604 case PCI_CHIP_RV410_5653:
605 case PCI_CHIP_RV410_5657:
606 case PCI_CHIP_RV410_5E48:
607 case PCI_CHIP_RV410_5E4A:
608 case PCI_CHIP_RV410_5E4B:
609 case PCI_CHIP_RV410_5E4D:
610 screen->chip_family = CHIP_FAMILY_RV410;
611 screen->chip_flags = RADEON_CHIPSET_TCL;
612 break;
613
614 case PCI_CHIP_RS480_5954:
615 case PCI_CHIP_RS480_5955:
616 case PCI_CHIP_RS482_5974:
617 case PCI_CHIP_RS482_5975:
618 case PCI_CHIP_RS400_5A41:
619 case PCI_CHIP_RS400_5A42:
620 case PCI_CHIP_RC410_5A61:
621 case PCI_CHIP_RC410_5A62:
622 screen->chip_family = CHIP_FAMILY_RS400;
623 break;
624
625 case PCI_CHIP_RS600_793F:
626 case PCI_CHIP_RS600_7941:
627 case PCI_CHIP_RS600_7942:
628 screen->chip_family = CHIP_FAMILY_RS600;
629 break;
630
631 case PCI_CHIP_RS690_791E:
632 case PCI_CHIP_RS690_791F:
633 screen->chip_family = CHIP_FAMILY_RS690;
634 break;
635 case PCI_CHIP_RS740_796C:
636 case PCI_CHIP_RS740_796D:
637 case PCI_CHIP_RS740_796E:
638 case PCI_CHIP_RS740_796F:
639 screen->chip_family = CHIP_FAMILY_RS740;
640 break;
641
642 case PCI_CHIP_R520_7100:
643 case PCI_CHIP_R520_7101:
644 case PCI_CHIP_R520_7102:
645 case PCI_CHIP_R520_7103:
646 case PCI_CHIP_R520_7104:
647 case PCI_CHIP_R520_7105:
648 case PCI_CHIP_R520_7106:
649 case PCI_CHIP_R520_7108:
650 case PCI_CHIP_R520_7109:
651 case PCI_CHIP_R520_710A:
652 case PCI_CHIP_R520_710B:
653 case PCI_CHIP_R520_710C:
654 case PCI_CHIP_R520_710E:
655 case PCI_CHIP_R520_710F:
656 screen->chip_family = CHIP_FAMILY_R520;
657 screen->chip_flags = RADEON_CHIPSET_TCL;
658 break;
659
660 case PCI_CHIP_RV515_7140:
661 case PCI_CHIP_RV515_7141:
662 case PCI_CHIP_RV515_7142:
663 case PCI_CHIP_RV515_7143:
664 case PCI_CHIP_RV515_7144:
665 case PCI_CHIP_RV515_7145:
666 case PCI_CHIP_RV515_7146:
667 case PCI_CHIP_RV515_7147:
668 case PCI_CHIP_RV515_7149:
669 case PCI_CHIP_RV515_714A:
670 case PCI_CHIP_RV515_714B:
671 case PCI_CHIP_RV515_714C:
672 case PCI_CHIP_RV515_714D:
673 case PCI_CHIP_RV515_714E:
674 case PCI_CHIP_RV515_714F:
675 case PCI_CHIP_RV515_7151:
676 case PCI_CHIP_RV515_7152:
677 case PCI_CHIP_RV515_7153:
678 case PCI_CHIP_RV515_715E:
679 case PCI_CHIP_RV515_715F:
680 case PCI_CHIP_RV515_7180:
681 case PCI_CHIP_RV515_7181:
682 case PCI_CHIP_RV515_7183:
683 case PCI_CHIP_RV515_7186:
684 case PCI_CHIP_RV515_7187:
685 case PCI_CHIP_RV515_7188:
686 case PCI_CHIP_RV515_718A:
687 case PCI_CHIP_RV515_718B:
688 case PCI_CHIP_RV515_718C:
689 case PCI_CHIP_RV515_718D:
690 case PCI_CHIP_RV515_718F:
691 case PCI_CHIP_RV515_7193:
692 case PCI_CHIP_RV515_7196:
693 case PCI_CHIP_RV515_719B:
694 case PCI_CHIP_RV515_719F:
695 case PCI_CHIP_RV515_7200:
696 case PCI_CHIP_RV515_7210:
697 case PCI_CHIP_RV515_7211:
698 screen->chip_family = CHIP_FAMILY_RV515;
699 screen->chip_flags = RADEON_CHIPSET_TCL;
700 break;
701
702 case PCI_CHIP_RV530_71C0:
703 case PCI_CHIP_RV530_71C1:
704 case PCI_CHIP_RV530_71C2:
705 case PCI_CHIP_RV530_71C3:
706 case PCI_CHIP_RV530_71C4:
707 case PCI_CHIP_RV530_71C5:
708 case PCI_CHIP_RV530_71C6:
709 case PCI_CHIP_RV530_71C7:
710 case PCI_CHIP_RV530_71CD:
711 case PCI_CHIP_RV530_71CE:
712 case PCI_CHIP_RV530_71D2:
713 case PCI_CHIP_RV530_71D4:
714 case PCI_CHIP_RV530_71D5:
715 case PCI_CHIP_RV530_71D6:
716 case PCI_CHIP_RV530_71DA:
717 case PCI_CHIP_RV530_71DE:
718 screen->chip_family = CHIP_FAMILY_RV530;
719 screen->chip_flags = RADEON_CHIPSET_TCL;
720 break;
721
722 case PCI_CHIP_R580_7240:
723 case PCI_CHIP_R580_7243:
724 case PCI_CHIP_R580_7244:
725 case PCI_CHIP_R580_7245:
726 case PCI_CHIP_R580_7246:
727 case PCI_CHIP_R580_7247:
728 case PCI_CHIP_R580_7248:
729 case PCI_CHIP_R580_7249:
730 case PCI_CHIP_R580_724A:
731 case PCI_CHIP_R580_724B:
732 case PCI_CHIP_R580_724C:
733 case PCI_CHIP_R580_724D:
734 case PCI_CHIP_R580_724E:
735 case PCI_CHIP_R580_724F:
736 case PCI_CHIP_R580_7284:
737 screen->chip_family = CHIP_FAMILY_R580;
738 screen->chip_flags = RADEON_CHIPSET_TCL;
739 break;
740
741 case PCI_CHIP_RV570_7280:
742 case PCI_CHIP_RV560_7281:
743 case PCI_CHIP_RV560_7283:
744 case PCI_CHIP_RV560_7287:
745 case PCI_CHIP_RV570_7288:
746 case PCI_CHIP_RV570_7289:
747 case PCI_CHIP_RV570_728B:
748 case PCI_CHIP_RV570_728C:
749 case PCI_CHIP_RV560_7290:
750 case PCI_CHIP_RV560_7291:
751 case PCI_CHIP_RV560_7293:
752 case PCI_CHIP_RV560_7297:
753 screen->chip_family = CHIP_FAMILY_RV560;
754 screen->chip_flags = RADEON_CHIPSET_TCL;
755 break;
756
757 case PCI_CHIP_R600_9400:
758 case PCI_CHIP_R600_9401:
759 case PCI_CHIP_R600_9402:
760 case PCI_CHIP_R600_9403:
761 case PCI_CHIP_R600_9405:
762 case PCI_CHIP_R600_940A:
763 case PCI_CHIP_R600_940B:
764 case PCI_CHIP_R600_940F:
765 screen->chip_family = CHIP_FAMILY_R600;
766 screen->chip_flags = RADEON_CHIPSET_TCL;
767 break;
768
769 case PCI_CHIP_RV610_94C0:
770 case PCI_CHIP_RV610_94C1:
771 case PCI_CHIP_RV610_94C3:
772 case PCI_CHIP_RV610_94C4:
773 case PCI_CHIP_RV610_94C5:
774 case PCI_CHIP_RV610_94C6:
775 case PCI_CHIP_RV610_94C7:
776 case PCI_CHIP_RV610_94C8:
777 case PCI_CHIP_RV610_94C9:
778 case PCI_CHIP_RV610_94CB:
779 case PCI_CHIP_RV610_94CC:
780 case PCI_CHIP_RV610_94CD:
781 screen->chip_family = CHIP_FAMILY_RV610;
782 screen->chip_flags = RADEON_CHIPSET_TCL;
783 break;
784
785 case PCI_CHIP_RV630_9580:
786 case PCI_CHIP_RV630_9581:
787 case PCI_CHIP_RV630_9583:
788 case PCI_CHIP_RV630_9586:
789 case PCI_CHIP_RV630_9587:
790 case PCI_CHIP_RV630_9588:
791 case PCI_CHIP_RV630_9589:
792 case PCI_CHIP_RV630_958A:
793 case PCI_CHIP_RV630_958B:
794 case PCI_CHIP_RV630_958C:
795 case PCI_CHIP_RV630_958D:
796 case PCI_CHIP_RV630_958E:
797 case PCI_CHIP_RV630_958F:
798 screen->chip_family = CHIP_FAMILY_RV630;
799 screen->chip_flags = RADEON_CHIPSET_TCL;
800 break;
801
802 case PCI_CHIP_RV670_9500:
803 case PCI_CHIP_RV670_9501:
804 case PCI_CHIP_RV670_9504:
805 case PCI_CHIP_RV670_9505:
806 case PCI_CHIP_RV670_9506:
807 case PCI_CHIP_RV670_9507:
808 case PCI_CHIP_RV670_9508:
809 case PCI_CHIP_RV670_9509:
810 case PCI_CHIP_RV670_950F:
811 case PCI_CHIP_RV670_9511:
812 case PCI_CHIP_RV670_9515:
813 case PCI_CHIP_RV670_9517:
814 case PCI_CHIP_RV670_9519:
815 screen->chip_family = CHIP_FAMILY_RV670;
816 screen->chip_flags = RADEON_CHIPSET_TCL;
817 break;
818
819 case PCI_CHIP_RV620_95C0:
820 case PCI_CHIP_RV620_95C2:
821 case PCI_CHIP_RV620_95C4:
822 case PCI_CHIP_RV620_95C5:
823 case PCI_CHIP_RV620_95C6:
824 case PCI_CHIP_RV620_95C7:
825 case PCI_CHIP_RV620_95C9:
826 case PCI_CHIP_RV620_95CC:
827 case PCI_CHIP_RV620_95CD:
828 case PCI_CHIP_RV620_95CE:
829 case PCI_CHIP_RV620_95CF:
830 screen->chip_family = CHIP_FAMILY_RV620;
831 screen->chip_flags = RADEON_CHIPSET_TCL;
832 break;
833
834 case PCI_CHIP_RV635_9590:
835 case PCI_CHIP_RV635_9591:
836 case PCI_CHIP_RV635_9593:
837 case PCI_CHIP_RV635_9595:
838 case PCI_CHIP_RV635_9596:
839 case PCI_CHIP_RV635_9597:
840 case PCI_CHIP_RV635_9598:
841 case PCI_CHIP_RV635_9599:
842 case PCI_CHIP_RV635_959B:
843 screen->chip_family = CHIP_FAMILY_RV635;
844 screen->chip_flags = RADEON_CHIPSET_TCL;
845 break;
846
847 case PCI_CHIP_RS780_9611:
848 case PCI_CHIP_RS780_9612:
849 case PCI_CHIP_RS780_9613:
850 case PCI_CHIP_RS780_9614:
851 case PCI_CHIP_RS780_9615:
852 case PCI_CHIP_RS780_9616:
853 screen->chip_family = CHIP_FAMILY_RS780;
854 screen->chip_flags = RADEON_CHIPSET_TCL;
855 break;
856
857 case PCI_CHIP_RV770_9440:
858 case PCI_CHIP_RV770_9441:
859 case PCI_CHIP_RV770_9442:
860 case PCI_CHIP_RV770_9444:
861 case PCI_CHIP_RV770_9446:
862 case PCI_CHIP_RV770_944A:
863 case PCI_CHIP_RV770_944B:
864 case PCI_CHIP_RV770_944C:
865 case PCI_CHIP_RV770_944E:
866 case PCI_CHIP_RV770_9450:
867 case PCI_CHIP_RV770_9452:
868 case PCI_CHIP_RV770_9456:
869 case PCI_CHIP_RV770_945A:
870 case PCI_CHIP_RV770_945B:
871 case PCI_CHIP_RV790_9460:
872 case PCI_CHIP_RV790_9462:
873 case PCI_CHIP_RV770_946A:
874 case PCI_CHIP_RV770_946B:
875 case PCI_CHIP_RV770_947A:
876 case PCI_CHIP_RV770_947B:
877 screen->chip_family = CHIP_FAMILY_RV770;
878 screen->chip_flags = RADEON_CHIPSET_TCL;
879 break;
880
881 case PCI_CHIP_RV730_9487:
882 case PCI_CHIP_RV730_9489:
883 case PCI_CHIP_RV730_948F:
884 case PCI_CHIP_RV730_9490:
885 case PCI_CHIP_RV730_9491:
886 case PCI_CHIP_RV730_9498:
887 case PCI_CHIP_RV730_949C:
888 case PCI_CHIP_RV730_949E:
889 case PCI_CHIP_RV730_949F:
890 screen->chip_family = CHIP_FAMILY_RV730;
891 screen->chip_flags = RADEON_CHIPSET_TCL;
892 break;
893
894 case PCI_CHIP_RV710_9540:
895 case PCI_CHIP_RV710_9541:
896 case PCI_CHIP_RV710_9542:
897 case PCI_CHIP_RV710_954E:
898 case PCI_CHIP_RV710_954F:
899 case PCI_CHIP_RV710_9552:
900 case PCI_CHIP_RV710_9553:
901 case PCI_CHIP_RV710_9555:
902 screen->chip_family = CHIP_FAMILY_RV710;
903 screen->chip_flags = RADEON_CHIPSET_TCL;
904 break;
905
906 default:
907 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
908 device_id);
909 return -1;
910 }
911
912 return 0;
913 }
914
915
916 /* Create the device specific screen private data struct.
917 */
918 static radeonScreenPtr
919 radeonCreateScreen( __DRIscreenPrivate *sPriv )
920 {
921 radeonScreenPtr screen;
922 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
923 unsigned char *RADEONMMIO = NULL;
924 int i;
925 int ret;
926 uint32_t temp = 0;
927
928 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
929 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
930 return GL_FALSE;
931 }
932
933 /* Allocate the private area */
934 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
935 if ( !screen ) {
936 __driUtilMessage("%s: Could not allocate memory for screen structure",
937 __FUNCTION__);
938 return NULL;
939 }
940
941 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
942 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
943 #endif
944
945 /* parse information in __driConfigOptions */
946 driParseOptionInfo (&screen->optionCache,
947 __driConfigOptions, __driNConfigOptions);
948
949 /* This is first since which regions we map depends on whether or
950 * not we are using a PCI card.
951 */
952 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
953 {
954 int ret;
955
956 #ifdef RADEON_PARAM_KERNEL_MM
957 ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm);
958
959 if (ret && ret != -EINVAL) {
960 FREE( screen );
961 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
962 return NULL;
963 }
964
965 if (ret == -EINVAL)
966 screen->kernel_mm = 0;
967 #endif
968
969 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
970 &screen->gart_buffer_offset);
971
972 if (ret) {
973 FREE( screen );
974 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
975 return NULL;
976 }
977
978 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
979 &screen->gart_base);
980 if (ret) {
981 FREE( screen );
982 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
983 return NULL;
984 }
985
986 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
987 &screen->irq);
988 if (ret) {
989 FREE( screen );
990 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
991 return NULL;
992 }
993 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
994 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
995 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
996 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
997 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
998 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
999 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1000 }
1001
1002 if (!screen->kernel_mm) {
1003 screen->mmio.handle = dri_priv->registerHandle;
1004 screen->mmio.size = dri_priv->registerSize;
1005 if ( drmMap( sPriv->fd,
1006 screen->mmio.handle,
1007 screen->mmio.size,
1008 &screen->mmio.map ) ) {
1009 FREE( screen );
1010 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1011 return NULL;
1012 }
1013
1014 RADEONMMIO = screen->mmio.map;
1015
1016 screen->status.handle = dri_priv->statusHandle;
1017 screen->status.size = dri_priv->statusSize;
1018 if ( drmMap( sPriv->fd,
1019 screen->status.handle,
1020 screen->status.size,
1021 &screen->status.map ) ) {
1022 drmUnmap( screen->mmio.map, screen->mmio.size );
1023 FREE( screen );
1024 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1025 return NULL;
1026 }
1027 screen->scratch = (__volatile__ uint32_t *)
1028 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1029
1030 screen->buffers = drmMapBufs( sPriv->fd );
1031 if ( !screen->buffers ) {
1032 drmUnmap( screen->status.map, screen->status.size );
1033 drmUnmap( screen->mmio.map, screen->mmio.size );
1034 FREE( screen );
1035 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1036 return NULL;
1037 }
1038
1039 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1040 screen->gartTextures.handle = dri_priv->gartTexHandle;
1041 screen->gartTextures.size = dri_priv->gartTexMapSize;
1042 if ( drmMap( sPriv->fd,
1043 screen->gartTextures.handle,
1044 screen->gartTextures.size,
1045 (drmAddressPtr)&screen->gartTextures.map ) ) {
1046 drmUnmapBufs( screen->buffers );
1047 drmUnmap( screen->status.map, screen->status.size );
1048 drmUnmap( screen->mmio.map, screen->mmio.size );
1049 FREE( screen );
1050 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1051 return NULL;
1052 }
1053
1054 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1055 }
1056 }
1057
1058
1059 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1060 if (ret == -1)
1061 return NULL;
1062
1063 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1064 sPriv->ddx_version.minor < 2) {
1065 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1066 return NULL;
1067 }
1068
1069 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1070 fprintf(stderr, "R500 support requires a newer drm.\n");
1071 return NULL;
1072 }
1073
1074 if (getenv("R300_NO_TCL"))
1075 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1076
1077 if (screen->chip_family <= CHIP_FAMILY_RS200)
1078 screen->chip_flags |= RADEON_CLASS_R100;
1079 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1080 screen->chip_flags |= RADEON_CLASS_R200;
1081 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1082 screen->chip_flags |= RADEON_CLASS_R300;
1083 else
1084 screen->chip_flags |= RADEON_CLASS_R600;
1085
1086 screen->cpp = dri_priv->bpp / 8;
1087 screen->AGPMode = dri_priv->AGPMode;
1088
1089 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1090 if (ret) {
1091 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1092 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1093 else {
1094 FREE( screen );
1095 fprintf(stderr, "Unable to get fb location need newer drm\n");
1096 return NULL;
1097 }
1098 } else {
1099 screen->fbLocation = (temp & 0xffff) << 16;
1100 }
1101
1102 if (IS_R300_CLASS(screen)) {
1103 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1104 if (ret) {
1105 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1106 switch (screen->chip_family) {
1107 case CHIP_FAMILY_R300:
1108 case CHIP_FAMILY_R350:
1109 screen->num_gb_pipes = 2;
1110 break;
1111 case CHIP_FAMILY_R420:
1112 case CHIP_FAMILY_R520:
1113 case CHIP_FAMILY_R580:
1114 case CHIP_FAMILY_RV560:
1115 case CHIP_FAMILY_RV570:
1116 screen->num_gb_pipes = 4;
1117 break;
1118 case CHIP_FAMILY_RV350:
1119 case CHIP_FAMILY_RV515:
1120 case CHIP_FAMILY_RV530:
1121 case CHIP_FAMILY_RV410:
1122 default:
1123 screen->num_gb_pipes = 1;
1124 break;
1125 }
1126 } else {
1127 screen->num_gb_pipes = temp;
1128 }
1129 }
1130
1131 if ( sPriv->drm_version.minor >= 10 ) {
1132 drm_radeon_setparam_t sp;
1133
1134 sp.param = RADEON_SETPARAM_FB_LOCATION;
1135 sp.value = screen->fbLocation;
1136
1137 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1138 &sp, sizeof( sp ) );
1139 }
1140
1141 screen->frontOffset = dri_priv->frontOffset;
1142 screen->frontPitch = dri_priv->frontPitch;
1143 screen->backOffset = dri_priv->backOffset;
1144 screen->backPitch = dri_priv->backPitch;
1145 screen->depthOffset = dri_priv->depthOffset;
1146 screen->depthPitch = dri_priv->depthPitch;
1147
1148 /* Check if ddx has set up a surface reg to cover depth buffer */
1149 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1150 /* these chips don't use tiled z without hyperz. So always pretend
1151 we have set up a surface which will cause linear reads/writes */
1152 (IS_R100_CLASS(screen) &&
1153 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1154
1155 if ( dri_priv->textureSize == 0 ) {
1156 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1157 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1158 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1159 dri_priv->log2GARTTexGran;
1160 } else {
1161 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1162 + screen->fbLocation;
1163 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1164 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1165 dri_priv->log2TexGran;
1166 }
1167
1168 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1169 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1170 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1171 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1172 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1173 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1174 } else {
1175 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1176 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1177 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1178 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1179 dri_priv->log2GARTTexGran;
1180 }
1181
1182 i = 0;
1183 screen->extensions[i++] = &driCopySubBufferExtension.base;
1184 screen->extensions[i++] = &driFrameTrackingExtension.base;
1185 screen->extensions[i++] = &driReadDrawableExtension;
1186
1187 if ( screen->irq != 0 ) {
1188 screen->extensions[i++] = &driSwapControlExtension.base;
1189 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1190 }
1191
1192 if (!screen->kernel_mm) {
1193 #if !RADEON_COMMON
1194 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1195 #endif
1196
1197 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1198 if (IS_R200_CLASS(screen))
1199 screen->extensions[i++] = &r200AllocateExtension.base;
1200
1201 screen->extensions[i++] = &r200texOffsetExtension.base;
1202 #endif
1203
1204 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1205 screen->extensions[i++] = &r300texOffsetExtension.base;
1206 #endif
1207
1208 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1209 screen->extensions[i++] = &r600texOffsetExtension.base;
1210 #endif
1211 }
1212
1213 screen->extensions[i++] = NULL;
1214 sPriv->extensions = screen->extensions;
1215
1216 screen->driScreen = sPriv;
1217 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1218 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1219 screen->sarea_priv_offset);
1220
1221 if (screen->kernel_mm)
1222 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1223 else
1224 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1225 if (screen->bom == NULL) {
1226 free(screen);
1227 return NULL;
1228 }
1229
1230 return screen;
1231 }
1232
1233 static radeonScreenPtr
1234 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1235 {
1236 radeonScreenPtr screen;
1237 int i;
1238 int ret;
1239 uint32_t device_id;
1240 uint32_t temp = 0;
1241
1242 /* Allocate the private area */
1243 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1244 if ( !screen ) {
1245 __driUtilMessage("%s: Could not allocate memory for screen structure",
1246 __FUNCTION__);
1247 fprintf(stderr, "leaving here\n");
1248 return NULL;
1249 }
1250
1251 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1252 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1253 #endif
1254
1255 /* parse information in __driConfigOptions */
1256 driParseOptionInfo (&screen->optionCache,
1257 __driConfigOptions, __driNConfigOptions);
1258
1259 screen->kernel_mm = 1;
1260 screen->chip_flags = 0;
1261
1262 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq);
1263
1264 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1265 if (ret) {
1266 FREE( screen );
1267 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1268 return NULL;
1269 }
1270
1271 ret = radeon_set_screen_flags(screen, device_id);
1272 if (ret == -1)
1273 return NULL;
1274
1275 if (getenv("R300_NO_TCL"))
1276 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1277
1278 if (screen->chip_family <= CHIP_FAMILY_RS200)
1279 screen->chip_flags |= RADEON_CLASS_R100;
1280 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1281 screen->chip_flags |= RADEON_CLASS_R200;
1282 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1283 screen->chip_flags |= RADEON_CLASS_R300;
1284 else
1285 screen->chip_flags |= RADEON_CLASS_R600;
1286
1287 if (IS_R300_CLASS(screen)) {
1288 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1289 if (ret) {
1290 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1291 switch (screen->chip_family) {
1292 case CHIP_FAMILY_R300:
1293 case CHIP_FAMILY_R350:
1294 screen->num_gb_pipes = 2;
1295 break;
1296 case CHIP_FAMILY_R420:
1297 case CHIP_FAMILY_R520:
1298 case CHIP_FAMILY_R580:
1299 case CHIP_FAMILY_RV560:
1300 case CHIP_FAMILY_RV570:
1301 screen->num_gb_pipes = 4;
1302 break;
1303 case CHIP_FAMILY_RV350:
1304 case CHIP_FAMILY_RV515:
1305 case CHIP_FAMILY_RV530:
1306 case CHIP_FAMILY_RV410:
1307 default:
1308 screen->num_gb_pipes = 1;
1309 break;
1310 }
1311 } else {
1312 screen->num_gb_pipes = temp;
1313 }
1314 }
1315
1316 i = 0;
1317 screen->extensions[i++] = &driCopySubBufferExtension.base;
1318 screen->extensions[i++] = &driFrameTrackingExtension.base;
1319 screen->extensions[i++] = &driReadDrawableExtension;
1320
1321 if ( screen->irq != 0 ) {
1322 screen->extensions[i++] = &driSwapControlExtension.base;
1323 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1324 }
1325
1326 #if !RADEON_COMMON
1327 screen->extensions[i++] = &radeonTexBufferExtension.base;
1328 #endif
1329
1330 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1331 if (IS_R200_CLASS(screen))
1332 screen->extensions[i++] = &r200AllocateExtension.base;
1333
1334 screen->extensions[i++] = &r200TexBufferExtension.base;
1335 #endif
1336
1337 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1338 screen->extensions[i++] = &r300TexBufferExtension.base;
1339 #endif
1340
1341 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1342 screen->extensions[i++] = &r600TexBufferExtension.base;
1343 #endif
1344
1345 screen->extensions[i++] = NULL;
1346 sPriv->extensions = screen->extensions;
1347
1348 screen->driScreen = sPriv;
1349 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1350 if (screen->bom == NULL) {
1351 free(screen);
1352 return NULL;
1353 }
1354 return screen;
1355 }
1356
1357 /* Destroy the device specific screen private data struct.
1358 */
1359 static void
1360 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1361 {
1362 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1363
1364 if (!screen)
1365 return;
1366
1367 if (screen->kernel_mm) {
1368 #ifdef RADEON_BO_TRACK
1369 radeon_tracker_print(&screen->bom->tracker, stderr);
1370 #endif
1371 radeon_bo_manager_gem_dtor(screen->bom);
1372 } else {
1373 radeon_bo_manager_legacy_dtor(screen->bom);
1374
1375 if ( screen->gartTextures.map ) {
1376 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1377 }
1378 drmUnmapBufs( screen->buffers );
1379 drmUnmap( screen->status.map, screen->status.size );
1380 drmUnmap( screen->mmio.map, screen->mmio.size );
1381 }
1382
1383 /* free all option information */
1384 driDestroyOptionInfo (&screen->optionCache);
1385
1386 FREE( screen );
1387 sPriv->private = NULL;
1388 }
1389
1390
1391 /* Initialize the driver specific screen private data.
1392 */
1393 static GLboolean
1394 radeonInitDriver( __DRIscreenPrivate *sPriv )
1395 {
1396 if (sPriv->dri2.enabled) {
1397 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1398 } else {
1399 sPriv->private = (void *) radeonCreateScreen( sPriv );
1400 }
1401 if ( !sPriv->private ) {
1402 radeonDestroyScreen( sPriv );
1403 return GL_FALSE;
1404 }
1405
1406 return GL_TRUE;
1407 }
1408
1409
1410
1411 /**
1412 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1413 *
1414 * \todo This function (and its interface) will need to be updated to support
1415 * pbuffers.
1416 */
1417 static GLboolean
1418 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1419 __DRIdrawablePrivate *driDrawPriv,
1420 const __GLcontextModes *mesaVis,
1421 GLboolean isPixmap )
1422 {
1423 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1424
1425 const GLboolean swDepth = GL_FALSE;
1426 const GLboolean swAlpha = GL_FALSE;
1427 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1428 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1429 mesaVis->depthBits != 24;
1430 GLenum rgbFormat;
1431 struct radeon_framebuffer *rfb;
1432
1433 if (isPixmap)
1434 return GL_FALSE; /* not implemented */
1435
1436 rfb = CALLOC_STRUCT(radeon_framebuffer);
1437 if (!rfb)
1438 return GL_FALSE;
1439
1440 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1441
1442 if (mesaVis->redBits == 5)
1443 rgbFormat = GL_RGB5;
1444 else if (mesaVis->alphaBits == 0)
1445 rgbFormat = GL_RGB8;
1446 else
1447 rgbFormat = GL_RGBA8;
1448
1449 /* front color renderbuffer */
1450 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1451 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1452 rfb->color_rb[0]->has_surface = 1;
1453
1454 /* back color renderbuffer */
1455 if (mesaVis->doubleBufferMode) {
1456 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1457 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1458 rfb->color_rb[1]->has_surface = 1;
1459 }
1460
1461 if (mesaVis->depthBits == 24) {
1462 if (mesaVis->stencilBits == 8) {
1463 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
1464 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1465 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1466 depthStencilRb->has_surface = screen->depthHasSurface;
1467 } else {
1468 /* depth renderbuffer */
1469 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
1470 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1471 depth->has_surface = screen->depthHasSurface;
1472 }
1473 } else if (mesaVis->depthBits == 16) {
1474 /* just 16-bit depth buffer, no hw stencil */
1475 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
1476 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1477 depth->has_surface = screen->depthHasSurface;
1478 }
1479
1480 _mesa_add_soft_renderbuffers(&rfb->base,
1481 GL_FALSE, /* color */
1482 swDepth,
1483 swStencil,
1484 swAccum,
1485 swAlpha,
1486 GL_FALSE /* aux */);
1487 driDrawPriv->driverPrivate = (void *) rfb;
1488
1489 return (driDrawPriv->driverPrivate != NULL);
1490 }
1491
1492
1493 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1494 {
1495 struct radeon_renderbuffer *rb;
1496
1497 rb = rfb->color_rb[0];
1498 if (rb && rb->bo) {
1499 radeon_bo_unref(rb->bo);
1500 rb->bo = NULL;
1501 }
1502 rb = rfb->color_rb[1];
1503 if (rb && rb->bo) {
1504 radeon_bo_unref(rb->bo);
1505 rb->bo = NULL;
1506 }
1507 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1508 if (rb && rb->bo) {
1509 radeon_bo_unref(rb->bo);
1510 rb->bo = NULL;
1511 }
1512 }
1513
1514 void
1515 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1516 {
1517 struct radeon_framebuffer *rfb;
1518 if (!driDrawPriv)
1519 return;
1520
1521 rfb = (void*)driDrawPriv->driverPrivate;
1522 if (!rfb)
1523 return;
1524 radeon_cleanup_renderbuffers(rfb);
1525 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1526 }
1527
1528 /**
1529 * Choose the appropriate CreateContext function based on the chipset.
1530 * Eventually, all drivers will go through this process.
1531 */
1532 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1533 __DRIcontextPrivate * driContextPriv,
1534 void *sharedContextPriv)
1535 {
1536 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1537 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1538 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1539 if (IS_R600_CLASS(screen))
1540 return r600CreateContext(glVisual, driContextPriv, sharedContextPriv);
1541 #endif
1542
1543 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1544 if (IS_R300_CLASS(screen))
1545 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1546 #endif
1547
1548 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1549 if (IS_R200_CLASS(screen))
1550 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv);
1551 #endif
1552
1553 #if !RADEON_COMMON
1554 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
1555 #endif
1556 return GL_FALSE;
1557 }
1558
1559
1560 /**
1561 * This is the driver specific part of the createNewScreen entry point.
1562 *
1563 * \todo maybe fold this into intelInitDriver
1564 *
1565 * \return the __GLcontextModes supported by this driver
1566 */
1567 static const __DRIconfig **
1568 radeonInitScreen(__DRIscreenPrivate *psp)
1569 {
1570 #if !RADEON_COMMON
1571 static const char *driver_name = "Radeon";
1572 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1573 static const __DRIversion dri_expected = { 4, 0, 0 };
1574 static const __DRIversion drm_expected = { 1, 6, 0 };
1575 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1576 static const char *driver_name = "R200";
1577 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1578 static const __DRIversion dri_expected = { 4, 0, 0 };
1579 static const __DRIversion drm_expected = { 1, 6, 0 };
1580 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1581 static const char *driver_name = "R300";
1582 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1583 static const __DRIversion dri_expected = { 4, 0, 0 };
1584 static const __DRIversion drm_expected = { 1, 24, 0 };
1585 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1586 static const char *driver_name = "R600";
1587 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1588 static const __DRIversion dri_expected = { 4, 0, 0 };
1589 static const __DRIversion drm_expected = { 1, 24, 0 };
1590 #endif
1591 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1592
1593 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1594 &psp->dri_version, & dri_expected,
1595 &psp->ddx_version, & ddx_expected,
1596 &psp->drm_version, & drm_expected ) ) {
1597 return NULL;
1598 }
1599
1600 /* Calling driInitExtensions here, with a NULL context pointer,
1601 * does not actually enable the extensions. It just makes sure
1602 * that all the dispatch offsets for all the extensions that
1603 * *might* be enables are known. This is needed because the
1604 * dispatch offsets need to be known when _mesa_context_create
1605 * is called, but we can't enable the extensions until we have a
1606 * context pointer.
1607 *
1608 * Hello chicken. Hello egg. How are you two today?
1609 */
1610 driInitExtensions( NULL, card_extensions, GL_FALSE );
1611 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1612 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1613 driInitSingleExtension( NULL, ARB_vp_extension );
1614 driInitSingleExtension( NULL, NV_vp_extension );
1615 driInitSingleExtension( NULL, ATI_fs_extension );
1616 driInitExtensions( NULL, point_extensions, GL_FALSE );
1617 #elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
1618 driInitSingleExtension( NULL, gl_20_extension );
1619 #endif
1620
1621 if (!radeonInitDriver(psp))
1622 return NULL;
1623
1624 /* for now fill in all modes */
1625 return radeonFillInModes( psp,
1626 dri_priv->bpp,
1627 (dri_priv->bpp == 16) ? 16 : 24,
1628 (dri_priv->bpp == 16) ? 0 : 8, 1);
1629 }
1630 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1631
1632 /**
1633 * This is the driver specific part of the createNewScreen entry point.
1634 * Called when using DRI2.
1635 *
1636 * \return the __GLcontextModes supported by this driver
1637 */
1638 static const
1639 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1640 {
1641 GLenum fb_format[3];
1642 GLenum fb_type[3];
1643 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1644 * support pageflipping at all.
1645 */
1646 static const GLenum back_buffer_modes[] = {
1647 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1648 };
1649 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1650 int color;
1651 __DRIconfig **configs = NULL;
1652
1653 /* Calling driInitExtensions here, with a NULL context pointer,
1654 * does not actually enable the extensions. It just makes sure
1655 * that all the dispatch offsets for all the extensions that
1656 * *might* be enables are known. This is needed because the
1657 * dispatch offsets need to be known when _mesa_context_create
1658 * is called, but we can't enable the extensions until we have a
1659 * context pointer.
1660 *
1661 * Hello chicken. Hello egg. How are you two today?
1662 */
1663 driInitExtensions( NULL, card_extensions, GL_FALSE );
1664 driInitExtensions( NULL, mm_extensions, GL_FALSE );
1665 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1666 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1667 driInitSingleExtension( NULL, ARB_vp_extension );
1668 driInitSingleExtension( NULL, NV_vp_extension );
1669 driInitSingleExtension( NULL, ATI_fs_extension );
1670 driInitExtensions( NULL, point_extensions, GL_FALSE );
1671 #endif
1672
1673 if (!radeonInitDriver(psp)) {
1674 return NULL;
1675 }
1676 depth_bits[0] = 0;
1677 stencil_bits[0] = 0;
1678 depth_bits[1] = 16;
1679 stencil_bits[1] = 0;
1680 depth_bits[2] = 24;
1681 stencil_bits[2] = 0;
1682 depth_bits[3] = 24;
1683 stencil_bits[3] = 8;
1684
1685 msaa_samples_array[0] = 0;
1686
1687 fb_format[0] = GL_RGB;
1688 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1689
1690 fb_format[1] = GL_BGR;
1691 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1692
1693 fb_format[2] = GL_BGRA;
1694 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1695
1696 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1697 __DRIconfig **new_configs;
1698
1699 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1700 depth_bits,
1701 stencil_bits,
1702 ARRAY_SIZE(depth_bits),
1703 back_buffer_modes,
1704 ARRAY_SIZE(back_buffer_modes),
1705 msaa_samples_array,
1706 ARRAY_SIZE(msaa_samples_array));
1707 if (configs == NULL)
1708 configs = new_configs;
1709 else
1710 configs = driConcatConfigs(configs, new_configs);
1711 }
1712
1713 if (configs == NULL) {
1714 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1715 __LINE__);
1716 return NULL;
1717 }
1718
1719 return (const __DRIconfig **)configs;
1720 }
1721
1722 /**
1723 * Get information about previous buffer swaps.
1724 */
1725 static int
1726 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1727 {
1728 struct radeon_framebuffer *rfb;
1729
1730 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1731 || (dPriv->driContextPriv->driverPrivate == NULL)
1732 || (sInfo == NULL) ) {
1733 return -1;
1734 }
1735
1736 rfb = dPriv->driverPrivate;
1737 sInfo->swap_count = rfb->swap_count;
1738 sInfo->swap_ust = rfb->swap_ust;
1739 sInfo->swap_missed_count = rfb->swap_missed_count;
1740
1741 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1742 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1743 : 0.0;
1744
1745 return 0;
1746 }
1747
1748 const struct __DriverAPIRec driDriverAPI = {
1749 .InitScreen = radeonInitScreen,
1750 .DestroyScreen = radeonDestroyScreen,
1751 .CreateContext = radeonCreateContext,
1752 .DestroyContext = radeonDestroyContext,
1753 .CreateBuffer = radeonCreateBuffer,
1754 .DestroyBuffer = radeonDestroyBuffer,
1755 .SwapBuffers = radeonSwapBuffers,
1756 .MakeCurrent = radeonMakeCurrent,
1757 .UnbindContext = radeonUnbindContext,
1758 .GetSwapInfo = getSwapInfo,
1759 .GetDrawableMSC = driDrawableGetMSC32,
1760 .WaitForMSC = driWaitForMSC32,
1761 .WaitForSBC = NULL,
1762 .SwapBuffersMSC = NULL,
1763 .CopySubBuffer = radeonCopySubBuffer,
1764 /* DRI2 */
1765 .InitScreen2 = radeonInitScreen2,
1766 };
1767