src/mesa/drivers/dri/radeon/radeon_screen.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file radeon_screen.c
  32  * Screen initialization functions for the Radeon driver.
  33  *
  34  * \author Kevin E. Martin <martin@valinux.com>
  35  * \author  Gareth Hughes <gareth@valinux.com>
  36  */
  37
  38 #include <errno.h>
  39 #include "main/glheader.h"
  40 #include "main/imports.h"
  41 #include "main/mtypes.h"
  42 #include "main/framebuffer.h"
  43 #include "main/renderbuffer.h"
  44 #include "main/fbobject.h"
  45 #include "swrast/s_renderbuffer.h"
  46
  47 #include "radeon_chipset.h"
  48 #include "radeon_macros.h"
  49 #include "radeon_screen.h"
  50 #include "radeon_common.h"
  51 #include "radeon_common_context.h"
  52 #if defined(RADEON_R100)
  53 #include "radeon_context.h"
  54 #include "radeon_tex.h"
  55 #elif defined(RADEON_R200)
  56 #include "r200_context.h"
  57 #include "r200_tex.h"
  58 #endif
  59
  60 #include "utils.h"
  61
  62 #include "GL/internal/dri_interface.h"
  63
  64 /* Radeon configuration
  65  */
  66 #include "xmlpool.h"
  67
  68 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
  69 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
  70         DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
  71         DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
  72 DRI_CONF_OPT_END
  73
  74 #if defined(RADEON_R100)        /* R100 */
  75 static const __DRIconfigOptionsExtension radeon_config_options = {
  76    .base = { __DRI_CONFIG_OPTIONS, 1 },
  77    .xml =
  78 DRI_CONF_BEGIN
  79     DRI_CONF_SECTION_PERFORMANCE
  80         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
  81         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
  82         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
  83         DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
  84         DRI_CONF_HYPERZ("false")
  85         DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
  86     DRI_CONF_SECTION_END
  87     DRI_CONF_SECTION_QUALITY
  88         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
  89         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
  90         DRI_CONF_NO_NEG_LOD_BIAS("false")
  91         DRI_CONF_FORCE_S3TC_ENABLE("false")
  92         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
  93         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
  94         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
  95     DRI_CONF_SECTION_END
  96     DRI_CONF_SECTION_DEBUG
  97         DRI_CONF_NO_RAST("false")
  98     DRI_CONF_SECTION_END
  99 DRI_CONF_END
 100 };
 101
 102 #elif defined(RADEON_R200)
 103 static const __DRIconfigOptionsExtension radeon_config_options = {
 104    .base = { __DRI_CONFIG_OPTIONS, 1 },
 105    .xml =
 106 DRI_CONF_BEGIN
 107     DRI_CONF_SECTION_PERFORMANCE
 108         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
 109         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
 110         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
 111         DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
 112         DRI_CONF_HYPERZ("false")
 113         DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
 114     DRI_CONF_SECTION_END
 115     DRI_CONF_SECTION_QUALITY
 116         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 117         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
 118         DRI_CONF_NO_NEG_LOD_BIAS("false")
 119         DRI_CONF_FORCE_S3TC_ENABLE("false")
 120         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
 121         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 122         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 123         DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
 124     DRI_CONF_SECTION_END
 125     DRI_CONF_SECTION_DEBUG
 126         DRI_CONF_NO_RAST("false")
 127     DRI_CONF_SECTION_END
 128 DRI_CONF_END
 129 };
 130 #endif
 131
 132 #ifndef RADEON_INFO_TILE_CONFIG
 133 #define RADEON_INFO_TILE_CONFIG 0x6
 134 #endif
 135
 136 static int
 137 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
 138 {
 139   int ret;
 140   drm_radeon_getparam_t gp = { 0 };
 141   struct drm_radeon_info info = { 0 };
 142
 143   if (sPriv->drm_version.major >= 2) {
 144       info.value = (uint64_t)(uintptr_t)value;
 145       switch (param) {
 146       case RADEON_PARAM_DEVICE_ID:
 147           info.request = RADEON_INFO_DEVICE_ID;
 148           break;
 149       case RADEON_PARAM_NUM_GB_PIPES:
 150           info.request = RADEON_INFO_NUM_GB_PIPES;
 151           break;
 152       case RADEON_PARAM_NUM_Z_PIPES:
 153           info.request = RADEON_INFO_NUM_Z_PIPES;
 154           break;
 155       case RADEON_INFO_TILE_CONFIG:
 156           info.request = RADEON_INFO_TILE_CONFIG;
 157           break;
 158       default:
 159           return -EINVAL;
 160       }
 161       ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
 162   } else {
 163       gp.param = param;
 164       gp.value = value;
 165
 166       ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
 167   }
 168   return ret;
 169 }
 170
 171 #if defined(RADEON_R100)
 172 static const __DRItexBufferExtension radeonTexBufferExtension = {
 173    .base = { __DRI_TEX_BUFFER, 3 },
 174
 175    .setTexBuffer        = radeonSetTexBuffer,
 176    .setTexBuffer2       = radeonSetTexBuffer2,
 177    .releaseTexBuffer    = NULL,
 178 };
 179 #elif defined(RADEON_R200)
 180 static const __DRItexBufferExtension r200TexBufferExtension = {
 181    .base = { __DRI_TEX_BUFFER, 3 },
 182
 183    .setTexBuffer        = r200SetTexBuffer,
 184    .setTexBuffer2       = r200SetTexBuffer2,
 185    .releaseTexBuffer    = NULL,
 186 };
 187 #endif
 188
 189 static void
 190 radeonDRI2Flush(__DRIdrawable *drawable)
 191 {
 192     radeonContextPtr rmesa;
 193
 194     rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
 195     radeonFlush(&rmesa->glCtx);
 196 }
 197
 198 static const struct __DRI2flushExtensionRec radeonFlushExtension = {
 199    .base = { __DRI2_FLUSH, 3 },
 200
 201    .flush               = radeonDRI2Flush,
 202    .invalidate          = dri2InvalidateDrawable,
 203 };
 204
 205 static __DRIimage *
 206 radeon_create_image_from_name(__DRIscreen *screen,
 207                               int width, int height, int format,
 208                               int name, int pitch, void *loaderPrivate)
 209 {
 210    __DRIimage *image;
 211    radeonScreenPtr radeonScreen = screen->driverPrivate;
 212
 213    if (name == 0)
 214       return NULL;
 215
 216    image = calloc(1, sizeof *image);
 217    if (image == NULL)
 218       return NULL;
 219
 220    switch (format) {
 221    case __DRI_IMAGE_FORMAT_RGB565:
 222       image->format = MESA_FORMAT_B5G6R5_UNORM;
 223       image->internal_format = GL_RGB;
 224       image->data_type = GL_UNSIGNED_BYTE;
 225       break;
 226    case __DRI_IMAGE_FORMAT_XRGB8888:
 227       image->format = MESA_FORMAT_B8G8R8X8_UNORM;
 228       image->internal_format = GL_RGB;
 229       image->data_type = GL_UNSIGNED_BYTE;
 230       break;
 231    case __DRI_IMAGE_FORMAT_ARGB8888:
 232       image->format = MESA_FORMAT_B8G8R8A8_UNORM;
 233       image->internal_format = GL_RGBA;
 234       image->data_type = GL_UNSIGNED_BYTE;
 235       break;
 236    default:
 237       free(image);
 238       return NULL;
 239    }
 240
 241    image->data = loaderPrivate;
 242    image->cpp = _mesa_get_format_bytes(image->format);
 243    image->width = width;
 244    image->pitch = pitch;
 245    image->height = height;
 246
 247    image->bo = radeon_bo_open(radeonScreen->bom,
 248                               (uint32_t)name,
 249                               image->pitch * image->height * image->cpp,
 250                               0,
 251                               RADEON_GEM_DOMAIN_VRAM,
 252                               0);
 253
 254    if (image->bo == NULL) {
 255       free(image);
 256       return NULL;
 257    }
 258
 259    return image;
 260 }
 261
 262 static __DRIimage *
 263 radeon_create_image_from_renderbuffer(__DRIcontext *context,
 264                                       int renderbuffer, void *loaderPrivate)
 265 {
 266    __DRIimage *image;
 267    radeonContextPtr radeon = context->driverPrivate;
 268    struct gl_renderbuffer *rb;
 269    struct radeon_renderbuffer *rrb;
 270
 271    rb = _mesa_lookup_renderbuffer(&radeon->glCtx, renderbuffer);
 272    if (!rb) {
 273       _mesa_error(&radeon->glCtx,
 274                   GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
 275       return NULL;
 276    }
 277
 278    rrb = radeon_renderbuffer(rb);
 279    image = calloc(1, sizeof *image);
 280    if (image == NULL)
 281       return NULL;
 282
 283    image->internal_format = rb->InternalFormat;
 284    image->format = rb->Format;
 285    image->cpp = rrb->cpp;
 286    image->data_type = GL_UNSIGNED_BYTE;
 287    image->data = loaderPrivate;
 288    radeon_bo_ref(rrb->bo);
 289    image->bo = rrb->bo;
 290
 291    image->width = rb->Width;
 292    image->height = rb->Height;
 293    image->pitch = rrb->pitch / image->cpp;
 294
 295    return image;
 296 }
 297
 298 static void
 299 radeon_destroy_image(__DRIimage *image)
 300 {
 301    radeon_bo_unref(image->bo);
 302    free(image);
 303 }
 304
 305 static __DRIimage *
 306 radeon_create_image(__DRIscreen *screen,
 307                     int width, int height, int format,
 308                     unsigned int use,
 309                     void *loaderPrivate)
 310 {
 311    __DRIimage *image;
 312    radeonScreenPtr radeonScreen = screen->driverPrivate;
 313
 314    image = calloc(1, sizeof *image);
 315    if (image == NULL)
 316       return NULL;
 317
 318    image->dri_format = format;
 319
 320    switch (format) {
 321    case __DRI_IMAGE_FORMAT_RGB565:
 322       image->format = MESA_FORMAT_B5G6R5_UNORM;
 323       image->internal_format = GL_RGB;
 324       image->data_type = GL_UNSIGNED_BYTE;
 325       break;
 326    case __DRI_IMAGE_FORMAT_XRGB8888:
 327       image->format = MESA_FORMAT_B8G8R8X8_UNORM;
 328       image->internal_format = GL_RGB;
 329       image->data_type = GL_UNSIGNED_BYTE;
 330       break;
 331    case __DRI_IMAGE_FORMAT_ARGB8888:
 332       image->format = MESA_FORMAT_B8G8R8A8_UNORM;
 333       image->internal_format = GL_RGBA;
 334       image->data_type = GL_UNSIGNED_BYTE;
 335       break;
 336    default:
 337       free(image);
 338       return NULL;
 339    }
 340
 341    image->data = loaderPrivate;
 342    image->cpp = _mesa_get_format_bytes(image->format);
 343    image->width = width;
 344    image->height = height;
 345    image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
 346
 347    image->bo = radeon_bo_open(radeonScreen->bom,
 348                               0,
 349                               image->pitch * image->height * image->cpp,
 350                               0,
 351                               RADEON_GEM_DOMAIN_VRAM,
 352                               0);
 353
 354    if (image->bo == NULL) {
 355       free(image);
 356       return NULL;
 357    }
 358
 359    return image;
 360 }
 361
 362 static GLboolean
 363 radeon_query_image(__DRIimage *image, int attrib, int *value)
 364 {
 365    switch (attrib) {
 366    case __DRI_IMAGE_ATTRIB_STRIDE:
 367       *value = image->pitch * image->cpp;
 368       return GL_TRUE;
 369    case __DRI_IMAGE_ATTRIB_HANDLE:
 370       *value = image->bo->handle;
 371       return GL_TRUE;
 372    case __DRI_IMAGE_ATTRIB_NAME:
 373       radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
 374       return GL_TRUE;
 375    default:
 376       return GL_FALSE;
 377    }
 378 }
 379
 380 static const __DRIimageExtension radeonImageExtension = {
 381    .base = { __DRI_IMAGE, 1 },
 382
 383    .createImageFromName         = radeon_create_image_from_name,
 384    .createImageFromRenderbuffer = radeon_create_image_from_renderbuffer,
 385    .destroyImage                = radeon_destroy_image,
 386    .createImage                 = radeon_create_image,
 387    .queryImage                  = radeon_query_image
 388 };
 389
 390 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
 391 {
 392    screen->device_id = device_id;
 393    screen->chip_flags = 0;
 394    switch ( device_id ) {
 395 #if defined(RADEON_R100)
 396    case PCI_CHIP_RN50_515E:
 397    case PCI_CHIP_RN50_5969:
 398         return -1;
 399
 400    case PCI_CHIP_RADEON_LY:
 401    case PCI_CHIP_RADEON_LZ:
 402    case PCI_CHIP_RADEON_QY:
 403    case PCI_CHIP_RADEON_QZ:
 404       screen->chip_family = CHIP_FAMILY_RV100;
 405       break;
 406
 407    case PCI_CHIP_RS100_4136:
 408    case PCI_CHIP_RS100_4336:
 409       screen->chip_family = CHIP_FAMILY_RS100;
 410       break;
 411
 412    case PCI_CHIP_RS200_4137:
 413    case PCI_CHIP_RS200_4337:
 414    case PCI_CHIP_RS250_4237:
 415    case PCI_CHIP_RS250_4437:
 416       screen->chip_family = CHIP_FAMILY_RS200;
 417       break;
 418
 419    case PCI_CHIP_RADEON_QD:
 420    case PCI_CHIP_RADEON_QE:
 421    case PCI_CHIP_RADEON_QF:
 422    case PCI_CHIP_RADEON_QG:
 423       /* all original radeons (7200) presumably have a stencil op bug */
 424       screen->chip_family = CHIP_FAMILY_R100;
 425       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 426       break;
 427
 428    case PCI_CHIP_RV200_QW:
 429    case PCI_CHIP_RV200_QX:
 430    case PCI_CHIP_RADEON_LW:
 431    case PCI_CHIP_RADEON_LX:
 432       screen->chip_family = CHIP_FAMILY_RV200;
 433       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 434       break;
 435
 436 #elif defined(RADEON_R200)
 437    case PCI_CHIP_R200_BB:
 438    case PCI_CHIP_R200_QH:
 439    case PCI_CHIP_R200_QL:
 440    case PCI_CHIP_R200_QM:
 441       screen->chip_family = CHIP_FAMILY_R200;
 442       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 443       break;
 444
 445    case PCI_CHIP_RV250_If:
 446    case PCI_CHIP_RV250_Ig:
 447    case PCI_CHIP_RV250_Ld:
 448    case PCI_CHIP_RV250_Lf:
 449    case PCI_CHIP_RV250_Lg:
 450       screen->chip_family = CHIP_FAMILY_RV250;
 451       screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 452       break;
 453
 454    case PCI_CHIP_RV280_4C6E:
 455    case PCI_CHIP_RV280_5960:
 456    case PCI_CHIP_RV280_5961:
 457    case PCI_CHIP_RV280_5962:
 458    case PCI_CHIP_RV280_5964:
 459    case PCI_CHIP_RV280_5965:
 460    case PCI_CHIP_RV280_5C61:
 461    case PCI_CHIP_RV280_5C63:
 462       screen->chip_family = CHIP_FAMILY_RV280;
 463       screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 464       break;
 465
 466    case PCI_CHIP_RS300_5834:
 467    case PCI_CHIP_RS300_5835:
 468    case PCI_CHIP_RS350_7834:
 469    case PCI_CHIP_RS350_7835:
 470       screen->chip_family = CHIP_FAMILY_RS300;
 471       screen->chip_flags = RADEON_CHIPSET_DEPTH_ALWAYS_TILED;
 472       break;
 473 #endif
 474
 475    default:
 476       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
 477               device_id);
 478       return -1;
 479    }
 480
 481    return 0;
 482 }
 483
 484 static int
 485 radeonQueryRendererInteger(__DRIscreen *psp, int param,
 486                                unsigned int *value)
 487 {
 488    radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate;
 489
 490    switch (param) {
 491    case __DRI2_RENDERER_VENDOR_ID:
 492       value[0] = 0x1002;
 493       return 0;
 494    case __DRI2_RENDERER_DEVICE_ID:
 495       value[0] = screen->device_id;
 496       return 0;
 497    case __DRI2_RENDERER_ACCELERATED:
 498       value[0] = 1;
 499       return 0;
 500    case __DRI2_RENDERER_VIDEO_MEMORY: {
 501       struct drm_radeon_gem_info gem_info;
 502       int retval;
 503       memset(&gem_info, 0, sizeof(gem_info));
 504
 505       /* Get GEM info. */
 506       retval = drmCommandWriteRead(psp->fd, DRM_RADEON_GEM_INFO, &gem_info,
 507                                    sizeof(gem_info));
 508
 509       if (retval) {
 510          fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 511                 retval);
 512          return -1;
 513
 514       }
 515       /* XXX: Do we want to return vram_size or vram_visible ? */
 516       value[0] = gem_info.vram_size >> 20;
 517       return 0;
 518    }
 519    case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
 520       value[0] = 0;
 521       return 0;
 522    default:
 523       return driQueryRendererIntegerCommon(psp, param, value);
 524    }
 525 }
 526
 527 static int
 528 radeonQueryRendererString(__DRIscreen *psp, int param, const char **value)
 529 {
 530    radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate;
 531
 532    switch (param) {
 533    case __DRI2_RENDERER_VENDOR_ID:
 534       value[0] = radeonVendorString;
 535       return 0;
 536    case __DRI2_RENDERER_DEVICE_ID:
 537       value[0] = radeonGetRendererString(screen);
 538       return 0;
 539    default:
 540       return -1;
 541    }
 542 }
 543
 544 static const __DRI2rendererQueryExtension radeonRendererQueryExtension = {
 545    .base = { __DRI2_RENDERER_QUERY, 1 },
 546
 547    .queryInteger        = radeonQueryRendererInteger,
 548    .queryString         = radeonQueryRendererString
 549 };
 550
 551
 552 static const __DRIextension *radeon_screen_extensions[] = {
 553     &dri2ConfigQueryExtension.base,
 554 #if defined(RADEON_R100)
 555     &radeonTexBufferExtension.base,
 556 #elif defined(RADEON_R200)
 557     &r200TexBufferExtension.base,
 558 #endif
 559     &radeonFlushExtension.base,
 560     &radeonImageExtension.base,
 561     &radeonRendererQueryExtension.base,
 562     NULL
 563 };
 564
 565 static radeonScreenPtr
 566 radeonCreateScreen2(__DRIscreen *sPriv)
 567 {
 568    radeonScreenPtr screen;
 569    int ret;
 570    uint32_t device_id = 0;
 571
 572    /* Allocate the private area */
 573    screen = calloc(1, sizeof(*screen));
 574    if ( !screen ) {
 575       fprintf(stderr, "%s: Could not allocate memory for screen structure", __FUNCTION__);
 576       fprintf(stderr, "leaving here\n");
 577       return NULL;
 578    }
 579
 580    radeon_init_debug();
 581
 582    /* parse information in __driConfigOptions */
 583    driParseOptionInfo (&screen->optionCache, radeon_config_options.xml);
 584
 585    screen->chip_flags = 0;
 586
 587    screen->irq = 1;
 588
 589    ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
 590    if (ret) {
 591      free( screen );
 592      fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
 593      return NULL;
 594    }
 595
 596    ret = radeon_set_screen_flags(screen, device_id);
 597    if (ret == -1) {
 598      free(screen);
 599      return NULL;
 600    }
 601
 602    if (getenv("RADEON_NO_TCL"))
 603            screen->chip_flags &= ~RADEON_CHIPSET_TCL;
 604
 605    sPriv->extensions = radeon_screen_extensions;
 606
 607    screen->driScreen = sPriv;
 608    screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
 609    if (screen->bom == NULL) {
 610        free(screen);
 611        return NULL;
 612    }
 613    return screen;
 614 }
 615
 616 /* Destroy the device specific screen private data struct.
 617  */
 618 static void
 619 radeonDestroyScreen( __DRIscreen *sPriv )
 620 {
 621     radeonScreenPtr screen = (radeonScreenPtr)sPriv->driverPrivate;
 622
 623     if (!screen)
 624         return;
 625
 626 #ifdef RADEON_BO_TRACK
 627     radeon_tracker_print(&screen->bom->tracker, stderr);
 628 #endif
 629     radeon_bo_manager_gem_dtor(screen->bom);
 630
 631     /* free all option information */
 632     driDestroyOptionInfo (&screen->optionCache);
 633
 634     free( screen );
 635     sPriv->driverPrivate = NULL;
 636 }
 637
 638
 639 /* Initialize the driver specific screen private data.
 640  */
 641 static GLboolean
 642 radeonInitDriver( __DRIscreen *sPriv )
 643 {
 644     sPriv->driverPrivate = (void *) radeonCreateScreen2( sPriv );
 645     if ( !sPriv->driverPrivate ) {
 646         radeonDestroyScreen( sPriv );
 647         return GL_FALSE;
 648     }
 649
 650     return GL_TRUE;
 651 }
 652
 653
 654
 655 /**
 656  * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
 657  *
 658  * \todo This function (and its interface) will need to be updated to support
 659  * pbuffers.
 660  */
 661 static GLboolean
 662 radeonCreateBuffer( __DRIscreen *driScrnPriv,
 663                     __DRIdrawable *driDrawPriv,
 664                     const struct gl_config *mesaVis,
 665                     GLboolean isPixmap )
 666 {
 667     radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->driverPrivate;
 668
 669     const GLboolean swDepth = GL_FALSE;
 670     const GLboolean swAlpha = GL_FALSE;
 671     const GLboolean swAccum = mesaVis->accumRedBits > 0;
 672     const GLboolean swStencil = mesaVis->stencilBits > 0 &&
 673         mesaVis->depthBits != 24;
 674     mesa_format rgbFormat;
 675     struct radeon_framebuffer *rfb;
 676
 677     if (isPixmap)
 678       return GL_FALSE; /* not implemented */
 679
 680     rfb = CALLOC_STRUCT(radeon_framebuffer);
 681     if (!rfb)
 682       return GL_FALSE;
 683
 684     _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
 685
 686     if (mesaVis->redBits == 5)
 687         rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B5G6R5_UNORM : MESA_FORMAT_R5G6B5_UNORM;
 688     else if (mesaVis->alphaBits == 0)
 689         rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8X8_UNORM : MESA_FORMAT_X8R8G8B8_UNORM;
 690     else
 691         rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8A8_UNORM : MESA_FORMAT_A8R8G8B8_UNORM;
 692
 693     /* front color renderbuffer */
 694     rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
 695     _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
 696     rfb->color_rb[0]->has_surface = 1;
 697
 698     /* back color renderbuffer */
 699     if (mesaVis->doubleBufferMode) {
 700       rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
 701         _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
 702         rfb->color_rb[1]->has_surface = 1;
 703     }
 704
 705     if (mesaVis->depthBits == 24) {
 706       if (mesaVis->stencilBits == 8) {
 707         struct radeon_renderbuffer *depthStencilRb =
 708            radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, driDrawPriv);
 709         _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
 710         _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base);
 711         depthStencilRb->has_surface = screen->depthHasSurface;
 712       } else {
 713         /* depth renderbuffer */
 714         struct radeon_renderbuffer *depth =
 715            radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, driDrawPriv);
 716         _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
 717         depth->has_surface = screen->depthHasSurface;
 718       }
 719     } else if (mesaVis->depthBits == 16) {
 720         /* just 16-bit depth buffer, no hw stencil */
 721         struct radeon_renderbuffer *depth =
 722            radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16, driDrawPriv);
 723         _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
 724         depth->has_surface = screen->depthHasSurface;
 725     }
 726
 727     _swrast_add_soft_renderbuffers(&rfb->base,
 728             GL_FALSE, /* color */
 729             swDepth,
 730             swStencil,
 731             swAccum,
 732             swAlpha,
 733             GL_FALSE /* aux */);
 734     driDrawPriv->driverPrivate = (void *) rfb;
 735
 736     return (driDrawPriv->driverPrivate != NULL);
 737 }
 738
 739
 740 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
 741 {
 742         struct radeon_renderbuffer *rb;
 743
 744         rb = rfb->color_rb[0];
 745         if (rb && rb->bo) {
 746                 radeon_bo_unref(rb->bo);
 747                 rb->bo = NULL;
 748         }
 749         rb = rfb->color_rb[1];
 750         if (rb && rb->bo) {
 751                 radeon_bo_unref(rb->bo);
 752                 rb->bo = NULL;
 753         }
 754         rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
 755         if (rb && rb->bo) {
 756                 radeon_bo_unref(rb->bo);
 757                 rb->bo = NULL;
 758         }
 759 }
 760
 761 void
 762 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
 763 {
 764     struct radeon_framebuffer *rfb;
 765     if (!driDrawPriv)
 766         return;
 767
 768     rfb = (void*)driDrawPriv->driverPrivate;
 769     if (!rfb)
 770         return;
 771     radeon_cleanup_renderbuffers(rfb);
 772     _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
 773 }
 774
 775 /**
 776  * This is the driver specific part of the createNewScreen entry point.
 777  * Called when using DRI2.
 778  *
 779  * \return the struct gl_config supported by this driver
 780  */
 781 static const
 782 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
 783 {
 784    static const mesa_format formats[3] = {
 785       MESA_FORMAT_B5G6R5_UNORM,
 786       MESA_FORMAT_B8G8R8X8_UNORM,
 787       MESA_FORMAT_B8G8R8A8_UNORM
 788    };
 789    /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
 790     * support pageflipping at all.
 791     */
 792    static const GLenum back_buffer_modes[] = {
 793      GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
 794    };
 795    uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
 796    int color;
 797    __DRIconfig **configs = NULL;
 798
 799    psp->max_gl_compat_version = 13;
 800    psp->max_gl_es1_version = 11;
 801
 802    if (!radeonInitDriver(psp)) {
 803        return NULL;
 804     }
 805    depth_bits[0] = 0;
 806    stencil_bits[0] = 0;
 807    depth_bits[1] = 16;
 808    stencil_bits[1] = 0;
 809    depth_bits[2] = 24;
 810    stencil_bits[2] = 0;
 811    depth_bits[3] = 24;
 812    stencil_bits[3] = 8;
 813
 814    msaa_samples_array[0] = 0;
 815
 816    for (color = 0; color < ARRAY_SIZE(formats); color++) {
 817       __DRIconfig **new_configs;
 818
 819       new_configs = driCreateConfigs(formats[color],
 820                                      depth_bits,
 821                                      stencil_bits,
 822                                      ARRAY_SIZE(depth_bits),
 823                                      back_buffer_modes,
 824                                      ARRAY_SIZE(back_buffer_modes),
 825                                      msaa_samples_array,
 826                                      ARRAY_SIZE(msaa_samples_array),
 827                                      GL_TRUE);
 828       configs = driConcatConfigs(configs, new_configs);
 829    }
 830
 831    if (configs == NULL) {
 832       fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
 833               __LINE__);
 834       return NULL;
 835    }
 836
 837    return (const __DRIconfig **)configs;
 838 }
 839
 840 static const struct __DriverAPIRec radeon_driver_api = {
 841    .InitScreen      = radeonInitScreen2,
 842    .DestroyScreen   = radeonDestroyScreen,
 843 #if defined(RADEON_R200)
 844    .CreateContext   = r200CreateContext,
 845    .DestroyContext  = r200DestroyContext,
 846 #else
 847    .CreateContext   = r100CreateContext,
 848    .DestroyContext  = radeonDestroyContext,
 849 #endif
 850    .CreateBuffer    = radeonCreateBuffer,
 851    .DestroyBuffer   = radeonDestroyBuffer,
 852    .MakeCurrent     = radeonMakeCurrent,
 853    .UnbindContext   = radeonUnbindContext,
 854 };
 855
 856 static const struct __DRIDriverVtableExtensionRec radeon_vtable = {
 857    .base = { __DRI_DRIVER_VTABLE, 1 },
 858    .vtable = &radeon_driver_api,
 859 };
 860
 861 /* This is the table of extensions that the loader will dlsym() for. */
 862 static const __DRIextension *radeon_driver_extensions[] = {
 863     &driCoreExtension.base,
 864     &driDRI2Extension.base,
 865     &radeon_config_options.base,
 866     &radeon_vtable.base,
 867     NULL
 868 };
 869
 870 #ifdef RADEON_R200
 871 PUBLIC const __DRIextension **__driDriverGetExtensions_r200(void)
 872 {
 873    globalDriverAPI = &radeon_driver_api;
 874
 875    return radeon_driver_extensions;
 876 }
 877 #else
 878 PUBLIC const __DRIextension **__driDriverGetExtensions_radeon(void)
 879 {
 880    globalDriverAPI = &radeon_driver_api;
 881
 882    return radeon_driver_extensions;
 883 }
 884 #endif