1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #if defined(RADEON_R100)
51 #include "radeon_context.h"
52 #include "radeon_tex.h"
53 #elif defined(RADEON_R200)
54 #include "r200_context.h"
56 #elif defined(RADEON_R300)
57 #include "r300_context.h"
59 #elif defined(RADEON_R600)
60 #include "r600_context.h"
61 #include "r700_driconf.h" /* +r6/r7 */
62 #include "r600_tex.h" /* +r6/r7 */
68 #include "radeon_bocs_wrapper.h"
70 #include "GL/internal/dri_interface.h"
72 /* Radeon configuration
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 #if defined(RADEON_R100) /* R100 */
83 PUBLIC
const char __driConfigOptions
[] =
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
107 static const GLuint __driNConfigOptions
= 15;
109 #elif defined(RADEON_R200)
111 PUBLIC
const char __driConfigOptions
[] =
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 static const GLuint __driNConfigOptions
= 17;
141 #elif defined(RADEON_R300) || defined(RADEON_R600)
143 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
144 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
146 /* TODO: integrate these into xmlpool.h! */
147 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture image units") \
150 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Number of texture coordinate units") \
156 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
161 #define DRI_CONF_DISABLE_S3TC(def) \
162 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
163 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 #define DRI_CONF_DISABLE_FALLBACK(def) \
167 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
172 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 #define DRI_CONF_FP_OPTIMIZATION(def) \
177 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
179 DRI_CONF_ENUM(0,"Optimize for Speed") \
180 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 PUBLIC
const char __driConfigOptions
[] =
186 DRI_CONF_SECTION_PERFORMANCE
187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
193 DRI_CONF_DISABLE_FALLBACK(true)
194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196 DRI_CONF_SECTION_QUALITY
197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
199 DRI_CONF_FORCE_S3TC_ENABLE(false)
200 DRI_CONF_DISABLE_S3TC(false)
201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
206 DRI_CONF_SECTION_DEBUG
207 DRI_CONF_NO_RAST(false)
210 static const GLuint __driNConfigOptions
= 17;
214 static int getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
);
217 radeonGetParam(__DRIscreen
*sPriv
, int param
, void *value
)
220 drm_radeon_getparam_t gp
= { 0 };
221 struct drm_radeon_info info
= { 0 };
223 if (sPriv
->drm_version
.major
>= 2) {
224 info
.value
= (uint64_t)(uintptr_t)value
;
226 case RADEON_PARAM_DEVICE_ID
:
227 info
.request
= RADEON_INFO_DEVICE_ID
;
229 case RADEON_PARAM_NUM_GB_PIPES
:
230 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
232 case RADEON_PARAM_NUM_Z_PIPES
:
233 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
238 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
243 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
248 static const __DRIconfig
**
249 radeonFillInModes( __DRIscreen
*psp
,
250 unsigned pixel_bits
, unsigned depth_bits
,
251 unsigned stencil_bits
, GLboolean have_back_buffer
)
253 __DRIconfig
**configs
;
255 unsigned depth_buffer_factor
;
256 unsigned back_buffer_factor
;
259 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
260 * enough to add support. Basically, if a context is created with an
261 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
262 * will never be used.
264 static const GLenum back_buffer_modes
[] = {
265 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
268 uint8_t depth_bits_array
[2];
269 uint8_t stencil_bits_array
[2];
270 uint8_t msaa_samples_array
[1];
272 depth_bits_array
[0] = depth_bits
;
273 depth_bits_array
[1] = depth_bits
;
275 /* Just like with the accumulation buffer, always provide some modes
276 * with a stencil buffer. It will be a sw fallback, but some apps won't
279 stencil_bits_array
[0] = stencil_bits
;
280 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
282 msaa_samples_array
[0] = 0;
284 depth_buffer_factor
= (stencil_bits
== 0) ? 2 : 1;
285 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
287 if (pixel_bits
== 16) {
288 __DRIconfig
**configs_a8r8g8b8
;
289 __DRIconfig
**configs_r5g6b5
;
291 configs_r5g6b5
= driCreateConfigs(GL_RGB
, GL_UNSIGNED_SHORT_5_6_5
,
292 depth_bits_array
, stencil_bits_array
,
293 depth_buffer_factor
, back_buffer_modes
,
294 back_buffer_factor
, msaa_samples_array
,
296 configs_a8r8g8b8
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
297 depth_bits_array
, stencil_bits_array
,
298 1, back_buffer_modes
, 1,
299 msaa_samples_array
, 1, GL_TRUE
);
300 configs
= driConcatConfigs(configs_r5g6b5
, configs_a8r8g8b8
);
302 configs
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
303 depth_bits_array
, stencil_bits_array
,
305 back_buffer_modes
, back_buffer_factor
,
306 msaa_samples_array
, 1, GL_TRUE
);
308 if (configs
== NULL
) {
309 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
310 __func__
, __LINE__
);
314 /* Mark the visual as slow if there are "fake" stencil bits.
316 for (i
= 0; configs
[i
]; i
++) {
317 m
= &configs
[i
]->modes
;
318 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
319 m
->visualRating
= GLX_SLOW_CONFIG
;
323 return (const __DRIconfig
**) configs
;
326 #if defined(RADEON_R100)
327 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
328 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
332 static const __DRItexBufferExtension radeonTexBufferExtension
= {
333 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
339 #if defined(RADEON_R200)
341 static const __DRItexOffsetExtension r200texOffsetExtension
= {
342 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
346 static const __DRItexBufferExtension r200TexBufferExtension
= {
347 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
353 #if defined(RADEON_R300)
354 static const __DRItexOffsetExtension r300texOffsetExtension
= {
355 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
359 static const __DRItexBufferExtension r300TexBufferExtension
= {
360 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
366 #if defined(RADEON_R600)
367 static const __DRItexOffsetExtension r600texOffsetExtension
= {
368 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
369 r600SetTexOffset
, /* +r6/r7 */
372 static const __DRItexBufferExtension r600TexBufferExtension
= {
373 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
374 r600SetTexBuffer
, /* +r6/r7 */
375 r600SetTexBuffer2
, /* +r6/r7 */
379 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
381 screen
->device_id
= device_id
;
382 screen
->chip_flags
= 0;
383 switch ( device_id
) {
384 case PCI_CHIP_RN50_515E
:
385 case PCI_CHIP_RN50_5969
:
388 case PCI_CHIP_RADEON_LY
:
389 case PCI_CHIP_RADEON_LZ
:
390 case PCI_CHIP_RADEON_QY
:
391 case PCI_CHIP_RADEON_QZ
:
392 screen
->chip_family
= CHIP_FAMILY_RV100
;
395 case PCI_CHIP_RS100_4136
:
396 case PCI_CHIP_RS100_4336
:
397 screen
->chip_family
= CHIP_FAMILY_RS100
;
400 case PCI_CHIP_RS200_4137
:
401 case PCI_CHIP_RS200_4337
:
402 case PCI_CHIP_RS250_4237
:
403 case PCI_CHIP_RS250_4437
:
404 screen
->chip_family
= CHIP_FAMILY_RS200
;
407 case PCI_CHIP_RADEON_QD
:
408 case PCI_CHIP_RADEON_QE
:
409 case PCI_CHIP_RADEON_QF
:
410 case PCI_CHIP_RADEON_QG
:
411 /* all original radeons (7200) presumably have a stencil op bug */
412 screen
->chip_family
= CHIP_FAMILY_R100
;
413 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
416 case PCI_CHIP_RV200_QW
:
417 case PCI_CHIP_RV200_QX
:
418 case PCI_CHIP_RADEON_LW
:
419 case PCI_CHIP_RADEON_LX
:
420 screen
->chip_family
= CHIP_FAMILY_RV200
;
421 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
424 case PCI_CHIP_R200_BB
:
425 case PCI_CHIP_R200_BC
:
426 case PCI_CHIP_R200_QH
:
427 case PCI_CHIP_R200_QL
:
428 case PCI_CHIP_R200_QM
:
429 screen
->chip_family
= CHIP_FAMILY_R200
;
430 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
433 case PCI_CHIP_RV250_If
:
434 case PCI_CHIP_RV250_Ig
:
435 case PCI_CHIP_RV250_Ld
:
436 case PCI_CHIP_RV250_Lf
:
437 case PCI_CHIP_RV250_Lg
:
438 screen
->chip_family
= CHIP_FAMILY_RV250
;
439 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
442 case PCI_CHIP_RV280_5960
:
443 case PCI_CHIP_RV280_5961
:
444 case PCI_CHIP_RV280_5962
:
445 case PCI_CHIP_RV280_5964
:
446 case PCI_CHIP_RV280_5965
:
447 case PCI_CHIP_RV280_5C61
:
448 case PCI_CHIP_RV280_5C63
:
449 screen
->chip_family
= CHIP_FAMILY_RV280
;
450 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
453 case PCI_CHIP_RS300_5834
:
454 case PCI_CHIP_RS300_5835
:
455 case PCI_CHIP_RS350_7834
:
456 case PCI_CHIP_RS350_7835
:
457 screen
->chip_family
= CHIP_FAMILY_RS300
;
460 case PCI_CHIP_R300_AD
:
461 case PCI_CHIP_R300_AE
:
462 case PCI_CHIP_R300_AF
:
463 case PCI_CHIP_R300_AG
:
464 case PCI_CHIP_R300_ND
:
465 case PCI_CHIP_R300_NE
:
466 case PCI_CHIP_R300_NF
:
467 case PCI_CHIP_R300_NG
:
468 screen
->chip_family
= CHIP_FAMILY_R300
;
469 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
472 case PCI_CHIP_RV350_AP
:
473 case PCI_CHIP_RV350_AQ
:
474 case PCI_CHIP_RV350_AR
:
475 case PCI_CHIP_RV350_AS
:
476 case PCI_CHIP_RV350_AT
:
477 case PCI_CHIP_RV350_AV
:
478 case PCI_CHIP_RV350_AU
:
479 case PCI_CHIP_RV350_NP
:
480 case PCI_CHIP_RV350_NQ
:
481 case PCI_CHIP_RV350_NR
:
482 case PCI_CHIP_RV350_NS
:
483 case PCI_CHIP_RV350_NT
:
484 case PCI_CHIP_RV350_NV
:
485 screen
->chip_family
= CHIP_FAMILY_RV350
;
486 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
489 case PCI_CHIP_R350_AH
:
490 case PCI_CHIP_R350_AI
:
491 case PCI_CHIP_R350_AJ
:
492 case PCI_CHIP_R350_AK
:
493 case PCI_CHIP_R350_NH
:
494 case PCI_CHIP_R350_NI
:
495 case PCI_CHIP_R360_NJ
:
496 case PCI_CHIP_R350_NK
:
497 screen
->chip_family
= CHIP_FAMILY_R350
;
498 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
501 case PCI_CHIP_RV370_5460
:
502 case PCI_CHIP_RV370_5462
:
503 case PCI_CHIP_RV370_5464
:
504 case PCI_CHIP_RV370_5B60
:
505 case PCI_CHIP_RV370_5B62
:
506 case PCI_CHIP_RV370_5B63
:
507 case PCI_CHIP_RV370_5B64
:
508 case PCI_CHIP_RV370_5B65
:
509 case PCI_CHIP_RV380_3150
:
510 case PCI_CHIP_RV380_3152
:
511 case PCI_CHIP_RV380_3154
:
512 case PCI_CHIP_RV380_3155
:
513 case PCI_CHIP_RV380_3E50
:
514 case PCI_CHIP_RV380_3E54
:
515 screen
->chip_family
= CHIP_FAMILY_RV380
;
516 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
519 case PCI_CHIP_R420_JN
:
520 case PCI_CHIP_R420_JH
:
521 case PCI_CHIP_R420_JI
:
522 case PCI_CHIP_R420_JJ
:
523 case PCI_CHIP_R420_JK
:
524 case PCI_CHIP_R420_JL
:
525 case PCI_CHIP_R420_JM
:
526 case PCI_CHIP_R420_JO
:
527 case PCI_CHIP_R420_JP
:
528 case PCI_CHIP_R420_JT
:
529 case PCI_CHIP_R481_4B49
:
530 case PCI_CHIP_R481_4B4A
:
531 case PCI_CHIP_R481_4B4B
:
532 case PCI_CHIP_R481_4B4C
:
533 case PCI_CHIP_R423_UH
:
534 case PCI_CHIP_R423_UI
:
535 case PCI_CHIP_R423_UJ
:
536 case PCI_CHIP_R423_UK
:
537 case PCI_CHIP_R430_554C
:
538 case PCI_CHIP_R430_554D
:
539 case PCI_CHIP_R430_554E
:
540 case PCI_CHIP_R430_554F
:
541 case PCI_CHIP_R423_5550
:
542 case PCI_CHIP_R423_UQ
:
543 case PCI_CHIP_R423_UR
:
544 case PCI_CHIP_R423_UT
:
545 case PCI_CHIP_R430_5D48
:
546 case PCI_CHIP_R430_5D49
:
547 case PCI_CHIP_R430_5D4A
:
548 case PCI_CHIP_R480_5D4C
:
549 case PCI_CHIP_R480_5D4D
:
550 case PCI_CHIP_R480_5D4E
:
551 case PCI_CHIP_R480_5D4F
:
552 case PCI_CHIP_R480_5D50
:
553 case PCI_CHIP_R480_5D52
:
554 case PCI_CHIP_R423_5D57
:
555 screen
->chip_family
= CHIP_FAMILY_R420
;
556 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
559 case PCI_CHIP_RV410_5E4C
:
560 case PCI_CHIP_RV410_5E4F
:
561 case PCI_CHIP_RV410_564A
:
562 case PCI_CHIP_RV410_564B
:
563 case PCI_CHIP_RV410_564F
:
564 case PCI_CHIP_RV410_5652
:
565 case PCI_CHIP_RV410_5653
:
566 case PCI_CHIP_RV410_5657
:
567 case PCI_CHIP_RV410_5E48
:
568 case PCI_CHIP_RV410_5E4A
:
569 case PCI_CHIP_RV410_5E4B
:
570 case PCI_CHIP_RV410_5E4D
:
571 screen
->chip_family
= CHIP_FAMILY_RV410
;
572 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
575 case PCI_CHIP_RS480_5954
:
576 case PCI_CHIP_RS480_5955
:
577 case PCI_CHIP_RS482_5974
:
578 case PCI_CHIP_RS482_5975
:
579 case PCI_CHIP_RS400_5A41
:
580 case PCI_CHIP_RS400_5A42
:
581 case PCI_CHIP_RC410_5A61
:
582 case PCI_CHIP_RC410_5A62
:
583 screen
->chip_family
= CHIP_FAMILY_RS400
;
586 case PCI_CHIP_RS600_793F
:
587 case PCI_CHIP_RS600_7941
:
588 case PCI_CHIP_RS600_7942
:
589 screen
->chip_family
= CHIP_FAMILY_RS600
;
592 case PCI_CHIP_RS690_791E
:
593 case PCI_CHIP_RS690_791F
:
594 screen
->chip_family
= CHIP_FAMILY_RS690
;
596 case PCI_CHIP_RS740_796C
:
597 case PCI_CHIP_RS740_796D
:
598 case PCI_CHIP_RS740_796E
:
599 case PCI_CHIP_RS740_796F
:
600 screen
->chip_family
= CHIP_FAMILY_RS740
;
603 case PCI_CHIP_R520_7100
:
604 case PCI_CHIP_R520_7101
:
605 case PCI_CHIP_R520_7102
:
606 case PCI_CHIP_R520_7103
:
607 case PCI_CHIP_R520_7104
:
608 case PCI_CHIP_R520_7105
:
609 case PCI_CHIP_R520_7106
:
610 case PCI_CHIP_R520_7108
:
611 case PCI_CHIP_R520_7109
:
612 case PCI_CHIP_R520_710A
:
613 case PCI_CHIP_R520_710B
:
614 case PCI_CHIP_R520_710C
:
615 case PCI_CHIP_R520_710E
:
616 case PCI_CHIP_R520_710F
:
617 screen
->chip_family
= CHIP_FAMILY_R520
;
618 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
621 case PCI_CHIP_RV515_7140
:
622 case PCI_CHIP_RV515_7141
:
623 case PCI_CHIP_RV515_7142
:
624 case PCI_CHIP_RV515_7143
:
625 case PCI_CHIP_RV515_7144
:
626 case PCI_CHIP_RV515_7145
:
627 case PCI_CHIP_RV515_7146
:
628 case PCI_CHIP_RV515_7147
:
629 case PCI_CHIP_RV515_7149
:
630 case PCI_CHIP_RV515_714A
:
631 case PCI_CHIP_RV515_714B
:
632 case PCI_CHIP_RV515_714C
:
633 case PCI_CHIP_RV515_714D
:
634 case PCI_CHIP_RV515_714E
:
635 case PCI_CHIP_RV515_714F
:
636 case PCI_CHIP_RV515_7151
:
637 case PCI_CHIP_RV515_7152
:
638 case PCI_CHIP_RV515_7153
:
639 case PCI_CHIP_RV515_715E
:
640 case PCI_CHIP_RV515_715F
:
641 case PCI_CHIP_RV515_7180
:
642 case PCI_CHIP_RV515_7181
:
643 case PCI_CHIP_RV515_7183
:
644 case PCI_CHIP_RV515_7186
:
645 case PCI_CHIP_RV515_7187
:
646 case PCI_CHIP_RV515_7188
:
647 case PCI_CHIP_RV515_718A
:
648 case PCI_CHIP_RV515_718B
:
649 case PCI_CHIP_RV515_718C
:
650 case PCI_CHIP_RV515_718D
:
651 case PCI_CHIP_RV515_718F
:
652 case PCI_CHIP_RV515_7193
:
653 case PCI_CHIP_RV515_7196
:
654 case PCI_CHIP_RV515_719B
:
655 case PCI_CHIP_RV515_719F
:
656 case PCI_CHIP_RV515_7200
:
657 case PCI_CHIP_RV515_7210
:
658 case PCI_CHIP_RV515_7211
:
659 screen
->chip_family
= CHIP_FAMILY_RV515
;
660 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
663 case PCI_CHIP_RV530_71C0
:
664 case PCI_CHIP_RV530_71C1
:
665 case PCI_CHIP_RV530_71C2
:
666 case PCI_CHIP_RV530_71C3
:
667 case PCI_CHIP_RV530_71C4
:
668 case PCI_CHIP_RV530_71C5
:
669 case PCI_CHIP_RV530_71C6
:
670 case PCI_CHIP_RV530_71C7
:
671 case PCI_CHIP_RV530_71CD
:
672 case PCI_CHIP_RV530_71CE
:
673 case PCI_CHIP_RV530_71D2
:
674 case PCI_CHIP_RV530_71D4
:
675 case PCI_CHIP_RV530_71D5
:
676 case PCI_CHIP_RV530_71D6
:
677 case PCI_CHIP_RV530_71DA
:
678 case PCI_CHIP_RV530_71DE
:
679 screen
->chip_family
= CHIP_FAMILY_RV530
;
680 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
683 case PCI_CHIP_R580_7240
:
684 case PCI_CHIP_R580_7243
:
685 case PCI_CHIP_R580_7244
:
686 case PCI_CHIP_R580_7245
:
687 case PCI_CHIP_R580_7246
:
688 case PCI_CHIP_R580_7247
:
689 case PCI_CHIP_R580_7248
:
690 case PCI_CHIP_R580_7249
:
691 case PCI_CHIP_R580_724A
:
692 case PCI_CHIP_R580_724B
:
693 case PCI_CHIP_R580_724C
:
694 case PCI_CHIP_R580_724D
:
695 case PCI_CHIP_R580_724E
:
696 case PCI_CHIP_R580_724F
:
697 case PCI_CHIP_R580_7284
:
698 screen
->chip_family
= CHIP_FAMILY_R580
;
699 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
702 case PCI_CHIP_RV570_7280
:
703 case PCI_CHIP_RV560_7281
:
704 case PCI_CHIP_RV560_7283
:
705 case PCI_CHIP_RV560_7287
:
706 case PCI_CHIP_RV570_7288
:
707 case PCI_CHIP_RV570_7289
:
708 case PCI_CHIP_RV570_728B
:
709 case PCI_CHIP_RV570_728C
:
710 case PCI_CHIP_RV560_7290
:
711 case PCI_CHIP_RV560_7291
:
712 case PCI_CHIP_RV560_7293
:
713 case PCI_CHIP_RV560_7297
:
714 screen
->chip_family
= CHIP_FAMILY_RV560
;
715 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
718 case PCI_CHIP_R600_9400
:
719 case PCI_CHIP_R600_9401
:
720 case PCI_CHIP_R600_9402
:
721 case PCI_CHIP_R600_9403
:
722 case PCI_CHIP_R600_9405
:
723 case PCI_CHIP_R600_940A
:
724 case PCI_CHIP_R600_940B
:
725 case PCI_CHIP_R600_940F
:
726 screen
->chip_family
= CHIP_FAMILY_R600
;
727 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
730 case PCI_CHIP_RV610_94C0
:
731 case PCI_CHIP_RV610_94C1
:
732 case PCI_CHIP_RV610_94C3
:
733 case PCI_CHIP_RV610_94C4
:
734 case PCI_CHIP_RV610_94C5
:
735 case PCI_CHIP_RV610_94C6
:
736 case PCI_CHIP_RV610_94C7
:
737 case PCI_CHIP_RV610_94C8
:
738 case PCI_CHIP_RV610_94C9
:
739 case PCI_CHIP_RV610_94CB
:
740 case PCI_CHIP_RV610_94CC
:
741 case PCI_CHIP_RV610_94CD
:
742 screen
->chip_family
= CHIP_FAMILY_RV610
;
743 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
746 case PCI_CHIP_RV630_9580
:
747 case PCI_CHIP_RV630_9581
:
748 case PCI_CHIP_RV630_9583
:
749 case PCI_CHIP_RV630_9586
:
750 case PCI_CHIP_RV630_9587
:
751 case PCI_CHIP_RV630_9588
:
752 case PCI_CHIP_RV630_9589
:
753 case PCI_CHIP_RV630_958A
:
754 case PCI_CHIP_RV630_958B
:
755 case PCI_CHIP_RV630_958C
:
756 case PCI_CHIP_RV630_958D
:
757 case PCI_CHIP_RV630_958E
:
758 case PCI_CHIP_RV630_958F
:
759 screen
->chip_family
= CHIP_FAMILY_RV630
;
760 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
763 case PCI_CHIP_RV670_9500
:
764 case PCI_CHIP_RV670_9501
:
765 case PCI_CHIP_RV670_9504
:
766 case PCI_CHIP_RV670_9505
:
767 case PCI_CHIP_RV670_9506
:
768 case PCI_CHIP_RV670_9507
:
769 case PCI_CHIP_RV670_9508
:
770 case PCI_CHIP_RV670_9509
:
771 case PCI_CHIP_RV670_950F
:
772 case PCI_CHIP_RV670_9511
:
773 case PCI_CHIP_RV670_9515
:
774 case PCI_CHIP_RV670_9517
:
775 case PCI_CHIP_RV670_9519
:
776 screen
->chip_family
= CHIP_FAMILY_RV670
;
777 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
780 case PCI_CHIP_RV620_95C0
:
781 case PCI_CHIP_RV620_95C2
:
782 case PCI_CHIP_RV620_95C4
:
783 case PCI_CHIP_RV620_95C5
:
784 case PCI_CHIP_RV620_95C6
:
785 case PCI_CHIP_RV620_95C7
:
786 case PCI_CHIP_RV620_95C9
:
787 case PCI_CHIP_RV620_95CC
:
788 case PCI_CHIP_RV620_95CD
:
789 case PCI_CHIP_RV620_95CE
:
790 case PCI_CHIP_RV620_95CF
:
791 screen
->chip_family
= CHIP_FAMILY_RV620
;
792 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
795 case PCI_CHIP_RV635_9590
:
796 case PCI_CHIP_RV635_9591
:
797 case PCI_CHIP_RV635_9593
:
798 case PCI_CHIP_RV635_9595
:
799 case PCI_CHIP_RV635_9596
:
800 case PCI_CHIP_RV635_9597
:
801 case PCI_CHIP_RV635_9598
:
802 case PCI_CHIP_RV635_9599
:
803 case PCI_CHIP_RV635_959B
:
804 screen
->chip_family
= CHIP_FAMILY_RV635
;
805 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
808 case PCI_CHIP_RS780_9610
:
809 case PCI_CHIP_RS780_9611
:
810 case PCI_CHIP_RS780_9612
:
811 case PCI_CHIP_RS780_9613
:
812 case PCI_CHIP_RS780_9614
:
813 case PCI_CHIP_RS780_9615
:
814 case PCI_CHIP_RS780_9616
:
815 screen
->chip_family
= CHIP_FAMILY_RS780
;
816 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
818 case PCI_CHIP_RS880_9710
:
819 case PCI_CHIP_RS880_9711
:
820 case PCI_CHIP_RS880_9712
:
821 case PCI_CHIP_RS880_9713
:
822 case PCI_CHIP_RS880_9714
:
823 case PCI_CHIP_RS880_9715
:
824 screen
->chip_family
= CHIP_FAMILY_RS880
;
825 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
828 case PCI_CHIP_RV770_9440
:
829 case PCI_CHIP_RV770_9441
:
830 case PCI_CHIP_RV770_9442
:
831 case PCI_CHIP_RV770_9443
:
832 case PCI_CHIP_RV770_9444
:
833 case PCI_CHIP_RV770_9446
:
834 case PCI_CHIP_RV770_944A
:
835 case PCI_CHIP_RV770_944B
:
836 case PCI_CHIP_RV770_944C
:
837 case PCI_CHIP_RV770_944E
:
838 case PCI_CHIP_RV770_9450
:
839 case PCI_CHIP_RV770_9452
:
840 case PCI_CHIP_RV770_9456
:
841 case PCI_CHIP_RV770_945A
:
842 case PCI_CHIP_RV770_945B
:
843 case PCI_CHIP_RV770_945E
:
844 case PCI_CHIP_RV790_9460
:
845 case PCI_CHIP_RV790_9462
:
846 case PCI_CHIP_RV770_946A
:
847 case PCI_CHIP_RV770_946B
:
848 case PCI_CHIP_RV770_947A
:
849 case PCI_CHIP_RV770_947B
:
850 screen
->chip_family
= CHIP_FAMILY_RV770
;
851 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
854 case PCI_CHIP_RV730_9480
:
855 case PCI_CHIP_RV730_9487
:
856 case PCI_CHIP_RV730_9488
:
857 case PCI_CHIP_RV730_9489
:
858 case PCI_CHIP_RV730_948A
:
859 case PCI_CHIP_RV730_948F
:
860 case PCI_CHIP_RV730_9490
:
861 case PCI_CHIP_RV730_9491
:
862 case PCI_CHIP_RV730_9495
:
863 case PCI_CHIP_RV730_9498
:
864 case PCI_CHIP_RV730_949C
:
865 case PCI_CHIP_RV730_949E
:
866 case PCI_CHIP_RV730_949F
:
867 screen
->chip_family
= CHIP_FAMILY_RV730
;
868 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
871 case PCI_CHIP_RV710_9540
:
872 case PCI_CHIP_RV710_9541
:
873 case PCI_CHIP_RV710_9542
:
874 case PCI_CHIP_RV710_954E
:
875 case PCI_CHIP_RV710_954F
:
876 case PCI_CHIP_RV710_9552
:
877 case PCI_CHIP_RV710_9553
:
878 case PCI_CHIP_RV710_9555
:
879 case PCI_CHIP_RV710_9557
:
880 case PCI_CHIP_RV710_955F
:
881 screen
->chip_family
= CHIP_FAMILY_RV710
;
882 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
885 case PCI_CHIP_RV740_94A0
:
886 case PCI_CHIP_RV740_94A1
:
887 case PCI_CHIP_RV740_94A3
:
888 case PCI_CHIP_RV740_94B1
:
889 case PCI_CHIP_RV740_94B3
:
890 case PCI_CHIP_RV740_94B4
:
891 case PCI_CHIP_RV740_94B5
:
892 case PCI_CHIP_RV740_94B9
:
893 screen
->chip_family
= CHIP_FAMILY_RV740
;
894 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
898 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
907 /* Create the device specific screen private data struct.
909 static radeonScreenPtr
910 radeonCreateScreen( __DRIscreen
*sPriv
)
912 radeonScreenPtr screen
;
913 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
914 unsigned char *RADEONMMIO
= NULL
;
919 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
920 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
924 /* Allocate the private area */
925 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
927 __driUtilMessage("%s: Could not allocate memory for screen structure",
934 /* parse information in __driConfigOptions */
935 driParseOptionInfo (&screen
->optionCache
,
936 __driConfigOptions
, __driNConfigOptions
);
938 /* This is first since which regions we map depends on whether or
939 * not we are using a PCI card.
941 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
945 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BUFFER_OFFSET
,
946 &screen
->gart_buffer_offset
);
950 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
954 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BASE
,
958 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
962 ret
= radeonGetParam(sPriv
, RADEON_PARAM_IRQ_NR
,
966 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
969 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
970 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
971 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
972 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
973 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
974 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
975 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
976 screen
->drmSupportsOcclusionQueries
= (sPriv
->drm_version
.minor
>= 30);
979 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
983 screen
->mmio
.handle
= dri_priv
->registerHandle
;
984 screen
->mmio
.size
= dri_priv
->registerSize
;
985 if ( drmMap( sPriv
->fd
,
988 &screen
->mmio
.map
) ) {
990 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
994 RADEONMMIO
= screen
->mmio
.map
;
996 screen
->status
.handle
= dri_priv
->statusHandle
;
997 screen
->status
.size
= dri_priv
->statusSize
;
998 if ( drmMap( sPriv
->fd
,
999 screen
->status
.handle
,
1000 screen
->status
.size
,
1001 &screen
->status
.map
) ) {
1002 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1004 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
1007 if (screen
->chip_family
< CHIP_FAMILY_R600
)
1008 screen
->scratch
= (__volatile__
uint32_t *)
1009 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
1011 screen
->scratch
= (__volatile__
uint32_t *)
1012 ((GLubyte
*)screen
->status
.map
+ R600_SCRATCH_REG_OFFSET
);
1014 screen
->buffers
= drmMapBufs( sPriv
->fd
);
1015 if ( !screen
->buffers
) {
1016 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1017 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1019 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
1023 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
1024 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
1025 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
1026 if ( drmMap( sPriv
->fd
,
1027 screen
->gartTextures
.handle
,
1028 screen
->gartTextures
.size
,
1029 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
1030 drmUnmapBufs( screen
->buffers
);
1031 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1032 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1034 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
1038 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
1041 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
1042 sPriv
->ddx_version
.minor
< 2) {
1043 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1047 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
1048 fprintf(stderr
, "R500 support requires a newer drm.\n");
1052 if (getenv("R300_NO_TCL"))
1053 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1055 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1056 screen
->chip_flags
|= RADEON_CLASS_R100
;
1057 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1058 screen
->chip_flags
|= RADEON_CLASS_R200
;
1059 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1060 screen
->chip_flags
|= RADEON_CLASS_R300
;
1062 screen
->chip_flags
|= RADEON_CLASS_R600
;
1064 screen
->cpp
= dri_priv
->bpp
/ 8;
1065 screen
->AGPMode
= dri_priv
->AGPMode
;
1067 ret
= radeonGetParam(sPriv
, RADEON_PARAM_FB_LOCATION
, &temp
);
1070 if(screen
->chip_family
>= CHIP_FAMILY_R600
)
1075 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1080 screen
->fbLocation
= (temp
& 0xffff) << 24;
1087 if (screen
->chip_family
< CHIP_FAMILY_RS600
&& !screen
->kernel_mm
)
1088 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
1092 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1098 screen
->fbLocation
= (temp
& 0xffff) << 16;
1102 if (IS_R300_CLASS(screen
)) {
1103 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1105 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1106 switch (screen
->chip_family
) {
1107 case CHIP_FAMILY_R300
:
1108 case CHIP_FAMILY_R350
:
1109 screen
->num_gb_pipes
= 2;
1111 case CHIP_FAMILY_R420
:
1112 case CHIP_FAMILY_R520
:
1113 case CHIP_FAMILY_R580
:
1114 case CHIP_FAMILY_RV560
:
1115 case CHIP_FAMILY_RV570
:
1116 screen
->num_gb_pipes
= 4;
1118 case CHIP_FAMILY_RV350
:
1119 case CHIP_FAMILY_RV515
:
1120 case CHIP_FAMILY_RV530
:
1121 case CHIP_FAMILY_RV410
:
1123 screen
->num_gb_pipes
= 1;
1127 screen
->num_gb_pipes
= temp
;
1130 /* pipe overrides */
1131 switch (dri_priv
->deviceID
) {
1132 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1133 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1134 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1135 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1136 screen
->num_gb_pipes
= 1;
1142 if ( sPriv
->drm_version
.minor
>= 31 ) {
1143 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1145 screen
->num_z_pipes
= 2;
1147 screen
->num_z_pipes
= temp
;
1149 screen
->num_z_pipes
= 2;
1152 if ( sPriv
->drm_version
.minor
>= 10 ) {
1153 drm_radeon_setparam_t sp
;
1155 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
1156 sp
.value
= screen
->fbLocation
;
1158 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
1159 &sp
, sizeof( sp
) );
1162 screen
->frontOffset
= dri_priv
->frontOffset
;
1163 screen
->frontPitch
= dri_priv
->frontPitch
;
1164 screen
->backOffset
= dri_priv
->backOffset
;
1165 screen
->backPitch
= dri_priv
->backPitch
;
1166 screen
->depthOffset
= dri_priv
->depthOffset
;
1167 screen
->depthPitch
= dri_priv
->depthPitch
;
1169 /* Check if ddx has set up a surface reg to cover depth buffer */
1170 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
1171 /* these chips don't use tiled z without hyperz. So always pretend
1172 we have set up a surface which will cause linear reads/writes */
1173 (IS_R100_CLASS(screen
) &&
1174 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
1176 if ( dri_priv
->textureSize
== 0 ) {
1177 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
1178 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1179 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1180 dri_priv
->log2GARTTexGran
;
1182 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
1183 + screen
->fbLocation
;
1184 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
1185 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1186 dri_priv
->log2TexGran
;
1189 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
1190 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1191 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
1192 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
1193 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
1194 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
1196 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
1197 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
1198 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1199 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
1200 dri_priv
->log2GARTTexGran
;
1204 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1205 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1207 if ( screen
->irq
!= 0 ) {
1208 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1209 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1212 #if defined(RADEON_R100)
1213 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1216 #if defined(RADEON_R200)
1217 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1220 #if defined(RADEON_R300)
1221 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1224 #if defined(RADEON_R600)
1225 screen
->extensions
[i
++] = &r600texOffsetExtension
.base
;
1228 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1230 screen
->extensions
[i
++] = NULL
;
1231 sPriv
->extensions
= screen
->extensions
;
1233 screen
->driScreen
= sPriv
;
1234 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1235 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1236 screen
->sarea_priv_offset
);
1238 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1239 if (screen
->bom
== NULL
) {
1247 static radeonScreenPtr
1248 radeonCreateScreen2(__DRIscreen
*sPriv
)
1250 radeonScreenPtr screen
;
1253 uint32_t device_id
= 0;
1256 /* Allocate the private area */
1257 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1259 __driUtilMessage("%s: Could not allocate memory for screen structure",
1261 fprintf(stderr
, "leaving here\n");
1265 radeon_init_debug();
1267 /* parse information in __driConfigOptions */
1268 driParseOptionInfo (&screen
->optionCache
,
1269 __driConfigOptions
, __driNConfigOptions
);
1271 screen
->kernel_mm
= 1;
1272 screen
->chip_flags
= 0;
1274 /* if we have kms we can support all of these */
1275 screen
->drmSupportsCubeMapsR200
= 1;
1276 screen
->drmSupportsBlendColor
= 1;
1277 screen
->drmSupportsTriPerf
= 1;
1278 screen
->drmSupportsFragShader
= 1;
1279 screen
->drmSupportsPointSprites
= 1;
1280 screen
->drmSupportsCubeMapsR100
= 1;
1281 screen
->drmSupportsVertexProgram
= 1;
1282 screen
->drmSupportsOcclusionQueries
= 1;
1285 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
1288 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1292 ret
= radeon_set_screen_flags(screen
, device_id
);
1296 if (getenv("R300_NO_TCL"))
1297 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1299 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1300 screen
->chip_flags
|= RADEON_CLASS_R100
;
1301 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1302 screen
->chip_flags
|= RADEON_CLASS_R200
;
1303 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1304 screen
->chip_flags
|= RADEON_CLASS_R300
;
1306 screen
->chip_flags
|= RADEON_CLASS_R600
;
1308 if (IS_R300_CLASS(screen
)) {
1309 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1311 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1312 switch (screen
->chip_family
) {
1313 case CHIP_FAMILY_R300
:
1314 case CHIP_FAMILY_R350
:
1315 screen
->num_gb_pipes
= 2;
1317 case CHIP_FAMILY_R420
:
1318 case CHIP_FAMILY_R520
:
1319 case CHIP_FAMILY_R580
:
1320 case CHIP_FAMILY_RV560
:
1321 case CHIP_FAMILY_RV570
:
1322 screen
->num_gb_pipes
= 4;
1324 case CHIP_FAMILY_RV350
:
1325 case CHIP_FAMILY_RV515
:
1326 case CHIP_FAMILY_RV530
:
1327 case CHIP_FAMILY_RV410
:
1329 screen
->num_gb_pipes
= 1;
1333 screen
->num_gb_pipes
= temp
;
1336 /* pipe overrides */
1337 switch (device_id
) {
1338 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1339 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1340 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1341 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1342 screen
->num_gb_pipes
= 1;
1348 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1350 screen
->num_z_pipes
= 2;
1352 screen
->num_z_pipes
= temp
;
1357 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1358 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1359 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1361 if ( screen
->irq
!= 0 ) {
1362 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1363 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1366 #if defined(RADEON_R100)
1367 screen
->extensions
[i
++] = &radeonTexBufferExtension
.base
;
1370 #if defined(RADEON_R200)
1371 screen
->extensions
[i
++] = &r200TexBufferExtension
.base
;
1374 #if defined(RADEON_R300)
1375 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1378 #if defined(RADEON_R600)
1379 screen
->extensions
[i
++] = &r600TexBufferExtension
.base
;
1382 screen
->extensions
[i
++] = NULL
;
1383 sPriv
->extensions
= screen
->extensions
;
1385 screen
->driScreen
= sPriv
;
1386 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1387 if (screen
->bom
== NULL
) {
1394 /* Destroy the device specific screen private data struct.
1397 radeonDestroyScreen( __DRIscreen
*sPriv
)
1399 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1404 if (screen
->kernel_mm
) {
1405 #ifdef RADEON_BO_TRACK
1406 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1408 radeon_bo_manager_gem_dtor(screen
->bom
);
1410 radeon_bo_manager_legacy_dtor(screen
->bom
);
1412 if ( screen
->gartTextures
.map
) {
1413 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1415 drmUnmapBufs( screen
->buffers
);
1416 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1417 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1420 /* free all option information */
1421 driDestroyOptionInfo (&screen
->optionCache
);
1424 sPriv
->private = NULL
;
1428 /* Initialize the driver specific screen private data.
1431 radeonInitDriver( __DRIscreen
*sPriv
)
1433 if (sPriv
->dri2
.enabled
) {
1434 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1436 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1438 if ( !sPriv
->private ) {
1439 radeonDestroyScreen( sPriv
);
1449 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1451 * \todo This function (and its interface) will need to be updated to support
1455 radeonCreateBuffer( __DRIscreen
*driScrnPriv
,
1456 __DRIdrawable
*driDrawPriv
,
1457 const __GLcontextModes
*mesaVis
,
1458 GLboolean isPixmap
)
1460 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1462 const GLboolean swDepth
= GL_FALSE
;
1463 const GLboolean swAlpha
= GL_FALSE
;
1464 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1465 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1466 mesaVis
->depthBits
!= 24;
1467 gl_format rgbFormat
;
1468 struct radeon_framebuffer
*rfb
;
1471 return GL_FALSE
; /* not implemented */
1473 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
1477 _mesa_initialize_window_framebuffer(&rfb
->base
, mesaVis
);
1479 if (mesaVis
->redBits
== 5)
1480 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_RGB565
: MESA_FORMAT_RGB565_REV
;
1481 else if (mesaVis
->alphaBits
== 0)
1482 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_XRGB8888
: MESA_FORMAT_XRGB8888_REV
;
1484 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_ARGB8888
: MESA_FORMAT_ARGB8888_REV
;
1486 /* front color renderbuffer */
1487 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1488 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
);
1489 rfb
->color_rb
[0]->has_surface
= 1;
1491 /* back color renderbuffer */
1492 if (mesaVis
->doubleBufferMode
) {
1493 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1494 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
);
1495 rfb
->color_rb
[1]->has_surface
= 1;
1498 if (mesaVis
->depthBits
== 24) {
1499 if (mesaVis
->stencilBits
== 8) {
1500 struct radeon_renderbuffer
*depthStencilRb
=
1501 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24
, driDrawPriv
);
1502 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
);
1503 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
);
1504 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
1506 /* depth renderbuffer */
1507 struct radeon_renderbuffer
*depth
=
1508 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24
, driDrawPriv
);
1509 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1510 depth
->has_surface
= screen
->depthHasSurface
;
1512 } else if (mesaVis
->depthBits
== 16) {
1513 /* just 16-bit depth buffer, no hw stencil */
1514 struct radeon_renderbuffer
*depth
=
1515 radeon_create_renderbuffer(MESA_FORMAT_Z16
, driDrawPriv
);
1516 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1517 depth
->has_surface
= screen
->depthHasSurface
;
1520 _mesa_add_soft_renderbuffers(&rfb
->base
,
1521 GL_FALSE
, /* color */
1526 GL_FALSE
/* aux */);
1527 driDrawPriv
->driverPrivate
= (void *) rfb
;
1529 return (driDrawPriv
->driverPrivate
!= NULL
);
1533 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
1535 struct radeon_renderbuffer
*rb
;
1537 rb
= rfb
->color_rb
[0];
1539 radeon_bo_unref(rb
->bo
);
1542 rb
= rfb
->color_rb
[1];
1544 radeon_bo_unref(rb
->bo
);
1547 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
1549 radeon_bo_unref(rb
->bo
);
1555 radeonDestroyBuffer(__DRIdrawable
*driDrawPriv
)
1557 struct radeon_framebuffer
*rfb
;
1561 rfb
= (void*)driDrawPriv
->driverPrivate
;
1564 radeon_cleanup_renderbuffers(rfb
);
1565 _mesa_reference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
1570 * This is the driver specific part of the createNewScreen entry point.
1572 * \todo maybe fold this into intelInitDriver
1574 * \return the __GLcontextModes supported by this driver
1576 static const __DRIconfig
**
1577 radeonInitScreen(__DRIscreen
*psp
)
1579 #if defined(RADEON_R100)
1580 static const char *driver_name
= "Radeon";
1581 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1582 static const __DRIversion dri_expected
= { 4, 0, 0 };
1583 static const __DRIversion drm_expected
= { 1, 6, 0 };
1584 #elif defined(RADEON_R200)
1585 static const char *driver_name
= "R200";
1586 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1587 static const __DRIversion dri_expected
= { 4, 0, 0 };
1588 static const __DRIversion drm_expected
= { 1, 6, 0 };
1589 #elif defined(RADEON_R300)
1590 static const char *driver_name
= "R300";
1591 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1592 static const __DRIversion dri_expected
= { 4, 0, 0 };
1593 static const __DRIversion drm_expected
= { 1, 24, 0 };
1594 #elif defined(RADEON_R600)
1595 static const char *driver_name
= "R600";
1596 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1597 static const __DRIversion dri_expected
= { 4, 0, 0 };
1598 static const __DRIversion drm_expected
= { 1, 24, 0 };
1600 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1602 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1603 &psp
->dri_version
, & dri_expected
,
1604 &psp
->ddx_version
, & ddx_expected
,
1605 &psp
->drm_version
, & drm_expected
) ) {
1609 if (!radeonInitDriver(psp
))
1612 /* for now fill in all modes */
1613 return radeonFillInModes( psp
,
1615 (dri_priv
->bpp
== 16) ? 16 : 24,
1616 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1618 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1621 * This is the driver specific part of the createNewScreen entry point.
1622 * Called when using DRI2.
1624 * \return the __GLcontextModes supported by this driver
1627 __DRIconfig
**radeonInitScreen2(__DRIscreen
*psp
)
1629 GLenum fb_format
[3];
1631 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1632 * support pageflipping at all.
1634 static const GLenum back_buffer_modes
[] = {
1635 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
, /*, GLX_SWAP_COPY_OML*/
1637 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
1639 __DRIconfig
**configs
= NULL
;
1641 if (!radeonInitDriver(psp
)) {
1645 stencil_bits
[0] = 0;
1647 stencil_bits
[1] = 0;
1649 stencil_bits
[2] = 0;
1651 stencil_bits
[3] = 8;
1653 msaa_samples_array
[0] = 0;
1655 fb_format
[0] = GL_RGB
;
1656 fb_type
[0] = GL_UNSIGNED_SHORT_5_6_5
;
1658 fb_format
[1] = GL_BGR
;
1659 fb_type
[1] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1661 fb_format
[2] = GL_BGRA
;
1662 fb_type
[2] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1664 for (color
= 0; color
< ARRAY_SIZE(fb_format
); color
++) {
1665 __DRIconfig
**new_configs
;
1667 new_configs
= driCreateConfigs(fb_format
[color
], fb_type
[color
],
1670 ARRAY_SIZE(depth_bits
),
1672 ARRAY_SIZE(back_buffer_modes
),
1674 ARRAY_SIZE(msaa_samples_array
),
1676 if (configs
== NULL
)
1677 configs
= new_configs
;
1679 configs
= driConcatConfigs(configs
, new_configs
);
1682 if (configs
== NULL
) {
1683 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1688 return (const __DRIconfig
**)configs
;
1692 * Get information about previous buffer swaps.
1695 getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
)
1697 struct radeon_framebuffer
*rfb
;
1699 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1700 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1701 || (sInfo
== NULL
) ) {
1705 rfb
= dPriv
->driverPrivate
;
1706 sInfo
->swap_count
= rfb
->swap_count
;
1707 sInfo
->swap_ust
= rfb
->swap_ust
;
1708 sInfo
->swap_missed_count
= rfb
->swap_missed_count
;
1710 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1711 ? driCalculateSwapUsage( dPriv
, 0, rfb
->swap_missed_ust
)
1717 const struct __DriverAPIRec driDriverAPI
= {
1718 .InitScreen
= radeonInitScreen
,
1719 .DestroyScreen
= radeonDestroyScreen
,
1720 #if defined(RADEON_R200)
1721 .CreateContext
= r200CreateContext
,
1722 .DestroyContext
= r200DestroyContext
,
1723 #elif defined(RADEON_R600)
1724 .CreateContext
= r600CreateContext
,
1725 .DestroyContext
= radeonDestroyContext
,
1726 #elif defined(RADEON_R300)
1727 .CreateContext
= r300CreateContext
,
1728 .DestroyContext
= radeonDestroyContext
,
1730 .CreateContext
= r100CreateContext
,
1731 .DestroyContext
= radeonDestroyContext
,
1733 .CreateBuffer
= radeonCreateBuffer
,
1734 .DestroyBuffer
= radeonDestroyBuffer
,
1735 .SwapBuffers
= radeonSwapBuffers
,
1736 .MakeCurrent
= radeonMakeCurrent
,
1737 .UnbindContext
= radeonUnbindContext
,
1738 .GetSwapInfo
= getSwapInfo
,
1739 .GetDrawableMSC
= driDrawableGetMSC32
,
1740 .WaitForMSC
= driWaitForMSC32
,
1742 .SwapBuffersMSC
= NULL
,
1743 .CopySubBuffer
= radeonCopySubBuffer
,
1745 .InitScreen2
= radeonInitScreen2
,
1748 /* This is the table of extensions that the loader will dlsym() for. */
1749 PUBLIC
const __DRIextension
*__driDriverExtensions
[] = {
1750 &driCoreExtension
.base
,
1751 &driLegacyExtension
.base
,
1752 &driDRI2Extension
.base
,