src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( GLcontext *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    DECLARE_RENDERINPUTS(index_bitset);
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
 100
 101    /* Important:
 102     */
 103    if ( VB->NdcPtr != NULL ) {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 105    }
 106    else {
 107       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 108    }
 109
 110    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 111    rmesa->radeon.swtcl.vertex_attr_count = 0;
 112
 113    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 114     * build up a hardware vertex.
 115     */
 116    if ( !rmesa->swtcl.needproj ||
 117         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 118       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 119                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 120       offset = 4;
 121    }
 122    else {
 123       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 124                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 125       offset = 3;
 126    }
 127
 128    rmesa->swtcl.coloroffset = offset;
 129 #if MESA_LITTLE_ENDIAN
 130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 131               RADEON_CP_VC_FRMT_PKCOLOR );
 132 #else
 133    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 134               RADEON_CP_VC_FRMT_PKCOLOR );
 135 #endif
 136    offset += 1;
 137
 138    rmesa->swtcl.specoffset = 0;
 139    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 140        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 141
 142 #if MESA_LITTLE_ENDIAN
 143       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 144          rmesa->swtcl.specoffset = offset;
 145          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 146                     RADEON_CP_VC_FRMT_PKSPEC );
 147       }
 148       else {
 149          EMIT_PAD( 3 );
 150       }
 151
 152       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 153          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 154                     RADEON_CP_VC_FRMT_PKSPEC );
 155       }
 156       else {
 157          EMIT_PAD( 1 );
 158       }
 159 #else
 160       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 161          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 162                     RADEON_CP_VC_FRMT_PKSPEC );
 163       }
 164       else {
 165          EMIT_PAD( 1 );
 166       }
 167
 168       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 169          rmesa->swtcl.specoffset = offset;
 170          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 171                     RADEON_CP_VC_FRMT_PKSPEC );
 172       }
 173       else {
 174          EMIT_PAD( 3 );
 175       }
 176 #endif
 177    }
 178
 179    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 180       int i;
 181
 182       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 183          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 184             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 185
 186             switch (sz) {
 187             case 1:
 188             case 2:
 189                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 190                           radeon_cp_vc_frmts[i][0] );
 191                break;
 192             case 3:
 193             case 4:
 194                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 195                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 196                              radeon_cp_vc_frmts[i][1] );
 197                } else {
 198                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 199                              radeon_cp_vc_frmts[i][1] );
 200                }
 201                break;
 202             default:
 203                continue;
 204             };
 205          }
 206       }
 207    }
 208
 209    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 210         fmt_0 != rmesa->swtcl.vertex_format) {
 211       RADEON_NEWPRIM(rmesa);
 212       rmesa->swtcl.vertex_format = fmt_0;
 213       rmesa->radeon.swtcl.vertex_size =
 214           _tnl_install_attrs( ctx,
 215                               rmesa->radeon.swtcl.vertex_attrs,
 216                               rmesa->radeon.swtcl.vertex_attr_count,
 217                               NULL, 0 );
 218       rmesa->radeon.swtcl.vertex_size /= 4;
 219       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 220       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 221           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 222    }
 223 }
 224
 225 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 226 {
 227
 228     if (!rmesa->radeon.swtcl.emit_prediction) {
 229         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 230         const int scissor_size = 8;
 231         const int prims_size = 8;
 232         const int vertex_size = 7;
 233
 234         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 235                     state_size +
 236                     (scissor_size + prims_size + vertex_size),
 237                     __FUNCTION__))
 238             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 239         else
 240             rmesa->radeon.swtcl.emit_prediction = state_size;
 241         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 242             + rmesa->radeon.cmdbuf.cs->cdw;
 243     }
 244 }
 245
 246 static void radeonRenderStart( GLcontext *ctx )
 247 {
 248     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 249
 250     radeonSetVertexFormat( ctx );
 251
 252     if (rmesa->radeon.dma.flush != 0 &&
 253             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 254         rmesa->radeon.dma.flush( ctx );
 255 }
 256
 257
 258 /**
 259  * Set vertex state for SW TCL.  The primary purpose of this function is to
 260  * determine in advance whether or not the hardware can / should do the
 261  * projection divide or Mesa should do it.
 262  */
 263 void radeonChooseVertexState( GLcontext *ctx )
 264 {
 265    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 266    TNLcontext *tnl = TNL_CONTEXT(ctx);
 267
 268    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 269
 270    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 271                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 272                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 273
 274    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 275     * rasterization fallback.  As this function will be called again when we
 276     * leave a rasterization fallback, we can just skip it for now.
 277     */
 278    if (rmesa->radeon.Fallback != 0)
 279       return;
 280
 281    /* HW perspective divide is a win, but tiny vertex formats are a
 282     * bigger one.
 283     */
 284
 285    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 286        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 287        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 288       rmesa->swtcl.needproj = GL_TRUE;
 289       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 290                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 291    }
 292    else {
 293       rmesa->swtcl.needproj = GL_FALSE;
 294       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 295    }
 296
 297    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 298
 299    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 300       RADEON_STATECHANGE( rmesa, set );
 301       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 302    }
 303 }
 304
 305 void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 306 {
 307    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 308
 309
 310
 311    radeonEmitState(&rmesa->radeon);
 312    radeonEmitVertexAOS( rmesa,
 313                         rmesa->radeon.swtcl.vertex_size,
 314                         rmesa->radeon.swtcl.bo,
 315                         current_offset);
 316
 317
 318    radeonEmitVbufPrim( rmesa,
 319                        rmesa->swtcl.vertex_format,
 320                        rmesa->radeon.swtcl.hw_primitive,
 321                        rmesa->radeon.swtcl.numverts);
 322    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 323      WARN_ONCE("Rendering was %d commands larger than predicted size."
 324          " We might overflow  command buffer.\n",
 325          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 326
 327
 328    rmesa->radeon.swtcl.emit_prediction = 0;
 329
 330 }
 331
 332 /*
 333  * Render unclipped vertex buffers by emitting vertices directly to
 334  * dma buffers.  Use strip/fan hardware primitives where possible.
 335  * Try to simulate missing primitives with indexed vertices.
 336  */
 337 #define HAVE_POINTS      1
 338 #define HAVE_LINES       1
 339 #define HAVE_LINE_STRIPS 1
 340 #define HAVE_TRIANGLES   1
 341 #define HAVE_TRI_STRIPS  1
 342 #define HAVE_TRI_STRIP_1 0
 343 #define HAVE_TRI_FANS    1
 344 #define HAVE_QUADS       0
 345 #define HAVE_QUAD_STRIPS 0
 346 #define HAVE_POLYGONS    0
 347 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 348 #define HAVE_ELTS        0
 349
 350 static const GLuint hw_prim[GL_POLYGON+1] = {
 351    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 352    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 353    0,
 354    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 355    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 356    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 357    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 358    0,
 359    0,
 360    0
 361 };
 362
 363 static INLINE void
 364 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 365 {
 366    RADEON_NEWPRIM( rmesa );
 367    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 368    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 369 }
 370
 371 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 372 {
 373    void *rv;
 374    do {
 375      radeon_predict_emit_size( rmesa );
 376      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 377    } while (!rv);
 378    return rv;
 379 }
 380
 381 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 382 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 383 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 384 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 385 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 386 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 387   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 388 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 389 #define EMIT_VERTS( ctx, j, nr, buf ) \
 390   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 391
 392 #define TAG(x) radeon_dma_##x
 393 #include "tnl_dd/t_dd_dmatmp.h"
 394
 395
 396 /**********************************************************************/
 397 /*                          Render pipeline stage                     */
 398 /**********************************************************************/
 399
 400
 401 static GLboolean radeon_run_render( GLcontext *ctx,
 402                                     struct tnl_pipeline_stage *stage )
 403 {
 404    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 405    TNLcontext *tnl = TNL_CONTEXT(ctx);
 406    struct vertex_buffer *VB = &tnl->vb;
 407    tnl_render_func *tab = TAG(render_tab_verts);
 408    GLuint i;
 409
 410    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 411        !radeon_dma_validate_render( ctx, VB ))
 412       return GL_TRUE;
 413
 414    radeon_prepare_render(&rmesa->radeon);
 415
 416    tnl->Driver.Render.Start( ctx );
 417
 418    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 419    {
 420       GLuint prim = VB->Primitive[i].mode;
 421       GLuint start = VB->Primitive[i].start;
 422       GLuint length = VB->Primitive[i].count;
 423
 424       if (!length)
 425          continue;
 426
 427       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 428           "radeon_render.c: prim %s %d..%d\n",
 429                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 430                  start, start+length);
 431
 432       if (length)
 433          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 434    }
 435
 436    tnl->Driver.Render.Finish( ctx );
 437
 438    return GL_FALSE;             /* finished the pipe */
 439 }
 440
 441
 442
 443 const struct tnl_pipeline_stage _radeon_render_stage =
 444 {
 445    "radeon render",
 446    NULL,
 447    NULL,
 448    NULL,
 449    NULL,
 450    radeon_run_render            /* run */
 451 };
 452
 453
 454 /**************************************************************************/
 455
 456
 457 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 458    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 459    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 460    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 461    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 462    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 463    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 464    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 465    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 466    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 467    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 468 };
 469
 470 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 471 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 472 static void radeonResetLineStipple( GLcontext *ctx );
 473
 474
 475 /***********************************************************************
 476  *                    Emit primitives as inline vertices               *
 477  ***********************************************************************/
 478
 479 #undef LOCAL_VARS
 480 #undef ALLOC_VERTS
 481 #define CTX_ARG r100ContextPtr rmesa
 482 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 483 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 484 #undef LOCAL_VARS
 485 #define LOCAL_VARS                                              \
 486    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 487    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 488 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 489 #define VERTEX radeonVertex
 490 #undef TAG
 491 #define TAG(x) radeon_##x
 492 #include "tnl_dd/t_dd_triemit.h"
 493
 494
 495 /***********************************************************************
 496  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 497  ***********************************************************************/
 498
 499 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 500 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 501 #define LINE( a, b )       radeon_line( rmesa, a, b )
 502 #define POINT( a )         radeon_point( rmesa, a )
 503
 504 /***********************************************************************
 505  *              Build render functions from dd templates               *
 506  ***********************************************************************/
 507
 508 #define RADEON_TWOSIDE_BIT      0x01
 509 #define RADEON_UNFILLED_BIT     0x02
 510 #define RADEON_MAX_TRIFUNC      0x04
 511
 512
 513 static struct {
 514    tnl_points_func              points;
 515    tnl_line_func                line;
 516    tnl_triangle_func    triangle;
 517    tnl_quad_func                quad;
 518 } rast_tab[RADEON_MAX_TRIFUNC];
 519
 520
 521 #define DO_FALLBACK  0
 522 #define DO_OFFSET    0
 523 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 524 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 525 #define DO_FLAT      0
 526 #define DO_TRI       1
 527 #define DO_QUAD      1
 528 #define DO_LINE      1
 529 #define DO_POINTS    1
 530 #define DO_FULL_QUAD 1
 531
 532 #define HAVE_SPEC   1
 533 #define HAVE_BACK_COLORS  0
 534 #define HAVE_HW_FLATSHADE 1
 535 #define TAB rast_tab
 536
 537 #define DEPTH_SCALE 1.0
 538 #define UNFILLED_TRI unfilled_tri
 539 #define UNFILLED_QUAD unfilled_quad
 540 #define VERT_X(_v) _v->v.x
 541 #define VERT_Y(_v) _v->v.y
 542 #define VERT_Z(_v) _v->v.z
 543 #define AREA_IS_CCW( a ) (a < 0)
 544 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 545
 546 #define VERT_SET_RGBA( v, c )                                   \
 547 do {                                                            \
 548    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 549    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 550    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 551    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 552    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 553 } while (0)
 554
 555 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 556
 557 #define VERT_SET_SPEC( v, c )                                   \
 558 do {                                                            \
 559    if (specoffset) {                                            \
 560       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 561       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 562       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 563       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 564    }                                                            \
 565 } while (0)
 566 #define VERT_COPY_SPEC( v0, v1 )                        \
 567 do {                                                    \
 568    if (specoffset) {                                    \
 569       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 570       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 571       spec0->red   = spec1->red;        \
 572       spec0->green = spec1->green;      \
 573       spec0->blue  = spec1->blue;       \
 574    }                                                    \
 575 } while (0)
 576
 577 /* These don't need LE32_TO_CPU() as they used to save and restore
 578  * colors which are already in the correct format.
 579  */
 580 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 581 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 582 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 583 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 584
 585 #undef LOCAL_VARS
 586 #undef TAG
 587 #undef INIT
 588
 589 #define LOCAL_VARS(n)                                                   \
 590    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 591    GLuint color[n] = {0}, spec[n] = {0};                                                \
 592    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 593    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 594    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 595
 596 /***********************************************************************
 597  *                Helpers for rendering unfilled primitives            *
 598  ***********************************************************************/
 599
 600 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 601 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 602 #undef TAG
 603 #define TAG(x) x
 604 #include "tnl_dd/t_dd_unfilled.h"
 605 #undef IND
 606
 607
 608 /***********************************************************************
 609  *                      Generate GL render functions                   *
 610  ***********************************************************************/
 611
 612
 613 #define IND (0)
 614 #define TAG(x) x
 615 #include "tnl_dd/t_dd_tritmp.h"
 616
 617 #define IND (RADEON_TWOSIDE_BIT)
 618 #define TAG(x) x##_twoside
 619 #include "tnl_dd/t_dd_tritmp.h"
 620
 621 #define IND (RADEON_UNFILLED_BIT)
 622 #define TAG(x) x##_unfilled
 623 #include "tnl_dd/t_dd_tritmp.h"
 624
 625 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 626 #define TAG(x) x##_twoside_unfilled
 627 #include "tnl_dd/t_dd_tritmp.h"
 628
 629
 630 static void init_rast_tab( void )
 631 {
 632    init();
 633    init_twoside();
 634    init_unfilled();
 635    init_twoside_unfilled();
 636 }
 637
 638 /**********************************************************************/
 639 /*               Render unclipped begin/end objects                   */
 640 /**********************************************************************/
 641
 642 #define RENDER_POINTS( start, count )           \
 643    for ( ; start < count ; start++)             \
 644       radeon_point( rmesa, VERT(start) )
 645 #define RENDER_LINE( v0, v1 ) \
 646    radeon_line( rmesa, VERT(v0), VERT(v1) )
 647 #define RENDER_TRI( v0, v1, v2 )  \
 648    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 649 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 650    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 651 #undef INIT
 652 #define INIT(x) do {                                    \
 653    radeonRenderPrimitive( ctx, x );                     \
 654 } while (0)
 655 #undef LOCAL_VARS
 656 #define LOCAL_VARS                                              \
 657    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 658    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 659    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 660    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 661    const GLboolean stipple = ctx->Line.StippleFlag;             \
 662    (void) elt; (void) stipple;
 663 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 664 #define RESET_OCCLUSION
 665 #define PRESERVE_VB_DEFS
 666 #define ELT(x) (x)
 667 #define TAG(x) radeon_##x##_verts
 668 #include "tnl/t_vb_rendertmp.h"
 669 #undef ELT
 670 #undef TAG
 671 #define TAG(x) radeon_##x##_elts
 672 #define ELT(x) elt[x]
 673 #include "tnl/t_vb_rendertmp.h"
 674
 675
 676
 677 /**********************************************************************/
 678 /*                    Choose render functions                         */
 679 /**********************************************************************/
 680
 681 void radeonChooseRenderState( GLcontext *ctx )
 682 {
 683    TNLcontext *tnl = TNL_CONTEXT(ctx);
 684    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 685    GLuint index = 0;
 686    GLuint flags = ctx->_TriangleCaps;
 687
 688    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 689       return;
 690
 691    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 692    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 693
 694    if (index != rmesa->radeon.swtcl.RenderIndex) {
 695       tnl->Driver.Render.Points = rast_tab[index].points;
 696       tnl->Driver.Render.Line = rast_tab[index].line;
 697       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 698       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 699       tnl->Driver.Render.Quad = rast_tab[index].quad;
 700
 701       if (index == 0) {
 702          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 703          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 704          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 705       } else {
 706          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 707          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 708          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 709       }
 710
 711       rmesa->radeon.swtcl.RenderIndex = index;
 712    }
 713 }
 714
 715
 716 /**********************************************************************/
 717 /*                 High level hooks for t_vb_render.c                 */
 718 /**********************************************************************/
 719
 720
 721 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 722 {
 723    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 724
 725    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 726       RADEON_NEWPRIM( rmesa );
 727       rmesa->radeon.swtcl.hw_primitive = hwprim;
 728    }
 729 }
 730
 731 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 732 {
 733    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 734    rmesa->radeon.swtcl.render_primitive = prim;
 735    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 736       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 737 }
 738
 739 static void radeonRenderFinish( GLcontext *ctx )
 740 {
 741 }
 742
 743 static void radeonResetLineStipple( GLcontext *ctx )
 744 {
 745    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 746    RADEON_STATECHANGE( rmesa, lin );
 747 }
 748
 749
 750 /**********************************************************************/
 751 /*           Transition to/from hardware rasterization.               */
 752 /**********************************************************************/
 753
 754 static const char * const fallbackStrings[] = {
 755    "Texture mode",
 756    "glDrawBuffer(GL_FRONT_AND_BACK)",
 757    "glEnable(GL_STENCIL) without hw stencil buffer",
 758    "glRenderMode(selection or feedback)",
 759    "glBlendEquation",
 760    "glBlendFunc",
 761    "RADEON_NO_RAST",
 762    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 763 };
 764
 765
 766 static const char *getFallbackString(GLuint bit)
 767 {
 768    int i = 0;
 769    while (bit > 1) {
 770       i++;
 771       bit >>= 1;
 772    }
 773    return fallbackStrings[i];
 774 }
 775
 776
 777 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 778 {
 779    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 780    TNLcontext *tnl = TNL_CONTEXT(ctx);
 781    GLuint oldfallback = rmesa->radeon.Fallback;
 782
 783    if (mode) {
 784       rmesa->radeon.Fallback |= bit;
 785       if (oldfallback == 0) {
 786          radeon_firevertices(&rmesa->radeon);
 787          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 788          _swsetup_Wakeup( ctx );
 789          rmesa->radeon.swtcl.RenderIndex = ~0;
 790          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 791             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 792                     bit, getFallbackString(bit));
 793          }
 794       }
 795    }
 796    else {
 797       rmesa->radeon.Fallback &= ~bit;
 798       if (oldfallback == bit) {
 799          _swrast_flush( ctx );
 800          tnl->Driver.Render.Start = radeonRenderStart;
 801          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 802          tnl->Driver.Render.Finish = radeonRenderFinish;
 803
 804          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 805          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 806          tnl->Driver.Render.Interp = _tnl_interp;
 807
 808          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 809          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 810          if (rmesa->radeon.TclFallback) {
 811             /* These are already done if rmesa->radeon.TclFallback goes to
 812              * zero above. But not if it doesn't (RADEON_NO_TCL for
 813              * example?)
 814              */
 815             _tnl_invalidate_vertex_state( ctx, ~0 );
 816             _tnl_invalidate_vertices( ctx, ~0 );
 817             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 818             radeonChooseVertexState( ctx );
 819             radeonChooseRenderState( ctx );
 820          }
 821          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 822             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 823                     bit, getFallbackString(bit));
 824          }
 825       }
 826    }
 827 }
 828
 829
 830 /**********************************************************************/
 831 /*                            Initialization.                         */
 832 /**********************************************************************/
 833
 834 void radeonInitSwtcl( GLcontext *ctx )
 835 {
 836    TNLcontext *tnl = TNL_CONTEXT(ctx);
 837    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 838    static int firsttime = 1;
 839
 840    if (firsttime) {
 841       init_rast_tab();
 842       firsttime = 0;
 843    }
 844    rmesa->radeon.swtcl.emit_prediction = 0;
 845
 846    tnl->Driver.Render.Start = radeonRenderStart;
 847    tnl->Driver.Render.Finish = radeonRenderFinish;
 848    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 849    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 850    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 851    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 852    tnl->Driver.Render.Interp = _tnl_interp;
 853
 854    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 855                        RADEON_MAX_TNL_VERTEX_SIZE);
 856
 857    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 858    rmesa->radeon.swtcl.RenderIndex = ~0;
 859    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 860    rmesa->radeon.swtcl.hw_primitive = 0;
 861 }
 862