src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "swrast_setup/swrast_setup.h"
  44 #include "math/m_translate.h"
  45 #include "tnl/tnl.h"
  46 #include "tnl/t_context.h"
  47 #include "tnl/t_pipeline.h"
  48
  49 #include "radeon_context.h"
  50 #include "radeon_ioctl.h"
  51 #include "radeon_state.h"
  52 #include "radeon_swtcl.h"
  53 #include "radeon_tcl.h"
  54
  55
  56 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  57 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  58 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  59
  60 /***********************************************************************
  61  *                         Initialization
  62  ***********************************************************************/
  63
  64 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  65 do {                                                                    \
  66    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  67    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  68    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  69    fmt_0 |= F0;                                                         \
  70 } while (0)
  71
  72 #define EMIT_PAD( N )                                                   \
  73 do {                                                                    \
  74    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  75    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  76    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  77    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  78 } while (0)
  79
  80 static GLuint radeon_cp_vc_frmts[3][2] =
  81 {
  82    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  83    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  84    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  85 };
  86
  87 static void radeonSetVertexFormat( GLcontext *ctx )
  88 {
  89    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  90    TNLcontext *tnl = TNL_CONTEXT(ctx);
  91    struct vertex_buffer *VB = &tnl->vb;
  92    DECLARE_RENDERINPUTS(index_bitset);
  93    int fmt_0 = 0;
  94    int offset = 0;
  95
  96    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
  97
  98    /* Important:
  99     */
 100    if ( VB->NdcPtr != NULL ) {
 101       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 102    }
 103    else {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 105    }
 106
 107    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 108    rmesa->radeon.swtcl.vertex_attr_count = 0;
 109
 110    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 111     * build up a hardware vertex.
 112     */
 113    if ( !rmesa->swtcl.needproj ||
 114         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 115       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 116                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 117       offset = 4;
 118    }
 119    else {
 120       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 121                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 122       offset = 3;
 123    }
 124
 125    rmesa->swtcl.coloroffset = offset;
 126 #if MESA_LITTLE_ENDIAN
 127    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 128               RADEON_CP_VC_FRMT_PKCOLOR );
 129 #else
 130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 131               RADEON_CP_VC_FRMT_PKCOLOR );
 132 #endif
 133    offset += 1;
 134
 135    rmesa->swtcl.specoffset = 0;
 136    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 137        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 138
 139 #if MESA_LITTLE_ENDIAN
 140       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 141          rmesa->swtcl.specoffset = offset;
 142          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 143                     RADEON_CP_VC_FRMT_PKSPEC );
 144       }
 145       else {
 146          EMIT_PAD( 3 );
 147       }
 148
 149       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 150          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 151                     RADEON_CP_VC_FRMT_PKSPEC );
 152       }
 153       else {
 154          EMIT_PAD( 1 );
 155       }
 156 #else
 157       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 158          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 159                     RADEON_CP_VC_FRMT_PKSPEC );
 160       }
 161       else {
 162          EMIT_PAD( 1 );
 163       }
 164
 165       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 166          rmesa->swtcl.specoffset = offset;
 167          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 168                     RADEON_CP_VC_FRMT_PKSPEC );
 169       }
 170       else {
 171          EMIT_PAD( 3 );
 172       }
 173 #endif
 174    }
 175
 176    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 177       int i;
 178
 179       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 180          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 181             GLuint sz = VB->TexCoordPtr[i]->size;
 182
 183             switch (sz) {
 184             case 1:
 185             case 2:
 186                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 187                           radeon_cp_vc_frmts[i][0] );
 188                break;
 189             case 3:
 190             case 4:
 191                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 192                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 193                              radeon_cp_vc_frmts[i][1] );
 194                } else {
 195                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 196                              radeon_cp_vc_frmts[i][1] );
 197                }
 198                break;
 199             default:
 200                continue;
 201             };
 202          }
 203       }
 204    }
 205
 206    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 207         fmt_0 != rmesa->swtcl.vertex_format) {
 208       RADEON_NEWPRIM(rmesa);
 209       rmesa->swtcl.vertex_format = fmt_0;
 210       rmesa->radeon.swtcl.vertex_size =
 211           _tnl_install_attrs( ctx,
 212                               rmesa->radeon.swtcl.vertex_attrs,
 213                               rmesa->radeon.swtcl.vertex_attr_count,
 214                               NULL, 0 );
 215       rmesa->radeon.swtcl.vertex_size /= 4;
 216       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 217       if (RADEON_DEBUG & DEBUG_VERTS)
 218          fprintf( stderr, "%s: vertex_size= %d floats\n",
 219                   __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 220    }
 221 }
 222
 223 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 224 {
 225
 226     if (!rmesa->radeon.swtcl.emit_prediction) {
 227         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 228         const int scissor_size = 8;
 229         const int prims_size = 8;
 230         const int vertex_size = 7;
 231
 232         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 233                     state_size +
 234                     (scissor_size + prims_size + vertex_size),
 235                     __FUNCTION__))
 236             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 237         else
 238             rmesa->radeon.swtcl.emit_prediction = state_size;
 239         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 240             + rmesa->radeon.cmdbuf.cs->cdw;
 241     }
 242 }
 243
 244 static void radeonRenderStart( GLcontext *ctx )
 245 {
 246     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 247
 248     radeonSetVertexFormat( ctx );
 249
 250     if (rmesa->radeon.dma.flush != 0 &&
 251             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 252         rmesa->radeon.dma.flush( ctx );
 253 }
 254
 255
 256 /**
 257  * Set vertex state for SW TCL.  The primary purpose of this function is to
 258  * determine in advance whether or not the hardware can / should do the
 259  * projection divide or Mesa should do it.
 260  */
 261 void radeonChooseVertexState( GLcontext *ctx )
 262 {
 263    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 264    TNLcontext *tnl = TNL_CONTEXT(ctx);
 265
 266    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 267
 268    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 269                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 270                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 271
 272    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 273     * rasterization fallback.  As this function will be called again when we
 274     * leave a rasterization fallback, we can just skip it for now.
 275     */
 276    if (rmesa->radeon.Fallback != 0)
 277       return;
 278
 279    /* HW perspective divide is a win, but tiny vertex formats are a
 280     * bigger one.
 281     */
 282
 283    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 284        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 285        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 286       rmesa->swtcl.needproj = GL_TRUE;
 287       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 288                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 289    }
 290    else {
 291       rmesa->swtcl.needproj = GL_FALSE;
 292       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 293    }
 294
 295    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 296
 297    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 298       RADEON_STATECHANGE( rmesa, set );
 299       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 300    }
 301 }
 302
 303 void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 304 {
 305    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 306
 307
 308
 309    radeonEmitState(&rmesa->radeon);
 310    radeonEmitVertexAOS( rmesa,
 311                         rmesa->radeon.swtcl.vertex_size,
 312                         first_elem(&rmesa->radeon.dma.reserved)->bo,
 313                         current_offset);
 314
 315
 316    radeonEmitVbufPrim( rmesa,
 317                        rmesa->swtcl.vertex_format,
 318                        rmesa->radeon.swtcl.hw_primitive,
 319                        rmesa->radeon.swtcl.numverts);
 320    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 321      WARN_ONCE("Rendering was %d commands larger than predicted size."
 322          " We might overflow  command buffer.\n",
 323          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 324
 325
 326    rmesa->radeon.swtcl.emit_prediction = 0;
 327
 328 }
 329
 330 /*
 331  * Render unclipped vertex buffers by emitting vertices directly to
 332  * dma buffers.  Use strip/fan hardware primitives where possible.
 333  * Try to simulate missing primitives with indexed vertices.
 334  */
 335 #define HAVE_POINTS      1
 336 #define HAVE_LINES       1
 337 #define HAVE_LINE_STRIPS 1
 338 #define HAVE_TRIANGLES   1
 339 #define HAVE_TRI_STRIPS  1
 340 #define HAVE_TRI_STRIP_1 0
 341 #define HAVE_TRI_FANS    1
 342 #define HAVE_QUADS       0
 343 #define HAVE_QUAD_STRIPS 0
 344 #define HAVE_POLYGONS    0
 345 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 346 #define HAVE_ELTS        0
 347
 348 static const GLuint hw_prim[GL_POLYGON+1] = {
 349    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 350    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 351    0,
 352    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 353    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 354    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 355    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 356    0,
 357    0,
 358    0
 359 };
 360
 361 static INLINE void
 362 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 363 {
 364    RADEON_NEWPRIM( rmesa );
 365    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 366    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 367 }
 368
 369 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 370 {
 371    void *rv;
 372    do {
 373      radeon_predict_emit_size( rmesa );
 374      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 375    } while (!rv);
 376    return rv;
 377 }
 378
 379 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 380 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 381 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 382 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 383 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 384 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 385   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 386 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 387 #define EMIT_VERTS( ctx, j, nr, buf ) \
 388   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 389
 390 #define TAG(x) radeon_dma_##x
 391 #include "tnl_dd/t_dd_dmatmp.h"
 392
 393
 394 /**********************************************************************/
 395 /*                          Render pipeline stage                     */
 396 /**********************************************************************/
 397
 398
 399 static GLboolean radeon_run_render( GLcontext *ctx,
 400                                     struct tnl_pipeline_stage *stage )
 401 {
 402    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 403    TNLcontext *tnl = TNL_CONTEXT(ctx);
 404    struct vertex_buffer *VB = &tnl->vb;
 405    tnl_render_func *tab = TAG(render_tab_verts);
 406    GLuint i;
 407
 408    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 409        !radeon_dma_validate_render( ctx, VB ))
 410       return GL_TRUE;
 411
 412    tnl->Driver.Render.Start( ctx );
 413
 414    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 415    {
 416       GLuint prim = VB->Primitive[i].mode;
 417       GLuint start = VB->Primitive[i].start;
 418       GLuint length = VB->Primitive[i].count;
 419
 420       if (!length)
 421          continue;
 422
 423       if (RADEON_DEBUG & DEBUG_PRIMS)
 424          fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
 425                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 426                  start, start+length);
 427
 428       if (length)
 429          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 430    }
 431
 432    tnl->Driver.Render.Finish( ctx );
 433
 434    return GL_FALSE;             /* finished the pipe */
 435 }
 436
 437
 438
 439 const struct tnl_pipeline_stage _radeon_render_stage =
 440 {
 441    "radeon render",
 442    NULL,
 443    NULL,
 444    NULL,
 445    NULL,
 446    radeon_run_render            /* run */
 447 };
 448
 449
 450 /**************************************************************************/
 451
 452
 453 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 454    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 455    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 456    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 457    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 458    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 459    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 460    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 461    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 462    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 463    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 464 };
 465
 466 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 467 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 468 static void radeonResetLineStipple( GLcontext *ctx );
 469
 470
 471 /***********************************************************************
 472  *                    Emit primitives as inline vertices               *
 473  ***********************************************************************/
 474
 475 #undef LOCAL_VARS
 476 #undef ALLOC_VERTS
 477 #define CTX_ARG r100ContextPtr rmesa
 478 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 479 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 480 #undef LOCAL_VARS
 481 #define LOCAL_VARS                                              \
 482    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 483    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 484 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 485 #define VERTEX radeonVertex
 486 #undef TAG
 487 #define TAG(x) radeon_##x
 488 #include "tnl_dd/t_dd_triemit.h"
 489
 490
 491 /***********************************************************************
 492  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 493  ***********************************************************************/
 494
 495 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 496 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 497 #define LINE( a, b )       radeon_line( rmesa, a, b )
 498 #define POINT( a )         radeon_point( rmesa, a )
 499
 500 /***********************************************************************
 501  *              Build render functions from dd templates               *
 502  ***********************************************************************/
 503
 504 #define RADEON_TWOSIDE_BIT      0x01
 505 #define RADEON_UNFILLED_BIT     0x02
 506 #define RADEON_MAX_TRIFUNC      0x04
 507
 508
 509 static struct {
 510    tnl_points_func              points;
 511    tnl_line_func                line;
 512    tnl_triangle_func    triangle;
 513    tnl_quad_func                quad;
 514 } rast_tab[RADEON_MAX_TRIFUNC];
 515
 516
 517 #define DO_FALLBACK  0
 518 #define DO_OFFSET    0
 519 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 520 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 521 #define DO_FLAT      0
 522 #define DO_TRI       1
 523 #define DO_QUAD      1
 524 #define DO_LINE      1
 525 #define DO_POINTS    1
 526 #define DO_FULL_QUAD 1
 527
 528 #define HAVE_RGBA   1
 529 #define HAVE_SPEC   1
 530 #define HAVE_BACK_COLORS  0
 531 #define HAVE_HW_FLATSHADE 1
 532 #define TAB rast_tab
 533
 534 #define DEPTH_SCALE 1.0
 535 #define UNFILLED_TRI unfilled_tri
 536 #define UNFILLED_QUAD unfilled_quad
 537 #define VERT_X(_v) _v->v.x
 538 #define VERT_Y(_v) _v->v.y
 539 #define VERT_Z(_v) _v->v.z
 540 #define AREA_IS_CCW( a ) (a < 0)
 541 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 542
 543 #define VERT_SET_RGBA( v, c )                                   \
 544 do {                                                            \
 545    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 546    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 547    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 548    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 549    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 550 } while (0)
 551
 552 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 553
 554 #define VERT_SET_SPEC( v, c )                                   \
 555 do {                                                            \
 556    if (specoffset) {                                            \
 557       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 558       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 559       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 560       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 561    }                                                            \
 562 } while (0)
 563 #define VERT_COPY_SPEC( v0, v1 )                        \
 564 do {                                                    \
 565    if (specoffset) {                                    \
 566       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 567       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 568       spec0->red   = spec1->red;        \
 569       spec0->green = spec1->green;      \
 570       spec0->blue  = spec1->blue;       \
 571    }                                                    \
 572 } while (0)
 573
 574 /* These don't need LE32_TO_CPU() as they used to save and restore
 575  * colors which are already in the correct format.
 576  */
 577 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 578 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 579 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 580 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 581
 582 #undef LOCAL_VARS
 583 #undef TAG
 584 #undef INIT
 585
 586 #define LOCAL_VARS(n)                                                   \
 587    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 588    GLuint color[n] = {0}, spec[n] = {0};                                                \
 589    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 590    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 591    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 592
 593 /***********************************************************************
 594  *                Helpers for rendering unfilled primitives            *
 595  ***********************************************************************/
 596
 597 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 598 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 599 #undef TAG
 600 #define TAG(x) x
 601 #include "tnl_dd/t_dd_unfilled.h"
 602 #undef IND
 603
 604
 605 /***********************************************************************
 606  *                      Generate GL render functions                   *
 607  ***********************************************************************/
 608
 609
 610 #define IND (0)
 611 #define TAG(x) x
 612 #include "tnl_dd/t_dd_tritmp.h"
 613
 614 #define IND (RADEON_TWOSIDE_BIT)
 615 #define TAG(x) x##_twoside
 616 #include "tnl_dd/t_dd_tritmp.h"
 617
 618 #define IND (RADEON_UNFILLED_BIT)
 619 #define TAG(x) x##_unfilled
 620 #include "tnl_dd/t_dd_tritmp.h"
 621
 622 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 623 #define TAG(x) x##_twoside_unfilled
 624 #include "tnl_dd/t_dd_tritmp.h"
 625
 626
 627 static void init_rast_tab( void )
 628 {
 629    init();
 630    init_twoside();
 631    init_unfilled();
 632    init_twoside_unfilled();
 633 }
 634
 635 /**********************************************************************/
 636 /*               Render unclipped begin/end objects                   */
 637 /**********************************************************************/
 638
 639 #define RENDER_POINTS( start, count )           \
 640    for ( ; start < count ; start++)             \
 641       radeon_point( rmesa, VERT(start) )
 642 #define RENDER_LINE( v0, v1 ) \
 643    radeon_line( rmesa, VERT(v0), VERT(v1) )
 644 #define RENDER_TRI( v0, v1, v2 )  \
 645    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 646 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 647    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 648 #undef INIT
 649 #define INIT(x) do {                                    \
 650    radeonRenderPrimitive( ctx, x );                     \
 651 } while (0)
 652 #undef LOCAL_VARS
 653 #define LOCAL_VARS                                              \
 654    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 655    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 656    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 657    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 658    const GLboolean stipple = ctx->Line.StippleFlag;             \
 659    (void) elt; (void) stipple;
 660 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 661 #define RESET_OCCLUSION
 662 #define PRESERVE_VB_DEFS
 663 #define ELT(x) (x)
 664 #define TAG(x) radeon_##x##_verts
 665 #include "tnl/t_vb_rendertmp.h"
 666 #undef ELT
 667 #undef TAG
 668 #define TAG(x) radeon_##x##_elts
 669 #define ELT(x) elt[x]
 670 #include "tnl/t_vb_rendertmp.h"
 671
 672
 673
 674 /**********************************************************************/
 675 /*                    Choose render functions                         */
 676 /**********************************************************************/
 677
 678 void radeonChooseRenderState( GLcontext *ctx )
 679 {
 680    TNLcontext *tnl = TNL_CONTEXT(ctx);
 681    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 682    GLuint index = 0;
 683    GLuint flags = ctx->_TriangleCaps;
 684
 685    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 686       return;
 687
 688    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 689    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 690
 691    if (index != rmesa->radeon.swtcl.RenderIndex) {
 692       tnl->Driver.Render.Points = rast_tab[index].points;
 693       tnl->Driver.Render.Line = rast_tab[index].line;
 694       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 695       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 696       tnl->Driver.Render.Quad = rast_tab[index].quad;
 697
 698       if (index == 0) {
 699          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 700          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 701          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 702       } else {
 703          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 704          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 705          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 706       }
 707
 708       rmesa->radeon.swtcl.RenderIndex = index;
 709    }
 710 }
 711
 712
 713 /**********************************************************************/
 714 /*                 High level hooks for t_vb_render.c                 */
 715 /**********************************************************************/
 716
 717
 718 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 719 {
 720    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 721
 722    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 723       RADEON_NEWPRIM( rmesa );
 724       rmesa->radeon.swtcl.hw_primitive = hwprim;
 725    }
 726 }
 727
 728 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 729 {
 730    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 731    rmesa->radeon.swtcl.render_primitive = prim;
 732    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 733       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 734 }
 735
 736 static void radeonRenderFinish( GLcontext *ctx )
 737 {
 738 }
 739
 740 static void radeonResetLineStipple( GLcontext *ctx )
 741 {
 742    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 743    RADEON_STATECHANGE( rmesa, lin );
 744 }
 745
 746
 747 /**********************************************************************/
 748 /*           Transition to/from hardware rasterization.               */
 749 /**********************************************************************/
 750
 751 static const char * const fallbackStrings[] = {
 752    "Texture mode",
 753    "glDrawBuffer(GL_FRONT_AND_BACK)",
 754    "glEnable(GL_STENCIL) without hw stencil buffer",
 755    "glRenderMode(selection or feedback)",
 756    "glBlendEquation",
 757    "glBlendFunc",
 758    "RADEON_NO_RAST",
 759    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 760 };
 761
 762
 763 static const char *getFallbackString(GLuint bit)
 764 {
 765    int i = 0;
 766    while (bit > 1) {
 767       i++;
 768       bit >>= 1;
 769    }
 770    return fallbackStrings[i];
 771 }
 772
 773
 774 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 775 {
 776    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 777    TNLcontext *tnl = TNL_CONTEXT(ctx);
 778    GLuint oldfallback = rmesa->radeon.Fallback;
 779
 780    if (mode) {
 781       rmesa->radeon.Fallback |= bit;
 782       if (oldfallback == 0) {
 783          radeon_firevertices(&rmesa->radeon);
 784          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 785          _swsetup_Wakeup( ctx );
 786          rmesa->radeon.swtcl.RenderIndex = ~0;
 787          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 788             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 789                     bit, getFallbackString(bit));
 790          }
 791       }
 792    }
 793    else {
 794       rmesa->radeon.Fallback &= ~bit;
 795       if (oldfallback == bit) {
 796          _swrast_flush( ctx );
 797          tnl->Driver.Render.Start = radeonRenderStart;
 798          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 799          tnl->Driver.Render.Finish = radeonRenderFinish;
 800
 801          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 802          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 803          tnl->Driver.Render.Interp = _tnl_interp;
 804
 805          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 806          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 807          if (rmesa->radeon.TclFallback) {
 808             /* These are already done if rmesa->radeon.TclFallback goes to
 809              * zero above. But not if it doesn't (RADEON_NO_TCL for
 810              * example?)
 811              */
 812             _tnl_invalidate_vertex_state( ctx, ~0 );
 813             _tnl_invalidate_vertices( ctx, ~0 );
 814             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 815             radeonChooseVertexState( ctx );
 816             radeonChooseRenderState( ctx );
 817          }
 818          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 819             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 820                     bit, getFallbackString(bit));
 821          }
 822       }
 823    }
 824 }
 825
 826
 827 /**********************************************************************/
 828 /*                            Initialization.                         */
 829 /**********************************************************************/
 830
 831 void radeonInitSwtcl( GLcontext *ctx )
 832 {
 833    TNLcontext *tnl = TNL_CONTEXT(ctx);
 834    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 835    static int firsttime = 1;
 836
 837    if (firsttime) {
 838       init_rast_tab();
 839       firsttime = 0;
 840    }
 841    rmesa->radeon.swtcl.emit_prediction = 0;
 842
 843    tnl->Driver.Render.Start = radeonRenderStart;
 844    tnl->Driver.Render.Finish = radeonRenderFinish;
 845    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 846    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 847    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 848    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 849    tnl->Driver.Render.Interp = _tnl_interp;
 850
 851    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 852                        RADEON_MAX_TNL_VERTEX_SIZE);
 853
 854    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 855    rmesa->radeon.swtcl.RenderIndex = ~0;
 856    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 857    rmesa->radeon.swtcl.hw_primitive = 0;
 858 }
 859