src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keithw@vmware.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( struct gl_context *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->radeon.swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
 116       /* for projtex */
 117       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 118                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 119       offset = 4;
 120    }
 121    else {
 122       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 123                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 124       offset = 3;
 125    }
 126
 127    rmesa->swtcl.coloroffset = offset;
 128 #if MESA_LITTLE_ENDIAN
 129    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 130               RADEON_CP_VC_FRMT_PKCOLOR );
 131 #else
 132    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 133               RADEON_CP_VC_FRMT_PKCOLOR );
 134 #endif
 135    offset += 1;
 136
 137    rmesa->swtcl.specoffset = 0;
 138    if (index_bitset &
 139        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
 140
 141 #if MESA_LITTLE_ENDIAN
 142       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 143          rmesa->swtcl.specoffset = offset;
 144          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 145                     RADEON_CP_VC_FRMT_PKSPEC );
 146       }
 147       else {
 148          EMIT_PAD( 3 );
 149       }
 150
 151       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 152          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 153                     RADEON_CP_VC_FRMT_PKSPEC );
 154       }
 155       else {
 156          EMIT_PAD( 1 );
 157       }
 158 #else
 159       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 160          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 161                     RADEON_CP_VC_FRMT_PKSPEC );
 162       }
 163       else {
 164          EMIT_PAD( 1 );
 165       }
 166
 167       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 168          rmesa->swtcl.specoffset = offset;
 169          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 170                     RADEON_CP_VC_FRMT_PKSPEC );
 171       }
 172       else {
 173          EMIT_PAD( 3 );
 174       }
 175 #endif
 176    }
 177
 178    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
 179       int i;
 180
 181       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 182          if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
 183             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 184
 185             switch (sz) {
 186             case 1:
 187             case 2:
 188                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 189                           radeon_cp_vc_frmts[i][0] );
 190                break;
 191             case 3:
 192                if (ctx->Texture.Unit[i]._Current &&
 193                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 194                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 195                               radeon_cp_vc_frmts[i][1] );
 196                } else {
 197                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 198                               radeon_cp_vc_frmts[i][0] );
 199                }
 200                break;
 201             case 4:
 202                if (ctx->Texture.Unit[i]._Current &&
 203                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 204                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 205                              radeon_cp_vc_frmts[i][1] );
 206                } else {
 207                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 208                              radeon_cp_vc_frmts[i][1] );
 209                }
 210                break;
 211             default:
 212                continue;
 213             };
 214          }
 215       }
 216    }
 217
 218    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
 219        fmt_0 != rmesa->swtcl.vertex_format) {
 220       RADEON_NEWPRIM(rmesa);
 221       rmesa->swtcl.vertex_format = fmt_0;
 222       rmesa->radeon.swtcl.vertex_size =
 223           _tnl_install_attrs( ctx,
 224                               rmesa->radeon.swtcl.vertex_attrs,
 225                               rmesa->radeon.swtcl.vertex_attr_count,
 226                               NULL, 0 );
 227       rmesa->radeon.swtcl.vertex_size /= 4;
 228       rmesa->radeon.tnl_index_bitset = index_bitset;
 229       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 230           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 231    }
 232 }
 233
 234 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 235 {
 236
 237     if (!rmesa->radeon.swtcl.emit_prediction) {
 238         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 239         const int scissor_size = 8;
 240         const int prims_size = 8;
 241         const int vertex_size = 7;
 242
 243         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 244                     state_size +
 245                     (scissor_size + prims_size + vertex_size),
 246                     __FUNCTION__))
 247             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 248         else
 249             rmesa->radeon.swtcl.emit_prediction = state_size;
 250         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 251             + rmesa->radeon.cmdbuf.cs->cdw;
 252     }
 253 }
 254
 255 static void radeonRenderStart( struct gl_context *ctx )
 256 {
 257     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 258
 259     radeonSetVertexFormat( ctx );
 260
 261     if (rmesa->radeon.dma.flush != 0 &&
 262             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 263         rmesa->radeon.dma.flush( ctx );
 264 }
 265
 266
 267 /**
 268  * Set vertex state for SW TCL.  The primary purpose of this function is to
 269  * determine in advance whether or not the hardware can / should do the
 270  * projection divide or Mesa should do it.
 271  */
 272 void radeonChooseVertexState( struct gl_context *ctx )
 273 {
 274    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 275    TNLcontext *tnl = TNL_CONTEXT(ctx);
 276
 277    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 278    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 279                          ctx->Polygon.BackMode != GL_FILL);
 280    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 281
 282    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 283                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 284                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 285
 286    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 287     * rasterization fallback.  As this function will be called again when we
 288     * leave a rasterization fallback, we can just skip it for now.
 289     */
 290    if (rmesa->radeon.Fallback != 0)
 291       return;
 292
 293    /* HW perspective divide is a win, but tiny vertex formats are a
 294     * bigger one.
 295     */
 296
 297    if ((0 == (tnl->render_inputs_bitset &
 298         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
 299          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
 300        || twosided
 301        || unfilled) {
 302       rmesa->swtcl.needproj = GL_TRUE;
 303       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 304                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 305    }
 306    else {
 307       rmesa->swtcl.needproj = GL_FALSE;
 308       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 309    }
 310
 311    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 312
 313    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 314       RADEON_STATECHANGE( rmesa, set );
 315       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 316    }
 317 }
 318
 319 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 320 {
 321    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 322
 323
 324
 325    radeonEmitState(&rmesa->radeon);
 326    radeonEmitVertexAOS( rmesa,
 327                         rmesa->radeon.swtcl.vertex_size,
 328                         rmesa->radeon.swtcl.bo,
 329                         current_offset);
 330
 331
 332    radeonEmitVbufPrim( rmesa,
 333                        rmesa->swtcl.vertex_format,
 334                        rmesa->radeon.swtcl.hw_primitive,
 335                        rmesa->radeon.swtcl.numverts);
 336    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 337      WARN_ONCE("Rendering was %d commands larger than predicted size."
 338          " We might overflow  command buffer.\n",
 339          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 340
 341
 342    rmesa->radeon.swtcl.emit_prediction = 0;
 343
 344 }
 345
 346 /*
 347  * Render unclipped vertex buffers by emitting vertices directly to
 348  * dma buffers.  Use strip/fan hardware primitives where possible.
 349  * Try to simulate missing primitives with indexed vertices.
 350  */
 351 #define HAVE_POINTS      1
 352 #define HAVE_LINES       1
 353 #define HAVE_LINE_STRIPS 1
 354 #define HAVE_TRIANGLES   1
 355 #define HAVE_TRI_STRIPS  1
 356 #define HAVE_TRI_STRIP_1 0
 357 #define HAVE_TRI_FANS    1
 358 #define HAVE_QUADS       0
 359 #define HAVE_QUAD_STRIPS 0
 360 #define HAVE_POLYGONS    0
 361 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 362 #define HAVE_ELTS        0
 363
 364 static const GLuint hw_prim[GL_POLYGON+1] = {
 365    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 366    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 367    0,
 368    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 369    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 370    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 371    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 372    0,
 373    0,
 374    0
 375 };
 376
 377 static INLINE void
 378 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 379 {
 380    RADEON_NEWPRIM( rmesa );
 381    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 382    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 383 }
 384
 385 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 386 {
 387    void *rv;
 388    do {
 389      radeon_predict_emit_size( rmesa );
 390      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 391    } while (!rv);
 392    return rv;
 393 }
 394
 395 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 396 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 397 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 398 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 399 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 400 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 401   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 402 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 403 #define EMIT_VERTS( ctx, j, nr, buf ) \
 404   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 405
 406 #define TAG(x) radeon_dma_##x
 407 #include "tnl_dd/t_dd_dmatmp.h"
 408
 409
 410 /**********************************************************************/
 411 /*                          Render pipeline stage                     */
 412 /**********************************************************************/
 413
 414
 415 static GLboolean radeon_run_render( struct gl_context *ctx,
 416                                     struct tnl_pipeline_stage *stage )
 417 {
 418    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 419    TNLcontext *tnl = TNL_CONTEXT(ctx);
 420    struct vertex_buffer *VB = &tnl->vb;
 421    tnl_render_func *tab = TAG(render_tab_verts);
 422    GLuint i;
 423
 424    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 425        !radeon_dma_validate_render( ctx, VB ))
 426       return GL_TRUE;
 427
 428    radeon_prepare_render(&rmesa->radeon);
 429    if (rmesa->radeon.NewGLState)
 430       radeonValidateState( ctx );
 431
 432    tnl->Driver.Render.Start( ctx );
 433
 434    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 435    {
 436       GLuint prim = VB->Primitive[i].mode;
 437       GLuint start = VB->Primitive[i].start;
 438       GLuint length = VB->Primitive[i].count;
 439
 440       if (!length)
 441          continue;
 442
 443       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 444           "radeon_render.c: prim %s %d..%d\n",
 445                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 446                  start, start+length);
 447
 448       if (length)
 449          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 450    }
 451
 452    tnl->Driver.Render.Finish( ctx );
 453
 454    return GL_FALSE;             /* finished the pipe */
 455 }
 456
 457
 458
 459 const struct tnl_pipeline_stage _radeon_render_stage =
 460 {
 461    "radeon render",
 462    NULL,
 463    NULL,
 464    NULL,
 465    NULL,
 466    radeon_run_render            /* run */
 467 };
 468
 469
 470 /**************************************************************************/
 471
 472
 473 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 474    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 475    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 476    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 481    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 482    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 483    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 484 };
 485
 486 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 487 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 488 static void radeonResetLineStipple( struct gl_context *ctx );
 489
 490
 491 /***********************************************************************
 492  *                    Emit primitives as inline vertices               *
 493  ***********************************************************************/
 494
 495 #undef LOCAL_VARS
 496 #undef ALLOC_VERTS
 497 #define CTX_ARG r100ContextPtr rmesa
 498 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 499 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 500 #undef LOCAL_VARS
 501 #define LOCAL_VARS                                              \
 502    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 503    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 504 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 505 #define VERTEX radeonVertex
 506 #undef TAG
 507 #define TAG(x) radeon_##x
 508 #include "tnl_dd/t_dd_triemit.h"
 509
 510
 511 /***********************************************************************
 512  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 513  ***********************************************************************/
 514
 515 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 516 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 517 #define LINE( a, b )       radeon_line( rmesa, a, b )
 518 #define POINT( a )         radeon_point( rmesa, a )
 519
 520 /***********************************************************************
 521  *              Build render functions from dd templates               *
 522  ***********************************************************************/
 523
 524 #define RADEON_TWOSIDE_BIT      0x01
 525 #define RADEON_UNFILLED_BIT     0x02
 526 #define RADEON_MAX_TRIFUNC      0x04
 527
 528
 529 static struct {
 530    tnl_points_func              points;
 531    tnl_line_func                line;
 532    tnl_triangle_func    triangle;
 533    tnl_quad_func                quad;
 534 } rast_tab[RADEON_MAX_TRIFUNC];
 535
 536
 537 #define DO_FALLBACK  0
 538 #define DO_OFFSET    0
 539 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 540 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 541 #define DO_FLAT      0
 542 #define DO_TRI       1
 543 #define DO_QUAD      1
 544 #define DO_LINE      1
 545 #define DO_POINTS    1
 546 #define DO_FULL_QUAD 1
 547
 548 #define HAVE_SPEC   1
 549 #define HAVE_BACK_COLORS  0
 550 #define HAVE_HW_FLATSHADE 1
 551 #define TAB rast_tab
 552
 553 #define DEPTH_SCALE 1.0
 554 #define UNFILLED_TRI unfilled_tri
 555 #define UNFILLED_QUAD unfilled_quad
 556 #define VERT_X(_v) _v->v.x
 557 #define VERT_Y(_v) _v->v.y
 558 #define VERT_Z(_v) _v->v.z
 559 #define AREA_IS_CCW( a ) (a < 0)
 560 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 561
 562 #define VERT_SET_RGBA( v, c )                                   \
 563 do {                                                            \
 564    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 565    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 566    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 567    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 568    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 569 } while (0)
 570
 571 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 572
 573 #define VERT_SET_SPEC( v, c )                                   \
 574 do {                                                            \
 575    if (specoffset) {                                            \
 576       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 577       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 578       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 579       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 580    }                                                            \
 581 } while (0)
 582 #define VERT_COPY_SPEC( v0, v1 )                        \
 583 do {                                                    \
 584    if (specoffset) {                                    \
 585       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 586       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 587       spec0->red   = spec1->red;        \
 588       spec0->green = spec1->green;      \
 589       spec0->blue  = spec1->blue;       \
 590    }                                                    \
 591 } while (0)
 592
 593 /* These don't need LE32_TO_CPU() as they used to save and restore
 594  * colors which are already in the correct format.
 595  */
 596 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 597 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 598 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 599 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 600
 601 #undef LOCAL_VARS
 602 #undef TAG
 603 #undef INIT
 604
 605 #define LOCAL_VARS(n)                                                   \
 606    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 607    GLuint color[n] = {0}, spec[n] = {0};                                                \
 608    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 609    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 610    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 611
 612 /***********************************************************************
 613  *                Helpers for rendering unfilled primitives            *
 614  ***********************************************************************/
 615
 616 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 617 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 618 #undef TAG
 619 #define TAG(x) x
 620 #include "tnl_dd/t_dd_unfilled.h"
 621 #undef IND
 622
 623
 624 /***********************************************************************
 625  *                      Generate GL render functions                   *
 626  ***********************************************************************/
 627
 628
 629 #define IND (0)
 630 #define TAG(x) x
 631 #include "tnl_dd/t_dd_tritmp.h"
 632
 633 #define IND (RADEON_TWOSIDE_BIT)
 634 #define TAG(x) x##_twoside
 635 #include "tnl_dd/t_dd_tritmp.h"
 636
 637 #define IND (RADEON_UNFILLED_BIT)
 638 #define TAG(x) x##_unfilled
 639 #include "tnl_dd/t_dd_tritmp.h"
 640
 641 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 642 #define TAG(x) x##_twoside_unfilled
 643 #include "tnl_dd/t_dd_tritmp.h"
 644
 645
 646 static void init_rast_tab( void )
 647 {
 648    init();
 649    init_twoside();
 650    init_unfilled();
 651    init_twoside_unfilled();
 652 }
 653
 654 /**********************************************************************/
 655 /*               Render unclipped begin/end objects                   */
 656 /**********************************************************************/
 657
 658 #define RENDER_POINTS( start, count )           \
 659    for ( ; start < count ; start++)             \
 660       radeon_point( rmesa, VERT(start) )
 661 #define RENDER_LINE( v0, v1 ) \
 662    radeon_line( rmesa, VERT(v0), VERT(v1) )
 663 #define RENDER_TRI( v0, v1, v2 )  \
 664    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 665 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 666    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 667 #undef INIT
 668 #define INIT(x) do {                                    \
 669    radeonRenderPrimitive( ctx, x );                     \
 670 } while (0)
 671 #undef LOCAL_VARS
 672 #define LOCAL_VARS                                              \
 673    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 674    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 675    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 676    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 677    const GLboolean stipple = ctx->Line.StippleFlag;             \
 678    (void) elt; (void) stipple;
 679 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 680 #define RESET_OCCLUSION
 681 #define PRESERVE_VB_DEFS
 682 #define ELT(x) (x)
 683 #define TAG(x) radeon_##x##_verts
 684 #include "tnl/t_vb_rendertmp.h"
 685 #undef ELT
 686 #undef TAG
 687 #define TAG(x) radeon_##x##_elts
 688 #define ELT(x) elt[x]
 689 #include "tnl/t_vb_rendertmp.h"
 690
 691
 692
 693 /**********************************************************************/
 694 /*                    Choose render functions                         */
 695 /**********************************************************************/
 696
 697 void radeonChooseRenderState( struct gl_context *ctx )
 698 {
 699    TNLcontext *tnl = TNL_CONTEXT(ctx);
 700    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 701    GLuint index = 0;
 702    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 703                          ctx->Polygon.BackMode != GL_FILL);
 704    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 705
 706    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 707       return;
 708
 709    if (twosided)
 710       index |= RADEON_TWOSIDE_BIT;
 711    if (unfilled)
 712       index |= RADEON_UNFILLED_BIT;
 713
 714    if (index != rmesa->radeon.swtcl.RenderIndex) {
 715       tnl->Driver.Render.Points = rast_tab[index].points;
 716       tnl->Driver.Render.Line = rast_tab[index].line;
 717       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 718       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 719       tnl->Driver.Render.Quad = rast_tab[index].quad;
 720
 721       if (index == 0) {
 722          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 723          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 724          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 725       } else {
 726          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 727          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 728          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 729       }
 730
 731       rmesa->radeon.swtcl.RenderIndex = index;
 732    }
 733 }
 734
 735
 736 /**********************************************************************/
 737 /*                 High level hooks for t_vb_render.c                 */
 738 /**********************************************************************/
 739
 740
 741 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 742 {
 743    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 744
 745    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 746       RADEON_NEWPRIM( rmesa );
 747       rmesa->radeon.swtcl.hw_primitive = hwprim;
 748    }
 749 }
 750
 751 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 752 {
 753    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 754    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 755                          ctx->Polygon.BackMode != GL_FILL);
 756
 757    rmesa->radeon.swtcl.render_primitive = prim;
 758    if (prim < GL_TRIANGLES || !unfilled)
 759       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 760 }
 761
 762 static void radeonRenderFinish( struct gl_context *ctx )
 763 {
 764 }
 765
 766 static void radeonResetLineStipple( struct gl_context *ctx )
 767 {
 768    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 769    RADEON_STATECHANGE( rmesa, lin );
 770 }
 771
 772
 773 /**********************************************************************/
 774 /*           Transition to/from hardware rasterization.               */
 775 /**********************************************************************/
 776
 777 static const char * const fallbackStrings[] = {
 778    "Texture mode",
 779    "glDrawBuffer(GL_FRONT_AND_BACK)",
 780    "glEnable(GL_STENCIL) without hw stencil buffer",
 781    "glRenderMode(selection or feedback)",
 782    "glBlendEquation",
 783    "glBlendFunc",
 784    "RADEON_NO_RAST",
 785    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 786 };
 787
 788
 789 static const char *getFallbackString(GLuint bit)
 790 {
 791    int i = 0;
 792    while (bit > 1) {
 793       i++;
 794       bit >>= 1;
 795    }
 796    return fallbackStrings[i];
 797 }
 798
 799
 800 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 801 {
 802    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 803    TNLcontext *tnl = TNL_CONTEXT(ctx);
 804    GLuint oldfallback = rmesa->radeon.Fallback;
 805
 806    if (mode) {
 807       rmesa->radeon.Fallback |= bit;
 808       if (oldfallback == 0) {
 809          radeon_firevertices(&rmesa->radeon);
 810          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 811          _swsetup_Wakeup( ctx );
 812          rmesa->radeon.swtcl.RenderIndex = ~0;
 813          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 814             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 815                     bit, getFallbackString(bit));
 816          }
 817       }
 818    }
 819    else {
 820       rmesa->radeon.Fallback &= ~bit;
 821       if (oldfallback == bit) {
 822          _swrast_flush( ctx );
 823          tnl->Driver.Render.Start = radeonRenderStart;
 824          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 825          tnl->Driver.Render.Finish = radeonRenderFinish;
 826
 827          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 828          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 829          tnl->Driver.Render.Interp = _tnl_interp;
 830
 831          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 832          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 833          if (rmesa->radeon.TclFallback) {
 834             /* These are already done if rmesa->radeon.TclFallback goes to
 835              * zero above. But not if it doesn't (RADEON_NO_TCL for
 836              * example?)
 837              */
 838             _tnl_invalidate_vertex_state( ctx, ~0 );
 839             _tnl_invalidate_vertices( ctx, ~0 );
 840             rmesa->radeon.tnl_index_bitset = 0;
 841             radeonChooseVertexState( ctx );
 842             radeonChooseRenderState( ctx );
 843          }
 844          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 845             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 846                     bit, getFallbackString(bit));
 847          }
 848       }
 849    }
 850 }
 851
 852
 853 /**********************************************************************/
 854 /*                            Initialization.                         */
 855 /**********************************************************************/
 856
 857 void radeonInitSwtcl( struct gl_context *ctx )
 858 {
 859    TNLcontext *tnl = TNL_CONTEXT(ctx);
 860    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 861    static int firsttime = 1;
 862
 863    if (firsttime) {
 864       init_rast_tab();
 865       firsttime = 0;
 866    }
 867    rmesa->radeon.swtcl.emit_prediction = 0;
 868
 869    tnl->Driver.Render.Start = radeonRenderStart;
 870    tnl->Driver.Render.Finish = radeonRenderFinish;
 871    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 872    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 873    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 874    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 875    tnl->Driver.Render.Interp = _tnl_interp;
 876
 877    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 878                        RADEON_MAX_TNL_VERTEX_SIZE);
 879
 880    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 881    rmesa->radeon.swtcl.RenderIndex = ~0;
 882    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 883    rmesa->radeon.swtcl.hw_primitive = 0;
 884 }
 885