src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "swrast_setup/swrast_setup.h"
  44 #include "tnl/tnl.h"
  45 #include "tnl/t_context.h"
  46 #include "tnl/t_pipeline.h"
  47
  48 #include "radeon_context.h"
  49 #include "radeon_ioctl.h"
  50 #include "radeon_state.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_tcl.h"
  53 #include "radeon_debug.h"
  54
  55
  56 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  57 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  58 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  59
  60 /***********************************************************************
  61  *                         Initialization
  62  ***********************************************************************/
  63
  64 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  65 do {                                                                    \
  66    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  67    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  68    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  69    fmt_0 |= F0;                                                         \
  70 } while (0)
  71
  72 #define EMIT_PAD( N )                                                   \
  73 do {                                                                    \
  74    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  75    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  76    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  77    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  78 } while (0)
  79
  80 static GLuint radeon_cp_vc_frmts[3][2] =
  81 {
  82    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  83    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  84    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  85 };
  86
  87 static void radeonSetVertexFormat( GLcontext *ctx )
  88 {
  89    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  90    TNLcontext *tnl = TNL_CONTEXT(ctx);
  91    struct vertex_buffer *VB = &tnl->vb;
  92    DECLARE_RENDERINPUTS(index_bitset);
  93    int fmt_0 = 0;
  94    int offset = 0;
  95
  96    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
  97
  98    /* Important:
  99     */
 100    if ( VB->NdcPtr != NULL ) {
 101       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 102    }
 103    else {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 105    }
 106
 107    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 108    rmesa->radeon.swtcl.vertex_attr_count = 0;
 109
 110    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 111     * build up a hardware vertex.
 112     */
 113    if ( !rmesa->swtcl.needproj ||
 114         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 115       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 116                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 117       offset = 4;
 118    }
 119    else {
 120       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 121                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 122       offset = 3;
 123    }
 124
 125    rmesa->swtcl.coloroffset = offset;
 126 #if MESA_LITTLE_ENDIAN
 127    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 128               RADEON_CP_VC_FRMT_PKCOLOR );
 129 #else
 130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 131               RADEON_CP_VC_FRMT_PKCOLOR );
 132 #endif
 133    offset += 1;
 134
 135    rmesa->swtcl.specoffset = 0;
 136    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 137        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 138
 139 #if MESA_LITTLE_ENDIAN
 140       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 141          rmesa->swtcl.specoffset = offset;
 142          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 143                     RADEON_CP_VC_FRMT_PKSPEC );
 144       }
 145       else {
 146          EMIT_PAD( 3 );
 147       }
 148
 149       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 150          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 151                     RADEON_CP_VC_FRMT_PKSPEC );
 152       }
 153       else {
 154          EMIT_PAD( 1 );
 155       }
 156 #else
 157       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 158          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 159                     RADEON_CP_VC_FRMT_PKSPEC );
 160       }
 161       else {
 162          EMIT_PAD( 1 );
 163       }
 164
 165       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 166          rmesa->swtcl.specoffset = offset;
 167          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 168                     RADEON_CP_VC_FRMT_PKSPEC );
 169       }
 170       else {
 171          EMIT_PAD( 3 );
 172       }
 173 #endif
 174    }
 175
 176    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 177       int i;
 178
 179       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 180          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 181             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 182
 183             switch (sz) {
 184             case 1:
 185             case 2:
 186                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 187                           radeon_cp_vc_frmts[i][0] );
 188                break;
 189             case 3:
 190             case 4:
 191                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 192                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 193                              radeon_cp_vc_frmts[i][1] );
 194                } else {
 195                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 196                              radeon_cp_vc_frmts[i][1] );
 197                }
 198                break;
 199             default:
 200                continue;
 201             };
 202          }
 203       }
 204    }
 205
 206    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 207         fmt_0 != rmesa->swtcl.vertex_format) {
 208       RADEON_NEWPRIM(rmesa);
 209       rmesa->swtcl.vertex_format = fmt_0;
 210       rmesa->radeon.swtcl.vertex_size =
 211           _tnl_install_attrs( ctx,
 212                               rmesa->radeon.swtcl.vertex_attrs,
 213                               rmesa->radeon.swtcl.vertex_attr_count,
 214                               NULL, 0 );
 215       rmesa->radeon.swtcl.vertex_size /= 4;
 216       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 217       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 218           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 219    }
 220 }
 221
 222 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 223 {
 224
 225     if (!rmesa->radeon.swtcl.emit_prediction) {
 226         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 227         const int scissor_size = 8;
 228         const int prims_size = 8;
 229         const int vertex_size = 7;
 230
 231         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 232                     state_size +
 233                     (scissor_size + prims_size + vertex_size),
 234                     __FUNCTION__))
 235             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 236         else
 237             rmesa->radeon.swtcl.emit_prediction = state_size;
 238         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 239             + rmesa->radeon.cmdbuf.cs->cdw;
 240     }
 241 }
 242
 243 static void radeonRenderStart( GLcontext *ctx )
 244 {
 245     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 246
 247     radeonSetVertexFormat( ctx );
 248
 249     if (rmesa->radeon.dma.flush != 0 &&
 250             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 251         rmesa->radeon.dma.flush( ctx );
 252 }
 253
 254
 255 /**
 256  * Set vertex state for SW TCL.  The primary purpose of this function is to
 257  * determine in advance whether or not the hardware can / should do the
 258  * projection divide or Mesa should do it.
 259  */
 260 void radeonChooseVertexState( GLcontext *ctx )
 261 {
 262    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 263    TNLcontext *tnl = TNL_CONTEXT(ctx);
 264
 265    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 266
 267    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 268                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 269                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 270
 271    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 272     * rasterization fallback.  As this function will be called again when we
 273     * leave a rasterization fallback, we can just skip it for now.
 274     */
 275    if (rmesa->radeon.Fallback != 0)
 276       return;
 277
 278    /* HW perspective divide is a win, but tiny vertex formats are a
 279     * bigger one.
 280     */
 281
 282    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 283        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 284        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 285       rmesa->swtcl.needproj = GL_TRUE;
 286       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 287                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 288    }
 289    else {
 290       rmesa->swtcl.needproj = GL_FALSE;
 291       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 292    }
 293
 294    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 295
 296    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 297       RADEON_STATECHANGE( rmesa, set );
 298       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 299    }
 300 }
 301
 302 void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 303 {
 304    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 305
 306
 307
 308    radeonEmitState(&rmesa->radeon);
 309    radeonEmitVertexAOS( rmesa,
 310                         rmesa->radeon.swtcl.vertex_size,
 311                         rmesa->radeon.swtcl.bo,
 312                         current_offset);
 313
 314
 315    radeonEmitVbufPrim( rmesa,
 316                        rmesa->swtcl.vertex_format,
 317                        rmesa->radeon.swtcl.hw_primitive,
 318                        rmesa->radeon.swtcl.numverts);
 319    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 320      WARN_ONCE("Rendering was %d commands larger than predicted size."
 321          " We might overflow  command buffer.\n",
 322          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 323
 324
 325    rmesa->radeon.swtcl.emit_prediction = 0;
 326
 327 }
 328
 329 /*
 330  * Render unclipped vertex buffers by emitting vertices directly to
 331  * dma buffers.  Use strip/fan hardware primitives where possible.
 332  * Try to simulate missing primitives with indexed vertices.
 333  */
 334 #define HAVE_POINTS      1
 335 #define HAVE_LINES       1
 336 #define HAVE_LINE_STRIPS 1
 337 #define HAVE_TRIANGLES   1
 338 #define HAVE_TRI_STRIPS  1
 339 #define HAVE_TRI_STRIP_1 0
 340 #define HAVE_TRI_FANS    1
 341 #define HAVE_QUADS       0
 342 #define HAVE_QUAD_STRIPS 0
 343 #define HAVE_POLYGONS    0
 344 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 345 #define HAVE_ELTS        0
 346
 347 static const GLuint hw_prim[GL_POLYGON+1] = {
 348    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 349    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 350    0,
 351    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 352    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 353    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 354    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 355    0,
 356    0,
 357    0
 358 };
 359
 360 static INLINE void
 361 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 362 {
 363    RADEON_NEWPRIM( rmesa );
 364    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 365    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 366 }
 367
 368 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 369 {
 370    void *rv;
 371    do {
 372      radeon_predict_emit_size( rmesa );
 373      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 374    } while (!rv);
 375    return rv;
 376 }
 377
 378 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 379 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 380 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 381 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 382 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 383 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 384   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 385 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 386 #define EMIT_VERTS( ctx, j, nr, buf ) \
 387   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 388
 389 #define TAG(x) radeon_dma_##x
 390 #include "tnl_dd/t_dd_dmatmp.h"
 391
 392
 393 /**********************************************************************/
 394 /*                          Render pipeline stage                     */
 395 /**********************************************************************/
 396
 397
 398 static GLboolean radeon_run_render( GLcontext *ctx,
 399                                     struct tnl_pipeline_stage *stage )
 400 {
 401    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 402    TNLcontext *tnl = TNL_CONTEXT(ctx);
 403    struct vertex_buffer *VB = &tnl->vb;
 404    tnl_render_func *tab = TAG(render_tab_verts);
 405    GLuint i;
 406
 407    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 408        !radeon_dma_validate_render( ctx, VB ))
 409       return GL_TRUE;
 410
 411    tnl->Driver.Render.Start( ctx );
 412
 413    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 414    {
 415       GLuint prim = VB->Primitive[i].mode;
 416       GLuint start = VB->Primitive[i].start;
 417       GLuint length = VB->Primitive[i].count;
 418
 419       if (!length)
 420          continue;
 421
 422       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 423           "radeon_render.c: prim %s %d..%d\n",
 424                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 425                  start, start+length);
 426
 427       if (length)
 428          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 429    }
 430
 431    tnl->Driver.Render.Finish( ctx );
 432
 433    return GL_FALSE;             /* finished the pipe */
 434 }
 435
 436
 437
 438 const struct tnl_pipeline_stage _radeon_render_stage =
 439 {
 440    "radeon render",
 441    NULL,
 442    NULL,
 443    NULL,
 444    NULL,
 445    radeon_run_render            /* run */
 446 };
 447
 448
 449 /**************************************************************************/
 450
 451
 452 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 453    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 454    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 455    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 456    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 457    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 458    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 459    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 460    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 461    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 462    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 463 };
 464
 465 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 466 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 467 static void radeonResetLineStipple( GLcontext *ctx );
 468
 469
 470 /***********************************************************************
 471  *                    Emit primitives as inline vertices               *
 472  ***********************************************************************/
 473
 474 #undef LOCAL_VARS
 475 #undef ALLOC_VERTS
 476 #define CTX_ARG r100ContextPtr rmesa
 477 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 478 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 479 #undef LOCAL_VARS
 480 #define LOCAL_VARS                                              \
 481    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 482    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 483 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 484 #define VERTEX radeonVertex
 485 #undef TAG
 486 #define TAG(x) radeon_##x
 487 #include "tnl_dd/t_dd_triemit.h"
 488
 489
 490 /***********************************************************************
 491  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 492  ***********************************************************************/
 493
 494 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 495 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 496 #define LINE( a, b )       radeon_line( rmesa, a, b )
 497 #define POINT( a )         radeon_point( rmesa, a )
 498
 499 /***********************************************************************
 500  *              Build render functions from dd templates               *
 501  ***********************************************************************/
 502
 503 #define RADEON_TWOSIDE_BIT      0x01
 504 #define RADEON_UNFILLED_BIT     0x02
 505 #define RADEON_MAX_TRIFUNC      0x04
 506
 507
 508 static struct {
 509    tnl_points_func              points;
 510    tnl_line_func                line;
 511    tnl_triangle_func    triangle;
 512    tnl_quad_func                quad;
 513 } rast_tab[RADEON_MAX_TRIFUNC];
 514
 515
 516 #define DO_FALLBACK  0
 517 #define DO_OFFSET    0
 518 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 519 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 520 #define DO_FLAT      0
 521 #define DO_TRI       1
 522 #define DO_QUAD      1
 523 #define DO_LINE      1
 524 #define DO_POINTS    1
 525 #define DO_FULL_QUAD 1
 526
 527 #define HAVE_SPEC   1
 528 #define HAVE_BACK_COLORS  0
 529 #define HAVE_HW_FLATSHADE 1
 530 #define TAB rast_tab
 531
 532 #define DEPTH_SCALE 1.0
 533 #define UNFILLED_TRI unfilled_tri
 534 #define UNFILLED_QUAD unfilled_quad
 535 #define VERT_X(_v) _v->v.x
 536 #define VERT_Y(_v) _v->v.y
 537 #define VERT_Z(_v) _v->v.z
 538 #define AREA_IS_CCW( a ) (a < 0)
 539 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 540
 541 #define VERT_SET_RGBA( v, c )                                   \
 542 do {                                                            \
 543    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 544    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 545    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 546    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 547    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 548 } while (0)
 549
 550 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 551
 552 #define VERT_SET_SPEC( v, c )                                   \
 553 do {                                                            \
 554    if (specoffset) {                                            \
 555       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 556       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 557       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 558       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 559    }                                                            \
 560 } while (0)
 561 #define VERT_COPY_SPEC( v0, v1 )                        \
 562 do {                                                    \
 563    if (specoffset) {                                    \
 564       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 565       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 566       spec0->red   = spec1->red;        \
 567       spec0->green = spec1->green;      \
 568       spec0->blue  = spec1->blue;       \
 569    }                                                    \
 570 } while (0)
 571
 572 /* These don't need LE32_TO_CPU() as they used to save and restore
 573  * colors which are already in the correct format.
 574  */
 575 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 576 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 577 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 578 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 579
 580 #undef LOCAL_VARS
 581 #undef TAG
 582 #undef INIT
 583
 584 #define LOCAL_VARS(n)                                                   \
 585    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 586    GLuint color[n] = {0}, spec[n] = {0};                                                \
 587    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 588    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 589    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 590
 591 /***********************************************************************
 592  *                Helpers for rendering unfilled primitives            *
 593  ***********************************************************************/
 594
 595 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 596 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 597 #undef TAG
 598 #define TAG(x) x
 599 #include "tnl_dd/t_dd_unfilled.h"
 600 #undef IND
 601
 602
 603 /***********************************************************************
 604  *                      Generate GL render functions                   *
 605  ***********************************************************************/
 606
 607
 608 #define IND (0)
 609 #define TAG(x) x
 610 #include "tnl_dd/t_dd_tritmp.h"
 611
 612 #define IND (RADEON_TWOSIDE_BIT)
 613 #define TAG(x) x##_twoside
 614 #include "tnl_dd/t_dd_tritmp.h"
 615
 616 #define IND (RADEON_UNFILLED_BIT)
 617 #define TAG(x) x##_unfilled
 618 #include "tnl_dd/t_dd_tritmp.h"
 619
 620 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 621 #define TAG(x) x##_twoside_unfilled
 622 #include "tnl_dd/t_dd_tritmp.h"
 623
 624
 625 static void init_rast_tab( void )
 626 {
 627    init();
 628    init_twoside();
 629    init_unfilled();
 630    init_twoside_unfilled();
 631 }
 632
 633 /**********************************************************************/
 634 /*               Render unclipped begin/end objects                   */
 635 /**********************************************************************/
 636
 637 #define RENDER_POINTS( start, count )           \
 638    for ( ; start < count ; start++)             \
 639       radeon_point( rmesa, VERT(start) )
 640 #define RENDER_LINE( v0, v1 ) \
 641    radeon_line( rmesa, VERT(v0), VERT(v1) )
 642 #define RENDER_TRI( v0, v1, v2 )  \
 643    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 644 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 645    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 646 #undef INIT
 647 #define INIT(x) do {                                    \
 648    radeonRenderPrimitive( ctx, x );                     \
 649 } while (0)
 650 #undef LOCAL_VARS
 651 #define LOCAL_VARS                                              \
 652    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 653    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 654    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 655    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 656    const GLboolean stipple = ctx->Line.StippleFlag;             \
 657    (void) elt; (void) stipple;
 658 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 659 #define RESET_OCCLUSION
 660 #define PRESERVE_VB_DEFS
 661 #define ELT(x) (x)
 662 #define TAG(x) radeon_##x##_verts
 663 #include "tnl/t_vb_rendertmp.h"
 664 #undef ELT
 665 #undef TAG
 666 #define TAG(x) radeon_##x##_elts
 667 #define ELT(x) elt[x]
 668 #include "tnl/t_vb_rendertmp.h"
 669
 670
 671
 672 /**********************************************************************/
 673 /*                    Choose render functions                         */
 674 /**********************************************************************/
 675
 676 void radeonChooseRenderState( GLcontext *ctx )
 677 {
 678    TNLcontext *tnl = TNL_CONTEXT(ctx);
 679    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 680    GLuint index = 0;
 681    GLuint flags = ctx->_TriangleCaps;
 682
 683    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 684       return;
 685
 686    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 687    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 688
 689    if (index != rmesa->radeon.swtcl.RenderIndex) {
 690       tnl->Driver.Render.Points = rast_tab[index].points;
 691       tnl->Driver.Render.Line = rast_tab[index].line;
 692       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 693       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 694       tnl->Driver.Render.Quad = rast_tab[index].quad;
 695
 696       if (index == 0) {
 697          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 698          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 699          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 700       } else {
 701          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 702          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 703          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 704       }
 705
 706       rmesa->radeon.swtcl.RenderIndex = index;
 707    }
 708 }
 709
 710
 711 /**********************************************************************/
 712 /*                 High level hooks for t_vb_render.c                 */
 713 /**********************************************************************/
 714
 715
 716 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 717 {
 718    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 719
 720    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 721       RADEON_NEWPRIM( rmesa );
 722       rmesa->radeon.swtcl.hw_primitive = hwprim;
 723    }
 724 }
 725
 726 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 727 {
 728    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 729    rmesa->radeon.swtcl.render_primitive = prim;
 730    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 731       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 732 }
 733
 734 static void radeonRenderFinish( GLcontext *ctx )
 735 {
 736 }
 737
 738 static void radeonResetLineStipple( GLcontext *ctx )
 739 {
 740    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 741    RADEON_STATECHANGE( rmesa, lin );
 742 }
 743
 744
 745 /**********************************************************************/
 746 /*           Transition to/from hardware rasterization.               */
 747 /**********************************************************************/
 748
 749 static const char * const fallbackStrings[] = {
 750    "Texture mode",
 751    "glDrawBuffer(GL_FRONT_AND_BACK)",
 752    "glEnable(GL_STENCIL) without hw stencil buffer",
 753    "glRenderMode(selection or feedback)",
 754    "glBlendEquation",
 755    "glBlendFunc",
 756    "RADEON_NO_RAST",
 757    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 758 };
 759
 760
 761 static const char *getFallbackString(GLuint bit)
 762 {
 763    int i = 0;
 764    while (bit > 1) {
 765       i++;
 766       bit >>= 1;
 767    }
 768    return fallbackStrings[i];
 769 }
 770
 771
 772 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 773 {
 774    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 775    TNLcontext *tnl = TNL_CONTEXT(ctx);
 776    GLuint oldfallback = rmesa->radeon.Fallback;
 777
 778    if (mode) {
 779       rmesa->radeon.Fallback |= bit;
 780       if (oldfallback == 0) {
 781          radeon_firevertices(&rmesa->radeon);
 782          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 783          _swsetup_Wakeup( ctx );
 784          rmesa->radeon.swtcl.RenderIndex = ~0;
 785          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 786             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 787                     bit, getFallbackString(bit));
 788          }
 789       }
 790    }
 791    else {
 792       rmesa->radeon.Fallback &= ~bit;
 793       if (oldfallback == bit) {
 794          _swrast_flush( ctx );
 795          tnl->Driver.Render.Start = radeonRenderStart;
 796          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 797          tnl->Driver.Render.Finish = radeonRenderFinish;
 798
 799          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 800          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 801          tnl->Driver.Render.Interp = _tnl_interp;
 802
 803          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 804          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 805          if (rmesa->radeon.TclFallback) {
 806             /* These are already done if rmesa->radeon.TclFallback goes to
 807              * zero above. But not if it doesn't (RADEON_NO_TCL for
 808              * example?)
 809              */
 810             _tnl_invalidate_vertex_state( ctx, ~0 );
 811             _tnl_invalidate_vertices( ctx, ~0 );
 812             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 813             radeonChooseVertexState( ctx );
 814             radeonChooseRenderState( ctx );
 815          }
 816          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 817             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 818                     bit, getFallbackString(bit));
 819          }
 820       }
 821    }
 822 }
 823
 824
 825 /**********************************************************************/
 826 /*                            Initialization.                         */
 827 /**********************************************************************/
 828
 829 void radeonInitSwtcl( GLcontext *ctx )
 830 {
 831    TNLcontext *tnl = TNL_CONTEXT(ctx);
 832    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 833    static int firsttime = 1;
 834
 835    if (firsttime) {
 836       init_rast_tab();
 837       firsttime = 0;
 838    }
 839    rmesa->radeon.swtcl.emit_prediction = 0;
 840
 841    tnl->Driver.Render.Start = radeonRenderStart;
 842    tnl->Driver.Render.Finish = radeonRenderFinish;
 843    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 844    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 845    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 846    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 847    tnl->Driver.Render.Interp = _tnl_interp;
 848
 849    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 850                        RADEON_MAX_TNL_VERTEX_SIZE);
 851
 852    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 853    rmesa->radeon.swtcl.RenderIndex = ~0;
 854    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 855    rmesa->radeon.swtcl.hw_primitive = 0;
 856 }
 857