src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( struct gl_context *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->radeon.swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
 116       /* for projtex */
 117       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 118                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 119       offset = 4;
 120    }
 121    else {
 122       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 123                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 124       offset = 3;
 125    }
 126
 127    rmesa->swtcl.coloroffset = offset;
 128 #if MESA_LITTLE_ENDIAN
 129    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 130               RADEON_CP_VC_FRMT_PKCOLOR );
 131 #else
 132    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 133               RADEON_CP_VC_FRMT_PKCOLOR );
 134 #endif
 135    offset += 1;
 136
 137    rmesa->swtcl.specoffset = 0;
 138    if (index_bitset &
 139        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
 140
 141 #if MESA_LITTLE_ENDIAN
 142       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 143          rmesa->swtcl.specoffset = offset;
 144          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 145                     RADEON_CP_VC_FRMT_PKSPEC );
 146       }
 147       else {
 148          EMIT_PAD( 3 );
 149       }
 150
 151       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 152          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 153                     RADEON_CP_VC_FRMT_PKSPEC );
 154       }
 155       else {
 156          EMIT_PAD( 1 );
 157       }
 158 #else
 159       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 160          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 161                     RADEON_CP_VC_FRMT_PKSPEC );
 162       }
 163       else {
 164          EMIT_PAD( 1 );
 165       }
 166
 167       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 168          rmesa->swtcl.specoffset = offset;
 169          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 170                     RADEON_CP_VC_FRMT_PKSPEC );
 171       }
 172       else {
 173          EMIT_PAD( 3 );
 174       }
 175 #endif
 176    }
 177
 178    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
 179       int i;
 180
 181       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 182          if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
 183             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 184
 185             switch (sz) {
 186             case 1:
 187             case 2:
 188                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 189                           radeon_cp_vc_frmts[i][0] );
 190                break;
 191             case 3:
 192                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 193                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 194                               radeon_cp_vc_frmts[i][1] );
 195                } else {
 196                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 197                               radeon_cp_vc_frmts[i][0] );
 198                }
 199                break;
 200             case 4:
 201                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 202                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 203                              radeon_cp_vc_frmts[i][1] );
 204                } else {
 205                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 206                              radeon_cp_vc_frmts[i][1] );
 207                }
 208                break;
 209             default:
 210                continue;
 211             };
 212          }
 213       }
 214    }
 215
 216    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
 217        fmt_0 != rmesa->swtcl.vertex_format) {
 218       RADEON_NEWPRIM(rmesa);
 219       rmesa->swtcl.vertex_format = fmt_0;
 220       rmesa->radeon.swtcl.vertex_size =
 221           _tnl_install_attrs( ctx,
 222                               rmesa->radeon.swtcl.vertex_attrs,
 223                               rmesa->radeon.swtcl.vertex_attr_count,
 224                               NULL, 0 );
 225       rmesa->radeon.swtcl.vertex_size /= 4;
 226       rmesa->radeon.tnl_index_bitset = index_bitset;
 227       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 228           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 229    }
 230 }
 231
 232 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 233 {
 234
 235     if (!rmesa->radeon.swtcl.emit_prediction) {
 236         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 237         const int scissor_size = 8;
 238         const int prims_size = 8;
 239         const int vertex_size = 7;
 240
 241         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 242                     state_size +
 243                     (scissor_size + prims_size + vertex_size),
 244                     __FUNCTION__))
 245             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 246         else
 247             rmesa->radeon.swtcl.emit_prediction = state_size;
 248         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 249             + rmesa->radeon.cmdbuf.cs->cdw;
 250     }
 251 }
 252
 253 static void radeonRenderStart( struct gl_context *ctx )
 254 {
 255     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 256
 257     radeonSetVertexFormat( ctx );
 258
 259     if (rmesa->radeon.dma.flush != 0 &&
 260             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 261         rmesa->radeon.dma.flush( ctx );
 262 }
 263
 264
 265 /**
 266  * Set vertex state for SW TCL.  The primary purpose of this function is to
 267  * determine in advance whether or not the hardware can / should do the
 268  * projection divide or Mesa should do it.
 269  */
 270 void radeonChooseVertexState( struct gl_context *ctx )
 271 {
 272    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 273    TNLcontext *tnl = TNL_CONTEXT(ctx);
 274
 275    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 276    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 277                          ctx->Polygon.BackMode != GL_FILL);
 278
 279    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 280                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 281                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 282
 283    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 284     * rasterization fallback.  As this function will be called again when we
 285     * leave a rasterization fallback, we can just skip it for now.
 286     */
 287    if (rmesa->radeon.Fallback != 0)
 288       return;
 289
 290    /* HW perspective divide is a win, but tiny vertex formats are a
 291     * bigger one.
 292     */
 293
 294    if ((0 == (tnl->render_inputs_bitset &
 295         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
 296          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
 297        || (ctx->_TriangleCaps & DD_TRI_LIGHT_TWOSIDE)
 298        || unfilled) {
 299       rmesa->swtcl.needproj = GL_TRUE;
 300       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 301                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 302    }
 303    else {
 304       rmesa->swtcl.needproj = GL_FALSE;
 305       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 306    }
 307
 308    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 309
 310    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 311       RADEON_STATECHANGE( rmesa, set );
 312       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 313    }
 314 }
 315
 316 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 317 {
 318    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 319
 320
 321
 322    radeonEmitState(&rmesa->radeon);
 323    radeonEmitVertexAOS( rmesa,
 324                         rmesa->radeon.swtcl.vertex_size,
 325                         rmesa->radeon.swtcl.bo,
 326                         current_offset);
 327
 328
 329    radeonEmitVbufPrim( rmesa,
 330                        rmesa->swtcl.vertex_format,
 331                        rmesa->radeon.swtcl.hw_primitive,
 332                        rmesa->radeon.swtcl.numverts);
 333    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 334      WARN_ONCE("Rendering was %d commands larger than predicted size."
 335          " We might overflow  command buffer.\n",
 336          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 337
 338
 339    rmesa->radeon.swtcl.emit_prediction = 0;
 340
 341 }
 342
 343 /*
 344  * Render unclipped vertex buffers by emitting vertices directly to
 345  * dma buffers.  Use strip/fan hardware primitives where possible.
 346  * Try to simulate missing primitives with indexed vertices.
 347  */
 348 #define HAVE_POINTS      1
 349 #define HAVE_LINES       1
 350 #define HAVE_LINE_STRIPS 1
 351 #define HAVE_TRIANGLES   1
 352 #define HAVE_TRI_STRIPS  1
 353 #define HAVE_TRI_STRIP_1 0
 354 #define HAVE_TRI_FANS    1
 355 #define HAVE_QUADS       0
 356 #define HAVE_QUAD_STRIPS 0
 357 #define HAVE_POLYGONS    0
 358 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 359 #define HAVE_ELTS        0
 360
 361 static const GLuint hw_prim[GL_POLYGON+1] = {
 362    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 363    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 364    0,
 365    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 366    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 367    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 368    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 369    0,
 370    0,
 371    0
 372 };
 373
 374 static INLINE void
 375 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 376 {
 377    RADEON_NEWPRIM( rmesa );
 378    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 379    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 380 }
 381
 382 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 383 {
 384    void *rv;
 385    do {
 386      radeon_predict_emit_size( rmesa );
 387      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 388    } while (!rv);
 389    return rv;
 390 }
 391
 392 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 393 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 394 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 395 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 396 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 397 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 398   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 399 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 400 #define EMIT_VERTS( ctx, j, nr, buf ) \
 401   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 402
 403 #define TAG(x) radeon_dma_##x
 404 #include "tnl_dd/t_dd_dmatmp.h"
 405
 406
 407 /**********************************************************************/
 408 /*                          Render pipeline stage                     */
 409 /**********************************************************************/
 410
 411
 412 static GLboolean radeon_run_render( struct gl_context *ctx,
 413                                     struct tnl_pipeline_stage *stage )
 414 {
 415    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 416    TNLcontext *tnl = TNL_CONTEXT(ctx);
 417    struct vertex_buffer *VB = &tnl->vb;
 418    tnl_render_func *tab = TAG(render_tab_verts);
 419    GLuint i;
 420
 421    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 422        !radeon_dma_validate_render( ctx, VB ))
 423       return GL_TRUE;
 424
 425    radeon_prepare_render(&rmesa->radeon);
 426    if (rmesa->radeon.NewGLState)
 427       radeonValidateState( ctx );
 428
 429    tnl->Driver.Render.Start( ctx );
 430
 431    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 432    {
 433       GLuint prim = VB->Primitive[i].mode;
 434       GLuint start = VB->Primitive[i].start;
 435       GLuint length = VB->Primitive[i].count;
 436
 437       if (!length)
 438          continue;
 439
 440       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 441           "radeon_render.c: prim %s %d..%d\n",
 442                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 443                  start, start+length);
 444
 445       if (length)
 446          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 447    }
 448
 449    tnl->Driver.Render.Finish( ctx );
 450
 451    return GL_FALSE;             /* finished the pipe */
 452 }
 453
 454
 455
 456 const struct tnl_pipeline_stage _radeon_render_stage =
 457 {
 458    "radeon render",
 459    NULL,
 460    NULL,
 461    NULL,
 462    NULL,
 463    radeon_run_render            /* run */
 464 };
 465
 466
 467 /**************************************************************************/
 468
 469
 470 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 471    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 472    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 473    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 474    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 475    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 476    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 481 };
 482
 483 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 484 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 485 static void radeonResetLineStipple( struct gl_context *ctx );
 486
 487
 488 /***********************************************************************
 489  *                    Emit primitives as inline vertices               *
 490  ***********************************************************************/
 491
 492 #undef LOCAL_VARS
 493 #undef ALLOC_VERTS
 494 #define CTX_ARG r100ContextPtr rmesa
 495 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 496 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 497 #undef LOCAL_VARS
 498 #define LOCAL_VARS                                              \
 499    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 500    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 501 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 502 #define VERTEX radeonVertex
 503 #undef TAG
 504 #define TAG(x) radeon_##x
 505 #include "tnl_dd/t_dd_triemit.h"
 506
 507
 508 /***********************************************************************
 509  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 510  ***********************************************************************/
 511
 512 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 513 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 514 #define LINE( a, b )       radeon_line( rmesa, a, b )
 515 #define POINT( a )         radeon_point( rmesa, a )
 516
 517 /***********************************************************************
 518  *              Build render functions from dd templates               *
 519  ***********************************************************************/
 520
 521 #define RADEON_TWOSIDE_BIT      0x01
 522 #define RADEON_UNFILLED_BIT     0x02
 523 #define RADEON_MAX_TRIFUNC      0x04
 524
 525
 526 static struct {
 527    tnl_points_func              points;
 528    tnl_line_func                line;
 529    tnl_triangle_func    triangle;
 530    tnl_quad_func                quad;
 531 } rast_tab[RADEON_MAX_TRIFUNC];
 532
 533
 534 #define DO_FALLBACK  0
 535 #define DO_OFFSET    0
 536 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 537 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 538 #define DO_FLAT      0
 539 #define DO_TRI       1
 540 #define DO_QUAD      1
 541 #define DO_LINE      1
 542 #define DO_POINTS    1
 543 #define DO_FULL_QUAD 1
 544
 545 #define HAVE_SPEC   1
 546 #define HAVE_BACK_COLORS  0
 547 #define HAVE_HW_FLATSHADE 1
 548 #define TAB rast_tab
 549
 550 #define DEPTH_SCALE 1.0
 551 #define UNFILLED_TRI unfilled_tri
 552 #define UNFILLED_QUAD unfilled_quad
 553 #define VERT_X(_v) _v->v.x
 554 #define VERT_Y(_v) _v->v.y
 555 #define VERT_Z(_v) _v->v.z
 556 #define AREA_IS_CCW( a ) (a < 0)
 557 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 558
 559 #define VERT_SET_RGBA( v, c )                                   \
 560 do {                                                            \
 561    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 562    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 563    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 564    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 565    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 566 } while (0)
 567
 568 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 569
 570 #define VERT_SET_SPEC( v, c )                                   \
 571 do {                                                            \
 572    if (specoffset) {                                            \
 573       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 574       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 575       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 576       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 577    }                                                            \
 578 } while (0)
 579 #define VERT_COPY_SPEC( v0, v1 )                        \
 580 do {                                                    \
 581    if (specoffset) {                                    \
 582       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 583       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 584       spec0->red   = spec1->red;        \
 585       spec0->green = spec1->green;      \
 586       spec0->blue  = spec1->blue;       \
 587    }                                                    \
 588 } while (0)
 589
 590 /* These don't need LE32_TO_CPU() as they used to save and restore
 591  * colors which are already in the correct format.
 592  */
 593 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 594 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 595 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 596 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 597
 598 #undef LOCAL_VARS
 599 #undef TAG
 600 #undef INIT
 601
 602 #define LOCAL_VARS(n)                                                   \
 603    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 604    GLuint color[n] = {0}, spec[n] = {0};                                                \
 605    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 606    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 607    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 608
 609 /***********************************************************************
 610  *                Helpers for rendering unfilled primitives            *
 611  ***********************************************************************/
 612
 613 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 614 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 615 #undef TAG
 616 #define TAG(x) x
 617 #include "tnl_dd/t_dd_unfilled.h"
 618 #undef IND
 619
 620
 621 /***********************************************************************
 622  *                      Generate GL render functions                   *
 623  ***********************************************************************/
 624
 625
 626 #define IND (0)
 627 #define TAG(x) x
 628 #include "tnl_dd/t_dd_tritmp.h"
 629
 630 #define IND (RADEON_TWOSIDE_BIT)
 631 #define TAG(x) x##_twoside
 632 #include "tnl_dd/t_dd_tritmp.h"
 633
 634 #define IND (RADEON_UNFILLED_BIT)
 635 #define TAG(x) x##_unfilled
 636 #include "tnl_dd/t_dd_tritmp.h"
 637
 638 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 639 #define TAG(x) x##_twoside_unfilled
 640 #include "tnl_dd/t_dd_tritmp.h"
 641
 642
 643 static void init_rast_tab( void )
 644 {
 645    init();
 646    init_twoside();
 647    init_unfilled();
 648    init_twoside_unfilled();
 649 }
 650
 651 /**********************************************************************/
 652 /*               Render unclipped begin/end objects                   */
 653 /**********************************************************************/
 654
 655 #define RENDER_POINTS( start, count )           \
 656    for ( ; start < count ; start++)             \
 657       radeon_point( rmesa, VERT(start) )
 658 #define RENDER_LINE( v0, v1 ) \
 659    radeon_line( rmesa, VERT(v0), VERT(v1) )
 660 #define RENDER_TRI( v0, v1, v2 )  \
 661    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 662 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 663    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 664 #undef INIT
 665 #define INIT(x) do {                                    \
 666    radeonRenderPrimitive( ctx, x );                     \
 667 } while (0)
 668 #undef LOCAL_VARS
 669 #define LOCAL_VARS                                              \
 670    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 671    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 672    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 673    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 674    const GLboolean stipple = ctx->Line.StippleFlag;             \
 675    (void) elt; (void) stipple;
 676 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 677 #define RESET_OCCLUSION
 678 #define PRESERVE_VB_DEFS
 679 #define ELT(x) (x)
 680 #define TAG(x) radeon_##x##_verts
 681 #include "tnl/t_vb_rendertmp.h"
 682 #undef ELT
 683 #undef TAG
 684 #define TAG(x) radeon_##x##_elts
 685 #define ELT(x) elt[x]
 686 #include "tnl/t_vb_rendertmp.h"
 687
 688
 689
 690 /**********************************************************************/
 691 /*                    Choose render functions                         */
 692 /**********************************************************************/
 693
 694 void radeonChooseRenderState( struct gl_context *ctx )
 695 {
 696    TNLcontext *tnl = TNL_CONTEXT(ctx);
 697    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 698    GLuint index = 0;
 699    GLuint flags = ctx->_TriangleCaps;
 700    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 701                          ctx->Polygon.BackMode != GL_FILL);
 702
 703    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 704       return;
 705
 706    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 707    if (unfilled)                     index |= RADEON_UNFILLED_BIT;
 708
 709    if (index != rmesa->radeon.swtcl.RenderIndex) {
 710       tnl->Driver.Render.Points = rast_tab[index].points;
 711       tnl->Driver.Render.Line = rast_tab[index].line;
 712       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 713       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 714       tnl->Driver.Render.Quad = rast_tab[index].quad;
 715
 716       if (index == 0) {
 717          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 718          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 719          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 720       } else {
 721          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 722          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 723          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 724       }
 725
 726       rmesa->radeon.swtcl.RenderIndex = index;
 727    }
 728 }
 729
 730
 731 /**********************************************************************/
 732 /*                 High level hooks for t_vb_render.c                 */
 733 /**********************************************************************/
 734
 735
 736 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 737 {
 738    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 739
 740    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 741       RADEON_NEWPRIM( rmesa );
 742       rmesa->radeon.swtcl.hw_primitive = hwprim;
 743    }
 744 }
 745
 746 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 747 {
 748    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 749    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 750                          ctx->Polygon.BackMode != GL_FILL);
 751
 752    rmesa->radeon.swtcl.render_primitive = prim;
 753    if (prim < GL_TRIANGLES || !unfilled)
 754       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 755 }
 756
 757 static void radeonRenderFinish( struct gl_context *ctx )
 758 {
 759 }
 760
 761 static void radeonResetLineStipple( struct gl_context *ctx )
 762 {
 763    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 764    RADEON_STATECHANGE( rmesa, lin );
 765 }
 766
 767
 768 /**********************************************************************/
 769 /*           Transition to/from hardware rasterization.               */
 770 /**********************************************************************/
 771
 772 static const char * const fallbackStrings[] = {
 773    "Texture mode",
 774    "glDrawBuffer(GL_FRONT_AND_BACK)",
 775    "glEnable(GL_STENCIL) without hw stencil buffer",
 776    "glRenderMode(selection or feedback)",
 777    "glBlendEquation",
 778    "glBlendFunc",
 779    "RADEON_NO_RAST",
 780    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 781 };
 782
 783
 784 static const char *getFallbackString(GLuint bit)
 785 {
 786    int i = 0;
 787    while (bit > 1) {
 788       i++;
 789       bit >>= 1;
 790    }
 791    return fallbackStrings[i];
 792 }
 793
 794
 795 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 796 {
 797    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 798    TNLcontext *tnl = TNL_CONTEXT(ctx);
 799    GLuint oldfallback = rmesa->radeon.Fallback;
 800
 801    if (mode) {
 802       rmesa->radeon.Fallback |= bit;
 803       if (oldfallback == 0) {
 804          radeon_firevertices(&rmesa->radeon);
 805          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 806          _swsetup_Wakeup( ctx );
 807          rmesa->radeon.swtcl.RenderIndex = ~0;
 808          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 809             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 810                     bit, getFallbackString(bit));
 811          }
 812       }
 813    }
 814    else {
 815       rmesa->radeon.Fallback &= ~bit;
 816       if (oldfallback == bit) {
 817          _swrast_flush( ctx );
 818          tnl->Driver.Render.Start = radeonRenderStart;
 819          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 820          tnl->Driver.Render.Finish = radeonRenderFinish;
 821
 822          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 823          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 824          tnl->Driver.Render.Interp = _tnl_interp;
 825
 826          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 827          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 828          if (rmesa->radeon.TclFallback) {
 829             /* These are already done if rmesa->radeon.TclFallback goes to
 830              * zero above. But not if it doesn't (RADEON_NO_TCL for
 831              * example?)
 832              */
 833             _tnl_invalidate_vertex_state( ctx, ~0 );
 834             _tnl_invalidate_vertices( ctx, ~0 );
 835             rmesa->radeon.tnl_index_bitset = 0;
 836             radeonChooseVertexState( ctx );
 837             radeonChooseRenderState( ctx );
 838          }
 839          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 840             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 841                     bit, getFallbackString(bit));
 842          }
 843       }
 844    }
 845 }
 846
 847
 848 /**********************************************************************/
 849 /*                            Initialization.                         */
 850 /**********************************************************************/
 851
 852 void radeonInitSwtcl( struct gl_context *ctx )
 853 {
 854    TNLcontext *tnl = TNL_CONTEXT(ctx);
 855    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 856    static int firsttime = 1;
 857
 858    if (firsttime) {
 859       init_rast_tab();
 860       firsttime = 0;
 861    }
 862    rmesa->radeon.swtcl.emit_prediction = 0;
 863
 864    tnl->Driver.Render.Start = radeonRenderStart;
 865    tnl->Driver.Render.Finish = radeonRenderFinish;
 866    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 867    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 868    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 869    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 870    tnl->Driver.Render.Interp = _tnl_interp;
 871
 872    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 873                        RADEON_MAX_TNL_VERTEX_SIZE);
 874
 875    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 876    rmesa->radeon.swtcl.RenderIndex = ~0;
 877    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 878    rmesa->radeon.swtcl.hw_primitive = 0;
 879 }
 880