src/mesa/drivers/dri/radeon/radeon_tcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      Tungsten Graphics Inc., Austin, Texas.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/light.h"
  38 #include "main/mtypes.h"
  39 #include "main/enums.h"
  40
  41 #include "vbo/vbo.h"
  42 #include "tnl/tnl.h"
  43 #include "tnl/t_pipeline.h"
  44
  45 #include "radeon_common.h"
  46 #include "radeon_context.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tex.h"
  50 #include "radeon_tcl.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_maos.h"
  53
  54
  55
  56 /*
  57  * Render unclipped vertex buffers by emitting vertices directly to
  58  * dma buffers.  Use strip/fan hardware primitives where possible.
  59  * Try to simulate missing primitives with indexed vertices.
  60  */
  61 #define HAVE_POINTS      1
  62 #define HAVE_LINES       1
  63 #define HAVE_LINE_LOOP   0
  64 #define HAVE_LINE_STRIPS 1
  65 #define HAVE_TRIANGLES   1
  66 #define HAVE_TRI_STRIPS  1
  67 #define HAVE_TRI_STRIP_1 0
  68 #define HAVE_TRI_FANS    1
  69 #define HAVE_QUADS       0
  70 #define HAVE_QUAD_STRIPS 0
  71 #define HAVE_POLYGONS    1
  72 #define HAVE_ELTS        1
  73
  74
  75 #define HW_POINTS           RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
  76 #define HW_LINES            RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
  77 #define HW_LINE_LOOP        0
  78 #define HW_LINE_STRIP       RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
  79 #define HW_TRIANGLES        RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
  80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
  81 #define HW_TRIANGLE_STRIP_1 0
  82 #define HW_TRIANGLE_FAN     RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  83 #define HW_QUADS            0
  84 #define HW_QUAD_STRIP       0
  85 #define HW_POLYGON          RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  86
  87
  88 static GLboolean discrete_prim[0x10] = {
  89    0,                           /* 0 none */
  90    1,                           /* 1 points */
  91    1,                           /* 2 lines */
  92    0,                           /* 3 line_strip */
  93    1,                           /* 4 tri_list */
  94    0,                           /* 5 tri_fan */
  95    0,                           /* 6 tri_type2 */
  96    1,                           /* 7 rect list (unused) */
  97    1,                           /* 8 3vert point */
  98    1,                           /* 9 3vert line */
  99    0,
 100    0,
 101    0,
 102    0,
 103    0,
 104    0,
 105 };
 106
 107
 108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 109 #define ELT_TYPE  GLushort
 110
 111 #define ELT_INIT(prim, hw_prim) \
 112    radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
 113
 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
 115
 116
 117 /* Don't really know how many elts will fit in what's left of cmdbuf,
 118  * as there is state to emit, etc:
 119  */
 120
 121 /* Testing on isosurf shows a maximum around here.  Don't know if it's
 122  * the card or driver or kernel module that is causing the behaviour.
 123  */
 124 #define GET_MAX_HW_ELTS() 300
 125
 126
 127 #define RESET_STIPPLE() do {                    \
 128    RADEON_STATECHANGE( rmesa, lin );            \
 129    radeonEmitState(&rmesa->radeon);                     \
 130 } while (0)
 131
 132 #define AUTO_STIPPLE( mode )  do {              \
 133    RADEON_STATECHANGE( rmesa, lin );            \
 134    if (mode)                                    \
 135       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
 136          RADEON_LINE_PATTERN_AUTO_RESET;        \
 137    else                                         \
 138       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
 139          ~RADEON_LINE_PATTERN_AUTO_RESET;       \
 140    radeonEmitState(&rmesa->radeon);             \
 141 } while (0)
 142
 143
 144
 145 #define ALLOC_ELTS(nr)  radeonAllocElts( rmesa, nr )
 146
 147 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
 148 {
 149       if (rmesa->radeon.dma.flush)
 150          rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 151
 152       rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) +
 153                                AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
 154
 155       radeonEmitAOS( rmesa,
 156                      rmesa->radeon.tcl.aos_count, 0 );
 157
 158       return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
 159                                        rmesa->tcl.hw_primitive, nr );
 160 }
 161
 162 #define CLOSE_ELTS() if (0)  RADEON_NEWPRIM( rmesa )
 163
 164
 165
 166 /* TODO: Try to extend existing primitive if both are identical,
 167  * discrete and there are no intervening state changes.  (Somewhat
 168  * duplicates changes to DrawArrays code)
 169  */
 170 static void radeonEmitPrim( GLcontext *ctx,
 171                        GLenum prim,
 172                        GLuint hwprim,
 173                        GLuint start,
 174                        GLuint count)
 175 {
 176    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 177    radeonTclPrimitive( ctx, prim, hwprim );
 178
 179    rcommonEnsureCmdBufSpace( &rmesa->radeon,
 180                              AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
 181                              rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
 182
 183    radeonEmitAOS( rmesa,
 184                   rmesa->radeon.tcl.aos_count,
 185                   start );
 186
 187    /* Why couldn't this packet have taken an offset param?
 188     */
 189    radeonEmitVbufPrim( rmesa,
 190                        rmesa->tcl.vertex_format,
 191                        rmesa->tcl.hw_primitive,
 192                        count - start );
 193 }
 194
 195 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do {       \
 196    radeonEmitPrim( ctx, prim, hwprim, start, count );           \
 197    (void) rmesa; } while (0)
 198
 199 /* Try & join small primitives
 200  */
 201 #if 0
 202 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
 203 #else
 204 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM )                    \
 205   ((NR) < 20 ||                                                 \
 206    ((NR) < 40 &&                                                \
 207     rmesa->tcl.hw_primitive == (PRIM|                           \
 208                             RADEON_CP_VC_CNTL_PRIM_WALK_IND|    \
 209                             RADEON_CP_VC_CNTL_TCL_ENABLE)))
 210 #endif
 211
 212 #ifdef MESA_BIG_ENDIAN
 213 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
 214 #define EMIT_ELT(dest, offset, x) do {                          \
 215         int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 );     \
 216         GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 );    \
 217         (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x);     \
 218         (void)rmesa; } while (0)
 219 #else
 220 #define EMIT_ELT(dest, offset, x) do {                          \
 221         (dest)[offset] = (GLushort) (x);                        \
 222         (void)rmesa; } while (0)
 223 #endif
 224
 225 #define EMIT_TWO_ELTS(dest, offset, x, y)  *(GLuint *)(dest+offset) = ((y)<<16)|(x);
 226
 227
 228
 229 #define TAG(x) tcl_##x
 230 #include "tnl_dd/t_dd_dmatmp2.h"
 231
 232 /**********************************************************************/
 233 /*                          External entrypoints                     */
 234 /**********************************************************************/
 235
 236 void radeonEmitPrimitive( GLcontext *ctx,
 237                           GLuint first,
 238                           GLuint last,
 239                           GLuint flags )
 240 {
 241    tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 242 }
 243
 244 void radeonEmitEltPrimitive( GLcontext *ctx,
 245                              GLuint first,
 246                              GLuint last,
 247                              GLuint flags )
 248 {
 249    tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 250 }
 251
 252 void radeonTclPrimitive( GLcontext *ctx,
 253                          GLenum prim,
 254                          int hw_prim )
 255 {
 256    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 257    GLuint se_cntl;
 258    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 259
 260    if (newprim != rmesa->tcl.hw_primitive ||
 261        !discrete_prim[hw_prim&0xf]) {
 262       RADEON_NEWPRIM( rmesa );
 263       rmesa->tcl.hw_primitive = newprim;
 264    }
 265
 266    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 267    se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
 268
 269    if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
 270       se_cntl |= RADEON_FLAT_SHADE_VTX_0;
 271    else
 272       se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 273
 274    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 275       RADEON_STATECHANGE( rmesa, set );
 276       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 277    }
 278 }
 279
 280 /**********************************************************************/
 281 /*             Fog blend factor computation for hw tcl                */
 282 /*             same calculation used as in t_vb_fog.c                 */
 283 /**********************************************************************/
 284
 285 #define FOG_EXP_TABLE_SIZE 256
 286 #define FOG_MAX (10.0)
 287 #define EXP_FOG_MAX .0006595
 288 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
 289 static GLfloat exp_table[FOG_EXP_TABLE_SIZE];
 290
 291 #if 1
 292 #define NEG_EXP( result, narg )                                         \
 293 do {                                                                    \
 294    GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR));                       \
 295    GLint k = (GLint) f;                                                 \
 296    if (k > FOG_EXP_TABLE_SIZE-2)                                        \
 297       result = (GLfloat) EXP_FOG_MAX;                                   \
 298    else                                                                 \
 299       result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]);      \
 300 } while (0)
 301 #else
 302 #define NEG_EXP( result, narg )                                 \
 303 do {                                                            \
 304    result = exp(-narg);                                         \
 305 } while (0)
 306 #endif
 307
 308
 309 /**
 310  * Initialize the exp_table[] lookup table for approximating exp().
 311  */
 312 void
 313 radeonInitStaticFogData( void )
 314 {
 315    GLfloat f = 0.0F;
 316    GLint i = 0;
 317    for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
 318       exp_table[i] = (GLfloat) exp(-f);
 319    }
 320 }
 321
 322
 323 /**
 324  * Compute per-vertex fog blend factors from fog coordinates by
 325  * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
 326  * Fog coordinates are distances from the eye (typically between the
 327  * near and far clip plane distances).
 328  * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
 329  * Fog blend factors are in the range [0,1].
 330  */
 331 float
 332 radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
 333 {
 334    GLfloat end  = ctx->Fog.End;
 335    GLfloat d, temp;
 336    const GLfloat z = FABSF(fogcoord);
 337
 338    switch (ctx->Fog.Mode) {
 339    case GL_LINEAR:
 340       if (ctx->Fog.Start == ctx->Fog.End)
 341          d = 1.0F;
 342       else
 343          d = 1.0F / (ctx->Fog.End - ctx->Fog.Start);
 344       temp = (end - z) * d;
 345       return CLAMP(temp, 0.0F, 1.0F);
 346       break;
 347    case GL_EXP:
 348       d = ctx->Fog.Density;
 349       NEG_EXP( temp, d * z );
 350       return temp;
 351       break;
 352    case GL_EXP2:
 353       d = ctx->Fog.Density*ctx->Fog.Density;
 354       NEG_EXP( temp, d * z * z );
 355       return temp;
 356       break;
 357    default:
 358       _mesa_problem(ctx, "Bad fog mode in make_fog_coord");
 359       return 0;
 360    }
 361 }
 362
 363 /**********************************************************************/
 364 /*                          Render pipeline stage                     */
 365 /**********************************************************************/
 366
 367
 368 /* TCL render.
 369  */
 370 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 371                                         struct tnl_pipeline_stage *stage )
 372 {
 373    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 374    TNLcontext *tnl = TNL_CONTEXT(ctx);
 375    struct vertex_buffer *VB = &tnl->vb;
 376    GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
 377    GLuint i;
 378
 379    /* TODO: separate this from the swtnl pipeline
 380     */
 381    if (rmesa->radeon.TclFallback)
 382       return GL_TRUE;   /* fallback to software t&l */
 383
 384    if (VB->Count == 0)
 385       return GL_FALSE;
 386
 387    /* NOTE: inputs != tnl->render_inputs - these are the untransformed
 388     * inputs.
 389     */
 390    if (ctx->Light.Enabled) {
 391       inputs |= VERT_BIT_NORMAL;
 392    }
 393
 394    if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
 395       inputs |= VERT_BIT_COLOR1;
 396    }
 397
 398    if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
 399       inputs |= VERT_BIT_FOG;
 400    }
 401
 402    for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
 403       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 404       /* TODO: probably should not emit texture coords when texgen is enabled */
 405          if (rmesa->TexGenNeedNormals[i]) {
 406             inputs |= VERT_BIT_NORMAL;
 407          }
 408          inputs |= VERT_BIT_TEX(i);
 409       }
 410    }
 411
 412    radeonReleaseArrays( ctx, ~0 );
 413    radeonEmitArrays( ctx, inputs );
 414
 415    rmesa->tcl.Elts = VB->Elts;
 416
 417    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 418    {
 419       GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
 420       GLuint start = VB->Primitive[i].start;
 421       GLuint length = VB->Primitive[i].count;
 422
 423       if (!length)
 424          continue;
 425
 426       if (rmesa->tcl.Elts)
 427          radeonEmitEltPrimitive( ctx, start, start+length, prim );
 428       else
 429          radeonEmitPrimitive( ctx, start, start+length, prim );
 430    }
 431
 432    return GL_FALSE;             /* finished the pipe */
 433 }
 434
 435
 436
 437 /* Initial state for tcl stage.
 438  */
 439 const struct tnl_pipeline_stage _radeon_tcl_stage =
 440 {
 441    "radeon render",
 442    NULL,
 443    NULL,
 444    NULL,
 445    NULL,
 446    radeon_run_tcl_render        /* run */
 447 };
 448
 449
 450
 451 /**********************************************************************/
 452 /*                 Validate state at pipeline start                   */
 453 /**********************************************************************/
 454
 455
 456 /*-----------------------------------------------------------------------
 457  * Manage TCL fallbacks
 458  */
 459
 460
 461 static void transition_to_swtnl( GLcontext *ctx )
 462 {
 463    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 464    TNLcontext *tnl = TNL_CONTEXT(ctx);
 465    GLuint se_cntl;
 466
 467    RADEON_NEWPRIM( rmesa );
 468    rmesa->swtcl.vertex_format = 0;
 469
 470    radeonChooseVertexState( ctx );
 471    radeonChooseRenderState( ctx );
 472
 473    _mesa_validate_all_lighting_tables( ctx );
 474
 475    tnl->Driver.NotifyMaterialChange =
 476       _mesa_validate_all_lighting_tables;
 477
 478    radeonReleaseArrays( ctx, ~0 );
 479
 480    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 481    se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 482
 483    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 484       RADEON_STATECHANGE( rmesa, set );
 485       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 486    }
 487 }
 488
 489
 490 static void transition_to_hwtnl( GLcontext *ctx )
 491 {
 492    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 493    TNLcontext *tnl = TNL_CONTEXT(ctx);
 494    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 495
 496    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 497                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 498                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 499    se_coord_fmt |= RADEON_VTX_W0_IS_NOT_1_OVER_W0;
 500
 501    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 502       RADEON_STATECHANGE( rmesa, set );
 503       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 504       _tnl_need_projected_coords( ctx, GL_FALSE );
 505    }
 506
 507    radeonUpdateMaterial( ctx );
 508
 509    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 510
 511    if ( rmesa->radeon.dma.flush )
 512       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 513
 514    rmesa->radeon.dma.flush = NULL;
 515    rmesa->swtcl.vertex_format = 0;
 516
 517    //   if (rmesa->swtcl.indexed_verts.buf)
 518    //      radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 519    //                         __FUNCTION__ );
 520
 521    if (RADEON_DEBUG & DEBUG_FALLBACKS)
 522       fprintf(stderr, "Radeon end tcl fallback\n");
 523 }
 524
 525 static char *fallbackStrings[] = {
 526    "Rasterization fallback",
 527    "Unfilled triangles",
 528    "Twosided lighting, differing materials",
 529    "Materials in VB (maybe between begin/end)",
 530    "Texgen unit 0",
 531    "Texgen unit 1",
 532    "Texgen unit 2",
 533    "User disable",
 534    "Fogcoord with separate specular lighting"
 535 };
 536
 537
 538 static char *getFallbackString(GLuint bit)
 539 {
 540    int i = 0;
 541    while (bit > 1) {
 542       i++;
 543       bit >>= 1;
 544    }
 545    return fallbackStrings[i];
 546 }
 547
 548
 549
 550 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 551 {
 552    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 553    GLuint oldfallback = rmesa->radeon.TclFallback;
 554
 555    if (mode) {
 556       rmesa->radeon.TclFallback |= bit;
 557       if (oldfallback == 0) {
 558          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 559             fprintf(stderr, "Radeon begin tcl fallback %s\n",
 560                     getFallbackString( bit ));
 561          transition_to_swtnl( ctx );
 562       }
 563    }
 564    else {
 565       rmesa->radeon.TclFallback &= ~bit;
 566       if (oldfallback == bit) {
 567          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 568             fprintf(stderr, "Radeon end tcl fallback %s\n",
 569                     getFallbackString( bit ));
 570          transition_to_hwtnl( ctx );
 571       }
 572    }
 573 }