src/mesa/drivers/dri/radeon/radeon_tcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      Tungsten Graphics Inc., Austin, Texas.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/light.h"
  38 #include "main/mtypes.h"
  39 #include "main/enums.h"
  40
  41 #include "vbo/vbo.h"
  42 #include "tnl/tnl.h"
  43 #include "tnl/t_pipeline.h"
  44
  45 #include "radeon_common.h"
  46 #include "radeon_context.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tex.h"
  50 #include "radeon_tcl.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_maos.h"
  53 #include "radeon_common_context.h"
  54
  55
  56
  57 /*
  58  * Render unclipped vertex buffers by emitting vertices directly to
  59  * dma buffers.  Use strip/fan hardware primitives where possible.
  60  * Try to simulate missing primitives with indexed vertices.
  61  */
  62 #define HAVE_POINTS      1
  63 #define HAVE_LINES       1
  64 #define HAVE_LINE_LOOP   0
  65 #define HAVE_LINE_STRIPS 1
  66 #define HAVE_TRIANGLES   1
  67 #define HAVE_TRI_STRIPS  1
  68 #define HAVE_TRI_STRIP_1 0
  69 #define HAVE_TRI_FANS    1
  70 #define HAVE_QUADS       0
  71 #define HAVE_QUAD_STRIPS 0
  72 #define HAVE_POLYGONS    1
  73 #define HAVE_ELTS        1
  74
  75
  76 #define HW_POINTS           RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
  77 #define HW_LINES            RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
  78 #define HW_LINE_LOOP        0
  79 #define HW_LINE_STRIP       RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
  80 #define HW_TRIANGLES        RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
  81 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
  82 #define HW_TRIANGLE_STRIP_1 0
  83 #define HW_TRIANGLE_FAN     RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  84 #define HW_QUADS            0
  85 #define HW_QUAD_STRIP       0
  86 #define HW_POLYGON          RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  87
  88
  89 static GLboolean discrete_prim[0x10] = {
  90    0,                           /* 0 none */
  91    1,                           /* 1 points */
  92    1,                           /* 2 lines */
  93    0,                           /* 3 line_strip */
  94    1,                           /* 4 tri_list */
  95    0,                           /* 5 tri_fan */
  96    0,                           /* 6 tri_type2 */
  97    1,                           /* 7 rect list (unused) */
  98    1,                           /* 8 3vert point */
  99    1,                           /* 9 3vert line */
 100    0,
 101    0,
 102    0,
 103    0,
 104    0,
 105    0,
 106 };
 107
 108
 109 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 110 #define ELT_TYPE  GLushort
 111
 112 #define ELT_INIT(prim, hw_prim) \
 113    radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
 114
 115 #define GET_MESA_ELTS() rmesa->tcl.Elts
 116
 117
 118 /* Don't really know how many elts will fit in what's left of cmdbuf,
 119  * as there is state to emit, etc:
 120  */
 121
 122 /* Testing on isosurf shows a maximum around here.  Don't know if it's
 123  * the card or driver or kernel module that is causing the behaviour.
 124  */
 125 #define GET_MAX_HW_ELTS() 300
 126
 127
 128 #define RESET_STIPPLE() do {                    \
 129    RADEON_STATECHANGE( rmesa, lin );            \
 130    radeonEmitState(&rmesa->radeon);                     \
 131 } while (0)
 132
 133 #define AUTO_STIPPLE( mode )  do {              \
 134    RADEON_STATECHANGE( rmesa, lin );            \
 135    if (mode)                                    \
 136       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
 137          RADEON_LINE_PATTERN_AUTO_RESET;        \
 138    else                                         \
 139       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
 140          ~RADEON_LINE_PATTERN_AUTO_RESET;       \
 141    radeonEmitState(&rmesa->radeon);             \
 142 } while (0)
 143
 144
 145
 146 #define ALLOC_ELTS(nr)  radeonAllocElts( rmesa, nr )
 147
 148 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
 149 {
 150       if (rmesa->radeon.dma.flush)
 151          rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 152
 153       radeonEmitAOS( rmesa,
 154                      rmesa->radeon.tcl.aos_count, 0 );
 155
 156       return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
 157                                        rmesa->tcl.hw_primitive, nr );
 158 }
 159
 160 #define CLOSE_ELTS() if (0)  RADEON_NEWPRIM( rmesa )
 161
 162
 163
 164 /* TODO: Try to extend existing primitive if both are identical,
 165  * discrete and there are no intervening state changes.  (Somewhat
 166  * duplicates changes to DrawArrays code)
 167  */
 168 static void radeonEmitPrim( GLcontext *ctx,
 169                        GLenum prim,
 170                        GLuint hwprim,
 171                        GLuint start,
 172                        GLuint count)
 173 {
 174    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 175    radeonTclPrimitive( ctx, prim, hwprim );
 176
 177    radeonEmitAOS( rmesa,
 178                   rmesa->radeon.tcl.aos_count,
 179                   start );
 180
 181    /* Why couldn't this packet have taken an offset param?
 182     */
 183    radeonEmitVbufPrim( rmesa,
 184                        rmesa->tcl.vertex_format,
 185                        rmesa->tcl.hw_primitive,
 186                        count - start );
 187 }
 188
 189 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do {       \
 190    radeonEmitPrim( ctx, prim, hwprim, start, count );           \
 191    (void) rmesa; } while (0)
 192
 193 #define MAX_CONVERSION_SIZE 40
 194
 195 /* Try & join small primitives
 196  */
 197 #if 0
 198 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
 199 #else
 200 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM )                    \
 201   ((NR) < 20 ||                                                 \
 202    ((NR) < 40 &&                                                \
 203     rmesa->tcl.hw_primitive == (PRIM|                           \
 204                             RADEON_CP_VC_CNTL_PRIM_WALK_IND|    \
 205                             RADEON_CP_VC_CNTL_TCL_ENABLE)))
 206 #endif
 207
 208 #ifdef MESA_BIG_ENDIAN
 209 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
 210 #define EMIT_ELT(dest, offset, x) do {                          \
 211         int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 );     \
 212         GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 );    \
 213         (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x);     \
 214         (void)rmesa; } while (0)
 215 #else
 216 #define EMIT_ELT(dest, offset, x) do {                          \
 217         (dest)[offset] = (GLushort) (x);                        \
 218         (void)rmesa; } while (0)
 219 #endif
 220
 221 #define EMIT_TWO_ELTS(dest, offset, x, y)  *(GLuint *)(dest+offset) = ((y)<<16)|(x);
 222
 223
 224
 225 #define TAG(x) tcl_##x
 226 #include "tnl_dd/t_dd_dmatmp2.h"
 227
 228 /**********************************************************************/
 229 /*                          External entrypoints                     */
 230 /**********************************************************************/
 231
 232 void radeonEmitPrimitive( GLcontext *ctx,
 233                           GLuint first,
 234                           GLuint last,
 235                           GLuint flags )
 236 {
 237    tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 238 }
 239
 240 void radeonEmitEltPrimitive( GLcontext *ctx,
 241                              GLuint first,
 242                              GLuint last,
 243                              GLuint flags )
 244 {
 245    tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 246 }
 247
 248 void radeonTclPrimitive( GLcontext *ctx,
 249                          GLenum prim,
 250                          int hw_prim )
 251 {
 252    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 253    GLuint se_cntl;
 254    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 255
 256    if (newprim != rmesa->tcl.hw_primitive ||
 257        !discrete_prim[hw_prim&0xf]) {
 258       RADEON_NEWPRIM( rmesa );
 259       rmesa->tcl.hw_primitive = newprim;
 260    }
 261
 262    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 263    se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
 264
 265    if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
 266       se_cntl |= RADEON_FLAT_SHADE_VTX_0;
 267    else
 268       se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 269
 270    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 271       RADEON_STATECHANGE( rmesa, set );
 272       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 273    }
 274 }
 275
 276 /**********************************************************************/
 277 /*             Fog blend factor computation for hw tcl                */
 278 /*             same calculation used as in t_vb_fog.c                 */
 279 /**********************************************************************/
 280
 281 #define FOG_EXP_TABLE_SIZE 256
 282 #define FOG_MAX (10.0)
 283 #define EXP_FOG_MAX .0006595
 284 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
 285 static GLfloat exp_table[FOG_EXP_TABLE_SIZE];
 286
 287 #if 1
 288 #define NEG_EXP( result, narg )                                         \
 289 do {                                                                    \
 290    GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR));                       \
 291    GLint k = (GLint) f;                                                 \
 292    if (k > FOG_EXP_TABLE_SIZE-2)                                        \
 293       result = (GLfloat) EXP_FOG_MAX;                                   \
 294    else                                                                 \
 295       result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]);      \
 296 } while (0)
 297 #else
 298 #define NEG_EXP( result, narg )                                 \
 299 do {                                                            \
 300    result = exp(-narg);                                         \
 301 } while (0)
 302 #endif
 303
 304
 305 /**
 306  * Initialize the exp_table[] lookup table for approximating exp().
 307  */
 308 void
 309 radeonInitStaticFogData( void )
 310 {
 311    GLfloat f = 0.0F;
 312    GLint i = 0;
 313    for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
 314       exp_table[i] = (GLfloat) exp(-f);
 315    }
 316 }
 317
 318
 319 /**
 320  * Compute per-vertex fog blend factors from fog coordinates by
 321  * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
 322  * Fog coordinates are distances from the eye (typically between the
 323  * near and far clip plane distances).
 324  * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
 325  * Fog blend factors are in the range [0,1].
 326  */
 327 float
 328 radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
 329 {
 330    GLfloat end  = ctx->Fog.End;
 331    GLfloat d, temp;
 332    const GLfloat z = FABSF(fogcoord);
 333
 334    switch (ctx->Fog.Mode) {
 335    case GL_LINEAR:
 336       if (ctx->Fog.Start == ctx->Fog.End)
 337          d = 1.0F;
 338       else
 339          d = 1.0F / (ctx->Fog.End - ctx->Fog.Start);
 340       temp = (end - z) * d;
 341       return CLAMP(temp, 0.0F, 1.0F);
 342       break;
 343    case GL_EXP:
 344       d = ctx->Fog.Density;
 345       NEG_EXP( temp, d * z );
 346       return temp;
 347       break;
 348    case GL_EXP2:
 349       d = ctx->Fog.Density*ctx->Fog.Density;
 350       NEG_EXP( temp, d * z * z );
 351       return temp;
 352       break;
 353    default:
 354       _mesa_problem(ctx, "Bad fog mode in make_fog_coord");
 355       return 0;
 356    }
 357 }
 358
 359 /**
 360  * Predict total emit size for next rendering operation so there is no flush in middle of rendering
 361  * Prediction has to aim towards the best possible value that is worse than worst case scenario
 362  */
 363 static GLuint radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs )
 364 {
 365   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 366   TNLcontext *tnl = TNL_CONTEXT(ctx);
 367   struct vertex_buffer *VB = &tnl->vb;
 368   GLuint space_required;
 369   GLuint state_size;
 370   GLuint nr_aos = 1; /* radeonEmitArrays does always emit one */
 371   int i;
 372   /* list of flags that are allocating aos object */
 373   const GLuint flags_to_check[] = {
 374     VERT_BIT_NORMAL,
 375     VERT_BIT_COLOR0,
 376     VERT_BIT_COLOR1,
 377     VERT_BIT_FOG
 378   };
 379   /* predict number of aos to emit */
 380   for (i=0; i < sizeof(flags_to_check)/sizeof(flags_to_check[0]); ++i)
 381   {
 382     if (inputs & flags_to_check[i])
 383       ++nr_aos;
 384   }
 385   for (i = 0; i < ctx->Const.MaxTextureUnits; ++i)
 386   {
 387     if (inputs & VERT_BIT_TEX(i))
 388       ++nr_aos;
 389   }
 390
 391   {
 392     /* count the prediction for state size */
 393     space_required = 0;
 394     state_size = radeonCountStateEmitSize( &rmesa->radeon );
 395     /* tcl may be changed in radeonEmitArrays so account for it if not dirty */
 396     if (!rmesa->hw.tcl.dirty)
 397       state_size += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl );
 398     /* predict size for elements */
 399     for (i = 0; i < VB->PrimitiveCount; ++i)
 400     {
 401       if (!VB->Primitive[i].count)
 402         continue;
 403       /* If primitive.count is less than MAX_CONVERSION_SIZE
 404          rendering code may decide convert to elts.
 405          In that case we have to make pessimistic prediction.
 406          and use larger of 2 paths. */
 407       const GLuint elts = ELTS_BUFSZ(nr_aos);
 408       const GLuint index = INDEX_BUFSZ;
 409       const GLuint vbuf = VBUF_BUFSZ;
 410       if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE)
 411           || vbuf > index + elts)
 412         space_required += vbuf;
 413       else
 414         space_required += index + elts;
 415       space_required += AOS_BUFSZ(nr_aos);
 416     }
 417     space_required += SCISSOR_BUFSZ;
 418   }
 419   /* flush the buffer in case we need more than is left. */
 420   if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__))
 421     return space_required + radeonCountStateEmitSize( &rmesa->radeon );
 422   else
 423     return space_required + state_size;
 424 }
 425
 426 /**********************************************************************/
 427 /*                          Render pipeline stage                     */
 428 /**********************************************************************/
 429
 430
 431 /* TCL render.
 432  */
 433 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 434                                         struct tnl_pipeline_stage *stage )
 435 {
 436    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 437    TNLcontext *tnl = TNL_CONTEXT(ctx);
 438    struct vertex_buffer *VB = &tnl->vb;
 439    GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
 440    GLuint i;
 441
 442    /* TODO: separate this from the swtnl pipeline
 443     */
 444    if (rmesa->radeon.TclFallback)
 445       return GL_TRUE;   /* fallback to software t&l */
 446
 447    if (VB->Count == 0)
 448       return GL_FALSE;
 449
 450    /* NOTE: inputs != tnl->render_inputs - these are the untransformed
 451     * inputs.
 452     */
 453    if (ctx->Light.Enabled) {
 454       inputs |= VERT_BIT_NORMAL;
 455    }
 456
 457    if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
 458       inputs |= VERT_BIT_COLOR1;
 459    }
 460
 461    if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
 462       inputs |= VERT_BIT_FOG;
 463    }
 464
 465    for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
 466       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 467       /* TODO: probably should not emit texture coords when texgen is enabled */
 468          if (rmesa->TexGenNeedNormals[i]) {
 469             inputs |= VERT_BIT_NORMAL;
 470          }
 471          inputs |= VERT_BIT_TEX(i);
 472       }
 473    }
 474
 475    radeonReleaseArrays( ctx, ~0 );
 476    GLuint emit_end = radeonEnsureEmitSize( ctx, inputs )
 477      + rmesa->radeon.cmdbuf.cs->cdw;
 478    radeonEmitArrays( ctx, inputs );
 479
 480    rmesa->tcl.Elts = VB->Elts;
 481
 482    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 483    {
 484       GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
 485       GLuint start = VB->Primitive[i].start;
 486       GLuint length = VB->Primitive[i].count;
 487
 488       if (!length)
 489          continue;
 490
 491       if (rmesa->tcl.Elts)
 492          radeonEmitEltPrimitive( ctx, start, start+length, prim );
 493       else
 494          radeonEmitPrimitive( ctx, start, start+length, prim );
 495    }
 496
 497    if (emit_end < rmesa->radeon.cmdbuf.cs->cdw)
 498       WARN_ONCE("Rendering was %d commands larger than predicted size."
 499           " We might overflow  command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end);
 500
 501    return GL_FALSE;             /* finished the pipe */
 502 }
 503
 504
 505
 506 /* Initial state for tcl stage.
 507  */
 508 const struct tnl_pipeline_stage _radeon_tcl_stage =
 509 {
 510    "radeon render",
 511    NULL,
 512    NULL,
 513    NULL,
 514    NULL,
 515    radeon_run_tcl_render        /* run */
 516 };
 517
 518
 519
 520 /**********************************************************************/
 521 /*                 Validate state at pipeline start                   */
 522 /**********************************************************************/
 523
 524
 525 /*-----------------------------------------------------------------------
 526  * Manage TCL fallbacks
 527  */
 528
 529
 530 static void transition_to_swtnl( GLcontext *ctx )
 531 {
 532    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 533    TNLcontext *tnl = TNL_CONTEXT(ctx);
 534    GLuint se_cntl;
 535
 536    RADEON_NEWPRIM( rmesa );
 537    rmesa->swtcl.vertex_format = 0;
 538
 539    radeonChooseVertexState( ctx );
 540    radeonChooseRenderState( ctx );
 541
 542    _mesa_validate_all_lighting_tables( ctx );
 543
 544    tnl->Driver.NotifyMaterialChange =
 545       _mesa_validate_all_lighting_tables;
 546
 547    radeonReleaseArrays( ctx, ~0 );
 548
 549    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 550    se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 551
 552    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 553       RADEON_STATECHANGE( rmesa, set );
 554       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 555    }
 556 }
 557
 558
 559 static void transition_to_hwtnl( GLcontext *ctx )
 560 {
 561    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 562    TNLcontext *tnl = TNL_CONTEXT(ctx);
 563    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 564
 565    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 566                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 567                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 568    se_coord_fmt |= RADEON_VTX_W0_IS_NOT_1_OVER_W0;
 569
 570    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 571       RADEON_STATECHANGE( rmesa, set );
 572       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 573       _tnl_need_projected_coords( ctx, GL_FALSE );
 574    }
 575
 576    radeonUpdateMaterial( ctx );
 577
 578    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 579
 580    if ( rmesa->radeon.dma.flush )
 581       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 582
 583    rmesa->radeon.dma.flush = NULL;
 584    rmesa->swtcl.vertex_format = 0;
 585
 586    //   if (rmesa->swtcl.indexed_verts.buf)
 587    //      radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 588    //                         __FUNCTION__ );
 589
 590    if (RADEON_DEBUG & RADEON_FALLBACKS)
 591       fprintf(stderr, "Radeon end tcl fallback\n");
 592 }
 593
 594 static char *fallbackStrings[] = {
 595    "Rasterization fallback",
 596    "Unfilled triangles",
 597    "Twosided lighting, differing materials",
 598    "Materials in VB (maybe between begin/end)",
 599    "Texgen unit 0",
 600    "Texgen unit 1",
 601    "Texgen unit 2",
 602    "User disable",
 603    "Fogcoord with separate specular lighting"
 604 };
 605
 606
 607 static char *getFallbackString(GLuint bit)
 608 {
 609    int i = 0;
 610    while (bit > 1) {
 611       i++;
 612       bit >>= 1;
 613    }
 614    return fallbackStrings[i];
 615 }
 616
 617
 618
 619 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 620 {
 621    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 622    GLuint oldfallback = rmesa->radeon.TclFallback;
 623
 624    if (mode) {
 625       rmesa->radeon.TclFallback |= bit;
 626       if (oldfallback == 0) {
 627          if (RADEON_DEBUG & RADEON_FALLBACKS)
 628             fprintf(stderr, "Radeon begin tcl fallback %s\n",
 629                     getFallbackString( bit ));
 630          transition_to_swtnl( ctx );
 631       }
 632    }
 633    else {
 634       rmesa->radeon.TclFallback &= ~bit;
 635       if (oldfallback == bit) {
 636          if (RADEON_DEBUG & RADEON_FALLBACKS)
 637             fprintf(stderr, "Radeon end tcl fallback %s\n",
 638                     getFallbackString( bit ));
 639          transition_to_hwtnl( ctx );
 640       }
 641    }
 642 }