2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
3 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Gareth Hughes <gareth@valinux.com>
31 * Brian Paul <brianp@valinux.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/colormac.h"
37 #include "main/context.h"
38 #include "main/enums.h"
39 #include "main/image.h"
40 #include "main/simple_list.h"
41 #include "main/texstore.h"
42 #include "main/teximage.h"
43 #include "main/texobj.h"
45 #include "radeon_context.h"
46 #include "radeon_mipmap_tree.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_swtcl.h"
50 #include "radeon_tex.h"
57 * Set the texture wrap modes.
59 * \param t Texture object whose wrap modes are to be set
60 * \param swrap Wrap mode for the \a s texture coordinate
61 * \param twrap Wrap mode for the \a t texture coordinate
64 static void radeonSetTexWrap( radeonTexObjPtr t
, GLenum swrap
, GLenum twrap
)
66 GLboolean is_clamp
= GL_FALSE
;
67 GLboolean is_clamp_to_border
= GL_FALSE
;
69 t
->pp_txfilter
&= ~(RADEON_CLAMP_S_MASK
| RADEON_CLAMP_T_MASK
| RADEON_BORDER_MODE_D3D
);
73 t
->pp_txfilter
|= RADEON_CLAMP_S_WRAP
;
76 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_GL
;
79 case GL_CLAMP_TO_EDGE
:
80 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_LAST
;
82 case GL_CLAMP_TO_BORDER
:
83 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_GL
;
84 is_clamp_to_border
= GL_TRUE
;
86 case GL_MIRRORED_REPEAT
:
87 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR
;
89 case GL_MIRROR_CLAMP_EXT
:
90 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_GL
;
93 case GL_MIRROR_CLAMP_TO_EDGE_EXT
:
94 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_LAST
;
96 case GL_MIRROR_CLAMP_TO_BORDER_EXT
:
97 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_GL
;
98 is_clamp_to_border
= GL_TRUE
;
101 _mesa_problem(NULL
, "bad S wrap mode in %s", __FUNCTION__
);
106 t
->pp_txfilter
|= RADEON_CLAMP_T_WRAP
;
109 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_GL
;
112 case GL_CLAMP_TO_EDGE
:
113 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_LAST
;
115 case GL_CLAMP_TO_BORDER
:
116 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_GL
;
117 is_clamp_to_border
= GL_TRUE
;
119 case GL_MIRRORED_REPEAT
:
120 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR
;
122 case GL_MIRROR_CLAMP_EXT
:
123 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_GL
;
126 case GL_MIRROR_CLAMP_TO_EDGE_EXT
:
127 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_LAST
;
129 case GL_MIRROR_CLAMP_TO_BORDER_EXT
:
130 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_GL
;
131 is_clamp_to_border
= GL_TRUE
;
134 _mesa_problem(NULL
, "bad T wrap mode in %s", __FUNCTION__
);
137 if ( is_clamp_to_border
) {
138 t
->pp_txfilter
|= RADEON_BORDER_MODE_D3D
;
141 t
->border_fallback
= (is_clamp
&& is_clamp_to_border
);
144 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t
, GLfloat max
)
146 t
->pp_txfilter
&= ~RADEON_MAX_ANISO_MASK
;
149 t
->pp_txfilter
|= RADEON_MAX_ANISO_1_TO_1
;
150 } else if ( max
<= 2.0 ) {
151 t
->pp_txfilter
|= RADEON_MAX_ANISO_2_TO_1
;
152 } else if ( max
<= 4.0 ) {
153 t
->pp_txfilter
|= RADEON_MAX_ANISO_4_TO_1
;
154 } else if ( max
<= 8.0 ) {
155 t
->pp_txfilter
|= RADEON_MAX_ANISO_8_TO_1
;
157 t
->pp_txfilter
|= RADEON_MAX_ANISO_16_TO_1
;
162 * Set the texture magnification and minification modes.
164 * \param t Texture whose filter modes are to be set
165 * \param minf Texture minification mode
166 * \param magf Texture magnification mode
169 static void radeonSetTexFilter( radeonTexObjPtr t
, GLenum minf
, GLenum magf
)
171 GLuint anisotropy
= (t
->pp_txfilter
& RADEON_MAX_ANISO_MASK
);
173 /* Force revalidation to account for switches from/to mipmapping. */
174 t
->validated
= GL_FALSE
;
176 t
->pp_txfilter
&= ~(RADEON_MIN_FILTER_MASK
| RADEON_MAG_FILTER_MASK
);
178 /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
179 if ( t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
182 case GL_NEAREST_MIPMAP_NEAREST
:
183 case GL_NEAREST_MIPMAP_LINEAR
:
184 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST
;
187 case GL_LINEAR_MIPMAP_NEAREST
:
188 case GL_LINEAR_MIPMAP_LINEAR
:
189 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR
;
195 else if ( anisotropy
== RADEON_MAX_ANISO_1_TO_1
) {
198 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST
;
201 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR
;
203 case GL_NEAREST_MIPMAP_NEAREST
:
204 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST
;
206 case GL_NEAREST_MIPMAP_LINEAR
:
207 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST
;
209 case GL_LINEAR_MIPMAP_NEAREST
:
210 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR
;
212 case GL_LINEAR_MIPMAP_LINEAR
:
213 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR
;
219 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST
;
222 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_LINEAR
;
224 case GL_NEAREST_MIPMAP_NEAREST
:
225 case GL_LINEAR_MIPMAP_NEAREST
:
226 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST
;
228 case GL_NEAREST_MIPMAP_LINEAR
:
229 case GL_LINEAR_MIPMAP_LINEAR
:
230 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR
;
237 t
->pp_txfilter
|= RADEON_MAG_FILTER_NEAREST
;
240 t
->pp_txfilter
|= RADEON_MAG_FILTER_LINEAR
;
245 static void radeonSetTexBorderColor( radeonTexObjPtr t
, const GLfloat color
[4] )
248 CLAMPED_FLOAT_TO_UBYTE(c
[0], color
[0]);
249 CLAMPED_FLOAT_TO_UBYTE(c
[1], color
[1]);
250 CLAMPED_FLOAT_TO_UBYTE(c
[2], color
[2]);
251 CLAMPED_FLOAT_TO_UBYTE(c
[3], color
[3]);
252 t
->pp_border_color
= radeonPackColor( 4, c
[0], c
[1], c
[2], c
[3] );
255 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
256 (((GLuint)((255.0F / scale) * (x))) / 2)
258 static void radeonTexEnv( GLcontext
*ctx
, GLenum target
,
259 GLenum pname
, const GLfloat
*param
)
261 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
262 GLuint unit
= ctx
->Texture
.CurrentUnit
;
263 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
265 if ( RADEON_DEBUG
& RADEON_STATE
) {
266 fprintf( stderr
, "%s( %s )\n",
267 __FUNCTION__
, _mesa_lookup_enum_by_nr( pname
) );
271 case GL_TEXTURE_ENV_COLOR
: {
274 UNCLAMPED_FLOAT_TO_RGBA_CHAN( c
, texUnit
->EnvColor
);
275 envColor
= radeonPackColor( 4, c
[0], c
[1], c
[2], c
[3] );
276 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TFACTOR
] != envColor
) {
277 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
278 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TFACTOR
] = envColor
;
283 case GL_TEXTURE_LOD_BIAS_EXT
: {
287 /* The Radeon's LOD bias is a signed 2's complement value with a
288 * range of -1.0 <= bias < 4.0. We break this into two linear
289 * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
290 * [0.0,4.0] to [0,127].
292 min
= driQueryOptionb (&rmesa
->radeon
.optionCache
, "no_neg_lod_bias") ?
294 bias
= CLAMP( *param
, min
, 4.0 );
297 } else if ( bias
> 0 ) {
298 b
= ((GLuint
)SCALED_FLOAT_TO_BYTE( bias
, 4.0 )) << RADEON_LOD_BIAS_SHIFT
;
300 b
= ((GLuint
)SCALED_FLOAT_TO_BYTE( bias
, 1.0 )) << RADEON_LOD_BIAS_SHIFT
;
302 if ( (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] & RADEON_LOD_BIAS_MASK
) != b
) {
303 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
304 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] &= ~RADEON_LOD_BIAS_MASK
;
305 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] |= (b
& RADEON_LOD_BIAS_MASK
);
317 * Changes variables and flags for a state update, which will happen at the
318 * next UpdateTextureState
321 static void radeonTexParameter( GLcontext
*ctx
, GLenum target
,
322 struct gl_texture_object
*texObj
,
323 GLenum pname
, const GLfloat
*params
)
325 radeonTexObj
* t
= radeon_tex_obj(texObj
);
327 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
, "%s( %s )\n", __FUNCTION__
,
328 _mesa_lookup_enum_by_nr( pname
) );
331 case GL_TEXTURE_MIN_FILTER
:
332 case GL_TEXTURE_MAG_FILTER
:
333 case GL_TEXTURE_MAX_ANISOTROPY_EXT
:
334 radeonSetTexMaxAnisotropy( t
, texObj
->MaxAnisotropy
);
335 radeonSetTexFilter( t
, texObj
->MinFilter
, texObj
->MagFilter
);
338 case GL_TEXTURE_WRAP_S
:
339 case GL_TEXTURE_WRAP_T
:
340 radeonSetTexWrap( t
, texObj
->WrapS
, texObj
->WrapT
);
343 case GL_TEXTURE_BORDER_COLOR
:
344 radeonSetTexBorderColor( t
, texObj
->BorderColor
);
347 case GL_TEXTURE_BASE_LEVEL
:
348 case GL_TEXTURE_MAX_LEVEL
:
349 case GL_TEXTURE_MIN_LOD
:
350 case GL_TEXTURE_MAX_LOD
:
352 /* This isn't the most efficient solution but there doesn't appear to
353 * be a nice alternative. Since there's no LOD clamping,
354 * we just have to rely on loading the right subset of mipmap levels
355 * to simulate a clamped LOD.
358 radeon_miptree_unreference(t
->mt
);
360 t
->validated
= GL_FALSE
;
369 static void radeonDeleteTexture( GLcontext
*ctx
,
370 struct gl_texture_object
*texObj
)
372 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
373 radeonTexObj
* t
= radeon_tex_obj(texObj
);
376 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
377 "%s( %p (target = %s) )\n", __FUNCTION__
, (void *)texObj
,
378 _mesa_lookup_enum_by_nr( texObj
->Target
) );
381 radeon_firevertices(&rmesa
->radeon
);
382 for ( i
= 0 ; i
< rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
; i
++ ) {
383 if ( t
== rmesa
->state
.texture
.unit
[i
].texobj
) {
384 rmesa
->state
.texture
.unit
[i
].texobj
= NULL
;
385 rmesa
->hw
.tex
[i
].dirty
= GL_FALSE
;
386 rmesa
->hw
.cube
[i
].dirty
= GL_FALSE
;
392 radeon_miptree_unreference(t
->mt
);
395 /* Free mipmap images and the texture object itself */
396 _mesa_delete_texture_object(ctx
, texObj
);
400 * - Same GEN_MODE for all active bits
401 * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
402 * - STRQ presumably all supported (matrix means incoming R values
403 * can end up in STQ, this has implications for vertex support,
404 * presumably ok if maos is used, though?)
406 * Basically impossible to do this on the fly - just collect some
407 * basic info & do the checks from ValidateState().
409 static void radeonTexGen( GLcontext
*ctx
,
412 const GLfloat
*params
)
414 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
415 GLuint unit
= ctx
->Texture
.CurrentUnit
;
416 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
420 * Allocate a new texture object.
421 * Called via ctx->Driver.NewTextureObject.
422 * Note: we could use containment here to 'derive' the driver-specific
423 * texture object from the core mesa gl_texture_object. Not done at this time.
425 static struct gl_texture_object
*
426 radeonNewTextureObject( GLcontext
*ctx
, GLuint name
, GLenum target
)
428 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
429 radeonTexObj
* t
= CALLOC_STRUCT(radeon_tex_obj
);
431 _mesa_initialize_texture_object(&t
->base
, name
, target
);
432 t
->base
.MaxAnisotropy
= rmesa
->radeon
.initialMaxAnisotropy
;
434 t
->border_fallback
= GL_FALSE
;
436 t
->pp_txfilter
= RADEON_BORDER_MODE_OGL
;
437 t
->pp_txformat
= (RADEON_TXFORMAT_ENDIAN_NO_SWAP
|
438 RADEON_TXFORMAT_PERSPECTIVE_ENABLE
);
440 radeonSetTexWrap( t
, t
->base
.WrapS
, t
->base
.WrapT
);
441 radeonSetTexMaxAnisotropy( t
, t
->base
.MaxAnisotropy
);
442 radeonSetTexFilter( t
, t
->base
.MinFilter
, t
->base
.MagFilter
);
443 radeonSetTexBorderColor( t
, t
->base
.BorderColor
);
449 void radeonInitTextureFuncs( struct dd_function_table
*functions
)
451 functions
->ChooseTextureFormat
= radeonChooseTextureFormat_mesa
;
452 functions
->TexImage1D
= radeonTexImage1D
;
453 functions
->TexImage2D
= radeonTexImage2D
;
454 functions
->TexSubImage1D
= radeonTexSubImage1D
;
455 functions
->TexSubImage2D
= radeonTexSubImage2D
;
456 functions
->GetTexImage
= radeonGetTexImage
;
457 functions
->GetCompressedTexImage
= radeonGetCompressedTexImage
;
459 functions
->NewTextureObject
= radeonNewTextureObject
;
460 // functions->BindTexture = radeonBindTexture;
461 functions
->DeleteTexture
= radeonDeleteTexture
;
463 functions
->TexEnv
= radeonTexEnv
;
464 functions
->TexParameter
= radeonTexParameter
;
465 functions
->TexGen
= radeonTexGen
;
467 functions
->CompressedTexImage2D
= radeonCompressedTexImage2D
;
468 functions
->CompressedTexSubImage2D
= radeonCompressedTexSubImage2D
;
470 functions
->GenerateMipmap
= radeonGenerateMipmap
;
472 functions
->NewTextureImage
= radeonNewTextureImage
;
473 functions
->FreeTexImageData
= radeonFreeTexImageData
;
474 functions
->MapTexture
= radeonMapTexture
;
475 functions
->UnmapTexture
= radeonUnmapTexture
;
477 driInitTextureFormats();