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[mesa.git] / src / mesa / drivers / dri / radeon / radeon_texstate.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/texformat.h"
42 #include "main/teximage.h"
43 #include "main/texobj.h"
44 #include "main/enums.h"
45
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
52 #include "radeon_tcl.h"
53
54
55 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
56 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
57 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
58 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
59 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
60 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
61 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
62 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
63 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
64
65 #define _COLOR(f) \
66 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
67 #define _COLOR_REV(f) \
68 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
69 #define _ALPHA(f) \
70 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
71 #define _ALPHA_REV(f) \
72 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
73 #define _YUV(f) \
74 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
75 #define _INVALID(f) \
76 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
77 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
78 && (tx_table[f].format != 0xffffffff) )
79
80 struct tx_table {
81 GLuint format, filter;
82 };
83
84 static const struct tx_table tx_table[] =
85 {
86 _ALPHA(RGBA8888),
87 _ALPHA_REV(RGBA8888),
88 _ALPHA(ARGB8888),
89 _ALPHA_REV(ARGB8888),
90 [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 },
91 _COLOR(RGB565),
92 _COLOR_REV(RGB565),
93 _ALPHA(ARGB4444),
94 _ALPHA_REV(ARGB4444),
95 _ALPHA(ARGB1555),
96 _ALPHA_REV(ARGB1555),
97 _ALPHA(AL88),
98 _ALPHA_REV(AL88),
99 _ALPHA(A8),
100 _COLOR(L8),
101 _ALPHA(I8),
102 _INVALID(CI8),
103 _YUV(YCBCR),
104 _YUV(YCBCR_REV),
105 _INVALID(RGB_FXT1),
106 _INVALID(RGBA_FXT1),
107 _COLOR(RGB_DXT1),
108 _ALPHA(RGBA_DXT1),
109 _ALPHA(RGBA_DXT3),
110 _ALPHA(RGBA_DXT5),
111 };
112
113 #undef _COLOR
114 #undef _ALPHA
115 #undef _INVALID
116
117 /* ================================================================
118 * Texture combine functions
119 */
120
121 /* GL_ARB_texture_env_combine support
122 */
123
124 /* The color tables have combine functions for GL_SRC_COLOR,
125 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
126 */
127 static GLuint radeon_texture_color[][RADEON_MAX_TEXTURE_UNITS] =
128 {
129 {
130 RADEON_COLOR_ARG_A_T0_COLOR,
131 RADEON_COLOR_ARG_A_T1_COLOR,
132 RADEON_COLOR_ARG_A_T2_COLOR
133 },
134 {
135 RADEON_COLOR_ARG_A_T0_COLOR | RADEON_COMP_ARG_A,
136 RADEON_COLOR_ARG_A_T1_COLOR | RADEON_COMP_ARG_A,
137 RADEON_COLOR_ARG_A_T2_COLOR | RADEON_COMP_ARG_A
138 },
139 {
140 RADEON_COLOR_ARG_A_T0_ALPHA,
141 RADEON_COLOR_ARG_A_T1_ALPHA,
142 RADEON_COLOR_ARG_A_T2_ALPHA
143 },
144 {
145 RADEON_COLOR_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
146 RADEON_COLOR_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
147 RADEON_COLOR_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
148 },
149 };
150
151 static GLuint radeon_tfactor_color[] =
152 {
153 RADEON_COLOR_ARG_A_TFACTOR_COLOR,
154 RADEON_COLOR_ARG_A_TFACTOR_COLOR | RADEON_COMP_ARG_A,
155 RADEON_COLOR_ARG_A_TFACTOR_ALPHA,
156 RADEON_COLOR_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
157 };
158
159 static GLuint radeon_primary_color[] =
160 {
161 RADEON_COLOR_ARG_A_DIFFUSE_COLOR,
162 RADEON_COLOR_ARG_A_DIFFUSE_COLOR | RADEON_COMP_ARG_A,
163 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA,
164 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
165 };
166
167 static GLuint radeon_previous_color[] =
168 {
169 RADEON_COLOR_ARG_A_CURRENT_COLOR,
170 RADEON_COLOR_ARG_A_CURRENT_COLOR | RADEON_COMP_ARG_A,
171 RADEON_COLOR_ARG_A_CURRENT_ALPHA,
172 RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
173 };
174
175 /* GL_ZERO table - indices 0-3
176 * GL_ONE table - indices 1-4
177 */
178 static GLuint radeon_zero_color[] =
179 {
180 RADEON_COLOR_ARG_A_ZERO,
181 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
182 RADEON_COLOR_ARG_A_ZERO,
183 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
184 RADEON_COLOR_ARG_A_ZERO
185 };
186
187
188 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
189 */
190 static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] =
191 {
192 {
193 RADEON_ALPHA_ARG_A_T0_ALPHA,
194 RADEON_ALPHA_ARG_A_T1_ALPHA,
195 RADEON_ALPHA_ARG_A_T2_ALPHA
196 },
197 {
198 RADEON_ALPHA_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
199 RADEON_ALPHA_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
200 RADEON_ALPHA_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
201 },
202 };
203
204 static GLuint radeon_tfactor_alpha[] =
205 {
206 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA,
207 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
208 };
209
210 static GLuint radeon_primary_alpha[] =
211 {
212 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA,
213 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
214 };
215
216 static GLuint radeon_previous_alpha[] =
217 {
218 RADEON_ALPHA_ARG_A_CURRENT_ALPHA,
219 RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
220 };
221
222 /* GL_ZERO table - indices 0-1
223 * GL_ONE table - indices 1-2
224 */
225 static GLuint radeon_zero_alpha[] =
226 {
227 RADEON_ALPHA_ARG_A_ZERO,
228 RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A,
229 RADEON_ALPHA_ARG_A_ZERO
230 };
231
232
233 /* Extract the arg from slot A, shift it into the correct argument slot
234 * and set the corresponding complement bit.
235 */
236 #define RADEON_COLOR_ARG( n, arg ) \
237 do { \
238 color_combine |= \
239 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
240 << RADEON_COLOR_ARG_##arg##_SHIFT); \
241 color_combine |= \
242 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
243 << RADEON_COMP_ARG_##arg##_SHIFT); \
244 } while (0)
245
246 #define RADEON_ALPHA_ARG( n, arg ) \
247 do { \
248 alpha_combine |= \
249 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
250 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
251 alpha_combine |= \
252 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
253 << RADEON_COMP_ARG_##arg##_SHIFT); \
254 } while (0)
255
256
257 /* ================================================================
258 * Texture unit state management
259 */
260
261 static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
262 {
263 r100ContextPtr rmesa = R100_CONTEXT(ctx);
264 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
265 GLuint color_combine, alpha_combine;
266 const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO
267 | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD
268 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
269 const GLuint alpha_combine0 = RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO
270 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | RADEON_BLEND_CTL_ADD
271 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
272
273
274 /* texUnit->_Current can be NULL if and only if the texture unit is
275 * not actually enabled.
276 */
277 assert( (texUnit->_ReallyEnabled == 0)
278 || (texUnit->_Current != NULL) );
279
280 if ( RADEON_DEBUG & RADEON_TEXTURE ) {
281 fprintf( stderr, "%s( %p, %d )\n", __FUNCTION__, (void *)ctx, unit );
282 }
283
284 /* Set the texture environment state. Isn't this nice and clean?
285 * The chip will automagically set the texture alpha to 0xff when
286 * the texture format does not include an alpha component. This
287 * reduces the amount of special-casing we have to do, alpha-only
288 * textures being a notable exception. Doesn't work for luminance
289 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
290 */
291 /* Don't cache these results.
292 */
293 rmesa->state.texture.unit[unit].format = 0;
294 rmesa->state.texture.unit[unit].envMode = 0;
295
296 if ( !texUnit->_ReallyEnabled ) {
297 color_combine = color_combine0;
298 alpha_combine = alpha_combine0;
299 }
300 else {
301 GLuint color_arg[3], alpha_arg[3];
302 GLuint i;
303 const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB;
304 const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA;
305 GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB;
306 GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA;
307
308
309 /* Step 1:
310 * Extract the color and alpha combine function arguments.
311 */
312 for ( i = 0 ; i < numColorArgs ; i++ ) {
313 const GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR;
314 const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i];
315 assert(op >= 0);
316 assert(op <= 3);
317 switch ( srcRGBi ) {
318 case GL_TEXTURE:
319 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_ALPHA)
320 color_arg[i] = radeon_zero_color[op];
321 else
322 color_arg[i] = radeon_texture_color[op][unit];
323 break;
324 case GL_CONSTANT:
325 color_arg[i] = radeon_tfactor_color[op];
326 break;
327 case GL_PRIMARY_COLOR:
328 color_arg[i] = radeon_primary_color[op];
329 break;
330 case GL_PREVIOUS:
331 color_arg[i] = radeon_previous_color[op];
332 break;
333 case GL_ZERO:
334 color_arg[i] = radeon_zero_color[op];
335 break;
336 case GL_ONE:
337 color_arg[i] = radeon_zero_color[op+1];
338 break;
339 case GL_TEXTURE0:
340 case GL_TEXTURE1:
341 case GL_TEXTURE2: {
342 GLuint txunit = srcRGBi - GL_TEXTURE0;
343 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_ALPHA)
344 color_arg[i] = radeon_zero_color[op];
345 else
346 /* implement ogl 1.4/1.5 core spec here, not specification of
347 * GL_ARB_texture_env_crossbar (which would require disabling blending
348 * instead of undefined results when referencing not enabled texunit) */
349 color_arg[i] = radeon_texture_color[op][txunit];
350 }
351 break;
352 default:
353 return GL_FALSE;
354 }
355 }
356
357 for ( i = 0 ; i < numAlphaArgs ; i++ ) {
358 const GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA;
359 const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i];
360 assert(op >= 0);
361 assert(op <= 1);
362 switch ( srcAi ) {
363 case GL_TEXTURE:
364 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_LUMINANCE)
365 alpha_arg[i] = radeon_zero_alpha[op+1];
366 else
367 alpha_arg[i] = radeon_texture_alpha[op][unit];
368 break;
369 case GL_CONSTANT:
370 alpha_arg[i] = radeon_tfactor_alpha[op];
371 break;
372 case GL_PRIMARY_COLOR:
373 alpha_arg[i] = radeon_primary_alpha[op];
374 break;
375 case GL_PREVIOUS:
376 alpha_arg[i] = radeon_previous_alpha[op];
377 break;
378 case GL_ZERO:
379 alpha_arg[i] = radeon_zero_alpha[op];
380 break;
381 case GL_ONE:
382 alpha_arg[i] = radeon_zero_alpha[op+1];
383 break;
384 case GL_TEXTURE0:
385 case GL_TEXTURE1:
386 case GL_TEXTURE2: {
387 GLuint txunit = srcAi - GL_TEXTURE0;
388 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_LUMINANCE)
389 alpha_arg[i] = radeon_zero_alpha[op+1];
390 else
391 alpha_arg[i] = radeon_texture_alpha[op][txunit];
392 }
393 break;
394 default:
395 return GL_FALSE;
396 }
397 }
398
399 /* Step 2:
400 * Build up the color and alpha combine functions.
401 */
402 switch ( texUnit->_CurrentCombine->ModeRGB ) {
403 case GL_REPLACE:
404 color_combine = (RADEON_COLOR_ARG_A_ZERO |
405 RADEON_COLOR_ARG_B_ZERO |
406 RADEON_BLEND_CTL_ADD |
407 RADEON_CLAMP_TX);
408 RADEON_COLOR_ARG( 0, C );
409 break;
410 case GL_MODULATE:
411 color_combine = (RADEON_COLOR_ARG_C_ZERO |
412 RADEON_BLEND_CTL_ADD |
413 RADEON_CLAMP_TX);
414 RADEON_COLOR_ARG( 0, A );
415 RADEON_COLOR_ARG( 1, B );
416 break;
417 case GL_ADD:
418 color_combine = (RADEON_COLOR_ARG_B_ZERO |
419 RADEON_COMP_ARG_B |
420 RADEON_BLEND_CTL_ADD |
421 RADEON_CLAMP_TX);
422 RADEON_COLOR_ARG( 0, A );
423 RADEON_COLOR_ARG( 1, C );
424 break;
425 case GL_ADD_SIGNED:
426 color_combine = (RADEON_COLOR_ARG_B_ZERO |
427 RADEON_COMP_ARG_B |
428 RADEON_BLEND_CTL_ADDSIGNED |
429 RADEON_CLAMP_TX);
430 RADEON_COLOR_ARG( 0, A );
431 RADEON_COLOR_ARG( 1, C );
432 break;
433 case GL_SUBTRACT:
434 color_combine = (RADEON_COLOR_ARG_B_ZERO |
435 RADEON_COMP_ARG_B |
436 RADEON_BLEND_CTL_SUBTRACT |
437 RADEON_CLAMP_TX);
438 RADEON_COLOR_ARG( 0, A );
439 RADEON_COLOR_ARG( 1, C );
440 break;
441 case GL_INTERPOLATE:
442 color_combine = (RADEON_BLEND_CTL_BLEND |
443 RADEON_CLAMP_TX);
444 RADEON_COLOR_ARG( 0, B );
445 RADEON_COLOR_ARG( 1, A );
446 RADEON_COLOR_ARG( 2, C );
447 break;
448
449 case GL_DOT3_RGB_EXT:
450 case GL_DOT3_RGBA_EXT:
451 /* The EXT version of the DOT3 extension does not support the
452 * scale factor, but the ARB version (and the version in OpenGL
453 * 1.3) does.
454 */
455 RGBshift = 0;
456 /* FALLTHROUGH */
457
458 case GL_DOT3_RGB:
459 case GL_DOT3_RGBA:
460 /* The R100 / RV200 only support a 1X multiplier in hardware
461 * w/the ARB version.
462 */
463 if ( RGBshift != (RADEON_SCALE_1X >> RADEON_SCALE_SHIFT) ) {
464 return GL_FALSE;
465 }
466
467 RGBshift += 2;
468 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT)
469 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) {
470 /* is it necessary to set this or will it be ignored anyway? */
471 Ashift = RGBshift;
472 }
473
474 color_combine = (RADEON_COLOR_ARG_C_ZERO |
475 RADEON_BLEND_CTL_DOT3 |
476 RADEON_CLAMP_TX);
477 RADEON_COLOR_ARG( 0, A );
478 RADEON_COLOR_ARG( 1, B );
479 break;
480
481 case GL_MODULATE_ADD_ATI:
482 color_combine = (RADEON_BLEND_CTL_ADD |
483 RADEON_CLAMP_TX);
484 RADEON_COLOR_ARG( 0, A );
485 RADEON_COLOR_ARG( 1, C );
486 RADEON_COLOR_ARG( 2, B );
487 break;
488 case GL_MODULATE_SIGNED_ADD_ATI:
489 color_combine = (RADEON_BLEND_CTL_ADDSIGNED |
490 RADEON_CLAMP_TX);
491 RADEON_COLOR_ARG( 0, A );
492 RADEON_COLOR_ARG( 1, C );
493 RADEON_COLOR_ARG( 2, B );
494 break;
495 case GL_MODULATE_SUBTRACT_ATI:
496 color_combine = (RADEON_BLEND_CTL_SUBTRACT |
497 RADEON_CLAMP_TX);
498 RADEON_COLOR_ARG( 0, A );
499 RADEON_COLOR_ARG( 1, C );
500 RADEON_COLOR_ARG( 2, B );
501 break;
502 default:
503 return GL_FALSE;
504 }
505
506 switch ( texUnit->_CurrentCombine->ModeA ) {
507 case GL_REPLACE:
508 alpha_combine = (RADEON_ALPHA_ARG_A_ZERO |
509 RADEON_ALPHA_ARG_B_ZERO |
510 RADEON_BLEND_CTL_ADD |
511 RADEON_CLAMP_TX);
512 RADEON_ALPHA_ARG( 0, C );
513 break;
514 case GL_MODULATE:
515 alpha_combine = (RADEON_ALPHA_ARG_C_ZERO |
516 RADEON_BLEND_CTL_ADD |
517 RADEON_CLAMP_TX);
518 RADEON_ALPHA_ARG( 0, A );
519 RADEON_ALPHA_ARG( 1, B );
520 break;
521 case GL_ADD:
522 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
523 RADEON_COMP_ARG_B |
524 RADEON_BLEND_CTL_ADD |
525 RADEON_CLAMP_TX);
526 RADEON_ALPHA_ARG( 0, A );
527 RADEON_ALPHA_ARG( 1, C );
528 break;
529 case GL_ADD_SIGNED:
530 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
531 RADEON_COMP_ARG_B |
532 RADEON_BLEND_CTL_ADDSIGNED |
533 RADEON_CLAMP_TX);
534 RADEON_ALPHA_ARG( 0, A );
535 RADEON_ALPHA_ARG( 1, C );
536 break;
537 case GL_SUBTRACT:
538 alpha_combine = (RADEON_COLOR_ARG_B_ZERO |
539 RADEON_COMP_ARG_B |
540 RADEON_BLEND_CTL_SUBTRACT |
541 RADEON_CLAMP_TX);
542 RADEON_ALPHA_ARG( 0, A );
543 RADEON_ALPHA_ARG( 1, C );
544 break;
545 case GL_INTERPOLATE:
546 alpha_combine = (RADEON_BLEND_CTL_BLEND |
547 RADEON_CLAMP_TX);
548 RADEON_ALPHA_ARG( 0, B );
549 RADEON_ALPHA_ARG( 1, A );
550 RADEON_ALPHA_ARG( 2, C );
551 break;
552
553 case GL_MODULATE_ADD_ATI:
554 alpha_combine = (RADEON_BLEND_CTL_ADD |
555 RADEON_CLAMP_TX);
556 RADEON_ALPHA_ARG( 0, A );
557 RADEON_ALPHA_ARG( 1, C );
558 RADEON_ALPHA_ARG( 2, B );
559 break;
560 case GL_MODULATE_SIGNED_ADD_ATI:
561 alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED |
562 RADEON_CLAMP_TX);
563 RADEON_ALPHA_ARG( 0, A );
564 RADEON_ALPHA_ARG( 1, C );
565 RADEON_ALPHA_ARG( 2, B );
566 break;
567 case GL_MODULATE_SUBTRACT_ATI:
568 alpha_combine = (RADEON_BLEND_CTL_SUBTRACT |
569 RADEON_CLAMP_TX);
570 RADEON_ALPHA_ARG( 0, A );
571 RADEON_ALPHA_ARG( 1, C );
572 RADEON_ALPHA_ARG( 2, B );
573 break;
574 default:
575 return GL_FALSE;
576 }
577
578 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB_EXT)
579 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB) ) {
580 alpha_combine |= RADEON_DOT_ALPHA_DONT_REPLICATE;
581 }
582
583 /* Step 3:
584 * Apply the scale factor.
585 */
586 color_combine |= (RGBshift << RADEON_SCALE_SHIFT);
587 alpha_combine |= (Ashift << RADEON_SCALE_SHIFT);
588
589 /* All done!
590 */
591 }
592
593 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
594 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
595 RADEON_STATECHANGE( rmesa, tex[unit] );
596 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
597 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
598 }
599
600 return GL_TRUE;
601 }
602
603 void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
604 unsigned long long offset, GLint depth, GLuint pitch)
605 {
606 r100ContextPtr rmesa = pDRICtx->driverPrivate;
607 struct gl_texture_object *tObj =
608 _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
609 radeonTexObjPtr t = radeon_tex_obj(tObj);
610
611 if (tObj == NULL)
612 return;
613
614 t->image_override = GL_TRUE;
615
616 if (!offset)
617 return;
618
619 t->bo = NULL;
620 t->override_offset = offset;
621 t->pp_txpitch = pitch - 32;
622
623 switch (depth) {
624 case 32:
625 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
626 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
627 break;
628 case 24:
629 default:
630 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
631 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
632 break;
633 case 16:
634 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
635 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
636 break;
637 }
638 }
639
640 void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format,
641 __DRIdrawable *dPriv)
642 {
643 struct gl_texture_unit *texUnit;
644 struct gl_texture_object *texObj;
645 struct gl_texture_image *texImage;
646 struct radeon_renderbuffer *rb;
647 radeon_texture_image *rImage;
648 radeonContextPtr radeon;
649 r100ContextPtr rmesa;
650 struct radeon_framebuffer *rfb;
651 radeonTexObjPtr t;
652 uint32_t pitch_val;
653 uint32_t internalFormat, type, format;
654
655 type = GL_BGRA;
656 format = GL_UNSIGNED_BYTE;
657 internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4);
658
659 radeon = pDRICtx->driverPrivate;
660 rmesa = pDRICtx->driverPrivate;
661
662 rfb = dPriv->driverPrivate;
663 texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
664 texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
665 texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
666
667 rImage = get_radeon_texture_image(texImage);
668 t = radeon_tex_obj(texObj);
669 if (t == NULL) {
670 return;
671 }
672
673 radeon_update_renderbuffers(pDRICtx, dPriv);
674 /* back & depth buffer are useless free them right away */
675 rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
676 if (rb && rb->bo) {
677 radeon_bo_unref(rb->bo);
678 rb->bo = NULL;
679 }
680 rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
681 if (rb && rb->bo) {
682 radeon_bo_unref(rb->bo);
683 rb->bo = NULL;
684 }
685 rb = rfb->color_rb[0];
686 if (rb->bo == NULL) {
687 /* Failed to BO for the buffer */
688 return;
689 }
690
691 _mesa_lock_texture(radeon->glCtx, texObj);
692 if (t->bo) {
693 radeon_bo_unref(t->bo);
694 t->bo = NULL;
695 }
696 if (rImage->bo) {
697 radeon_bo_unref(rImage->bo);
698 rImage->bo = NULL;
699 }
700 if (t->mt) {
701 radeon_miptree_unreference(t->mt);
702 t->mt = NULL;
703 }
704 if (rImage->mt) {
705 radeon_miptree_unreference(rImage->mt);
706 rImage->mt = NULL;
707 }
708 _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
709 rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
710 texImage->RowStride = rb->pitch / rb->cpp;
711 texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
712 internalFormat,
713 type, format, 0);
714 rImage->bo = rb->bo;
715 radeon_bo_ref(rImage->bo);
716 t->bo = rb->bo;
717 radeon_bo_ref(t->bo);
718 t->tile_bits = 0;
719 t->image_override = GL_TRUE;
720 t->override_offset = 0;
721 t->pp_txpitch &= (1 << 13) -1;
722 pitch_val = rb->pitch;
723 switch (rb->cpp) {
724 case 4:
725 if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT)
726 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
727 else
728 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
729 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
730 break;
731 case 3:
732 default:
733 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
734 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
735 break;
736 case 2:
737 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
738 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
739 break;
740 }
741 t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
742 | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
743 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
744 t->pp_txpitch = pitch_val;
745 t->pp_txpitch -= 32;
746
747 t->validated = GL_TRUE;
748 _mesa_unlock_texture(radeon->glCtx, texObj);
749 return;
750 }
751
752
753 void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
754 {
755 radeonSetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
756 }
757
758
759 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
760 RADEON_MIN_FILTER_MASK | \
761 RADEON_MAG_FILTER_MASK | \
762 RADEON_MAX_ANISO_MASK | \
763 RADEON_YUV_TO_RGB | \
764 RADEON_YUV_TEMPERATURE_MASK | \
765 RADEON_CLAMP_S_MASK | \
766 RADEON_CLAMP_T_MASK | \
767 RADEON_BORDER_MODE_D3D )
768
769 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
770 RADEON_TXFORMAT_HEIGHT_MASK | \
771 RADEON_TXFORMAT_FORMAT_MASK | \
772 RADEON_TXFORMAT_F5_WIDTH_MASK | \
773 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
774 RADEON_TXFORMAT_ALPHA_IN_MAP | \
775 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
776 RADEON_TXFORMAT_NON_POWER2)
777
778
779 static void disable_tex_obj_state( r100ContextPtr rmesa,
780 int unit )
781 {
782 RADEON_STATECHANGE( rmesa, tex[unit] );
783
784 RADEON_STATECHANGE( rmesa, tcl );
785 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
786 RADEON_Q_BIT(unit));
787
788 if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
789 TCL_FALLBACK( rmesa->radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
790 rmesa->recheck_texgen[unit] = GL_TRUE;
791 }
792
793 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) {
794 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
795 cubic_map bit on unit 2 when the unit is disabled, otherwise every
796 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
797 units, better be safe than sorry though).*/
798 RADEON_STATECHANGE( rmesa, tex[unit] );
799 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE;
800 }
801
802 {
803 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
804 GLuint tmp = rmesa->TexGenEnabled;
805
806 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit);
807 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit);
808 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
809 rmesa->TexGenNeedNormals[unit] = 0;
810 rmesa->TexGenEnabled |=
811 (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
812
813 if (tmp != rmesa->TexGenEnabled) {
814 rmesa->recheck_texgen[unit] = GL_TRUE;
815 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
816 }
817 }
818 }
819
820 static void import_tex_obj_state( r100ContextPtr rmesa,
821 int unit,
822 radeonTexObjPtr texobj )
823 {
824 /* do not use RADEON_DB_STATE to avoid stale texture caches */
825 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
826 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
827
828 RADEON_STATECHANGE( rmesa, tex[unit] );
829
830 cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK;
831 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
832 cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
833 cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
834 cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
835
836 if (texobj->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
837 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0];
838 txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
839 txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
840 RADEON_STATECHANGE( rmesa, txr[unit] );
841 }
842
843 if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
844 se_coord_fmt |= RADEON_VTX_ST0_NONPARAMETRIC << unit;
845 }
846 else {
847 se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit);
848
849 if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) {
850 uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
851
852 RADEON_STATECHANGE( rmesa, cube[unit] );
853 cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
854 /* state filled out in the cube_emit */
855 }
856 }
857
858 if (se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT]) {
859 RADEON_STATECHANGE( rmesa, set );
860 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
861 }
862
863 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
864 }
865
866
867 static void set_texgen_matrix( r100ContextPtr rmesa,
868 GLuint unit,
869 const GLfloat *s_plane,
870 const GLfloat *t_plane,
871 const GLfloat *r_plane,
872 const GLfloat *q_plane )
873 {
874 rmesa->TexGenMatrix[unit].m[0] = s_plane[0];
875 rmesa->TexGenMatrix[unit].m[4] = s_plane[1];
876 rmesa->TexGenMatrix[unit].m[8] = s_plane[2];
877 rmesa->TexGenMatrix[unit].m[12] = s_plane[3];
878
879 rmesa->TexGenMatrix[unit].m[1] = t_plane[0];
880 rmesa->TexGenMatrix[unit].m[5] = t_plane[1];
881 rmesa->TexGenMatrix[unit].m[9] = t_plane[2];
882 rmesa->TexGenMatrix[unit].m[13] = t_plane[3];
883
884 rmesa->TexGenMatrix[unit].m[2] = r_plane[0];
885 rmesa->TexGenMatrix[unit].m[6] = r_plane[1];
886 rmesa->TexGenMatrix[unit].m[10] = r_plane[2];
887 rmesa->TexGenMatrix[unit].m[14] = r_plane[3];
888
889 rmesa->TexGenMatrix[unit].m[3] = q_plane[0];
890 rmesa->TexGenMatrix[unit].m[7] = q_plane[1];
891 rmesa->TexGenMatrix[unit].m[11] = q_plane[2];
892 rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
893
894 rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
895 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
896 }
897
898 /* Returns GL_FALSE if fallback required.
899 */
900 static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
901 {
902 r100ContextPtr rmesa = R100_CONTEXT(ctx);
903 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
904 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
905 GLuint tmp = rmesa->TexGenEnabled;
906 static const GLfloat reflect[16] = {
907 -1, 0, 0, 0,
908 0, -1, 0, 0,
909 0, 0, -1, 0,
910 0, 0, 0, 1 };
911
912 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE << unit);
913 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE << unit);
914 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK << inputshift);
915 rmesa->TexGenNeedNormals[unit] = 0;
916
917 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) {
918 /* Disabled, no fallback:
919 */
920 rmesa->TexGenEnabled |=
921 (RADEON_TEXGEN_INPUT_TEXCOORD_0 + unit) << inputshift;
922 return GL_TRUE;
923 }
924 /* the r100 cannot do texgen for some coords and not for others
925 * we do not detect such cases (certainly can't do it here) and just
926 * ASSUME that when S and T are texgen enabled we do not need other
927 * non-texgen enabled coords, no matter if the R and Q bits are texgen
928 * enabled. Still check for mixed mode texgen for all coords.
929 */
930 else if ( (texUnit->TexGenEnabled & S_BIT) &&
931 (texUnit->TexGenEnabled & T_BIT) &&
932 (texUnit->GenS.Mode == texUnit->GenT.Mode) ) {
933 if ( ((texUnit->TexGenEnabled & R_BIT) &&
934 (texUnit->GenS.Mode != texUnit->GenR.Mode)) ||
935 ((texUnit->TexGenEnabled & Q_BIT) &&
936 (texUnit->GenS.Mode != texUnit->GenQ.Mode)) ) {
937 /* Mixed modes, fallback:
938 */
939 if (RADEON_DEBUG & RADEON_FALLBACKS)
940 fprintf(stderr, "fallback mixed texgen\n");
941 return GL_FALSE;
942 }
943 rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
944 }
945 else {
946 /* some texgen mode not including both S and T bits */
947 if (RADEON_DEBUG & RADEON_FALLBACKS)
948 fprintf(stderr, "fallback mixed texgen/nontexgen\n");
949 return GL_FALSE;
950 }
951
952 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) {
953 /* need this here for vtxfmt presumably. Argh we need to set
954 this from way too many places, would be much easier if we could leave
955 tcl q coord always enabled as on r200) */
956 RADEON_STATECHANGE( rmesa, tcl );
957 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit);
958 }
959
960 switch (texUnit->GenS.Mode) {
961 case GL_OBJECT_LINEAR:
962 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift;
963 set_texgen_matrix( rmesa, unit,
964 texUnit->GenS.ObjectPlane,
965 texUnit->GenT.ObjectPlane,
966 texUnit->GenR.ObjectPlane,
967 texUnit->GenQ.ObjectPlane);
968 break;
969
970 case GL_EYE_LINEAR:
971 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift;
972 set_texgen_matrix( rmesa, unit,
973 texUnit->GenS.EyePlane,
974 texUnit->GenT.EyePlane,
975 texUnit->GenR.EyePlane,
976 texUnit->GenQ.EyePlane);
977 break;
978
979 case GL_REFLECTION_MAP_NV:
980 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
981 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT << inputshift;
982 /* TODO: unknown if this is needed/correct */
983 set_texgen_matrix( rmesa, unit, reflect, reflect + 4,
984 reflect + 8, reflect + 12 );
985 break;
986
987 case GL_NORMAL_MAP_NV:
988 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
989 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL << inputshift;
990 break;
991
992 case GL_SPHERE_MAP:
993 /* the mode which everyone uses :-( */
994 default:
995 /* Unsupported mode, fallback:
996 */
997 if (RADEON_DEBUG & RADEON_FALLBACKS)
998 fprintf(stderr, "fallback GL_SPHERE_MAP\n");
999 return GL_FALSE;
1000 }
1001
1002 if (tmp != rmesa->TexGenEnabled) {
1003 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
1004 }
1005
1006 return GL_TRUE;
1007 }
1008
1009 /**
1010 * Compute the cached hardware register values for the given texture object.
1011 *
1012 * \param rmesa Context pointer
1013 * \param t the r300 texture object
1014 */
1015 static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int unit)
1016 {
1017 const struct gl_texture_image *firstImage;
1018 GLint log2Width, log2Height, log2Depth, texelBytes;
1019
1020 if ( t->bo ) {
1021 return GL_TRUE;
1022 }
1023
1024 firstImage = t->base.Image[0][t->mt->firstLevel];
1025
1026 if (firstImage->Border > 0) {
1027 fprintf(stderr, "%s: border\n", __FUNCTION__);
1028 return GL_FALSE;
1029 }
1030
1031 log2Width = firstImage->WidthLog2;
1032 log2Height = firstImage->HeightLog2;
1033 log2Depth = firstImage->DepthLog2;
1034 texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat);
1035
1036 if (!t->image_override) {
1037 if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) {
1038 const struct tx_table *table = tx_table;
1039
1040 t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
1041 RADEON_TXFORMAT_ALPHA_IN_MAP);
1042 t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
1043
1044 t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format;
1045 t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter;
1046 } else {
1047 _mesa_problem(NULL, "unexpected texture format in %s",
1048 __FUNCTION__);
1049 return GL_FALSE;
1050 }
1051 }
1052
1053 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
1054 t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << RADEON_MAX_MIP_LEVEL_SHIFT;
1055
1056 t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
1057 RADEON_TXFORMAT_HEIGHT_MASK |
1058 RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
1059 RADEON_TXFORMAT_F5_WIDTH_MASK |
1060 RADEON_TXFORMAT_F5_HEIGHT_MASK);
1061 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
1062 (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
1063
1064 t->tile_bits = 0;
1065
1066 if (t->base.Target == GL_TEXTURE_CUBE_MAP) {
1067 ASSERT(log2Width == log2Height);
1068 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) |
1069 (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) |
1070 /* don't think we need this bit, if it exists at all - fglrx does not set it */
1071 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE));
1072 t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) |
1073 (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) |
1074 (log2Width << RADEON_FACE_WIDTH_2_SHIFT) |
1075 (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) |
1076 (log2Width << RADEON_FACE_WIDTH_3_SHIFT) |
1077 (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) |
1078 (log2Width << RADEON_FACE_WIDTH_4_SHIFT) |
1079 (log2Height << RADEON_FACE_HEIGHT_4_SHIFT));
1080 }
1081
1082 t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT)
1083 | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT));
1084
1085 if ( !t->image_override ) {
1086 if (firstImage->IsCompressed)
1087 t->pp_txpitch = (firstImage->Width + 63) & ~(63);
1088 else
1089 t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63);
1090 t->pp_txpitch -= 32;
1091 }
1092
1093 if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
1094 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
1095 }
1096
1097 return GL_TRUE;
1098 }
1099
1100 static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit)
1101 {
1102 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1103 radeonTexObj *t = radeon_tex_obj(texObj);
1104 int ret;
1105
1106 if (!radeon_validate_texture_miptree(ctx, texObj))
1107 return GL_FALSE;
1108
1109 ret = setup_hardware_state(rmesa, t, unit);
1110 if (ret == GL_FALSE)
1111 return GL_FALSE;
1112
1113 /* yuv conversion only works in first unit */
1114 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB))
1115 return GL_FALSE;
1116
1117 RADEON_STATECHANGE( rmesa, ctx );
1118 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
1119 (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
1120 RADEON_STATECHANGE( rmesa, tcl );
1121 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
1122
1123 rmesa->recheck_texgen[unit] = GL_TRUE;
1124
1125 import_tex_obj_state( rmesa, unit, t );
1126
1127 if (rmesa->recheck_texgen[unit]) {
1128 GLboolean fallback = !radeon_validate_texgen( ctx, unit );
1129 TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
1130 rmesa->recheck_texgen[unit] = 0;
1131 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
1132 }
1133
1134 if ( ! radeonUpdateTextureEnv( ctx, unit ) ) {
1135 return GL_FALSE;
1136 }
1137 FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback );
1138
1139 t->validated = GL_TRUE;
1140 return !t->border_fallback;
1141 }
1142
1143 static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
1144 {
1145 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1146
1147 if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) {
1148 rmesa->state.texture.unit[unit].texobj = NULL;
1149 return GL_FALSE;
1150 }
1151
1152 if (!ctx->Texture.Unit[unit]._ReallyEnabled) {
1153 /* disable the unit */
1154 disable_tex_obj_state(rmesa, unit);
1155 rmesa->state.texture.unit[unit].texobj = NULL;
1156 return GL_TRUE;
1157 }
1158
1159 if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) {
1160 _mesa_warning(ctx,
1161 "failed to validate texture for unit %d.\n",
1162 unit);
1163 rmesa->state.texture.unit[unit].texobj = NULL;
1164 return GL_FALSE;
1165 }
1166 rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
1167 return GL_TRUE;
1168 }
1169
1170 void radeonUpdateTextureState( GLcontext *ctx )
1171 {
1172 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1173 GLboolean ok;
1174
1175 /* set the ctx all textures off */
1176 RADEON_STATECHANGE( rmesa, ctx );
1177 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK));
1178
1179 ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
1180 radeonUpdateTextureUnit( ctx, 1 ) &&
1181 radeonUpdateTextureUnit( ctx, 2 ));
1182
1183 FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
1184
1185 if (rmesa->radeon.TclFallback)
1186 radeonChooseVertexState( ctx );
1187 }