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drivers: don't include texformat.h
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_texstate.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/teximage.h"
42 #include "main/texobj.h"
43 #include "main/enums.h"
44
45 #include "radeon_context.h"
46 #include "radeon_mipmap_tree.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_swtcl.h"
50 #include "radeon_tex.h"
51 #include "radeon_tcl.h"
52
53
54 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
55 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
56 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
57 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
58 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
59 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
60 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
61 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
62 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
63
64 #define _COLOR(f) \
65 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
66 #define _COLOR_REV(f) \
67 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
68 #define _ALPHA(f) \
69 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
70 #define _ALPHA_REV(f) \
71 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
72 #define _YUV(f) \
73 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
74 #define _INVALID(f) \
75 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
76 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
77 && (tx_table[f].format != 0xffffffff) )
78
79 struct tx_table {
80 GLuint format, filter;
81 };
82
83 /* XXX verify this table against MESA_FORMAT_x values */
84 static const struct tx_table tx_table[] =
85 {
86 _INVALID(NONE), /* MESA_FORMAT_NONE */
87 _ALPHA(RGBA8888),
88 _ALPHA_REV(RGBA8888),
89 _ALPHA(ARGB8888),
90 _ALPHA_REV(ARGB8888),
91 [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 },
92 _COLOR(RGB565),
93 _COLOR_REV(RGB565),
94 _ALPHA(ARGB4444),
95 _ALPHA_REV(ARGB4444),
96 _ALPHA(ARGB1555),
97 _ALPHA_REV(ARGB1555),
98 _ALPHA(AL88),
99 _ALPHA_REV(AL88),
100 _ALPHA(A8),
101 _COLOR(L8),
102 _ALPHA(I8),
103 _INVALID(CI8),
104 _YUV(YCBCR),
105 _YUV(YCBCR_REV),
106 _INVALID(RGB_FXT1),
107 _INVALID(RGBA_FXT1),
108 _COLOR(RGB_DXT1),
109 _ALPHA(RGBA_DXT1),
110 _ALPHA(RGBA_DXT3),
111 _ALPHA(RGBA_DXT5),
112 };
113
114 #undef _COLOR
115 #undef _ALPHA
116 #undef _INVALID
117
118 /* ================================================================
119 * Texture combine functions
120 */
121
122 /* GL_ARB_texture_env_combine support
123 */
124
125 /* The color tables have combine functions for GL_SRC_COLOR,
126 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
127 */
128 static GLuint radeon_texture_color[][RADEON_MAX_TEXTURE_UNITS] =
129 {
130 {
131 RADEON_COLOR_ARG_A_T0_COLOR,
132 RADEON_COLOR_ARG_A_T1_COLOR,
133 RADEON_COLOR_ARG_A_T2_COLOR
134 },
135 {
136 RADEON_COLOR_ARG_A_T0_COLOR | RADEON_COMP_ARG_A,
137 RADEON_COLOR_ARG_A_T1_COLOR | RADEON_COMP_ARG_A,
138 RADEON_COLOR_ARG_A_T2_COLOR | RADEON_COMP_ARG_A
139 },
140 {
141 RADEON_COLOR_ARG_A_T0_ALPHA,
142 RADEON_COLOR_ARG_A_T1_ALPHA,
143 RADEON_COLOR_ARG_A_T2_ALPHA
144 },
145 {
146 RADEON_COLOR_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
147 RADEON_COLOR_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
148 RADEON_COLOR_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
149 },
150 };
151
152 static GLuint radeon_tfactor_color[] =
153 {
154 RADEON_COLOR_ARG_A_TFACTOR_COLOR,
155 RADEON_COLOR_ARG_A_TFACTOR_COLOR | RADEON_COMP_ARG_A,
156 RADEON_COLOR_ARG_A_TFACTOR_ALPHA,
157 RADEON_COLOR_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
158 };
159
160 static GLuint radeon_primary_color[] =
161 {
162 RADEON_COLOR_ARG_A_DIFFUSE_COLOR,
163 RADEON_COLOR_ARG_A_DIFFUSE_COLOR | RADEON_COMP_ARG_A,
164 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA,
165 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
166 };
167
168 static GLuint radeon_previous_color[] =
169 {
170 RADEON_COLOR_ARG_A_CURRENT_COLOR,
171 RADEON_COLOR_ARG_A_CURRENT_COLOR | RADEON_COMP_ARG_A,
172 RADEON_COLOR_ARG_A_CURRENT_ALPHA,
173 RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
174 };
175
176 /* GL_ZERO table - indices 0-3
177 * GL_ONE table - indices 1-4
178 */
179 static GLuint radeon_zero_color[] =
180 {
181 RADEON_COLOR_ARG_A_ZERO,
182 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
183 RADEON_COLOR_ARG_A_ZERO,
184 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
185 RADEON_COLOR_ARG_A_ZERO
186 };
187
188
189 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
190 */
191 static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] =
192 {
193 {
194 RADEON_ALPHA_ARG_A_T0_ALPHA,
195 RADEON_ALPHA_ARG_A_T1_ALPHA,
196 RADEON_ALPHA_ARG_A_T2_ALPHA
197 },
198 {
199 RADEON_ALPHA_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
200 RADEON_ALPHA_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
201 RADEON_ALPHA_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
202 },
203 };
204
205 static GLuint radeon_tfactor_alpha[] =
206 {
207 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA,
208 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
209 };
210
211 static GLuint radeon_primary_alpha[] =
212 {
213 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA,
214 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
215 };
216
217 static GLuint radeon_previous_alpha[] =
218 {
219 RADEON_ALPHA_ARG_A_CURRENT_ALPHA,
220 RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
221 };
222
223 /* GL_ZERO table - indices 0-1
224 * GL_ONE table - indices 1-2
225 */
226 static GLuint radeon_zero_alpha[] =
227 {
228 RADEON_ALPHA_ARG_A_ZERO,
229 RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A,
230 RADEON_ALPHA_ARG_A_ZERO
231 };
232
233
234 /* Extract the arg from slot A, shift it into the correct argument slot
235 * and set the corresponding complement bit.
236 */
237 #define RADEON_COLOR_ARG( n, arg ) \
238 do { \
239 color_combine |= \
240 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
241 << RADEON_COLOR_ARG_##arg##_SHIFT); \
242 color_combine |= \
243 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
244 << RADEON_COMP_ARG_##arg##_SHIFT); \
245 } while (0)
246
247 #define RADEON_ALPHA_ARG( n, arg ) \
248 do { \
249 alpha_combine |= \
250 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
251 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
252 alpha_combine |= \
253 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
254 << RADEON_COMP_ARG_##arg##_SHIFT); \
255 } while (0)
256
257
258 /* ================================================================
259 * Texture unit state management
260 */
261
262 static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
263 {
264 r100ContextPtr rmesa = R100_CONTEXT(ctx);
265 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
266 GLuint color_combine, alpha_combine;
267 const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO
268 | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD
269 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
270 const GLuint alpha_combine0 = RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO
271 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | RADEON_BLEND_CTL_ADD
272 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
273
274
275 /* texUnit->_Current can be NULL if and only if the texture unit is
276 * not actually enabled.
277 */
278 assert( (texUnit->_ReallyEnabled == 0)
279 || (texUnit->_Current != NULL) );
280
281 if ( RADEON_DEBUG & RADEON_TEXTURE ) {
282 fprintf( stderr, "%s( %p, %d )\n", __FUNCTION__, (void *)ctx, unit );
283 }
284
285 /* Set the texture environment state. Isn't this nice and clean?
286 * The chip will automagically set the texture alpha to 0xff when
287 * the texture format does not include an alpha component. This
288 * reduces the amount of special-casing we have to do, alpha-only
289 * textures being a notable exception. Doesn't work for luminance
290 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
291 */
292 /* Don't cache these results.
293 */
294 rmesa->state.texture.unit[unit].format = 0;
295 rmesa->state.texture.unit[unit].envMode = 0;
296
297 if ( !texUnit->_ReallyEnabled ) {
298 color_combine = color_combine0;
299 alpha_combine = alpha_combine0;
300 }
301 else {
302 GLuint color_arg[3], alpha_arg[3];
303 GLuint i;
304 const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB;
305 const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA;
306 GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB;
307 GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA;
308
309
310 /* Step 1:
311 * Extract the color and alpha combine function arguments.
312 */
313 for ( i = 0 ; i < numColorArgs ; i++ ) {
314 const GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR;
315 const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i];
316 assert(op >= 0);
317 assert(op <= 3);
318 switch ( srcRGBi ) {
319 case GL_TEXTURE:
320 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_ALPHA)
321 color_arg[i] = radeon_zero_color[op];
322 else
323 color_arg[i] = radeon_texture_color[op][unit];
324 break;
325 case GL_CONSTANT:
326 color_arg[i] = radeon_tfactor_color[op];
327 break;
328 case GL_PRIMARY_COLOR:
329 color_arg[i] = radeon_primary_color[op];
330 break;
331 case GL_PREVIOUS:
332 color_arg[i] = radeon_previous_color[op];
333 break;
334 case GL_ZERO:
335 color_arg[i] = radeon_zero_color[op];
336 break;
337 case GL_ONE:
338 color_arg[i] = radeon_zero_color[op+1];
339 break;
340 case GL_TEXTURE0:
341 case GL_TEXTURE1:
342 case GL_TEXTURE2: {
343 GLuint txunit = srcRGBi - GL_TEXTURE0;
344 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_ALPHA)
345 color_arg[i] = radeon_zero_color[op];
346 else
347 /* implement ogl 1.4/1.5 core spec here, not specification of
348 * GL_ARB_texture_env_crossbar (which would require disabling blending
349 * instead of undefined results when referencing not enabled texunit) */
350 color_arg[i] = radeon_texture_color[op][txunit];
351 }
352 break;
353 default:
354 return GL_FALSE;
355 }
356 }
357
358 for ( i = 0 ; i < numAlphaArgs ; i++ ) {
359 const GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA;
360 const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i];
361 assert(op >= 0);
362 assert(op <= 1);
363 switch ( srcAi ) {
364 case GL_TEXTURE:
365 if (texUnit->_Current->Image[0][0]->_BaseFormat == GL_LUMINANCE)
366 alpha_arg[i] = radeon_zero_alpha[op+1];
367 else
368 alpha_arg[i] = radeon_texture_alpha[op][unit];
369 break;
370 case GL_CONSTANT:
371 alpha_arg[i] = radeon_tfactor_alpha[op];
372 break;
373 case GL_PRIMARY_COLOR:
374 alpha_arg[i] = radeon_primary_alpha[op];
375 break;
376 case GL_PREVIOUS:
377 alpha_arg[i] = radeon_previous_alpha[op];
378 break;
379 case GL_ZERO:
380 alpha_arg[i] = radeon_zero_alpha[op];
381 break;
382 case GL_ONE:
383 alpha_arg[i] = radeon_zero_alpha[op+1];
384 break;
385 case GL_TEXTURE0:
386 case GL_TEXTURE1:
387 case GL_TEXTURE2: {
388 GLuint txunit = srcAi - GL_TEXTURE0;
389 if (ctx->Texture.Unit[txunit]._Current->Image[0][0]->_BaseFormat == GL_LUMINANCE)
390 alpha_arg[i] = radeon_zero_alpha[op+1];
391 else
392 alpha_arg[i] = radeon_texture_alpha[op][txunit];
393 }
394 break;
395 default:
396 return GL_FALSE;
397 }
398 }
399
400 /* Step 2:
401 * Build up the color and alpha combine functions.
402 */
403 switch ( texUnit->_CurrentCombine->ModeRGB ) {
404 case GL_REPLACE:
405 color_combine = (RADEON_COLOR_ARG_A_ZERO |
406 RADEON_COLOR_ARG_B_ZERO |
407 RADEON_BLEND_CTL_ADD |
408 RADEON_CLAMP_TX);
409 RADEON_COLOR_ARG( 0, C );
410 break;
411 case GL_MODULATE:
412 color_combine = (RADEON_COLOR_ARG_C_ZERO |
413 RADEON_BLEND_CTL_ADD |
414 RADEON_CLAMP_TX);
415 RADEON_COLOR_ARG( 0, A );
416 RADEON_COLOR_ARG( 1, B );
417 break;
418 case GL_ADD:
419 color_combine = (RADEON_COLOR_ARG_B_ZERO |
420 RADEON_COMP_ARG_B |
421 RADEON_BLEND_CTL_ADD |
422 RADEON_CLAMP_TX);
423 RADEON_COLOR_ARG( 0, A );
424 RADEON_COLOR_ARG( 1, C );
425 break;
426 case GL_ADD_SIGNED:
427 color_combine = (RADEON_COLOR_ARG_B_ZERO |
428 RADEON_COMP_ARG_B |
429 RADEON_BLEND_CTL_ADDSIGNED |
430 RADEON_CLAMP_TX);
431 RADEON_COLOR_ARG( 0, A );
432 RADEON_COLOR_ARG( 1, C );
433 break;
434 case GL_SUBTRACT:
435 color_combine = (RADEON_COLOR_ARG_B_ZERO |
436 RADEON_COMP_ARG_B |
437 RADEON_BLEND_CTL_SUBTRACT |
438 RADEON_CLAMP_TX);
439 RADEON_COLOR_ARG( 0, A );
440 RADEON_COLOR_ARG( 1, C );
441 break;
442 case GL_INTERPOLATE:
443 color_combine = (RADEON_BLEND_CTL_BLEND |
444 RADEON_CLAMP_TX);
445 RADEON_COLOR_ARG( 0, B );
446 RADEON_COLOR_ARG( 1, A );
447 RADEON_COLOR_ARG( 2, C );
448 break;
449
450 case GL_DOT3_RGB_EXT:
451 case GL_DOT3_RGBA_EXT:
452 /* The EXT version of the DOT3 extension does not support the
453 * scale factor, but the ARB version (and the version in OpenGL
454 * 1.3) does.
455 */
456 RGBshift = 0;
457 /* FALLTHROUGH */
458
459 case GL_DOT3_RGB:
460 case GL_DOT3_RGBA:
461 /* The R100 / RV200 only support a 1X multiplier in hardware
462 * w/the ARB version.
463 */
464 if ( RGBshift != (RADEON_SCALE_1X >> RADEON_SCALE_SHIFT) ) {
465 return GL_FALSE;
466 }
467
468 RGBshift += 2;
469 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT)
470 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) {
471 /* is it necessary to set this or will it be ignored anyway? */
472 Ashift = RGBshift;
473 }
474
475 color_combine = (RADEON_COLOR_ARG_C_ZERO |
476 RADEON_BLEND_CTL_DOT3 |
477 RADEON_CLAMP_TX);
478 RADEON_COLOR_ARG( 0, A );
479 RADEON_COLOR_ARG( 1, B );
480 break;
481
482 case GL_MODULATE_ADD_ATI:
483 color_combine = (RADEON_BLEND_CTL_ADD |
484 RADEON_CLAMP_TX);
485 RADEON_COLOR_ARG( 0, A );
486 RADEON_COLOR_ARG( 1, C );
487 RADEON_COLOR_ARG( 2, B );
488 break;
489 case GL_MODULATE_SIGNED_ADD_ATI:
490 color_combine = (RADEON_BLEND_CTL_ADDSIGNED |
491 RADEON_CLAMP_TX);
492 RADEON_COLOR_ARG( 0, A );
493 RADEON_COLOR_ARG( 1, C );
494 RADEON_COLOR_ARG( 2, B );
495 break;
496 case GL_MODULATE_SUBTRACT_ATI:
497 color_combine = (RADEON_BLEND_CTL_SUBTRACT |
498 RADEON_CLAMP_TX);
499 RADEON_COLOR_ARG( 0, A );
500 RADEON_COLOR_ARG( 1, C );
501 RADEON_COLOR_ARG( 2, B );
502 break;
503 default:
504 return GL_FALSE;
505 }
506
507 switch ( texUnit->_CurrentCombine->ModeA ) {
508 case GL_REPLACE:
509 alpha_combine = (RADEON_ALPHA_ARG_A_ZERO |
510 RADEON_ALPHA_ARG_B_ZERO |
511 RADEON_BLEND_CTL_ADD |
512 RADEON_CLAMP_TX);
513 RADEON_ALPHA_ARG( 0, C );
514 break;
515 case GL_MODULATE:
516 alpha_combine = (RADEON_ALPHA_ARG_C_ZERO |
517 RADEON_BLEND_CTL_ADD |
518 RADEON_CLAMP_TX);
519 RADEON_ALPHA_ARG( 0, A );
520 RADEON_ALPHA_ARG( 1, B );
521 break;
522 case GL_ADD:
523 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
524 RADEON_COMP_ARG_B |
525 RADEON_BLEND_CTL_ADD |
526 RADEON_CLAMP_TX);
527 RADEON_ALPHA_ARG( 0, A );
528 RADEON_ALPHA_ARG( 1, C );
529 break;
530 case GL_ADD_SIGNED:
531 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
532 RADEON_COMP_ARG_B |
533 RADEON_BLEND_CTL_ADDSIGNED |
534 RADEON_CLAMP_TX);
535 RADEON_ALPHA_ARG( 0, A );
536 RADEON_ALPHA_ARG( 1, C );
537 break;
538 case GL_SUBTRACT:
539 alpha_combine = (RADEON_COLOR_ARG_B_ZERO |
540 RADEON_COMP_ARG_B |
541 RADEON_BLEND_CTL_SUBTRACT |
542 RADEON_CLAMP_TX);
543 RADEON_ALPHA_ARG( 0, A );
544 RADEON_ALPHA_ARG( 1, C );
545 break;
546 case GL_INTERPOLATE:
547 alpha_combine = (RADEON_BLEND_CTL_BLEND |
548 RADEON_CLAMP_TX);
549 RADEON_ALPHA_ARG( 0, B );
550 RADEON_ALPHA_ARG( 1, A );
551 RADEON_ALPHA_ARG( 2, C );
552 break;
553
554 case GL_MODULATE_ADD_ATI:
555 alpha_combine = (RADEON_BLEND_CTL_ADD |
556 RADEON_CLAMP_TX);
557 RADEON_ALPHA_ARG( 0, A );
558 RADEON_ALPHA_ARG( 1, C );
559 RADEON_ALPHA_ARG( 2, B );
560 break;
561 case GL_MODULATE_SIGNED_ADD_ATI:
562 alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED |
563 RADEON_CLAMP_TX);
564 RADEON_ALPHA_ARG( 0, A );
565 RADEON_ALPHA_ARG( 1, C );
566 RADEON_ALPHA_ARG( 2, B );
567 break;
568 case GL_MODULATE_SUBTRACT_ATI:
569 alpha_combine = (RADEON_BLEND_CTL_SUBTRACT |
570 RADEON_CLAMP_TX);
571 RADEON_ALPHA_ARG( 0, A );
572 RADEON_ALPHA_ARG( 1, C );
573 RADEON_ALPHA_ARG( 2, B );
574 break;
575 default:
576 return GL_FALSE;
577 }
578
579 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB_EXT)
580 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB) ) {
581 alpha_combine |= RADEON_DOT_ALPHA_DONT_REPLICATE;
582 }
583
584 /* Step 3:
585 * Apply the scale factor.
586 */
587 color_combine |= (RGBshift << RADEON_SCALE_SHIFT);
588 alpha_combine |= (Ashift << RADEON_SCALE_SHIFT);
589
590 /* All done!
591 */
592 }
593
594 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
595 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
596 RADEON_STATECHANGE( rmesa, tex[unit] );
597 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
598 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
599 }
600
601 return GL_TRUE;
602 }
603
604 void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
605 unsigned long long offset, GLint depth, GLuint pitch)
606 {
607 r100ContextPtr rmesa = pDRICtx->driverPrivate;
608 struct gl_texture_object *tObj =
609 _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
610 radeonTexObjPtr t = radeon_tex_obj(tObj);
611
612 if (tObj == NULL)
613 return;
614
615 t->image_override = GL_TRUE;
616
617 if (!offset)
618 return;
619
620 t->bo = NULL;
621 t->override_offset = offset;
622 t->pp_txpitch = pitch - 32;
623
624 switch (depth) {
625 case 32:
626 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
627 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
628 break;
629 case 24:
630 default:
631 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
632 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
633 break;
634 case 16:
635 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
636 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
637 break;
638 }
639 }
640
641 void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format,
642 __DRIdrawable *dPriv)
643 {
644 struct gl_texture_unit *texUnit;
645 struct gl_texture_object *texObj;
646 struct gl_texture_image *texImage;
647 struct radeon_renderbuffer *rb;
648 radeon_texture_image *rImage;
649 radeonContextPtr radeon;
650 r100ContextPtr rmesa;
651 struct radeon_framebuffer *rfb;
652 radeonTexObjPtr t;
653 uint32_t pitch_val;
654 uint32_t internalFormat, type, format;
655
656 type = GL_BGRA;
657 format = GL_UNSIGNED_BYTE;
658 internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4);
659
660 radeon = pDRICtx->driverPrivate;
661 rmesa = pDRICtx->driverPrivate;
662
663 rfb = dPriv->driverPrivate;
664 texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
665 texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
666 texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
667
668 rImage = get_radeon_texture_image(texImage);
669 t = radeon_tex_obj(texObj);
670 if (t == NULL) {
671 return;
672 }
673
674 radeon_update_renderbuffers(pDRICtx, dPriv);
675 /* back & depth buffer are useless free them right away */
676 rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
677 if (rb && rb->bo) {
678 radeon_bo_unref(rb->bo);
679 rb->bo = NULL;
680 }
681 rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
682 if (rb && rb->bo) {
683 radeon_bo_unref(rb->bo);
684 rb->bo = NULL;
685 }
686 rb = rfb->color_rb[0];
687 if (rb->bo == NULL) {
688 /* Failed to BO for the buffer */
689 return;
690 }
691
692 _mesa_lock_texture(radeon->glCtx, texObj);
693 if (t->bo) {
694 radeon_bo_unref(t->bo);
695 t->bo = NULL;
696 }
697 if (rImage->bo) {
698 radeon_bo_unref(rImage->bo);
699 rImage->bo = NULL;
700 }
701 if (t->mt) {
702 radeon_miptree_unreference(t->mt);
703 t->mt = NULL;
704 }
705 if (rImage->mt) {
706 radeon_miptree_unreference(rImage->mt);
707 rImage->mt = NULL;
708 }
709 _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
710 rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
711 texImage->RowStride = rb->pitch / rb->cpp;
712 texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
713 internalFormat,
714 type, format, 0);
715 rImage->bo = rb->bo;
716 radeon_bo_ref(rImage->bo);
717 t->bo = rb->bo;
718 radeon_bo_ref(t->bo);
719 t->tile_bits = 0;
720 t->image_override = GL_TRUE;
721 t->override_offset = 0;
722 t->pp_txpitch &= (1 << 13) -1;
723 pitch_val = rb->pitch;
724 switch (rb->cpp) {
725 case 4:
726 if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT)
727 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
728 else
729 t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
730 t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
731 break;
732 case 3:
733 default:
734 t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
735 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
736 break;
737 case 2:
738 t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
739 t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
740 break;
741 }
742 t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
743 | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
744 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
745 t->pp_txpitch = pitch_val;
746 t->pp_txpitch -= 32;
747
748 t->validated = GL_TRUE;
749 _mesa_unlock_texture(radeon->glCtx, texObj);
750 return;
751 }
752
753
754 void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
755 {
756 radeonSetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
757 }
758
759
760 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
761 RADEON_MIN_FILTER_MASK | \
762 RADEON_MAG_FILTER_MASK | \
763 RADEON_MAX_ANISO_MASK | \
764 RADEON_YUV_TO_RGB | \
765 RADEON_YUV_TEMPERATURE_MASK | \
766 RADEON_CLAMP_S_MASK | \
767 RADEON_CLAMP_T_MASK | \
768 RADEON_BORDER_MODE_D3D )
769
770 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
771 RADEON_TXFORMAT_HEIGHT_MASK | \
772 RADEON_TXFORMAT_FORMAT_MASK | \
773 RADEON_TXFORMAT_F5_WIDTH_MASK | \
774 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
775 RADEON_TXFORMAT_ALPHA_IN_MAP | \
776 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
777 RADEON_TXFORMAT_NON_POWER2)
778
779
780 static void disable_tex_obj_state( r100ContextPtr rmesa,
781 int unit )
782 {
783 RADEON_STATECHANGE( rmesa, tex[unit] );
784
785 RADEON_STATECHANGE( rmesa, tcl );
786 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
787 RADEON_Q_BIT(unit));
788
789 if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
790 TCL_FALLBACK( rmesa->radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
791 rmesa->recheck_texgen[unit] = GL_TRUE;
792 }
793
794 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) {
795 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
796 cubic_map bit on unit 2 when the unit is disabled, otherwise every
797 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
798 units, better be safe than sorry though).*/
799 RADEON_STATECHANGE( rmesa, tex[unit] );
800 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE;
801 }
802
803 {
804 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
805 GLuint tmp = rmesa->TexGenEnabled;
806
807 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit);
808 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit);
809 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
810 rmesa->TexGenNeedNormals[unit] = 0;
811 rmesa->TexGenEnabled |=
812 (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
813
814 if (tmp != rmesa->TexGenEnabled) {
815 rmesa->recheck_texgen[unit] = GL_TRUE;
816 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
817 }
818 }
819 }
820
821 static void import_tex_obj_state( r100ContextPtr rmesa,
822 int unit,
823 radeonTexObjPtr texobj )
824 {
825 /* do not use RADEON_DB_STATE to avoid stale texture caches */
826 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
827 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
828
829 RADEON_STATECHANGE( rmesa, tex[unit] );
830
831 cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK;
832 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
833 cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
834 cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
835 cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
836
837 if (texobj->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
838 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0];
839 txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
840 txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
841 RADEON_STATECHANGE( rmesa, txr[unit] );
842 }
843
844 if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
845 se_coord_fmt |= RADEON_VTX_ST0_NONPARAMETRIC << unit;
846 }
847 else {
848 se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit);
849
850 if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) {
851 uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
852
853 RADEON_STATECHANGE( rmesa, cube[unit] );
854 cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
855 /* state filled out in the cube_emit */
856 }
857 }
858
859 if (se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT]) {
860 RADEON_STATECHANGE( rmesa, set );
861 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
862 }
863
864 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
865 }
866
867
868 static void set_texgen_matrix( r100ContextPtr rmesa,
869 GLuint unit,
870 const GLfloat *s_plane,
871 const GLfloat *t_plane,
872 const GLfloat *r_plane,
873 const GLfloat *q_plane )
874 {
875 rmesa->TexGenMatrix[unit].m[0] = s_plane[0];
876 rmesa->TexGenMatrix[unit].m[4] = s_plane[1];
877 rmesa->TexGenMatrix[unit].m[8] = s_plane[2];
878 rmesa->TexGenMatrix[unit].m[12] = s_plane[3];
879
880 rmesa->TexGenMatrix[unit].m[1] = t_plane[0];
881 rmesa->TexGenMatrix[unit].m[5] = t_plane[1];
882 rmesa->TexGenMatrix[unit].m[9] = t_plane[2];
883 rmesa->TexGenMatrix[unit].m[13] = t_plane[3];
884
885 rmesa->TexGenMatrix[unit].m[2] = r_plane[0];
886 rmesa->TexGenMatrix[unit].m[6] = r_plane[1];
887 rmesa->TexGenMatrix[unit].m[10] = r_plane[2];
888 rmesa->TexGenMatrix[unit].m[14] = r_plane[3];
889
890 rmesa->TexGenMatrix[unit].m[3] = q_plane[0];
891 rmesa->TexGenMatrix[unit].m[7] = q_plane[1];
892 rmesa->TexGenMatrix[unit].m[11] = q_plane[2];
893 rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
894
895 rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
896 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
897 }
898
899 /* Returns GL_FALSE if fallback required.
900 */
901 static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
902 {
903 r100ContextPtr rmesa = R100_CONTEXT(ctx);
904 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
905 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
906 GLuint tmp = rmesa->TexGenEnabled;
907 static const GLfloat reflect[16] = {
908 -1, 0, 0, 0,
909 0, -1, 0, 0,
910 0, 0, -1, 0,
911 0, 0, 0, 1 };
912
913 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE << unit);
914 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE << unit);
915 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK << inputshift);
916 rmesa->TexGenNeedNormals[unit] = 0;
917
918 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) {
919 /* Disabled, no fallback:
920 */
921 rmesa->TexGenEnabled |=
922 (RADEON_TEXGEN_INPUT_TEXCOORD_0 + unit) << inputshift;
923 return GL_TRUE;
924 }
925 /* the r100 cannot do texgen for some coords and not for others
926 * we do not detect such cases (certainly can't do it here) and just
927 * ASSUME that when S and T are texgen enabled we do not need other
928 * non-texgen enabled coords, no matter if the R and Q bits are texgen
929 * enabled. Still check for mixed mode texgen for all coords.
930 */
931 else if ( (texUnit->TexGenEnabled & S_BIT) &&
932 (texUnit->TexGenEnabled & T_BIT) &&
933 (texUnit->GenS.Mode == texUnit->GenT.Mode) ) {
934 if ( ((texUnit->TexGenEnabled & R_BIT) &&
935 (texUnit->GenS.Mode != texUnit->GenR.Mode)) ||
936 ((texUnit->TexGenEnabled & Q_BIT) &&
937 (texUnit->GenS.Mode != texUnit->GenQ.Mode)) ) {
938 /* Mixed modes, fallback:
939 */
940 if (RADEON_DEBUG & RADEON_FALLBACKS)
941 fprintf(stderr, "fallback mixed texgen\n");
942 return GL_FALSE;
943 }
944 rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
945 }
946 else {
947 /* some texgen mode not including both S and T bits */
948 if (RADEON_DEBUG & RADEON_FALLBACKS)
949 fprintf(stderr, "fallback mixed texgen/nontexgen\n");
950 return GL_FALSE;
951 }
952
953 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) {
954 /* need this here for vtxfmt presumably. Argh we need to set
955 this from way too many places, would be much easier if we could leave
956 tcl q coord always enabled as on r200) */
957 RADEON_STATECHANGE( rmesa, tcl );
958 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit);
959 }
960
961 switch (texUnit->GenS.Mode) {
962 case GL_OBJECT_LINEAR:
963 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift;
964 set_texgen_matrix( rmesa, unit,
965 texUnit->GenS.ObjectPlane,
966 texUnit->GenT.ObjectPlane,
967 texUnit->GenR.ObjectPlane,
968 texUnit->GenQ.ObjectPlane);
969 break;
970
971 case GL_EYE_LINEAR:
972 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift;
973 set_texgen_matrix( rmesa, unit,
974 texUnit->GenS.EyePlane,
975 texUnit->GenT.EyePlane,
976 texUnit->GenR.EyePlane,
977 texUnit->GenQ.EyePlane);
978 break;
979
980 case GL_REFLECTION_MAP_NV:
981 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
982 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT << inputshift;
983 /* TODO: unknown if this is needed/correct */
984 set_texgen_matrix( rmesa, unit, reflect, reflect + 4,
985 reflect + 8, reflect + 12 );
986 break;
987
988 case GL_NORMAL_MAP_NV:
989 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
990 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL << inputshift;
991 break;
992
993 case GL_SPHERE_MAP:
994 /* the mode which everyone uses :-( */
995 default:
996 /* Unsupported mode, fallback:
997 */
998 if (RADEON_DEBUG & RADEON_FALLBACKS)
999 fprintf(stderr, "fallback GL_SPHERE_MAP\n");
1000 return GL_FALSE;
1001 }
1002
1003 if (tmp != rmesa->TexGenEnabled) {
1004 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
1005 }
1006
1007 return GL_TRUE;
1008 }
1009
1010 /**
1011 * Compute the cached hardware register values for the given texture object.
1012 *
1013 * \param rmesa Context pointer
1014 * \param t the r300 texture object
1015 */
1016 static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int unit)
1017 {
1018 const struct gl_texture_image *firstImage;
1019 GLint log2Width, log2Height, log2Depth, texelBytes;
1020
1021 if ( t->bo ) {
1022 return GL_TRUE;
1023 }
1024
1025 firstImage = t->base.Image[0][t->mt->firstLevel];
1026
1027 if (firstImage->Border > 0) {
1028 fprintf(stderr, "%s: border\n", __FUNCTION__);
1029 return GL_FALSE;
1030 }
1031
1032 log2Width = firstImage->WidthLog2;
1033 log2Height = firstImage->HeightLog2;
1034 log2Depth = firstImage->DepthLog2;
1035 texelBytes = _mesa_get_format_bytes(firstImage->TexFormat);
1036
1037 if (!t->image_override) {
1038 if (VALID_FORMAT(firstImage->TexFormat)) {
1039 const struct tx_table *table = tx_table;
1040
1041 t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
1042 RADEON_TXFORMAT_ALPHA_IN_MAP);
1043 t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
1044
1045 t->pp_txformat |= table[ firstImage->TexFormat ].format;
1046 t->pp_txfilter |= table[ firstImage->TexFormat ].filter;
1047 } else {
1048 _mesa_problem(NULL, "unexpected texture format in %s",
1049 __FUNCTION__);
1050 return GL_FALSE;
1051 }
1052 }
1053
1054 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
1055 t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << RADEON_MAX_MIP_LEVEL_SHIFT;
1056
1057 t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
1058 RADEON_TXFORMAT_HEIGHT_MASK |
1059 RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
1060 RADEON_TXFORMAT_F5_WIDTH_MASK |
1061 RADEON_TXFORMAT_F5_HEIGHT_MASK);
1062 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
1063 (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
1064
1065 t->tile_bits = 0;
1066
1067 if (t->base.Target == GL_TEXTURE_CUBE_MAP) {
1068 ASSERT(log2Width == log2Height);
1069 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) |
1070 (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) |
1071 /* don't think we need this bit, if it exists at all - fglrx does not set it */
1072 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE));
1073 t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) |
1074 (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) |
1075 (log2Width << RADEON_FACE_WIDTH_2_SHIFT) |
1076 (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) |
1077 (log2Width << RADEON_FACE_WIDTH_3_SHIFT) |
1078 (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) |
1079 (log2Width << RADEON_FACE_WIDTH_4_SHIFT) |
1080 (log2Height << RADEON_FACE_HEIGHT_4_SHIFT));
1081 }
1082
1083 t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT)
1084 | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT));
1085
1086 if ( !t->image_override ) {
1087 if (_mesa_is_format_compressed(firstImage->TexFormat))
1088 t->pp_txpitch = (firstImage->Width + 63) & ~(63);
1089 else
1090 t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63);
1091 t->pp_txpitch -= 32;
1092 }
1093
1094 if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
1095 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
1096 }
1097
1098 return GL_TRUE;
1099 }
1100
1101 static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_object *texObj, int unit)
1102 {
1103 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1104 radeonTexObj *t = radeon_tex_obj(texObj);
1105 int ret;
1106
1107 if (!radeon_validate_texture_miptree(ctx, texObj))
1108 return GL_FALSE;
1109
1110 ret = setup_hardware_state(rmesa, t, unit);
1111 if (ret == GL_FALSE)
1112 return GL_FALSE;
1113
1114 /* yuv conversion only works in first unit */
1115 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB))
1116 return GL_FALSE;
1117
1118 RADEON_STATECHANGE( rmesa, ctx );
1119 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
1120 (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
1121 RADEON_STATECHANGE( rmesa, tcl );
1122 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
1123
1124 rmesa->recheck_texgen[unit] = GL_TRUE;
1125
1126 import_tex_obj_state( rmesa, unit, t );
1127
1128 if (rmesa->recheck_texgen[unit]) {
1129 GLboolean fallback = !radeon_validate_texgen( ctx, unit );
1130 TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
1131 rmesa->recheck_texgen[unit] = 0;
1132 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
1133 }
1134
1135 if ( ! radeonUpdateTextureEnv( ctx, unit ) ) {
1136 return GL_FALSE;
1137 }
1138 FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback );
1139
1140 t->validated = GL_TRUE;
1141 return !t->border_fallback;
1142 }
1143
1144 static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
1145 {
1146 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1147
1148 if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) {
1149 rmesa->state.texture.unit[unit].texobj = NULL;
1150 return GL_FALSE;
1151 }
1152
1153 if (!ctx->Texture.Unit[unit]._ReallyEnabled) {
1154 /* disable the unit */
1155 disable_tex_obj_state(rmesa, unit);
1156 rmesa->state.texture.unit[unit].texobj = NULL;
1157 return GL_TRUE;
1158 }
1159
1160 if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) {
1161 _mesa_warning(ctx,
1162 "failed to validate texture for unit %d.\n",
1163 unit);
1164 rmesa->state.texture.unit[unit].texobj = NULL;
1165 return GL_FALSE;
1166 }
1167 rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
1168 return GL_TRUE;
1169 }
1170
1171 void radeonUpdateTextureState( GLcontext *ctx )
1172 {
1173 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1174 GLboolean ok;
1175
1176 /* set the ctx all textures off */
1177 RADEON_STATECHANGE( rmesa, ctx );
1178 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK));
1179
1180 ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
1181 radeonUpdateTextureUnit( ctx, 1 ) &&
1182 radeonUpdateTextureUnit( ctx, 2 ));
1183
1184 FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
1185
1186 if (rmesa->radeon.TclFallback)
1187 radeonChooseVertexState( ctx );
1188 }