2 * Copyright (C) 2008 Nicolai Haehnle.
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining
10 * a copy of this software and associated documentation files (the
11 * "Software"), to deal in the Software without restriction, including
12 * without limitation the rights to use, copy, modify, merge, publish,
13 * distribute, sublicense, and/or sell copies of the Software, and to
14 * permit persons to whom the Software is furnished to do so, subject to
15 * the following conditions:
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial
19 * portions of the Software.
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "main/glheader.h"
32 #include "main/imports.h"
33 #include "main/context.h"
34 #include "main/convolve.h"
35 #include "main/mipmap.h"
36 #include "main/texcompress.h"
37 #include "main/texfetch.h"
38 #include "main/texformat.h"
39 #include "main/texstore.h"
40 #include "main/teximage.h"
41 #include "main/texobj.h"
42 #include "main/texgetimage.h"
44 #include "xmlpool.h" /* for symbolic values of enum-type options */
46 #include "radeon_common.h"
48 #include "radeon_mipmap_tree.h"
51 static void copy_rows(void* dst
, GLuint dststride
, const void* src
, GLuint srcstride
,
52 GLuint numrows
, GLuint rowsize
)
54 assert(rowsize
<= dststride
);
55 assert(rowsize
<= srcstride
);
57 if (rowsize
== srcstride
&& rowsize
== dststride
) {
58 memcpy(dst
, src
, numrows
*rowsize
);
61 for(i
= 0; i
< numrows
; ++i
) {
62 memcpy(dst
, src
, rowsize
);
71 * Allocate an empty texture image object.
73 struct gl_texture_image
*radeonNewTextureImage(GLcontext
*ctx
)
75 return CALLOC(sizeof(radeon_texture_image
));
79 * Free memory associated with this texture image.
81 void radeonFreeTexImageData(GLcontext
*ctx
, struct gl_texture_image
*timage
)
83 radeon_texture_image
* image
= get_radeon_texture_image(timage
);
86 radeon_miptree_unreference(image
->mt
);
88 assert(!image
->base
.Data
);
90 _mesa_free_texture_image_data(ctx
, timage
);
93 radeon_bo_unref(image
->bo
);
97 _mesa_free_texmemory(timage
->Data
);
102 /* Set Data pointer and additional data for mapped texture image */
103 static void teximage_set_map_data(radeon_texture_image
*image
)
105 radeon_mipmap_level
*lvl
= &image
->mt
->levels
[image
->mtlevel
];
107 image
->base
.Data
= image
->mt
->bo
->ptr
+ lvl
->faces
[image
->mtface
].offset
;
108 image
->base
.RowStride
= lvl
->rowstride
/ image
->mt
->bpp
;
113 * Map a single texture image for glTexImage and friends.
115 void radeon_teximage_map(radeon_texture_image
*image
, GLboolean write_enable
)
118 assert(!image
->base
.Data
);
120 radeon_bo_map(image
->mt
->bo
, write_enable
);
121 teximage_set_map_data(image
);
126 void radeon_teximage_unmap(radeon_texture_image
*image
)
129 assert(image
->base
.Data
);
131 image
->base
.Data
= 0;
132 radeon_bo_unmap(image
->mt
->bo
);
136 static void map_override(GLcontext
*ctx
, radeonTexObj
*t
)
138 radeon_texture_image
*img
= get_radeon_texture_image(t
->base
.Image
[0][0]);
140 radeon_bo_map(t
->bo
, GL_FALSE
);
142 img
->base
.Data
= t
->bo
->ptr
;
143 _mesa_set_fetch_functions(&img
->base
, 2);
146 static void unmap_override(GLcontext
*ctx
, radeonTexObj
*t
)
148 radeon_texture_image
*img
= get_radeon_texture_image(t
->base
.Image
[0][0]);
150 radeon_bo_unmap(t
->bo
);
152 img
->base
.Data
= NULL
;
156 * Map a validated texture for reading during software rendering.
158 void radeonMapTexture(GLcontext
*ctx
, struct gl_texture_object
*texObj
)
160 radeonTexObj
* t
= radeon_tex_obj(texObj
);
163 if (!radeon_validate_texture_miptree(ctx
, texObj
))
166 /* for r100 3D sw fallbacks don't have mt */
167 if (t
->image_override
&& t
->bo
)
168 map_override(ctx
, t
);
173 radeon_bo_map(t
->mt
->bo
, GL_FALSE
);
174 for(face
= 0; face
< t
->mt
->faces
; ++face
) {
175 for(level
= t
->mt
->firstLevel
; level
<= t
->mt
->lastLevel
; ++level
)
176 teximage_set_map_data(get_radeon_texture_image(texObj
->Image
[face
][level
]));
180 void radeonUnmapTexture(GLcontext
*ctx
, struct gl_texture_object
*texObj
)
182 radeonTexObj
* t
= radeon_tex_obj(texObj
);
185 if (t
->image_override
&& t
->bo
)
186 unmap_override(ctx
, t
);
187 /* for r100 3D sw fallbacks don't have mt */
191 for(face
= 0; face
< t
->mt
->faces
; ++face
) {
192 for(level
= t
->mt
->firstLevel
; level
<= t
->mt
->lastLevel
; ++level
)
193 texObj
->Image
[face
][level
]->Data
= 0;
195 radeon_bo_unmap(t
->mt
->bo
);
198 GLuint
radeon_face_for_target(GLenum target
)
201 case GL_TEXTURE_CUBE_MAP_POSITIVE_X
:
202 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X
:
203 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y
:
204 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y
:
205 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z
:
206 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z
:
207 return (GLuint
) target
- (GLuint
) GL_TEXTURE_CUBE_MAP_POSITIVE_X
;
214 * Wraps Mesa's implementation to ensure that the base level image is mapped.
216 * This relies on internal details of _mesa_generate_mipmap, in particular
217 * the fact that the memory for recreated texture images is always freed.
219 static void radeon_generate_mipmap(GLcontext
*ctx
, GLenum target
,
220 struct gl_texture_object
*texObj
)
222 radeonTexObj
* t
= radeon_tex_obj(texObj
);
223 GLuint nr_faces
= (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
227 _mesa_generate_mipmap(ctx
, target
, texObj
);
229 for (face
= 0; face
< nr_faces
; face
++) {
230 for (i
= texObj
->BaseLevel
+ 1; i
< texObj
->MaxLevel
; i
++) {
231 radeon_texture_image
*image
;
233 image
= get_radeon_texture_image(texObj
->Image
[face
][i
]);
239 image
->mtface
= face
;
241 radeon_miptree_unreference(image
->mt
);
248 void radeonGenerateMipmap(GLcontext
* ctx
, GLenum target
, struct gl_texture_object
*texObj
)
250 GLuint face
= radeon_face_for_target(target
);
251 radeon_texture_image
*baseimage
= get_radeon_texture_image(texObj
->Image
[face
][texObj
->BaseLevel
]);
253 radeon_teximage_map(baseimage
, GL_FALSE
);
254 radeon_generate_mipmap(ctx
, target
, texObj
);
255 radeon_teximage_unmap(baseimage
);
259 /* try to find a format which will only need a memcopy */
260 static gl_format
radeonChoose8888TexFormat(radeonContextPtr rmesa
,
262 GLenum srcType
, GLboolean fbo
)
265 const GLubyte littleEndian
= *((const GLubyte
*)&ui
);
267 /* r100 can only do this */
268 if (IS_R100_CLASS(rmesa
->radeonScreen
) || fbo
)
269 return _dri_texformat_argb8888
;
271 if ((srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_INT_8_8_8_8
) ||
272 (srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
) ||
273 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
) ||
274 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_BYTE
&& littleEndian
)) {
275 return MESA_FORMAT_RGBA8888
;
276 } else if ((srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
) ||
277 (srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_BYTE
&& littleEndian
) ||
278 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_INT_8_8_8_8
) ||
279 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
)) {
280 return MESA_FORMAT_RGBA8888_REV
;
281 } else if (IS_R200_CLASS(rmesa
->radeonScreen
)) {
282 return _dri_texformat_argb8888
;
283 } else if (srcFormat
== GL_BGRA
&& ((srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
) ||
284 srcType
== GL_UNSIGNED_INT_8_8_8_8
)) {
285 return MESA_FORMAT_ARGB8888_REV
;
286 } else if (srcFormat
== GL_BGRA
&& ((srcType
== GL_UNSIGNED_BYTE
&& littleEndian
) ||
287 srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
)) {
288 return MESA_FORMAT_ARGB8888
;
290 return _dri_texformat_argb8888
;
293 gl_format
radeonChooseTextureFormat_mesa(GLcontext
* ctx
,
294 GLint internalFormat
,
298 return radeonChooseTextureFormat(ctx
, internalFormat
, format
,
302 gl_format
radeonChooseTextureFormat(GLcontext
* ctx
,
303 GLint internalFormat
,
305 GLenum type
, GLboolean fbo
)
307 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
308 const GLboolean do32bpt
=
309 (rmesa
->texture_depth
== DRI_CONF_TEXTURE_DEPTH_32
);
310 const GLboolean force16bpt
=
311 (rmesa
->texture_depth
== DRI_CONF_TEXTURE_DEPTH_FORCE_16
);
315 fprintf(stderr
, "InternalFormat=%s(%d) type=%s format=%s\n",
316 _mesa_lookup_enum_by_nr(internalFormat
), internalFormat
,
317 _mesa_lookup_enum_by_nr(type
), _mesa_lookup_enum_by_nr(format
));
318 fprintf(stderr
, "do32bpt=%d force16bpt=%d\n", do32bpt
, force16bpt
);
321 switch (internalFormat
) {
324 case GL_COMPRESSED_RGBA
:
326 case GL_UNSIGNED_INT_10_10_10_2
:
327 case GL_UNSIGNED_INT_2_10_10_10_REV
:
328 return do32bpt
? _dri_texformat_argb8888
:
329 _dri_texformat_argb1555
;
330 case GL_UNSIGNED_SHORT_4_4_4_4
:
331 case GL_UNSIGNED_SHORT_4_4_4_4_REV
:
332 return _dri_texformat_argb4444
;
333 case GL_UNSIGNED_SHORT_5_5_5_1
:
334 case GL_UNSIGNED_SHORT_1_5_5_5_REV
:
335 return _dri_texformat_argb1555
;
337 return do32bpt
? radeonChoose8888TexFormat(rmesa
, format
, type
, fbo
) :
338 _dri_texformat_argb4444
;
343 case GL_COMPRESSED_RGB
:
345 case GL_UNSIGNED_SHORT_4_4_4_4
:
346 case GL_UNSIGNED_SHORT_4_4_4_4_REV
:
347 return _dri_texformat_argb4444
;
348 case GL_UNSIGNED_SHORT_5_5_5_1
:
349 case GL_UNSIGNED_SHORT_1_5_5_5_REV
:
350 return _dri_texformat_argb1555
;
351 case GL_UNSIGNED_SHORT_5_6_5
:
352 case GL_UNSIGNED_SHORT_5_6_5_REV
:
353 return _dri_texformat_rgb565
;
355 return do32bpt
? _dri_texformat_argb8888
:
356 _dri_texformat_rgb565
;
364 radeonChoose8888TexFormat(rmesa
, format
, type
, fbo
) :
365 _dri_texformat_argb4444
;
369 return _dri_texformat_argb4444
;
372 return _dri_texformat_argb1555
;
378 return !force16bpt
? _dri_texformat_argb8888
:
379 _dri_texformat_rgb565
;
384 return _dri_texformat_rgb565
;
391 case GL_COMPRESSED_ALPHA
:
392 /* r200: can't use a8 format since interpreting hw I8 as a8 would result
393 in wrong rgb values (same as alpha value instead of 0). */
394 if (IS_R200_CLASS(rmesa
->radeonScreen
))
395 return _dri_texformat_al88
;
397 return _dri_texformat_a8
;
404 case GL_COMPRESSED_LUMINANCE
:
405 return _dri_texformat_l8
;
408 case GL_LUMINANCE_ALPHA
:
409 case GL_LUMINANCE4_ALPHA4
:
410 case GL_LUMINANCE6_ALPHA2
:
411 case GL_LUMINANCE8_ALPHA8
:
412 case GL_LUMINANCE12_ALPHA4
:
413 case GL_LUMINANCE12_ALPHA12
:
414 case GL_LUMINANCE16_ALPHA16
:
415 case GL_COMPRESSED_LUMINANCE_ALPHA
:
416 return _dri_texformat_al88
;
423 case GL_COMPRESSED_INTENSITY
:
424 return _dri_texformat_i8
;
427 if (type
== GL_UNSIGNED_SHORT_8_8_APPLE
||
428 type
== GL_UNSIGNED_BYTE
)
429 return MESA_FORMAT_YCBCR
;
431 return MESA_FORMAT_YCBCR_REV
;
435 case GL_COMPRESSED_RGB_S3TC_DXT1_EXT
:
436 return MESA_FORMAT_RGB_DXT1
;
438 case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT
:
439 return MESA_FORMAT_RGBA_DXT1
;
443 case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT
:
444 return MESA_FORMAT_RGBA_DXT3
;
446 case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT
:
447 return MESA_FORMAT_RGBA_DXT5
;
449 case GL_ALPHA16F_ARB
:
450 return MESA_FORMAT_ALPHA_FLOAT16
;
451 case GL_ALPHA32F_ARB
:
452 return MESA_FORMAT_ALPHA_FLOAT32
;
453 case GL_LUMINANCE16F_ARB
:
454 return MESA_FORMAT_LUMINANCE_FLOAT16
;
455 case GL_LUMINANCE32F_ARB
:
456 return MESA_FORMAT_LUMINANCE_FLOAT32
;
457 case GL_LUMINANCE_ALPHA16F_ARB
:
458 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
;
459 case GL_LUMINANCE_ALPHA32F_ARB
:
460 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
;
461 case GL_INTENSITY16F_ARB
:
462 return MESA_FORMAT_INTENSITY_FLOAT16
;
463 case GL_INTENSITY32F_ARB
:
464 return MESA_FORMAT_INTENSITY_FLOAT32
;
466 return MESA_FORMAT_RGBA_FLOAT16
;
468 return MESA_FORMAT_RGBA_FLOAT32
;
470 return MESA_FORMAT_RGBA_FLOAT16
;
472 return MESA_FORMAT_RGBA_FLOAT32
;
474 case GL_DEPTH_COMPONENT
:
475 case GL_DEPTH_COMPONENT16
:
476 case GL_DEPTH_COMPONENT24
:
477 case GL_DEPTH_COMPONENT32
:
478 case GL_DEPTH_STENCIL_EXT
:
479 case GL_DEPTH24_STENCIL8_EXT
:
480 return MESA_FORMAT_S8_Z24
;
482 /* EXT_texture_sRGB */
486 case GL_SRGB8_ALPHA8
:
487 case GL_COMPRESSED_SRGB
:
488 case GL_COMPRESSED_SRGB_ALPHA
:
489 return MESA_FORMAT_SRGBA8
;
493 case GL_COMPRESSED_SLUMINANCE
:
494 return MESA_FORMAT_SL8
;
496 case GL_SLUMINANCE_ALPHA
:
497 case GL_SLUMINANCE8_ALPHA8
:
498 case GL_COMPRESSED_SLUMINANCE_ALPHA
:
499 return MESA_FORMAT_SLA8
;
503 "unexpected internalFormat 0x%x in %s",
504 (int)internalFormat
, __func__
);
505 return MESA_FORMAT_NONE
;
508 return MESA_FORMAT_NONE
; /* never get here */
512 * All glTexImage calls go through this function.
514 static void radeon_teximage(
515 GLcontext
*ctx
, int dims
,
516 GLenum target
, GLint level
,
517 GLint internalFormat
,
518 GLint width
, GLint height
, GLint depth
,
520 GLenum format
, GLenum type
, const GLvoid
* pixels
,
521 const struct gl_pixelstore_attrib
*packing
,
522 struct gl_texture_object
*texObj
,
523 struct gl_texture_image
*texImage
,
526 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
527 radeonTexObj
* t
= radeon_tex_obj(texObj
);
528 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
530 GLint postConvWidth
= width
;
531 GLint postConvHeight
= height
;
533 GLuint face
= radeon_face_for_target(target
);
535 radeon_firevertices(rmesa
);
537 t
->validated
= GL_FALSE
;
539 if (ctx
->_ImageTransferState
& IMAGE_CONVOLUTION_BIT
) {
540 _mesa_adjust_image_for_convolution(ctx
, dims
, &postConvWidth
,
544 /* Choose and fill in the texture format for this image */
545 texImage
->TexFormat
= radeonChooseTextureFormat(ctx
, internalFormat
, format
, type
, 0);
546 _mesa_set_fetch_functions(texImage
, dims
);
548 if (_mesa_is_format_compressed(texImage
->TexFormat
)) {
551 texelBytes
= _mesa_get_format_bytes(texImage
->TexFormat
);
552 /* Minimum pitch of 32 bytes */
553 if (postConvWidth
* texelBytes
< 32) {
554 postConvWidth
= 32 / texelBytes
;
555 texImage
->RowStride
= postConvWidth
;
558 assert(texImage
->RowStride
== postConvWidth
);
562 /* Allocate memory for image */
563 radeonFreeTexImageData(ctx
, texImage
); /* Mesa core only clears texImage->Data but not image->mt */
566 t
->mt
->firstLevel
== level
&&
567 t
->mt
->lastLevel
== level
&&
568 t
->mt
->target
!= GL_TEXTURE_CUBE_MAP_ARB
&&
569 !radeon_miptree_matches_image(t
->mt
, texImage
, face
, level
)) {
570 radeon_miptree_unreference(t
->mt
);
575 radeon_try_alloc_miptree(rmesa
, t
, image
, face
, level
);
576 if (t
->mt
&& radeon_miptree_matches_image(t
->mt
, texImage
, face
, level
)) {
577 radeon_mipmap_level
*lvl
;
579 image
->mtlevel
= level
- t
->mt
->firstLevel
;
580 image
->mtface
= face
;
581 radeon_miptree_reference(t
->mt
);
582 lvl
= &image
->mt
->levels
[image
->mtlevel
];
583 dstRowStride
= lvl
->rowstride
;
586 if (_mesa_is_format_compressed(texImage
->TexFormat
)) {
587 size
= ctx
->Driver
.CompressedTextureSize(ctx
,
591 texImage
->TexFormat
);
594 size
= texImage
->Width
* texImage
->Height
* texImage
->Depth
* _mesa_get_format_bytes(texImage
->TexFormat
);
596 texImage
->Data
= _mesa_alloc_texmemory(size
);
599 /* Upload texture image; note that the spec allows pixels to be NULL */
601 pixels
= _mesa_validate_pbo_compressed_teximage(
602 ctx
, imageSize
, pixels
, packing
, "glCompressedTexImage");
604 pixels
= _mesa_validate_pbo_teximage(
605 ctx
, dims
, width
, height
, depth
,
606 format
, type
, pixels
, packing
, "glTexImage");
610 radeon_teximage_map(image
, GL_TRUE
);
613 uint32_t srcRowStride
, bytesPerRow
, rows
;
614 srcRowStride
= _mesa_compressed_row_stride(texImage
->TexFormat
, width
);
615 bytesPerRow
= srcRowStride
;
616 rows
= (height
+ 3) / 4;
617 copy_rows(texImage
->Data
, image
->mt
->levels
[level
].rowstride
,
618 pixels
, srcRowStride
, rows
, bytesPerRow
);
620 memcpy(texImage
->Data
, pixels
, imageSize
);
624 GLuint
*dstImageOffsets
;
627 radeon_mipmap_level
*lvl
= &image
->mt
->levels
[image
->mtlevel
];
628 dstRowStride
= lvl
->rowstride
;
630 dstRowStride
= texImage
->Width
* _mesa_get_format_bytes(texImage
->TexFormat
);
636 dstImageOffsets
= _mesa_malloc(depth
* sizeof(GLuint
)) ;
637 if (!dstImageOffsets
)
638 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "glTexImage");
640 for (i
= 0; i
< depth
; ++i
) {
641 dstImageOffsets
[i
] = dstRowStride
/_mesa_get_format_bytes(texImage
->TexFormat
) * height
* i
;
644 dstImageOffsets
= texImage
->ImageOffsets
;
647 if (!_mesa_texstore(ctx
, dims
,
648 texImage
->_BaseFormat
,
650 texImage
->Data
, 0, 0, 0, /* dstX/Y/Zoffset */
653 width
, height
, depth
,
654 format
, type
, pixels
, packing
)) {
655 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "glTexImage");
659 _mesa_free(dstImageOffsets
);
663 _mesa_unmap_teximage_pbo(ctx
, packing
);
666 radeon_teximage_unmap(image
);
671 void radeonTexImage1D(GLcontext
* ctx
, GLenum target
, GLint level
,
672 GLint internalFormat
,
673 GLint width
, GLint border
,
674 GLenum format
, GLenum type
, const GLvoid
* pixels
,
675 const struct gl_pixelstore_attrib
*packing
,
676 struct gl_texture_object
*texObj
,
677 struct gl_texture_image
*texImage
)
679 radeon_teximage(ctx
, 1, target
, level
, internalFormat
, width
, 1, 1,
680 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
683 void radeonTexImage2D(GLcontext
* ctx
, GLenum target
, GLint level
,
684 GLint internalFormat
,
685 GLint width
, GLint height
, GLint border
,
686 GLenum format
, GLenum type
, const GLvoid
* pixels
,
687 const struct gl_pixelstore_attrib
*packing
,
688 struct gl_texture_object
*texObj
,
689 struct gl_texture_image
*texImage
)
692 radeon_teximage(ctx
, 2, target
, level
, internalFormat
, width
, height
, 1,
693 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
696 void radeonCompressedTexImage2D(GLcontext
* ctx
, GLenum target
,
697 GLint level
, GLint internalFormat
,
698 GLint width
, GLint height
, GLint border
,
699 GLsizei imageSize
, const GLvoid
* data
,
700 struct gl_texture_object
*texObj
,
701 struct gl_texture_image
*texImage
)
703 radeon_teximage(ctx
, 2, target
, level
, internalFormat
, width
, height
, 1,
704 imageSize
, 0, 0, data
, &ctx
->Unpack
, texObj
, texImage
, 1);
707 void radeonTexImage3D(GLcontext
* ctx
, GLenum target
, GLint level
,
708 GLint internalFormat
,
709 GLint width
, GLint height
, GLint depth
,
711 GLenum format
, GLenum type
, const GLvoid
* pixels
,
712 const struct gl_pixelstore_attrib
*packing
,
713 struct gl_texture_object
*texObj
,
714 struct gl_texture_image
*texImage
)
716 radeon_teximage(ctx
, 3, target
, level
, internalFormat
, width
, height
, depth
,
717 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
721 * Update a subregion of the given texture image.
723 static void radeon_texsubimage(GLcontext
* ctx
, int dims
, GLenum target
, int level
,
724 GLint xoffset
, GLint yoffset
, GLint zoffset
,
725 GLsizei width
, GLsizei height
, GLsizei depth
,
727 GLenum format
, GLenum type
,
728 const GLvoid
* pixels
,
729 const struct gl_pixelstore_attrib
*packing
,
730 struct gl_texture_object
*texObj
,
731 struct gl_texture_image
*texImage
,
734 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
735 radeonTexObj
* t
= radeon_tex_obj(texObj
);
736 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
738 radeon_firevertices(rmesa
);
740 t
->validated
= GL_FALSE
;
742 pixels
= _mesa_validate_pbo_compressed_teximage(
743 ctx
, imageSize
, pixels
, packing
, "glCompressedTexImage");
745 pixels
= _mesa_validate_pbo_teximage(ctx
, dims
,
746 width
, height
, depth
, format
, type
, pixels
, packing
, "glTexSubImage1D");
751 radeon_teximage_map(image
, GL_TRUE
);
754 radeon_mipmap_level
*lvl
= &image
->mt
->levels
[image
->mtlevel
];
755 dstRowStride
= lvl
->rowstride
;
757 dstRowStride
= texImage
->RowStride
* _mesa_get_format_bytes(texImage
->TexFormat
);
761 uint32_t srcRowStride
, bytesPerRow
, rows
;
764 dstRowStride
= _mesa_compressed_row_stride(texImage
->TexFormat
, texImage
->Width
);
765 img_start
= _mesa_compressed_image_address(xoffset
, yoffset
, 0,
767 texImage
->Width
, texImage
->Data
);
770 uint32_t blocks_x
= dstRowStride
/ (image
->mt
->bpp
* 4);
771 img_start
= texImage
->Data
+ image
->mt
->bpp
* 4 * (blocks_x
* (yoffset
/ 4) + xoffset
/ 4);
773 srcRowStride
= _mesa_compressed_row_stride(texImage
->TexFormat
, width
);
774 bytesPerRow
= srcRowStride
;
775 rows
= (height
+ 3) / 4;
777 copy_rows(img_start
, dstRowStride
, pixels
, srcRowStride
, rows
, bytesPerRow
);
781 if (!_mesa_texstore(ctx
, dims
, texImage
->_BaseFormat
,
782 texImage
->TexFormat
, texImage
->Data
,
783 xoffset
, yoffset
, zoffset
,
785 texImage
->ImageOffsets
,
786 width
, height
, depth
,
787 format
, type
, pixels
, packing
)) {
788 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "glTexSubImage");
793 radeon_teximage_unmap(image
);
795 _mesa_unmap_teximage_pbo(ctx
, packing
);
800 void radeonTexSubImage1D(GLcontext
* ctx
, GLenum target
, GLint level
,
803 GLenum format
, GLenum type
,
804 const GLvoid
* pixels
,
805 const struct gl_pixelstore_attrib
*packing
,
806 struct gl_texture_object
*texObj
,
807 struct gl_texture_image
*texImage
)
809 radeon_texsubimage(ctx
, 1, target
, level
, xoffset
, 0, 0, width
, 1, 1, 0,
810 format
, type
, pixels
, packing
, texObj
, texImage
, 0);
813 void radeonTexSubImage2D(GLcontext
* ctx
, GLenum target
, GLint level
,
814 GLint xoffset
, GLint yoffset
,
815 GLsizei width
, GLsizei height
,
816 GLenum format
, GLenum type
,
817 const GLvoid
* pixels
,
818 const struct gl_pixelstore_attrib
*packing
,
819 struct gl_texture_object
*texObj
,
820 struct gl_texture_image
*texImage
)
822 radeon_texsubimage(ctx
, 2, target
, level
, xoffset
, yoffset
, 0, width
, height
, 1,
823 0, format
, type
, pixels
, packing
, texObj
, texImage
,
827 void radeonCompressedTexSubImage2D(GLcontext
* ctx
, GLenum target
,
828 GLint level
, GLint xoffset
,
829 GLint yoffset
, GLsizei width
,
830 GLsizei height
, GLenum format
,
831 GLsizei imageSize
, const GLvoid
* data
,
832 struct gl_texture_object
*texObj
,
833 struct gl_texture_image
*texImage
)
835 radeon_texsubimage(ctx
, 2, target
, level
, xoffset
, yoffset
, 0, width
, height
, 1,
836 imageSize
, format
, 0, data
, &ctx
->Unpack
, texObj
, texImage
, 1);
840 void radeonTexSubImage3D(GLcontext
* ctx
, GLenum target
, GLint level
,
841 GLint xoffset
, GLint yoffset
, GLint zoffset
,
842 GLsizei width
, GLsizei height
, GLsizei depth
,
843 GLenum format
, GLenum type
,
844 const GLvoid
* pixels
,
845 const struct gl_pixelstore_attrib
*packing
,
846 struct gl_texture_object
*texObj
,
847 struct gl_texture_image
*texImage
)
849 radeon_texsubimage(ctx
, 3, target
, level
, xoffset
, yoffset
, zoffset
, width
, height
, depth
, 0,
850 format
, type
, pixels
, packing
, texObj
, texImage
, 0);
856 * Ensure that the given image is stored in the given miptree from now on.
858 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
, radeon_texture_image
*image
, int face
, int level
)
860 radeon_mipmap_level
*dstlvl
= &mt
->levels
[level
- mt
->firstLevel
];
863 assert(image
->mt
!= mt
);
864 assert(dstlvl
->width
== image
->base
.Width
);
865 assert(dstlvl
->height
== image
->base
.Height
);
866 assert(dstlvl
->depth
== image
->base
.Depth
);
869 radeon_bo_map(mt
->bo
, GL_TRUE
);
870 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
873 /* Format etc. should match, so we really just need a memcpy().
874 * In fact, that memcpy() could be done by the hardware in many
875 * cases, provided that we have a proper memory manager.
877 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
-image
->mt
->firstLevel
];
879 assert(srclvl
->size
== dstlvl
->size
);
880 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
882 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
885 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
887 radeon_bo_unmap(image
->mt
->bo
);
889 radeon_miptree_unreference(image
->mt
);
891 uint32_t srcrowstride
;
893 /* need to confirm this value is correct */
894 if (mt
->compressed
) {
895 height
= (image
->base
.Height
+ 3) / 4;
896 srcrowstride
= _mesa_compressed_row_stride(image
->base
.TexFormat
, image
->base
.Width
);
898 height
= image
->base
.Height
* image
->base
.Depth
;
899 srcrowstride
= image
->base
.Width
* _mesa_get_format_bytes(image
->base
.TexFormat
);
903 // WARN_ONCE("%s: tiling not supported yet", __FUNCTION__);
905 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
906 height
, srcrowstride
);
908 _mesa_free_texmemory(image
->base
.Data
);
909 image
->base
.Data
= 0;
912 radeon_bo_unmap(mt
->bo
);
915 image
->mtface
= face
;
916 image
->mtlevel
= level
;
917 radeon_miptree_reference(image
->mt
);
920 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
922 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
923 radeonTexObj
*t
= radeon_tex_obj(texObj
);
924 radeon_texture_image
*baseimage
= get_radeon_texture_image(texObj
->Image
[0][texObj
->BaseLevel
]);
927 if (t
->validated
|| t
->image_override
)
930 if (RADEON_DEBUG
& RADEON_TEXTURE
)
931 fprintf(stderr
, "%s: Validating texture %p now\n", __FUNCTION__
, texObj
);
933 if (baseimage
->base
.Border
> 0)
936 /* Ensure a matching miptree exists.
938 * Differing mipmap trees can result when the app uses TexImage to
939 * change texture dimensions.
941 * Prefer to use base image's miptree if it
942 * exists, since that most likely contains more valid data (remember
943 * that the base level is usually significantly larger than the rest
944 * of the miptree, so cubemaps are the only possible exception).
947 baseimage
->mt
!= t
->mt
&&
948 radeon_miptree_matches_texture(baseimage
->mt
, &t
->base
)) {
949 radeon_miptree_unreference(t
->mt
);
950 t
->mt
= baseimage
->mt
;
951 radeon_miptree_reference(t
->mt
);
952 } else if (t
->mt
&& !radeon_miptree_matches_texture(t
->mt
, &t
->base
)) {
953 radeon_miptree_unreference(t
->mt
);
958 if (RADEON_DEBUG
& RADEON_TEXTURE
)
959 fprintf(stderr
, " Allocate new miptree\n");
960 radeon_try_alloc_miptree(rmesa
, t
, baseimage
, 0, texObj
->BaseLevel
);
962 _mesa_problem(ctx
, "radeon_validate_texture failed to alloc miptree");
967 /* Ensure all images are stored in the single main miptree */
968 for(face
= 0; face
< t
->mt
->faces
; ++face
) {
969 for(level
= t
->mt
->firstLevel
; level
<= t
->mt
->lastLevel
; ++level
) {
970 radeon_texture_image
*image
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
971 if (RADEON_DEBUG
& RADEON_TEXTURE
)
972 fprintf(stderr
, " face %i, level %i... %p vs %p ", face
, level
, t
->mt
, image
->mt
);
973 if (t
->mt
== image
->mt
) {
974 if (RADEON_DEBUG
& RADEON_TEXTURE
)
975 fprintf(stderr
, "OK\n");
980 if (RADEON_DEBUG
& RADEON_TEXTURE
)
981 fprintf(stderr
, "migrating\n");
982 migrate_image_to_miptree(t
->mt
, image
, face
, level
);
991 * Need to map texture image into memory before copying image data,
995 radeon_get_tex_image(GLcontext
* ctx
, GLenum target
, GLint level
,
996 GLenum format
, GLenum type
, GLvoid
* pixels
,
997 struct gl_texture_object
*texObj
,
998 struct gl_texture_image
*texImage
, int compressed
)
1000 radeon_texture_image
*image
= get_radeon_texture_image(texImage
);
1003 /* Map the texture image read-only */
1004 radeon_teximage_map(image
, GL_FALSE
);
1006 /* Image hasn't been uploaded to a miptree yet */
1007 assert(image
->base
.Data
);
1011 /* FIXME: this can't work for small textures (mips) which
1012 use different hw stride */
1013 _mesa_get_compressed_teximage(ctx
, target
, level
, pixels
,
1016 _mesa_get_teximage(ctx
, target
, level
, format
, type
, pixels
,
1021 radeon_teximage_unmap(image
);
1026 radeonGetTexImage(GLcontext
* ctx
, GLenum target
, GLint level
,
1027 GLenum format
, GLenum type
, GLvoid
* pixels
,
1028 struct gl_texture_object
*texObj
,
1029 struct gl_texture_image
*texImage
)
1031 radeon_get_tex_image(ctx
, target
, level
, format
, type
, pixels
,
1032 texObj
, texImage
, 0);
1036 radeonGetCompressedTexImage(GLcontext
*ctx
, GLenum target
, GLint level
,
1038 struct gl_texture_object
*texObj
,
1039 struct gl_texture_image
*texImage
)
1041 radeon_get_tex_image(ctx
, target
, level
, 0, 0, pixels
,
1042 texObj
, texImage
, 1);