src/mesa/shader/slang/slang_emit.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2005-2008  Brian Paul   All Rights Reserved.
   5  * Copyright (C) 2008 VMware, Inc.   All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file slang_emit.c
  27  * Emit program instructions (PI code) from IR trees.
  28  * \author Brian Paul
  29  */
  30
  31 /***
  32  *** NOTES
  33  ***
  34  *** To emit GPU instructions, we basically just do an in-order traversal
  35  *** of the IR tree.
  36  ***/
  37
  38
  39 #include "main/imports.h"
  40 #include "main/context.h"
  41 #include "main/macros.h"
  42 #include "shader/program.h"
  43 #include "shader/prog_instruction.h"
  44 #include "shader/prog_parameter.h"
  45 #include "shader/prog_print.h"
  46 #include "slang_builtin.h"
  47 #include "slang_emit.h"
  48 #include "slang_mem.h"
  49
  50
  51 #define PEEPHOLE_OPTIMIZATIONS 1
  52 #define ANNOTATE 0
  53
  54
  55 typedef struct
  56 {
  57    slang_info_log *log;
  58    slang_var_table *vt;
  59    struct gl_program *prog;
  60    struct gl_program **Subroutines;
  61    GLuint NumSubroutines;
  62
  63    GLuint MaxInstructions;  /**< size of prog->Instructions[] buffer */
  64
  65    /* code-gen options */
  66    GLboolean EmitHighLevelInstructions;
  67    GLboolean EmitCondCodes;
  68    GLboolean EmitComments;
  69    GLboolean EmitBeginEndSub; /* XXX TEMPORARY */
  70 } slang_emit_info;
  71
  72
  73
  74 static struct gl_program *
  75 new_subroutine(slang_emit_info *emitInfo, GLuint *id)
  76 {
  77    GET_CURRENT_CONTEXT(ctx);
  78    const GLuint n = emitInfo->NumSubroutines;
  79
  80    emitInfo->Subroutines = (struct gl_program **)
  81       _mesa_realloc(emitInfo->Subroutines,
  82                     n * sizeof(struct gl_program),
  83                     (n + 1) * sizeof(struct gl_program));
  84    emitInfo->Subroutines[n] = ctx->Driver.NewProgram(ctx, emitInfo->prog->Target, 0);
  85    emitInfo->Subroutines[n]->Parameters = emitInfo->prog->Parameters;
  86    emitInfo->NumSubroutines++;
  87    *id = n;
  88    return emitInfo->Subroutines[n];
  89 }
  90
  91
  92 /**
  93  * Convert a writemask to a swizzle.  Used for testing cond codes because
  94  * we only want to test the cond code component(s) that was set by the
  95  * previous instruction.
  96  */
  97 static GLuint
  98 writemask_to_swizzle(GLuint writemask)
  99 {
 100    if (writemask == WRITEMASK_X)
 101       return SWIZZLE_XXXX;
 102    if (writemask == WRITEMASK_Y)
 103       return SWIZZLE_YYYY;
 104    if (writemask == WRITEMASK_Z)
 105       return SWIZZLE_ZZZZ;
 106    if (writemask == WRITEMASK_W)
 107       return SWIZZLE_WWWW;
 108    return SWIZZLE_XYZW;  /* shouldn't be hit */
 109 }
 110
 111
 112 /**
 113  * Convert a swizzle mask to a writemask.
 114  * Note that the slang_ir_storage->Swizzle field can represent either a
 115  * swizzle mask or a writemask, depending on how it's used.  For example,
 116  * when we parse "direction.yz" alone, we don't know whether .yz is a
 117  * writemask or a swizzle.  In this case, we encode ".yz" in store->Swizzle
 118  * as a swizzle mask (.yz?? actually).  Later, if direction.yz is used as
 119  * an R-value, we use store->Swizzle as-is.  Otherwise, if direction.yz is
 120  * used as an L-value, we convert it to a writemask.
 121  */
 122 static GLuint
 123 swizzle_to_writemask(GLuint swizzle)
 124 {
 125    GLuint i, writemask = 0x0;
 126    for (i = 0; i < 4; i++) {
 127       GLuint swz = GET_SWZ(swizzle, i);
 128       if (swz <= SWIZZLE_W) {
 129          writemask |= (1 << swz);
 130       }
 131    }
 132    return writemask;
 133 }
 134
 135
 136 /**
 137  * Swizzle a swizzle (function composition).
 138  * That is, return swz2(swz1), or said another way: swz1.szw2
 139  * Example: swizzle_swizzle(".zwxx", ".xxyw") yields ".zzwx"
 140  */
 141 GLuint
 142 _slang_swizzle_swizzle(GLuint swz1, GLuint swz2)
 143 {
 144    GLuint i, swz, s[4];
 145    for (i = 0; i < 4; i++) {
 146       GLuint c = GET_SWZ(swz2, i);
 147       if (c <= SWIZZLE_W)
 148          s[i] = GET_SWZ(swz1, c);
 149       else
 150          s[i] = c;
 151    }
 152    swz = MAKE_SWIZZLE4(s[0], s[1], s[2], s[3]);
 153    return swz;
 154 }
 155
 156
 157 /**
 158  * Return the default swizzle mask for accessing a variable of the
 159  * given size (in floats).  If size = 1, comp is used to identify
 160  * which component [0..3] of the register holds the variable.
 161  */
 162 GLuint
 163 _slang_var_swizzle(GLint size, GLint comp)
 164 {
 165    switch (size) {
 166    case 1:
 167       return MAKE_SWIZZLE4(comp, comp, comp, comp);
 168    case 2:
 169       return MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_NIL, SWIZZLE_NIL);
 170    case 3:
 171       return MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_NIL);
 172    default:
 173       return SWIZZLE_XYZW;
 174    }
 175 }
 176
 177
 178
 179 /**
 180  * Allocate storage for the given node (if it hasn't already been allocated).
 181  *
 182  * Typically this is temporary storage for an intermediate result (such as
 183  * for a multiply or add, etc).
 184  *
 185  * If n->Store does not exist it will be created and will be of the size
 186  * specified by defaultSize.
 187  */
 188 static GLboolean
 189 alloc_node_storage(slang_emit_info *emitInfo, slang_ir_node *n,
 190                    GLint defaultSize)
 191 {
 192    assert(!n->Var);
 193    if (!n->Store) {
 194       assert(defaultSize > 0);
 195       n->Store = _slang_new_ir_storage(PROGRAM_TEMPORARY, -1, defaultSize);
 196    }
 197
 198    /* now allocate actual register(s).  I.e. set n->Store->Index >= 0 */
 199    if (n->Store->Index < 0) {
 200       if (!_slang_alloc_temp(emitInfo->vt, n->Store)) {
 201          slang_info_log_error(emitInfo->log,
 202                               "Ran out of registers, too many temporaries");
 203          _slang_free(n->Store);
 204          n->Store = NULL;
 205          return GL_FALSE;
 206       }
 207    }
 208    return GL_TRUE;
 209 }
 210
 211
 212 /**
 213  * Free temporary storage, if n->Store is, in fact, temp storage.
 214  * Otherwise, no-op.
 215  */
 216 static void
 217 free_node_storage(slang_var_table *vt, slang_ir_node *n)
 218 {
 219    if (n->Store->File == PROGRAM_TEMPORARY &&
 220        n->Store->Index >= 0 &&
 221        n->Opcode != IR_SWIZZLE) {
 222       if (_slang_is_temp(vt, n->Store)) {
 223          _slang_free_temp(vt, n->Store);
 224          n->Store->Index = -1;
 225          n->Store = NULL; /* XXX this may not be needed */
 226       }
 227    }
 228 }
 229
 230
 231 /**
 232  * Helper function to allocate a short-term temporary.
 233  * Free it with _slang_free_temp().
 234  */
 235 static GLboolean
 236 alloc_local_temp(slang_emit_info *emitInfo, slang_ir_storage *temp, GLint size)
 237 {
 238    assert(size >= 1);
 239    assert(size <= 4);
 240    _mesa_bzero(temp, sizeof(*temp));
 241    temp->Size = size;
 242    temp->File = PROGRAM_TEMPORARY;
 243    temp->Index = -1;
 244    return _slang_alloc_temp(emitInfo->vt, temp);
 245 }
 246
 247
 248 /**
 249  * Remove any SWIZZLE_NIL terms from given swizzle mask.
 250  * For a swizzle like .z??? generate .zzzz (replicate single component).
 251  * Else, for .wx?? generate .wxzw (insert default component for the position).
 252  */
 253 static GLuint
 254 fix_swizzle(GLuint swizzle)
 255 {
 256    GLuint c0 = GET_SWZ(swizzle, 0),
 257       c1 = GET_SWZ(swizzle, 1),
 258       c2 = GET_SWZ(swizzle, 2),
 259       c3 = GET_SWZ(swizzle, 3);
 260    if (c1 == SWIZZLE_NIL && c2 == SWIZZLE_NIL && c3 == SWIZZLE_NIL) {
 261       /* smear first component across all positions */
 262       c1 = c2 = c3 = c0;
 263    }
 264    else {
 265       /* insert default swizzle components */
 266       if (c0 == SWIZZLE_NIL)
 267          c0 = SWIZZLE_X;
 268       if (c1 == SWIZZLE_NIL)
 269          c1 = SWIZZLE_Y;
 270       if (c2 == SWIZZLE_NIL)
 271          c2 = SWIZZLE_Z;
 272       if (c3 == SWIZZLE_NIL)
 273          c3 = SWIZZLE_W;
 274    }
 275    return MAKE_SWIZZLE4(c0, c1, c2, c3);
 276 }
 277
 278
 279
 280 /**
 281  * Convert IR storage to an instruction dst register.
 282  */
 283 static void
 284 storage_to_dst_reg(struct prog_dst_register *dst, const slang_ir_storage *st)
 285 {
 286    const GLboolean relAddr = st->RelAddr;
 287    const GLint size = st->Size;
 288    GLint index = st->Index;
 289    GLuint swizzle = st->Swizzle;
 290
 291    assert(index >= 0);
 292    /* if this is storage relative to some parent storage, walk up the tree */
 293    while (st->Parent) {
 294       st = st->Parent;
 295       assert(st->Index >= 0);
 296       index += st->Index;
 297       swizzle = _slang_swizzle_swizzle(st->Swizzle, swizzle);
 298    }
 299
 300    assert(st->File != PROGRAM_UNDEFINED);
 301    dst->File = st->File;
 302
 303    assert(index >= 0);
 304    dst->Index = index;
 305
 306    assert(size >= 1);
 307    assert(size <= 4);
 308
 309    if (swizzle != SWIZZLE_XYZW) {
 310       dst->WriteMask = swizzle_to_writemask(swizzle);
 311    }
 312    else {
 313       switch (size) {
 314       case 1:
 315          dst->WriteMask = WRITEMASK_X << GET_SWZ(st->Swizzle, 0);
 316          break;
 317       case 2:
 318          dst->WriteMask = WRITEMASK_XY;
 319          break;
 320       case 3:
 321          dst->WriteMask = WRITEMASK_XYZ;
 322          break;
 323       case 4:
 324          dst->WriteMask = WRITEMASK_XYZW;
 325          break;
 326       default:
 327          ; /* error would have been caught above */
 328       }
 329    }
 330
 331    dst->RelAddr = relAddr;
 332 }
 333
 334
 335 /**
 336  * Convert IR storage to an instruction src register.
 337  */
 338 static void
 339 storage_to_src_reg(struct prog_src_register *src, const slang_ir_storage *st)
 340 {
 341    const GLboolean relAddr = st->RelAddr;
 342    GLint index = st->Index;
 343    GLuint swizzle = st->Swizzle;
 344
 345    /* if this is storage relative to some parent storage, walk up the tree */
 346    assert(index >= 0);
 347    while (st->Parent) {
 348       st = st->Parent;
 349       if (st->Index < 0) {
 350          /* an error should have been reported already */
 351          return;
 352       }
 353       assert(st->Index >= 0);
 354       index += st->Index;
 355       swizzle = _slang_swizzle_swizzle(fix_swizzle(st->Swizzle), swizzle);
 356    }
 357
 358    assert(st->File >= 0);
 359 #if 1 /* XXX temporary */
 360    if (st->File == PROGRAM_UNDEFINED) {
 361       slang_ir_storage *st0 = (slang_ir_storage *) st;
 362       st0->File = PROGRAM_TEMPORARY;
 363    }
 364 #endif
 365    assert(st->File < PROGRAM_UNDEFINED);
 366    src->File = st->File;
 367
 368    assert(index >= 0);
 369    src->Index = index;
 370
 371    swizzle = fix_swizzle(swizzle);
 372    assert(GET_SWZ(swizzle, 0) <= SWIZZLE_W);
 373    assert(GET_SWZ(swizzle, 1) <= SWIZZLE_W);
 374    assert(GET_SWZ(swizzle, 2) <= SWIZZLE_W);
 375    assert(GET_SWZ(swizzle, 3) <= SWIZZLE_W);
 376    src->Swizzle = swizzle;
 377
 378    src->RelAddr = relAddr;
 379 }
 380
 381
 382 /*
 383  * Setup storage pointing to a scalar constant/literal.
 384  */
 385 static void
 386 constant_to_storage(slang_emit_info *emitInfo,
 387                     GLfloat val,
 388                     slang_ir_storage *store)
 389 {
 390    GLuint swizzle;
 391    GLint reg;
 392    GLfloat value[4];
 393
 394    value[0] = val;
 395    reg = _mesa_add_unnamed_constant(emitInfo->prog->Parameters,
 396                                         value, 1, &swizzle);
 397
 398    memset(store, 0, sizeof(*store));
 399    store->File = PROGRAM_CONSTANT;
 400    store->Index = reg;
 401    store->Swizzle = swizzle;
 402 }
 403
 404
 405 /**
 406  * Add new instruction at end of given program.
 407  * \param prog  the program to append instruction onto
 408  * \param opcode  opcode for the new instruction
 409  * \return pointer to the new instruction
 410  */
 411 static struct prog_instruction *
 412 new_instruction(slang_emit_info *emitInfo, gl_inst_opcode opcode)
 413 {
 414    struct gl_program *prog = emitInfo->prog;
 415    struct prog_instruction *inst;
 416
 417 #if 0
 418    /* print prev inst */
 419    if (prog->NumInstructions > 0) {
 420       _mesa_print_instruction(prog->Instructions + prog->NumInstructions - 1);
 421    }
 422 #endif
 423    assert(prog->NumInstructions <= emitInfo->MaxInstructions);
 424
 425    if (prog->NumInstructions == emitInfo->MaxInstructions) {
 426       /* grow the instruction buffer */
 427       emitInfo->MaxInstructions += 20;
 428       prog->Instructions =
 429          _mesa_realloc_instructions(prog->Instructions,
 430                                     prog->NumInstructions,
 431                                     emitInfo->MaxInstructions);
 432    }
 433
 434    inst = prog->Instructions + prog->NumInstructions;
 435    prog->NumInstructions++;
 436    _mesa_init_instructions(inst, 1);
 437    inst->Opcode = opcode;
 438    inst->BranchTarget = -1; /* invalid */
 439    /*
 440    printf("New inst %d: %p %s\n", prog->NumInstructions-1,(void*)inst,
 441           _mesa_opcode_string(inst->Opcode));
 442    */
 443    return inst;
 444 }
 445
 446
 447 static struct prog_instruction *
 448 emit_arl_load(slang_emit_info *emitInfo,
 449               enum register_file file, GLint index, GLuint swizzle)
 450 {
 451    struct prog_instruction *inst = new_instruction(emitInfo, OPCODE_ARL);
 452    inst->SrcReg[0].File = file;
 453    inst->SrcReg[0].Index = index;
 454    inst->SrcReg[0].Swizzle = fix_swizzle(swizzle);
 455    inst->DstReg.File = PROGRAM_ADDRESS;
 456    inst->DstReg.Index = 0;
 457    inst->DstReg.WriteMask = WRITEMASK_X;
 458    return inst;
 459 }
 460
 461
 462 /**
 463  * Emit a new instruction with given opcode, operands.
 464  * At this point the instruction may have multiple indirect register
 465  * loads/stores.  We convert those into ARL loads and address-relative
 466  * operands.  See comments inside.
 467  * At some point in the future we could directly emit indirectly addressed
 468  * registers in Mesa GPU instructions.
 469  */
 470 static struct prog_instruction *
 471 emit_instruction(slang_emit_info *emitInfo,
 472                  gl_inst_opcode opcode,
 473                  const slang_ir_storage *dst,
 474                  const slang_ir_storage *src0,
 475                  const slang_ir_storage *src1,
 476                  const slang_ir_storage *src2)
 477 {
 478    struct prog_instruction *inst;
 479    GLuint numIndirect = 0;
 480    const slang_ir_storage *src[3];
 481    slang_ir_storage newSrc[3], newDst;
 482    GLuint i;
 483    GLboolean isTemp[3];
 484
 485    isTemp[0] = isTemp[1] = isTemp[2] = GL_FALSE;
 486
 487    src[0] = src0;
 488    src[1] = src1;
 489    src[2] = src2;
 490
 491    /* count up how many operands are indirect loads */
 492    for (i = 0; i < 3; i++) {
 493       if (src[i] && src[i]->IsIndirect)
 494          numIndirect++;
 495    }
 496    if (dst && dst->IsIndirect)
 497       numIndirect++;
 498
 499    /* Take special steps for indirect register loads.
 500     * If we had multiple address registers this would be simpler.
 501     * For example, this GLSL code:
 502     *    x[i] = y[j] + z[k];
 503     * would translate into something like:
 504     *    ARL ADDR.x, i;
 505     *    ARL ADDR.y, j;
 506     *    ARL ADDR.z, k;
 507     *    ADD TEMP[ADDR.x+5], TEMP[ADDR.y+9], TEMP[ADDR.z+4];
 508     * But since we currently only have one address register we have to do this:
 509     *    ARL ADDR.x, i;
 510     *    MOV t1, TEMP[ADDR.x+9];
 511     *    ARL ADDR.x, j;
 512     *    MOV t2, TEMP[ADDR.x+4];
 513     *    ARL ADDR.x, k;
 514     *    ADD TEMP[ADDR.x+5], t1, t2;
 515     * The code here figures this out...
 516     */
 517    if (numIndirect > 0) {
 518       for (i = 0; i < 3; i++) {
 519          if (src[i] && src[i]->IsIndirect) {
 520             /* load the ARL register with the indirect register */
 521             emit_arl_load(emitInfo,
 522                           src[i]->IndirectFile,
 523                           src[i]->IndirectIndex,
 524                           src[i]->IndirectSwizzle);
 525
 526             if (numIndirect > 1) {
 527                /* Need to load src[i] into a temporary register */
 528                slang_ir_storage srcRelAddr;
 529                alloc_local_temp(emitInfo, &newSrc[i], src[i]->Size);
 530                isTemp[i] = GL_TRUE;
 531
 532                /* set RelAddr flag on src register */
 533                srcRelAddr = *src[i];
 534                srcRelAddr.RelAddr = GL_TRUE;
 535                srcRelAddr.IsIndirect = GL_FALSE; /* not really needed */
 536
 537                /* MOV newSrc, srcRelAddr; */
 538                inst = emit_instruction(emitInfo,
 539                                        OPCODE_MOV,
 540                                        &newSrc[i],
 541                                        &srcRelAddr,
 542                                        NULL,
 543                                        NULL);
 544
 545                src[i] = &newSrc[i];
 546             }
 547             else {
 548                /* just rewrite the src[i] storage to be ARL-relative */
 549                newSrc[i] = *src[i];
 550                newSrc[i].RelAddr = GL_TRUE;
 551                newSrc[i].IsIndirect = GL_FALSE; /* not really needed */
 552                src[i] = &newSrc[i];
 553             }
 554          }
 555       }
 556    }
 557
 558    /* Take special steps for indirect dest register write */
 559    if (dst && dst->IsIndirect) {
 560       /* load the ARL register with the indirect register */
 561       emit_arl_load(emitInfo,
 562                     dst->IndirectFile,
 563                     dst->IndirectIndex,
 564                     dst->IndirectSwizzle);
 565       newDst = *dst;
 566       newDst.RelAddr = GL_TRUE;
 567       newDst.IsIndirect = GL_FALSE;
 568       dst = &newDst;
 569    }
 570
 571    /* OK, emit the instruction and its dst, src regs */
 572    inst = new_instruction(emitInfo, opcode);
 573    if (!inst)
 574       return NULL;
 575
 576    if (dst)
 577       storage_to_dst_reg(&inst->DstReg, dst);
 578
 579    for (i = 0; i < 3; i++) {
 580       if (src[i])
 581          storage_to_src_reg(&inst->SrcReg[i], src[i]);
 582    }
 583
 584    /* Free any temp registers that we allocated above */
 585    for (i = 0; i < 3; i++) {
 586       if (isTemp[i])
 587          _slang_free_temp(emitInfo->vt, &newSrc[i]);
 588    }
 589
 590    return inst;
 591 }
 592
 593
 594
 595 /**
 596  * Put a comment on the given instruction.
 597  */
 598 static void
 599 inst_comment(struct prog_instruction *inst, const char *comment)
 600 {
 601    if (inst)
 602       inst->Comment = _mesa_strdup(comment);
 603 }
 604
 605
 606
 607 /**
 608  * Return pointer to last instruction in program.
 609  */
 610 static struct prog_instruction *
 611 prev_instruction(slang_emit_info *emitInfo)
 612 {
 613    struct gl_program *prog = emitInfo->prog;
 614    if (prog->NumInstructions == 0)
 615       return NULL;
 616    else
 617       return prog->Instructions + prog->NumInstructions - 1;
 618 }
 619
 620
 621 static struct prog_instruction *
 622 emit(slang_emit_info *emitInfo, slang_ir_node *n);
 623
 624
 625 /**
 626  * Return an annotation string for given node's storage.
 627  */
 628 static char *
 629 storage_annotation(const slang_ir_node *n, const struct gl_program *prog)
 630 {
 631 #if ANNOTATE
 632    const slang_ir_storage *st = n->Store;
 633    static char s[100] = "";
 634
 635    if (!st)
 636       return _mesa_strdup("");
 637
 638    switch (st->File) {
 639    case PROGRAM_CONSTANT:
 640       if (st->Index >= 0) {
 641          const GLfloat *val = prog->Parameters->ParameterValues[st->Index];
 642          if (st->Swizzle == SWIZZLE_NOOP)
 643             sprintf(s, "{%g, %g, %g, %g}", val[0], val[1], val[2], val[3]);
 644          else {
 645             sprintf(s, "%g", val[GET_SWZ(st->Swizzle, 0)]);
 646          }
 647       }
 648       break;
 649    case PROGRAM_TEMPORARY:
 650       if (n->Var)
 651          sprintf(s, "%s", (char *) n->Var->a_name);
 652       else
 653          sprintf(s, "t[%d]", st->Index);
 654       break;
 655    case PROGRAM_STATE_VAR:
 656    case PROGRAM_UNIFORM:
 657       sprintf(s, "%s", prog->Parameters->Parameters[st->Index].Name);
 658       break;
 659    case PROGRAM_VARYING:
 660       sprintf(s, "%s", prog->Varying->Parameters[st->Index].Name);
 661       break;
 662    case PROGRAM_INPUT:
 663       sprintf(s, "input[%d]", st->Index);
 664       break;
 665    case PROGRAM_OUTPUT:
 666       sprintf(s, "output[%d]", st->Index);
 667       break;
 668    default:
 669       s[0] = 0;
 670    }
 671    return _mesa_strdup(s);
 672 #else
 673    return NULL;
 674 #endif
 675 }
 676
 677
 678 /**
 679  * Return an annotation string for an instruction.
 680  */
 681 static char *
 682 instruction_annotation(gl_inst_opcode opcode, char *dstAnnot,
 683                        char *srcAnnot0, char *srcAnnot1, char *srcAnnot2)
 684 {
 685 #if ANNOTATE
 686    const char *operator;
 687    char *s;
 688    int len = 50;
 689
 690    if (dstAnnot)
 691       len += strlen(dstAnnot);
 692    else
 693       dstAnnot = _mesa_strdup("");
 694
 695    if (srcAnnot0)
 696       len += strlen(srcAnnot0);
 697    else
 698       srcAnnot0 = _mesa_strdup("");
 699
 700    if (srcAnnot1)
 701       len += strlen(srcAnnot1);
 702    else
 703       srcAnnot1 = _mesa_strdup("");
 704
 705    if (srcAnnot2)
 706       len += strlen(srcAnnot2);
 707    else
 708       srcAnnot2 = _mesa_strdup("");
 709
 710    switch (opcode) {
 711    case OPCODE_ADD:
 712       operator = "+";
 713       break;
 714    case OPCODE_SUB:
 715       operator = "-";
 716       break;
 717    case OPCODE_MUL:
 718       operator = "*";
 719       break;
 720    case OPCODE_DP2:
 721       operator = "DP2";
 722       break;
 723    case OPCODE_DP3:
 724       operator = "DP3";
 725       break;
 726    case OPCODE_DP4:
 727       operator = "DP4";
 728       break;
 729    case OPCODE_XPD:
 730       operator = "XPD";
 731       break;
 732    case OPCODE_RSQ:
 733       operator = "RSQ";
 734       break;
 735    case OPCODE_SGT:
 736       operator = ">";
 737       break;
 738    default:
 739       operator = ",";
 740    }
 741
 742    s = (char *) malloc(len);
 743    sprintf(s, "%s = %s %s %s %s", dstAnnot,
 744            srcAnnot0, operator, srcAnnot1, srcAnnot2);
 745    assert(_mesa_strlen(s) < len);
 746
 747    free(dstAnnot);
 748    free(srcAnnot0);
 749    free(srcAnnot1);
 750    free(srcAnnot2);
 751
 752    return s;
 753 #else
 754    return NULL;
 755 #endif
 756 }
 757
 758
 759 /**
 760  * Emit an instruction that's just a comment.
 761  */
 762 static struct prog_instruction *
 763 emit_comment(slang_emit_info *emitInfo, const char *comment)
 764 {
 765    struct prog_instruction *inst = new_instruction(emitInfo, OPCODE_NOP);
 766    inst_comment(inst, comment);
 767    return inst;
 768 }
 769
 770
 771 /**
 772  * Generate code for a simple arithmetic instruction.
 773  * Either 1, 2 or 3 operands.
 774  */
 775 static struct prog_instruction *
 776 emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
 777 {
 778    const slang_ir_info *info = _slang_ir_info(n->Opcode);
 779    struct prog_instruction *inst;
 780    GLuint i;
 781
 782    assert(info);
 783    assert(info->InstOpcode != OPCODE_NOP);
 784
 785 #if PEEPHOLE_OPTIMIZATIONS
 786    /* Look for MAD opportunity */
 787    if (info->NumParams == 2 &&
 788        n->Opcode == IR_ADD && n->Children[0]->Opcode == IR_MUL) {
 789       /* found pattern IR_ADD(IR_MUL(A, B), C) */
 790       emit(emitInfo, n->Children[0]->Children[0]);  /* A */
 791       emit(emitInfo, n->Children[0]->Children[1]);  /* B */
 792       emit(emitInfo, n->Children[1]);  /* C */
 793       alloc_node_storage(emitInfo, n, -1);  /* dest */
 794
 795       inst = emit_instruction(emitInfo,
 796                               OPCODE_MAD,
 797                               n->Store,
 798                               n->Children[0]->Children[0]->Store,
 799                               n->Children[0]->Children[1]->Store,
 800                               n->Children[1]->Store);
 801
 802       free_node_storage(emitInfo->vt, n->Children[0]->Children[0]);
 803       free_node_storage(emitInfo->vt, n->Children[0]->Children[1]);
 804       free_node_storage(emitInfo->vt, n->Children[1]);
 805       return inst;
 806    }
 807
 808    if (info->NumParams == 2 &&
 809        n->Opcode == IR_ADD && n->Children[1]->Opcode == IR_MUL) {
 810       /* found pattern IR_ADD(A, IR_MUL(B, C)) */
 811       emit(emitInfo, n->Children[0]);  /* A */
 812       emit(emitInfo, n->Children[1]->Children[0]);  /* B */
 813       emit(emitInfo, n->Children[1]->Children[1]);  /* C */
 814       alloc_node_storage(emitInfo, n, -1);  /* dest */
 815
 816       inst = emit_instruction(emitInfo,
 817                               OPCODE_MAD,
 818                               n->Store,
 819                               n->Children[1]->Children[0]->Store,
 820                               n->Children[1]->Children[1]->Store,
 821                               n->Children[0]->Store);
 822
 823       free_node_storage(emitInfo->vt, n->Children[1]->Children[0]);
 824       free_node_storage(emitInfo->vt, n->Children[1]->Children[1]);
 825       free_node_storage(emitInfo->vt, n->Children[0]);
 826       return inst;
 827    }
 828 #endif
 829
 830    /* gen code for children, may involve temp allocation */
 831    for (i = 0; i < info->NumParams; i++) {
 832       emit(emitInfo, n->Children[i]);
 833       if (!n->Children[i] || !n->Children[i]->Store) {
 834          /* error recovery */
 835          return NULL;
 836       }
 837    }
 838
 839    /* result storage */
 840    alloc_node_storage(emitInfo, n, -1);
 841
 842    inst = emit_instruction(emitInfo,
 843                            info->InstOpcode,
 844                            n->Store,  /* dest */
 845                            (info->NumParams > 0 ? n->Children[0]->Store : NULL),
 846                            (info->NumParams > 1 ? n->Children[1]->Store : NULL),
 847                            (info->NumParams > 2 ? n->Children[2]->Store : NULL)
 848                            );
 849
 850    /* free temps */
 851    for (i = 0; i < info->NumParams; i++)
 852       free_node_storage(emitInfo->vt, n->Children[i]);
 853
 854    return inst;
 855 }
 856
 857
 858 /**
 859  * Emit code for == and != operators.  These could normally be handled
 860  * by emit_arith() except we need to be able to handle structure comparisons.
 861  */
 862 static struct prog_instruction *
 863 emit_compare(slang_emit_info *emitInfo, slang_ir_node *n)
 864 {
 865    struct prog_instruction *inst = NULL;
 866    GLint size;
 867
 868    assert(n->Opcode == IR_EQUAL || n->Opcode == IR_NOTEQUAL);
 869
 870    /* gen code for children */
 871    emit(emitInfo, n->Children[0]);
 872    emit(emitInfo, n->Children[1]);
 873
 874    if (n->Children[0]->Store->Size != n->Children[1]->Store->Size) {
 875       slang_info_log_error(emitInfo->log, "invalid operands to == or !=");
 876       n->Store = NULL;
 877       return NULL;
 878    }
 879
 880    /* final result is 1 bool */
 881    if (!alloc_node_storage(emitInfo, n, 1))
 882       return NULL;
 883
 884    size = n->Children[0]->Store->Size;
 885
 886    if (size == 1) {
 887       gl_inst_opcode opcode = n->Opcode == IR_EQUAL ? OPCODE_SEQ : OPCODE_SNE;
 888       inst =  emit_instruction(emitInfo,
 889                                opcode,
 890                                n->Store, /* dest */
 891                                n->Children[0]->Store,
 892                                n->Children[1]->Store,
 893                                NULL);
 894    }
 895    else if (size <= 4) {
 896       /* compare two vectors.
 897        * Unfortunately, there's no instruction to compare vectors and
 898        * return a scalar result.  Do it with some compare and dot product
 899        * instructions...
 900        */
 901       GLuint swizzle;
 902       gl_inst_opcode dotOp;
 903       slang_ir_storage tempStore;
 904
 905       if (!alloc_local_temp(emitInfo, &tempStore, 4)) {
 906          n->Store = NULL;
 907          return NULL;
 908          /* out of temps */
 909       }
 910
 911       if (size == 4) {
 912          dotOp = OPCODE_DP4;
 913          swizzle = SWIZZLE_XYZW;
 914       }
 915       else if (size == 3) {
 916          dotOp = OPCODE_DP3;
 917          swizzle = SWIZZLE_XYZW;
 918       }
 919       else {
 920          assert(size == 2);
 921          dotOp = OPCODE_DP3; /* XXX use OPCODE_DP2 eventually */
 922          swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y);
 923       }
 924
 925       /* Compute inequality (temp = (A != B)) */
 926       inst = emit_instruction(emitInfo,
 927                               OPCODE_SNE,
 928                               &tempStore,
 929                               n->Children[0]->Store,
 930                               n->Children[1]->Store,
 931                               NULL);
 932       inst_comment(inst, "Compare values");
 933
 934       /* Compute val = DOT(temp, temp)  (reduction) */
 935       inst = emit_instruction(emitInfo,
 936                               dotOp,
 937                               n->Store,
 938                               &tempStore,
 939                               &tempStore,
 940                               NULL);
 941       inst->SrcReg[0].Swizzle = inst->SrcReg[1].Swizzle = swizzle; /*override*/
 942       inst_comment(inst, "Reduce vec to bool");
 943
 944       _slang_free_temp(emitInfo->vt, &tempStore); /* free temp */
 945
 946       if (n->Opcode == IR_EQUAL) {
 947          /* compute val = !val.x  with SEQ val, val, 0; */
 948          slang_ir_storage zero;
 949          constant_to_storage(emitInfo, 0.0, &zero);
 950          inst = emit_instruction(emitInfo,
 951                                  OPCODE_SEQ,
 952                                  n->Store, /* dest */
 953                                  n->Store,
 954                                  &zero,
 955                                  NULL);
 956          inst_comment(inst, "Invert true/false");
 957       }
 958    }
 959    else {
 960       /* size > 4, struct or array compare.
 961        * XXX this won't work reliably for structs with padding!!
 962        */
 963       GLint i, num = (n->Children[0]->Store->Size + 3) / 4;
 964       slang_ir_storage accTemp, sneTemp;
 965
 966       if (!alloc_local_temp(emitInfo, &accTemp, 4))
 967          return NULL;
 968
 969       if (!alloc_local_temp(emitInfo, &sneTemp, 4))
 970          return NULL;
 971
 972       for (i = 0; i < num; i++) {
 973          slang_ir_storage srcStore0 = *n->Children[0]->Store;
 974          slang_ir_storage srcStore1 = *n->Children[1]->Store;
 975          srcStore0.Index += i;
 976          srcStore1.Index += i;
 977
 978          if (i == 0) {
 979             /* SNE accTemp, left[i], right[i] */
 980             inst = emit_instruction(emitInfo, OPCODE_SNE,
 981                                     &accTemp, /* dest */
 982                                     &srcStore0,
 983                                     &srcStore1,
 984                                     NULL);
 985             inst_comment(inst, "Begin struct/array comparison");
 986          }
 987          else {
 988             /* SNE sneTemp, left[i], right[i] */
 989             inst = emit_instruction(emitInfo, OPCODE_SNE,
 990                                     &sneTemp, /* dest */
 991                                     &srcStore0,
 992                                     &srcStore1,
 993                                     NULL);
 994             /* ADD accTemp, accTemp, sneTemp; # like logical-OR */
 995             inst = emit_instruction(emitInfo, OPCODE_ADD,
 996                                     &accTemp, /* dest */
 997                                     &accTemp,
 998                                     &sneTemp,
 999                                     NULL);
1000          }
1001       }
1002
1003       /* compute accTemp.x || accTemp.y || accTemp.z || accTemp.w with DOT4 */
1004       inst = emit_instruction(emitInfo, OPCODE_DP4,
1005                               n->Store,
1006                               &accTemp,
1007                               &accTemp,
1008                               NULL);
1009       inst_comment(inst, "End struct/array comparison");
1010
1011       if (n->Opcode == IR_EQUAL) {
1012          /* compute tmp.x = !tmp.x  via tmp.x = (tmp.x == 0) */
1013          slang_ir_storage zero;
1014          constant_to_storage(emitInfo, 0.0, &zero);
1015          inst = emit_instruction(emitInfo, OPCODE_SEQ,
1016                                  n->Store, /* dest */
1017                                  n->Store,
1018                                  &zero,
1019                                  NULL);
1020          inst_comment(inst, "Invert true/false");
1021       }
1022
1023       _slang_free_temp(emitInfo->vt, &accTemp);
1024       _slang_free_temp(emitInfo->vt, &sneTemp);
1025    }
1026
1027    /* free temps */
1028    free_node_storage(emitInfo->vt, n->Children[0]);
1029    free_node_storage(emitInfo->vt, n->Children[1]);
1030
1031    return inst;
1032 }
1033
1034
1035
1036 /**
1037  * Generate code for an IR_CLAMP instruction.
1038  */
1039 static struct prog_instruction *
1040 emit_clamp(slang_emit_info *emitInfo, slang_ir_node *n)
1041 {
1042    struct prog_instruction *inst;
1043    slang_ir_node tmpNode;
1044
1045    assert(n->Opcode == IR_CLAMP);
1046    /* ch[0] = value
1047     * ch[1] = min limit
1048     * ch[2] = max limit
1049     */
1050
1051    inst = emit(emitInfo, n->Children[0]);
1052
1053    /* If lower limit == 0.0 and upper limit == 1.0,
1054     *    set prev instruction's SaturateMode field to SATURATE_ZERO_ONE.
1055     * Else,
1056     *    emit OPCODE_MIN, OPCODE_MAX sequence.
1057     */
1058 #if 0
1059    /* XXX this isn't quite finished yet */
1060    if (n->Children[1]->Opcode == IR_FLOAT &&
1061        n->Children[1]->Value[0] == 0.0 &&
1062        n->Children[1]->Value[1] == 0.0 &&
1063        n->Children[1]->Value[2] == 0.0 &&
1064        n->Children[1]->Value[3] == 0.0 &&
1065        n->Children[2]->Opcode == IR_FLOAT &&
1066        n->Children[2]->Value[0] == 1.0 &&
1067        n->Children[2]->Value[1] == 1.0 &&
1068        n->Children[2]->Value[2] == 1.0 &&
1069        n->Children[2]->Value[3] == 1.0) {
1070       if (!inst) {
1071          inst = prev_instruction(prog);
1072       }
1073       if (inst && inst->Opcode != OPCODE_NOP) {
1074          /* and prev instruction's DstReg matches n->Children[0]->Store */
1075          inst->SaturateMode = SATURATE_ZERO_ONE;
1076          n->Store = n->Children[0]->Store;
1077          return inst;
1078       }
1079    }
1080 #endif
1081
1082    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
1083       return NULL;
1084
1085    emit(emitInfo, n->Children[1]);
1086    emit(emitInfo, n->Children[2]);
1087
1088    /* Some GPUs don't allow reading from output registers.  So if the
1089     * dest for this clamp() is an output reg, we can't use that reg for
1090     * the intermediate result.  Use a temp register instead.
1091     */
1092    _mesa_bzero(&tmpNode, sizeof(tmpNode));
1093    alloc_node_storage(emitInfo, &tmpNode, n->Store->Size);
1094
1095    /* tmp = max(ch[0], ch[1]) */
1096    inst = emit_instruction(emitInfo, OPCODE_MAX,
1097                            tmpNode.Store, /* dest */
1098                            n->Children[0]->Store,
1099                            n->Children[1]->Store,
1100                            NULL);
1101
1102    /* n->dest = min(tmp, ch[2]) */
1103    inst = emit_instruction(emitInfo, OPCODE_MIN,
1104                            n->Store, /* dest */
1105                            tmpNode.Store,
1106                            n->Children[2]->Store,
1107                            NULL);
1108
1109    free_node_storage(emitInfo->vt, &tmpNode);
1110
1111    return inst;
1112 }
1113
1114
1115 static struct prog_instruction *
1116 emit_negation(slang_emit_info *emitInfo, slang_ir_node *n)
1117 {
1118    /* Implement as MOV dst, -src; */
1119    /* XXX we could look at the previous instruction and in some circumstances
1120     * modify it to accomplish the negation.
1121     */
1122    struct prog_instruction *inst;
1123
1124    emit(emitInfo, n->Children[0]);
1125
1126    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
1127       return NULL;
1128
1129    inst = emit_instruction(emitInfo,
1130                            OPCODE_MOV,
1131                            n->Store, /* dest */
1132                            n->Children[0]->Store,
1133                            NULL,
1134                            NULL);
1135    inst->SrcReg[0].NegateBase = NEGATE_XYZW;
1136    return inst;
1137 }
1138
1139
1140 static struct prog_instruction *
1141 emit_label(slang_emit_info *emitInfo, const slang_ir_node *n)
1142 {
1143    assert(n->Label);
1144 #if 0
1145    /* XXX this fails in loop tail code - investigate someday */
1146    assert(_slang_label_get_location(n->Label) < 0);
1147    _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
1148                              emitInfo->prog);
1149 #else
1150    if (_slang_label_get_location(n->Label) < 0)
1151       _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
1152                                 emitInfo->prog);
1153 #endif
1154    return NULL;
1155 }
1156
1157
1158 /**
1159  * Emit code for a function call.
1160  * Note that for each time a function is called, we emit the function's
1161  * body code again because the set of available registers may be different.
1162  */
1163 static struct prog_instruction *
1164 emit_fcall(slang_emit_info *emitInfo, slang_ir_node *n)
1165 {
1166    struct gl_program *progSave;
1167    struct prog_instruction *inst;
1168    GLuint subroutineId;
1169    GLuint maxInstSave;
1170
1171    assert(n->Opcode == IR_CALL);
1172    assert(n->Label);
1173
1174    /* save/push cur program */
1175    maxInstSave = emitInfo->MaxInstructions;
1176    progSave = emitInfo->prog;
1177
1178    emitInfo->prog = new_subroutine(emitInfo, &subroutineId);
1179    emitInfo->MaxInstructions = emitInfo->prog->NumInstructions;
1180
1181    _slang_label_set_location(n->Label, emitInfo->prog->NumInstructions,
1182                              emitInfo->prog);
1183
1184    if (emitInfo->EmitBeginEndSub) {
1185       /* BGNSUB isn't a real instruction.
1186        * We require a label (i.e. "foobar:") though, if we're going to
1187        * print the program in the NV format.  The BNGSUB instruction is
1188        * really just a NOP to attach the label to.
1189        */
1190       inst = new_instruction(emitInfo, OPCODE_BGNSUB);
1191       inst_comment(inst, n->Label->Name);
1192    }
1193
1194    /* body of function: */
1195    emit(emitInfo, n->Children[0]);
1196    n->Store = n->Children[0]->Store;
1197
1198    /* add RET instruction now, if needed */
1199    inst = prev_instruction(emitInfo);
1200    if (inst && inst->Opcode != OPCODE_RET) {
1201       inst = new_instruction(emitInfo, OPCODE_RET);
1202    }
1203
1204    if (emitInfo->EmitBeginEndSub) {
1205       inst = new_instruction(emitInfo, OPCODE_ENDSUB);
1206       inst_comment(inst, n->Label->Name);
1207    }
1208
1209    /* pop/restore cur program */
1210    emitInfo->prog = progSave;
1211    emitInfo->MaxInstructions = maxInstSave;
1212
1213    /* emit the function call */
1214    inst = new_instruction(emitInfo, OPCODE_CAL);
1215    /* The branch target is just the subroutine number (changed later) */
1216    inst->BranchTarget = subroutineId;
1217    inst_comment(inst, n->Label->Name);
1218    assert(inst->BranchTarget >= 0);
1219
1220    return inst;
1221 }
1222
1223
1224 /**
1225  * Emit code for a 'return' statement.
1226  */
1227 static struct prog_instruction *
1228 emit_return(slang_emit_info *emitInfo, slang_ir_node *n)
1229 {
1230    struct prog_instruction *inst;
1231    assert(n);
1232    assert(n->Opcode == IR_RETURN);
1233    assert(n->Label);
1234    inst = new_instruction(emitInfo, OPCODE_RET);
1235    inst->DstReg.CondMask = COND_TR;  /* always return */
1236    return inst;
1237 }
1238
1239
1240 static struct prog_instruction *
1241 emit_kill(slang_emit_info *emitInfo)
1242 {
1243    struct gl_fragment_program *fp;
1244    struct prog_instruction *inst;
1245    /* NV-KILL - discard fragment depending on condition code.
1246     * Note that ARB-KILL depends on sign of vector operand.
1247     */
1248    inst = new_instruction(emitInfo, OPCODE_KIL_NV);
1249    inst->DstReg.CondMask = COND_TR;  /* always kill */
1250
1251    assert(emitInfo->prog->Target == GL_FRAGMENT_PROGRAM_ARB);
1252    fp = (struct gl_fragment_program *) emitInfo->prog;
1253    fp->UsesKill = GL_TRUE;
1254
1255    return inst;
1256 }
1257
1258
1259 static struct prog_instruction *
1260 emit_tex(slang_emit_info *emitInfo, slang_ir_node *n)
1261 {
1262    struct prog_instruction *inst;
1263    gl_inst_opcode opcode;
1264
1265    if (n->Opcode == IR_TEX) {
1266       opcode = OPCODE_TEX;
1267    }
1268    else if (n->Opcode == IR_TEXB) {
1269       opcode = OPCODE_TXB;
1270    }
1271    else {
1272       assert(n->Opcode == IR_TEXP);
1273       opcode = OPCODE_TXP;
1274    }
1275
1276    if (n->Children[0]->Opcode == IR_ELEMENT) {
1277       /* array is the sampler (a uniform which'll indicate the texture unit) */
1278       assert(n->Children[0]->Children[0]->Store);
1279       assert(n->Children[0]->Children[0]->Store->File == PROGRAM_SAMPLER);
1280
1281       emit(emitInfo, n->Children[0]);
1282
1283       n->Children[0]->Var = n->Children[0]->Children[0]->Var;
1284    } else {
1285       /* this is the sampler (a uniform which'll indicate the texture unit) */
1286       assert(n->Children[0]->Store);
1287       assert(n->Children[0]->Store->File == PROGRAM_SAMPLER);
1288    }
1289
1290    /* emit code for the texcoord operand */
1291    (void) emit(emitInfo, n->Children[1]);
1292
1293    /* alloc storage for result of texture fetch */
1294    if (!alloc_node_storage(emitInfo, n, 4))
1295       return NULL;
1296
1297    /* emit TEX instruction;  Child[1] is the texcoord */
1298    inst = emit_instruction(emitInfo,
1299                            opcode,
1300                            n->Store,
1301                            n->Children[1]->Store,
1302                            NULL,
1303                            NULL);
1304
1305    /* Store->Index is the uniform/sampler index */
1306    assert(n->Children[0]->Store->Index >= 0);
1307    inst->TexSrcUnit = n->Children[0]->Store->Index;
1308    inst->TexSrcTarget = n->Children[0]->Store->TexTarget;
1309
1310    /* mark the sampler as being used */
1311    _mesa_use_uniform(emitInfo->prog->Parameters,
1312                      (char *) n->Children[0]->Var->a_name);
1313
1314    return inst;
1315 }
1316
1317
1318 /**
1319  * Assignment/copy
1320  */
1321 static struct prog_instruction *
1322 emit_copy(slang_emit_info *emitInfo, slang_ir_node *n)
1323 {
1324    struct prog_instruction *inst;
1325
1326    assert(n->Opcode == IR_COPY);
1327
1328    /* lhs */
1329    emit(emitInfo, n->Children[0]);
1330    if (!n->Children[0]->Store || n->Children[0]->Store->Index < 0) {
1331       /* an error should have been already recorded */
1332       return NULL;
1333    }
1334
1335    /* rhs */
1336    assert(n->Children[1]);
1337    inst = emit(emitInfo, n->Children[1]);
1338
1339    if (!n->Children[1]->Store || n->Children[1]->Store->Index < 0) {
1340       if (!emitInfo->log->text) {
1341          slang_info_log_error(emitInfo->log, "invalid assignment");
1342       }
1343       return NULL;
1344    }
1345
1346    assert(n->Children[1]->Store->Index >= 0);
1347
1348    /*assert(n->Children[0]->Store->Size == n->Children[1]->Store->Size);*/
1349
1350    n->Store = n->Children[0]->Store;
1351
1352    if (n->Store->File == PROGRAM_SAMPLER) {
1353       /* no code generated for sampler assignments,
1354        * just copy the sampler index/target at compile time.
1355        */
1356       n->Store->Index = n->Children[1]->Store->Index;
1357       n->Store->TexTarget = n->Children[1]->Store->TexTarget;
1358       return NULL;
1359    }
1360
1361 #if PEEPHOLE_OPTIMIZATIONS
1362    if (inst &&
1363        _slang_is_temp(emitInfo->vt, n->Children[1]->Store) &&
1364        (inst->DstReg.File == n->Children[1]->Store->File) &&
1365        (inst->DstReg.Index == n->Children[1]->Store->Index) &&
1366        !n->Children[0]->Store->IsIndirect &&
1367        n->Children[0]->Store->Size <= 4) {
1368       /* Peephole optimization:
1369        * The Right-Hand-Side has its results in a temporary place.
1370        * Modify the RHS (and the prev instruction) to store its results
1371        * in the destination specified by n->Children[0].
1372        * Then, this MOVE is a no-op.
1373        * Ex:
1374        *   MUL tmp, x, y;
1375        *   MOV a, tmp;
1376        * becomes:
1377        *   MUL a, x, y;
1378        */
1379       if (n->Children[1]->Opcode != IR_SWIZZLE)
1380          _slang_free_temp(emitInfo->vt, n->Children[1]->Store);
1381       *n->Children[1]->Store = *n->Children[0]->Store;
1382
1383       /* fixup the previous instruction (which stored the RHS result) */
1384       assert(n->Children[0]->Store->Index >= 0);
1385
1386       storage_to_dst_reg(&inst->DstReg, n->Children[0]->Store);
1387       return inst;
1388    }
1389    else
1390 #endif
1391    {
1392       if (n->Children[0]->Store->Size > 4) {
1393          /* move matrix/struct etc (block of registers) */
1394          slang_ir_storage dstStore = *n->Children[0]->Store;
1395          slang_ir_storage srcStore = *n->Children[1]->Store;
1396          GLint size = srcStore.Size;
1397          ASSERT(n->Children[1]->Store->Swizzle == SWIZZLE_NOOP);
1398          dstStore.Size = 4;
1399          srcStore.Size = 4;
1400          while (size >= 4) {
1401             inst = emit_instruction(emitInfo, OPCODE_MOV,
1402                                     &dstStore,
1403                                     &srcStore,
1404                                     NULL,
1405                                     NULL);
1406             inst_comment(inst, "IR_COPY block");
1407             srcStore.Index++;
1408             dstStore.Index++;
1409             size -= 4;
1410          }
1411       }
1412       else {
1413          /* single register move */
1414          char *srcAnnot, *dstAnnot;
1415          assert(n->Children[0]->Store->Index >= 0);
1416          inst = emit_instruction(emitInfo, OPCODE_MOV,
1417                                  n->Children[0]->Store, /* dest */
1418                                  n->Children[1]->Store,
1419                                  NULL,
1420                                  NULL);
1421          dstAnnot = storage_annotation(n->Children[0], emitInfo->prog);
1422          srcAnnot = storage_annotation(n->Children[1], emitInfo->prog);
1423          inst->Comment = instruction_annotation(inst->Opcode, dstAnnot,
1424                                                 srcAnnot, NULL, NULL);
1425       }
1426       free_node_storage(emitInfo->vt, n->Children[1]);
1427       return inst;
1428    }
1429 }
1430
1431
1432 /**
1433  * An IR_COND node wraps a boolean expression which is used by an
1434  * IF or WHILE test.  This is where we'll set condition codes, if needed.
1435  */
1436 static struct prog_instruction *
1437 emit_cond(slang_emit_info *emitInfo, slang_ir_node *n)
1438 {
1439    struct prog_instruction *inst;
1440
1441    assert(n->Opcode == IR_COND);
1442
1443    if (!n->Children[0])
1444       return NULL;
1445
1446    /* emit code for the expression */
1447    inst = emit(emitInfo, n->Children[0]);
1448
1449    if (!n->Children[0]->Store) {
1450       /* error recovery */
1451       return NULL;
1452    }
1453
1454    assert(n->Children[0]->Store);
1455    /*assert(n->Children[0]->Store->Size == 1);*/
1456
1457    if (emitInfo->EmitCondCodes) {
1458       if (inst &&
1459           n->Children[0]->Store &&
1460           inst->DstReg.File == n->Children[0]->Store->File &&
1461           inst->DstReg.Index == n->Children[0]->Store->Index) {
1462          /* The previous instruction wrote to the register who's value
1463           * we're testing.  Just fix that instruction so that the
1464           * condition codes are computed.
1465           */
1466          inst->CondUpdate = GL_TRUE;
1467          n->Store = n->Children[0]->Store;
1468          return inst;
1469       }
1470       else {
1471          /* This'll happen for things like "if (i) ..." where no code
1472           * is normally generated for the expression "i".
1473           * Generate a move instruction just to set condition codes.
1474           */
1475          if (!alloc_node_storage(emitInfo, n, 1))
1476             return NULL;
1477          inst = emit_instruction(emitInfo, OPCODE_MOV,
1478                                  n->Store, /* dest */
1479                                  n->Children[0]->Store,
1480                                  NULL,
1481                                  NULL);
1482          inst->CondUpdate = GL_TRUE;
1483          inst_comment(inst, "COND expr");
1484          _slang_free_temp(emitInfo->vt, n->Store);
1485          return inst;
1486       }
1487    }
1488    else {
1489       /* No-op: the boolean result of the expression is in a regular reg */
1490       n->Store = n->Children[0]->Store;
1491       return inst;
1492    }
1493 }
1494
1495
1496 /**
1497  * Logical-NOT
1498  */
1499 static struct prog_instruction *
1500 emit_not(slang_emit_info *emitInfo, slang_ir_node *n)
1501 {
1502    static const struct {
1503       gl_inst_opcode op, opNot;
1504    } operators[] = {
1505       { OPCODE_SLT, OPCODE_SGE },
1506       { OPCODE_SLE, OPCODE_SGT },
1507       { OPCODE_SGT, OPCODE_SLE },
1508       { OPCODE_SGE, OPCODE_SLT },
1509       { OPCODE_SEQ, OPCODE_SNE },
1510       { OPCODE_SNE, OPCODE_SEQ },
1511       { 0, 0 }
1512    };
1513    struct prog_instruction *inst;
1514    slang_ir_storage zero;
1515    GLuint i;
1516
1517    /* child expr */
1518    inst = emit(emitInfo, n->Children[0]);
1519
1520 #if PEEPHOLE_OPTIMIZATIONS
1521    if (inst) {
1522       /* if the prev instruction was a comparison instruction, invert it */
1523       for (i = 0; operators[i].op; i++) {
1524          if (inst->Opcode == operators[i].op) {
1525             inst->Opcode = operators[i].opNot;
1526             n->Store = n->Children[0]->Store;
1527             return inst;
1528          }
1529       }
1530    }
1531 #endif
1532
1533    /* else, invert using SEQ (v = v == 0) */
1534    if (!alloc_node_storage(emitInfo, n, n->Children[0]->Store->Size))
1535       return NULL;
1536
1537    constant_to_storage(emitInfo, 0.0, &zero);
1538    inst = emit_instruction(emitInfo,
1539                            OPCODE_SEQ,
1540                            n->Store,
1541                            n->Children[0]->Store,
1542                            &zero,
1543                            NULL);
1544    inst_comment(inst, "NOT");
1545
1546    free_node_storage(emitInfo->vt, n->Children[0]);
1547
1548    return inst;
1549 }
1550
1551
1552 static struct prog_instruction *
1553 emit_if(slang_emit_info *emitInfo, slang_ir_node *n)
1554 {
1555    struct gl_program *prog = emitInfo->prog;
1556    GLuint ifInstLoc, elseInstLoc = 0;
1557    GLuint condWritemask = 0;
1558
1559    /* emit condition expression code */
1560    {
1561       struct prog_instruction *inst;
1562       inst = emit(emitInfo, n->Children[0]);
1563       if (emitInfo->EmitCondCodes) {
1564          if (!inst) {
1565             /* error recovery */
1566             return NULL;
1567          }
1568          condWritemask = inst->DstReg.WriteMask;
1569       }
1570    }
1571
1572    if (!n->Children[0]->Store)
1573       return NULL;
1574
1575 #if 0
1576    assert(n->Children[0]->Store->Size == 1); /* a bool! */
1577 #endif
1578
1579    ifInstLoc = prog->NumInstructions;
1580    if (emitInfo->EmitHighLevelInstructions) {
1581       if (emitInfo->EmitCondCodes) {
1582          /* IF condcode THEN ... */
1583          struct prog_instruction *ifInst;
1584          ifInst = new_instruction(emitInfo, OPCODE_IF);
1585          ifInst->DstReg.CondMask = COND_NE;  /* if cond is non-zero */
1586          /* only test the cond code (1 of 4) that was updated by the
1587           * previous instruction.
1588           */
1589          ifInst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1590       }
1591       else {
1592          /* IF src[0] THEN ... */
1593          emit_instruction(emitInfo, OPCODE_IF,
1594                           NULL, /* dst */
1595                           n->Children[0]->Store, /* op0 */
1596                           NULL,
1597                           NULL);
1598       }
1599    }
1600    else {
1601       /* conditional jump to else, or endif */
1602       struct prog_instruction *ifInst = new_instruction(emitInfo, OPCODE_BRA);
1603       ifInst->DstReg.CondMask = COND_EQ;  /* BRA if cond is zero */
1604       inst_comment(ifInst, "if zero");
1605       ifInst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1606    }
1607
1608    /* if body */
1609    emit(emitInfo, n->Children[1]);
1610
1611    if (n->Children[2]) {
1612       /* have else body */
1613       elseInstLoc = prog->NumInstructions;
1614       if (emitInfo->EmitHighLevelInstructions) {
1615          (void) new_instruction(emitInfo, OPCODE_ELSE);
1616       }
1617       else {
1618          /* jump to endif instruction */
1619          struct prog_instruction *inst;
1620          inst = new_instruction(emitInfo, OPCODE_BRA);
1621          inst_comment(inst, "else");
1622          inst->DstReg.CondMask = COND_TR;  /* always branch */
1623       }
1624       prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
1625       emit(emitInfo, n->Children[2]);
1626    }
1627    else {
1628       /* no else body */
1629       prog->Instructions[ifInstLoc].BranchTarget = prog->NumInstructions;
1630    }
1631
1632    if (emitInfo->EmitHighLevelInstructions) {
1633       (void) new_instruction(emitInfo, OPCODE_ENDIF);
1634    }
1635
1636    if (n->Children[2]) {
1637       prog->Instructions[elseInstLoc].BranchTarget = prog->NumInstructions;
1638    }
1639    return NULL;
1640 }
1641
1642
1643 static struct prog_instruction *
1644 emit_loop(slang_emit_info *emitInfo, slang_ir_node *n)
1645 {
1646    struct gl_program *prog = emitInfo->prog;
1647    struct prog_instruction *endInst;
1648    GLuint beginInstLoc, tailInstLoc, endInstLoc;
1649    slang_ir_node *ir;
1650
1651    /* emit OPCODE_BGNLOOP */
1652    beginInstLoc = prog->NumInstructions;
1653    if (emitInfo->EmitHighLevelInstructions) {
1654       (void) new_instruction(emitInfo, OPCODE_BGNLOOP);
1655    }
1656
1657    /* body */
1658    emit(emitInfo, n->Children[0]);
1659
1660    /* tail */
1661    tailInstLoc = prog->NumInstructions;
1662    if (n->Children[1]) {
1663       if (emitInfo->EmitComments)
1664          emit_comment(emitInfo, "Loop tail code:");
1665       emit(emitInfo, n->Children[1]);
1666    }
1667
1668    endInstLoc = prog->NumInstructions;
1669    if (emitInfo->EmitHighLevelInstructions) {
1670       /* emit OPCODE_ENDLOOP */
1671       endInst = new_instruction(emitInfo, OPCODE_ENDLOOP);
1672    }
1673    else {
1674       /* emit unconditional BRA-nch */
1675       endInst = new_instruction(emitInfo, OPCODE_BRA);
1676       endInst->DstReg.CondMask = COND_TR;  /* always true */
1677    }
1678    /* ENDLOOP's BranchTarget points to the BGNLOOP inst */
1679    endInst->BranchTarget = beginInstLoc;
1680
1681    if (emitInfo->EmitHighLevelInstructions) {
1682       /* BGNLOOP's BranchTarget points to the ENDLOOP inst */
1683       prog->Instructions[beginInstLoc].BranchTarget = prog->NumInstructions -1;
1684    }
1685
1686    /* Done emitting loop code.  Now walk over the loop's linked list of
1687     * BREAK and CONT nodes, filling in their BranchTarget fields (which
1688     * will point to the ENDLOOP+1 or BGNLOOP instructions, respectively).
1689     */
1690    for (ir = n->List; ir; ir = ir->List) {
1691       struct prog_instruction *inst = prog->Instructions + ir->InstLocation;
1692       assert(inst->BranchTarget < 0);
1693       if (ir->Opcode == IR_BREAK ||
1694           ir->Opcode == IR_BREAK_IF_TRUE) {
1695          assert(inst->Opcode == OPCODE_BRK ||
1696                 inst->Opcode == OPCODE_BRA);
1697          /* go to instruction after end of loop */
1698          inst->BranchTarget = endInstLoc + 1;
1699       }
1700       else {
1701          assert(ir->Opcode == IR_CONT ||
1702                 ir->Opcode == IR_CONT_IF_TRUE);
1703          assert(inst->Opcode == OPCODE_CONT ||
1704                 inst->Opcode == OPCODE_BRA);
1705          /* go to instruction at tail of loop */
1706          inst->BranchTarget = endInstLoc;
1707       }
1708    }
1709    return NULL;
1710 }
1711
1712
1713 /**
1714  * Unconditional "continue" or "break" statement.
1715  * Either OPCODE_CONT, OPCODE_BRK or OPCODE_BRA will be emitted.
1716  */
1717 static struct prog_instruction *
1718 emit_cont_break(slang_emit_info *emitInfo, slang_ir_node *n)
1719 {
1720    gl_inst_opcode opcode;
1721    struct prog_instruction *inst;
1722
1723    if (n->Opcode == IR_CONT) {
1724       /* we need to execute the loop's tail code before doing CONT */
1725       assert(n->Parent);
1726       assert(n->Parent->Opcode == IR_LOOP);
1727       if (n->Parent->Children[1]) {
1728          /* emit tail code */
1729          if (emitInfo->EmitComments) {
1730             emit_comment(emitInfo, "continue - tail code:");
1731          }
1732          emit(emitInfo, n->Parent->Children[1]);
1733       }
1734    }
1735
1736    /* opcode selection */
1737    if (emitInfo->EmitHighLevelInstructions) {
1738       opcode = (n->Opcode == IR_CONT) ? OPCODE_CONT : OPCODE_BRK;
1739    }
1740    else {
1741       opcode = OPCODE_BRA;
1742    }
1743    n->InstLocation = emitInfo->prog->NumInstructions;
1744    inst = new_instruction(emitInfo, opcode);
1745    inst->DstReg.CondMask = COND_TR;  /* always true */
1746    return inst;
1747 }
1748
1749
1750 /**
1751  * Conditional "continue" or "break" statement.
1752  * Either OPCODE_CONT, OPCODE_BRK or OPCODE_BRA will be emitted.
1753  */
1754 static struct prog_instruction *
1755 emit_cont_break_if_true(slang_emit_info *emitInfo, slang_ir_node *n)
1756 {
1757    struct prog_instruction *inst;
1758
1759    assert(n->Opcode == IR_CONT_IF_TRUE ||
1760           n->Opcode == IR_BREAK_IF_TRUE);
1761
1762    /* evaluate condition expr, setting cond codes */
1763    inst = emit(emitInfo, n->Children[0]);
1764    if (emitInfo->EmitCondCodes) {
1765       assert(inst);
1766       inst->CondUpdate = GL_TRUE;
1767    }
1768
1769    n->InstLocation = emitInfo->prog->NumInstructions;
1770
1771    /* opcode selection */
1772    if (emitInfo->EmitHighLevelInstructions) {
1773       const gl_inst_opcode opcode
1774          = (n->Opcode == IR_CONT_IF_TRUE) ? OPCODE_CONT : OPCODE_BRK;
1775       if (emitInfo->EmitCondCodes) {
1776          /* Get the writemask from the previous instruction which set
1777           * the condcodes.  Use that writemask as the CondSwizzle.
1778           */
1779          const GLuint condWritemask = inst->DstReg.WriteMask;
1780          inst = new_instruction(emitInfo, opcode);
1781          inst->DstReg.CondMask = COND_NE;
1782          inst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1783          return inst;
1784       }
1785       else {
1786          /* IF reg
1787           *    BRK/CONT;
1788           * ENDIF
1789           */
1790          GLint ifInstLoc;
1791          ifInstLoc = emitInfo->prog->NumInstructions;
1792          inst = emit_instruction(emitInfo, OPCODE_IF,
1793                                  NULL, /* dest */
1794                                  n->Children[0]->Store,
1795                                  NULL,
1796                                  NULL);
1797          n->InstLocation = emitInfo->prog->NumInstructions;
1798
1799          inst = new_instruction(emitInfo, opcode);
1800          inst = new_instruction(emitInfo, OPCODE_ENDIF);
1801
1802          emitInfo->prog->Instructions[ifInstLoc].BranchTarget
1803             = emitInfo->prog->NumInstructions;
1804          return inst;
1805       }
1806    }
1807    else {
1808       const GLuint condWritemask = inst->DstReg.WriteMask;
1809       assert(emitInfo->EmitCondCodes);
1810       inst = new_instruction(emitInfo, OPCODE_BRA);
1811       inst->DstReg.CondMask = COND_NE;
1812       inst->DstReg.CondSwizzle = writemask_to_swizzle(condWritemask);
1813       return inst;
1814    }
1815 }
1816
1817
1818 /**
1819  * Return the size of a swizzle mask given that some swizzle components
1820  * may be NIL/undefined.  For example:
1821  *  swizzle_size(".zzxx") = 4
1822  *  swizzle_size(".xy??") = 2
1823  *  swizzle_size(".w???") = 1
1824  */
1825 static GLuint
1826 swizzle_size(GLuint swizzle)
1827 {
1828    GLuint i;
1829    for (i = 0; i < 4; i++) {
1830       if (GET_SWZ(swizzle, i) == SWIZZLE_NIL)
1831          return i;
1832    }
1833    return 4;
1834 }
1835
1836
1837 static struct prog_instruction *
1838 emit_swizzle(slang_emit_info *emitInfo, slang_ir_node *n)
1839 {
1840    struct prog_instruction *inst;
1841
1842    inst = emit(emitInfo, n->Children[0]);
1843
1844    if (n->Children[0]->Opcode == IR_VAR ||
1845        n->Children[0]->Opcode == IR_SWIZZLE ||
1846        n->Children[0]->Opcode == IR_ELEMENT) {
1847       /* We can resolve the swizzle now.  Other swizzles will be resolved
1848        * in storage_to_src_reg().
1849        */
1850       const GLuint swizzle = n->Store->Swizzle;
1851       assert(n->Store->Parent);
1852       /* new storage is parent storage with updated Swizzle + Size fields */
1853       _slang_copy_ir_storage(n->Store, n->Store->Parent);
1854       /* Apply this node's swizzle to parent's storage */
1855       n->Store->Swizzle = _slang_swizzle_swizzle(n->Store->Swizzle, swizzle);
1856       /* Update size */
1857       n->Store->Size = swizzle_size(n->Store->Swizzle);
1858       assert(!n->Store->Parent);
1859       assert(n->Store->Index >= 0);
1860    }
1861
1862    return inst;
1863 }
1864
1865
1866 /**
1867  * Dereference array element:  element == array[index]
1868  * This basically involves emitting code for computing the array index
1869  * and updating the node/element's storage info.
1870  */
1871 static struct prog_instruction *
1872 emit_array_element(slang_emit_info *emitInfo, slang_ir_node *n)
1873 {
1874    slang_ir_storage *arrayStore, *indexStore;
1875    const int elemSize = n->Store->Size;           /* number of floats */
1876    const GLint elemSizeVec = (elemSize + 3) / 4;  /* number of vec4 */
1877    struct prog_instruction *inst;
1878
1879    assert(n->Opcode == IR_ELEMENT);
1880    assert(elemSize > 0);
1881
1882    /* special case for built-in state variables, like light state */
1883    {
1884       slang_ir_storage *root = n->Store;
1885       assert(!root->Parent);
1886       while (root->Parent)
1887          root = root->Parent;
1888
1889       if (root->File == PROGRAM_STATE_VAR) {
1890          GLboolean direct;
1891          GLint index =
1892             _slang_alloc_statevar(n, emitInfo->prog->Parameters, &direct);
1893          if (index < 0) {
1894             /* error */
1895             return NULL;
1896          }
1897          if (direct) {
1898             n->Store->Index = index;
1899             return NULL; /* all done */
1900          }
1901       }
1902    }
1903
1904    /* do codegen for array itself */
1905    emit(emitInfo, n->Children[0]);
1906    arrayStore = n->Children[0]->Store;
1907
1908    /* The initial array element storage is the array's storage,
1909     * then modified below.
1910     */
1911    _slang_copy_ir_storage(n->Store, arrayStore);
1912
1913
1914    if (n->Children[1]->Opcode == IR_FLOAT) {
1915       /* Constant array index */
1916       const GLint element = (GLint) n->Children[1]->Value[0];
1917
1918       /* this element's storage is the array's storage, plus constant offset */
1919       n->Store->Index += elemSizeVec * element;
1920    }
1921    else {
1922       /* Variable array index */
1923
1924       /* do codegen for array index expression */
1925       emit(emitInfo, n->Children[1]);
1926       indexStore = n->Children[1]->Store;
1927
1928       if (indexStore->IsIndirect) {
1929          /* need to put the array index into a temporary since we can't
1930           * directly support a[b[i]] constructs.
1931           */
1932
1933
1934          /*indexStore = tempstore();*/
1935       }
1936
1937
1938       if (elemSize > 4) {
1939          /* need to multiply array index by array element size */
1940          struct prog_instruction *inst;
1941          slang_ir_storage *indexTemp;
1942          slang_ir_storage elemSizeStore;
1943
1944          /* allocate 1 float indexTemp */
1945          indexTemp = _slang_new_ir_storage(PROGRAM_TEMPORARY, -1, 1);
1946          _slang_alloc_temp(emitInfo->vt, indexTemp);
1947
1948          /* allocate a constant containing the element size */
1949          constant_to_storage(emitInfo, (float) elemSizeVec, &elemSizeStore);
1950
1951          /* multiply array index by element size */
1952          inst = emit_instruction(emitInfo,
1953                                  OPCODE_MUL,
1954                                  indexTemp, /* dest */
1955                                  indexStore, /* the index */
1956                                  &elemSizeStore,
1957                                  NULL);
1958
1959          indexStore = indexTemp;
1960       }
1961
1962       if (arrayStore->IsIndirect) {
1963          /* ex: in a[i][j], a[i] (the arrayStore) is indirect */
1964          /* Need to add indexStore to arrayStore->Indirect store */
1965          slang_ir_storage indirectArray;
1966          slang_ir_storage *indexTemp;
1967
1968          _slang_init_ir_storage(&indirectArray,
1969                                 arrayStore->IndirectFile,
1970                                 arrayStore->IndirectIndex,
1971                                 1,
1972                                 arrayStore->IndirectSwizzle);
1973
1974          /* allocate 1 float indexTemp */
1975          indexTemp = _slang_new_ir_storage(PROGRAM_TEMPORARY, -1, 1);
1976          _slang_alloc_temp(emitInfo->vt, indexTemp);
1977
1978          inst = emit_instruction(emitInfo,
1979                                  OPCODE_ADD,
1980                                  indexTemp,      /* dest */
1981                                  indexStore,     /* the index */
1982                                  &indirectArray, /* indirect array base */
1983                                  NULL);
1984
1985          indexStore = indexTemp;
1986       }
1987
1988       /* update the array element storage info */
1989       n->Store->IsIndirect = GL_TRUE;
1990       n->Store->IndirectFile = indexStore->File;
1991       n->Store->IndirectIndex = indexStore->Index;
1992       n->Store->IndirectSwizzle = indexStore->Swizzle;
1993    }
1994
1995    n->Store->Size = elemSize;
1996    n->Store->Swizzle = _slang_var_swizzle(elemSize, 0);
1997
1998    return NULL; /* no instruction */
1999 }
2000
2001
2002 /**
2003  * Resolve storage for accessing a structure field.
2004  */
2005 static struct prog_instruction *
2006 emit_struct_field(slang_emit_info *emitInfo, slang_ir_node *n)
2007 {
2008    slang_ir_storage *root = n->Store;
2009    GLint fieldOffset, fieldSize;
2010
2011    assert(n->Opcode == IR_FIELD);
2012
2013    assert(!root->Parent);
2014    while (root->Parent)
2015       root = root->Parent;
2016
2017    /* If this is the field of a state var, allocate constant/uniform
2018     * storage for it now if we haven't already.
2019     * Note that we allocate storage (uniform/constant slots) for state
2020     * variables here rather than at declaration time so we only allocate
2021     * space for the ones that we actually use!
2022     */
2023    if (root->File == PROGRAM_STATE_VAR) {
2024       GLboolean direct;
2025       GLint index = _slang_alloc_statevar(n, emitInfo->prog->Parameters, &direct);
2026       if (index < 0) {
2027          slang_info_log_error(emitInfo->log, "Error parsing state variable");
2028          return NULL;
2029       }
2030       if (direct) {
2031          root->Index = index;
2032          return NULL; /* all done */
2033       }
2034    }
2035
2036    /* do codegen for struct */
2037    emit(emitInfo, n->Children[0]);
2038    assert(n->Children[0]->Store->Index >= 0);
2039
2040
2041    fieldOffset = n->Store->Index;
2042    fieldSize = n->Store->Size;
2043
2044    _slang_copy_ir_storage(n->Store, n->Children[0]->Store);
2045
2046    n->Store->Index = n->Children[0]->Store->Index + fieldOffset / 4;
2047    n->Store->Size = fieldSize;
2048
2049    switch (fieldSize) {
2050    case 1:
2051       {
2052          GLint swz = fieldOffset % 4;
2053          n->Store->Swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
2054       }
2055       break;
2056    case 2:
2057       n->Store->Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
2058                                         SWIZZLE_NIL, SWIZZLE_NIL);
2059       break;
2060    case 3:
2061       n->Store->Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
2062                                         SWIZZLE_Z, SWIZZLE_NIL);
2063       break;
2064    default:
2065       n->Store->Swizzle = SWIZZLE_XYZW;
2066    }
2067
2068    assert(n->Store->Index >= 0);
2069
2070    return NULL; /* no instruction */
2071 }
2072
2073
2074 /**
2075  * Emit code for a variable declaration.
2076  * This usually doesn't result in any code generation, but just
2077  * memory allocation.
2078  */
2079 static struct prog_instruction *
2080 emit_var_decl(slang_emit_info *emitInfo, slang_ir_node *n)
2081 {
2082    assert(n->Store);
2083    assert(n->Store->File != PROGRAM_UNDEFINED);
2084    assert(n->Store->Size > 0);
2085    /*assert(n->Store->Index < 0);*/
2086
2087    if (!n->Var || n->Var->isTemp) {
2088       /* a nameless/temporary variable, will be freed after first use */
2089       /*NEW*/
2090       if (n->Store->Index < 0 && !_slang_alloc_temp(emitInfo->vt, n->Store)) {
2091          slang_info_log_error(emitInfo->log,
2092                               "Ran out of registers, too many temporaries");
2093          return NULL;
2094       }
2095    }
2096    else {
2097       /* a regular variable */
2098       _slang_add_variable(emitInfo->vt, n->Var);
2099       if (!_slang_alloc_var(emitInfo->vt, n->Store)) {
2100          slang_info_log_error(emitInfo->log,
2101                               "Ran out of registers, too many variables");
2102          return NULL;
2103       }
2104       /*
2105         printf("IR_VAR_DECL %s %d store %p\n",
2106         (char*) n->Var->a_name, n->Store->Index, (void*) n->Store);
2107       */
2108       assert(n->Var->store == n->Store);
2109    }
2110    if (emitInfo->EmitComments) {
2111       /* emit NOP with comment describing the variable's storage location */
2112       char s[1000];
2113       sprintf(s, "TEMP[%d]%s = variable %s (size %d)",
2114               n->Store->Index,
2115               _mesa_swizzle_string(n->Store->Swizzle, 0, GL_FALSE),
2116               (n->Var ? (char *) n->Var->a_name : "anonymous"),
2117               n->Store->Size);
2118       emit_comment(emitInfo, s);
2119    }
2120    return NULL;
2121 }
2122
2123
2124 /**
2125  * Emit code for a reference to a variable.
2126  * Actually, no code is generated but we may do some memory allocation.
2127  * In particular, state vars (uniforms) are allocated on an as-needed basis.
2128  */
2129 static struct prog_instruction *
2130 emit_var_ref(slang_emit_info *emitInfo, slang_ir_node *n)
2131 {
2132    assert(n->Store);
2133    assert(n->Store->File != PROGRAM_UNDEFINED);
2134
2135    if (n->Store->File == PROGRAM_STATE_VAR && n->Store->Index < 0) {
2136       GLboolean direct;
2137       GLint index = _slang_alloc_statevar(n, emitInfo->prog->Parameters, &direct);
2138       if (index < 0) {
2139          /* error */
2140          char s[100];
2141          _mesa_snprintf(s, sizeof(s), "Undefined variable '%s'",
2142                         (char *) n->Var->a_name);
2143          slang_info_log_error(emitInfo->log, s);
2144          return NULL;
2145       }
2146
2147       n->Store->Index = index;
2148    }
2149    else if (n->Store->File == PROGRAM_UNIFORM ||
2150             n->Store->File == PROGRAM_SAMPLER) {
2151       /* mark var as used */
2152       _mesa_use_uniform(emitInfo->prog->Parameters, (char *) n->Var->a_name);
2153    }
2154    else if (n->Store->File == PROGRAM_INPUT) {
2155       assert(n->Store->Index >= 0);
2156       emitInfo->prog->InputsRead |= (1 << n->Store->Index);
2157    }
2158
2159    if (n->Store->Index < 0) {
2160       /* probably ran out of registers */
2161       return NULL;
2162    }
2163    assert(n->Store->Size > 0);
2164
2165    return NULL;
2166 }
2167
2168
2169 static struct prog_instruction *
2170 emit(slang_emit_info *emitInfo, slang_ir_node *n)
2171 {
2172    struct prog_instruction *inst;
2173    if (!n)
2174       return NULL;
2175
2176    if (emitInfo->log->error_flag) {
2177       return NULL;
2178    }
2179
2180    switch (n->Opcode) {
2181    case IR_SEQ:
2182       /* sequence of two sub-trees */
2183       assert(n->Children[0]);
2184       assert(n->Children[1]);
2185       emit(emitInfo, n->Children[0]);
2186       if (emitInfo->log->error_flag)
2187          return NULL;
2188       inst = emit(emitInfo, n->Children[1]);
2189 #if 0
2190       assert(!n->Store);
2191 #endif
2192       n->Store = n->Children[1]->Store;
2193       return inst;
2194
2195    case IR_SCOPE:
2196       /* new variable scope */
2197       _slang_push_var_table(emitInfo->vt);
2198       inst = emit(emitInfo, n->Children[0]);
2199       _slang_pop_var_table(emitInfo->vt);
2200       return inst;
2201
2202    case IR_VAR_DECL:
2203       /* Variable declaration - allocate a register for it */
2204       inst = emit_var_decl(emitInfo, n);
2205       return inst;
2206
2207    case IR_VAR:
2208       /* Reference to a variable
2209        * Storage should have already been resolved/allocated.
2210        */
2211       return emit_var_ref(emitInfo, n);
2212
2213    case IR_ELEMENT:
2214       return emit_array_element(emitInfo, n);
2215    case IR_FIELD:
2216       return emit_struct_field(emitInfo, n);
2217    case IR_SWIZZLE:
2218       return emit_swizzle(emitInfo, n);
2219
2220    /* Simple arithmetic */
2221    /* unary */
2222    case IR_MOVE:
2223    case IR_RSQ:
2224    case IR_RCP:
2225    case IR_FLOOR:
2226    case IR_FRAC:
2227    case IR_F_TO_I:
2228    case IR_I_TO_F:
2229    case IR_ABS:
2230    case IR_SIN:
2231    case IR_COS:
2232    case IR_DDX:
2233    case IR_DDY:
2234    case IR_EXP:
2235    case IR_EXP2:
2236    case IR_LOG2:
2237    case IR_NOISE1:
2238    case IR_NOISE2:
2239    case IR_NOISE3:
2240    case IR_NOISE4:
2241    case IR_NRM4:
2242    case IR_NRM3:
2243    /* binary */
2244    case IR_ADD:
2245    case IR_SUB:
2246    case IR_MUL:
2247    case IR_DOT4:
2248    case IR_DOT3:
2249    case IR_DOT2:
2250    case IR_CROSS:
2251    case IR_MIN:
2252    case IR_MAX:
2253    case IR_SEQUAL:
2254    case IR_SNEQUAL:
2255    case IR_SGE:
2256    case IR_SGT:
2257    case IR_SLE:
2258    case IR_SLT:
2259    case IR_POW:
2260    /* trinary operators */
2261    case IR_LRP:
2262       return emit_arith(emitInfo, n);
2263
2264    case IR_EQUAL:
2265    case IR_NOTEQUAL:
2266       return emit_compare(emitInfo, n);
2267
2268    case IR_CLAMP:
2269       return emit_clamp(emitInfo, n);
2270    case IR_TEX:
2271    case IR_TEXB:
2272    case IR_TEXP:
2273       return emit_tex(emitInfo, n);
2274    case IR_NEG:
2275       return emit_negation(emitInfo, n);
2276    case IR_FLOAT:
2277       /* find storage location for this float constant */
2278       n->Store->Index = _mesa_add_unnamed_constant(emitInfo->prog->Parameters,
2279                                                    n->Value,
2280                                                    n->Store->Size,
2281                                                    &n->Store->Swizzle);
2282       if (n->Store->Index < 0) {
2283          slang_info_log_error(emitInfo->log, "Ran out of space for constants");
2284          return NULL;
2285       }
2286       return NULL;
2287
2288    case IR_COPY:
2289       return emit_copy(emitInfo, n);
2290
2291    case IR_COND:
2292       return emit_cond(emitInfo, n);
2293
2294    case IR_NOT:
2295       return emit_not(emitInfo, n);
2296
2297    case IR_LABEL:
2298       return emit_label(emitInfo, n);
2299
2300    case IR_KILL:
2301       return emit_kill(emitInfo);
2302
2303    case IR_CALL:
2304       /* new variable scope for subroutines/function calls */
2305       _slang_push_var_table(emitInfo->vt);
2306       inst = emit_fcall(emitInfo, n);
2307       _slang_pop_var_table(emitInfo->vt);
2308       return inst;
2309
2310    case IR_IF:
2311       return emit_if(emitInfo, n);
2312
2313    case IR_LOOP:
2314       return emit_loop(emitInfo, n);
2315    case IR_BREAK_IF_TRUE:
2316    case IR_CONT_IF_TRUE:
2317       return emit_cont_break_if_true(emitInfo, n);
2318    case IR_BREAK:
2319       /* fall-through */
2320    case IR_CONT:
2321       return emit_cont_break(emitInfo, n);
2322
2323    case IR_BEGIN_SUB:
2324       return new_instruction(emitInfo, OPCODE_BGNSUB);
2325    case IR_END_SUB:
2326       return new_instruction(emitInfo, OPCODE_ENDSUB);
2327    case IR_RETURN:
2328       return emit_return(emitInfo, n);
2329
2330    case IR_NOP:
2331       return NULL;
2332
2333    default:
2334       _mesa_problem(NULL, "Unexpected IR opcode in emit()\n");
2335    }
2336    return NULL;
2337 }
2338
2339
2340 /**
2341  * After code generation, any subroutines will be in separate program
2342  * objects.  This function appends all the subroutines onto the main
2343  * program and resolves the linking of all the branch/call instructions.
2344  * XXX this logic should really be part of the linking process...
2345  */
2346 static void
2347 _slang_resolve_subroutines(slang_emit_info *emitInfo)
2348 {
2349    GET_CURRENT_CONTEXT(ctx);
2350    struct gl_program *mainP = emitInfo->prog;
2351    GLuint *subroutineLoc, i, total;
2352
2353    subroutineLoc
2354       = (GLuint *) _mesa_malloc(emitInfo->NumSubroutines * sizeof(GLuint));
2355
2356    /* total number of instructions */
2357    total = mainP->NumInstructions;
2358    for (i = 0; i < emitInfo->NumSubroutines; i++) {
2359       subroutineLoc[i] = total;
2360       total += emitInfo->Subroutines[i]->NumInstructions;
2361    }
2362
2363    /* adjust BranchTargets within the functions */
2364    for (i = 0; i < emitInfo->NumSubroutines; i++) {
2365       struct gl_program *sub = emitInfo->Subroutines[i];
2366       GLuint j;
2367       for (j = 0; j < sub->NumInstructions; j++) {
2368          struct prog_instruction *inst = sub->Instructions + j;
2369          if (inst->Opcode != OPCODE_CAL && inst->BranchTarget >= 0) {
2370             inst->BranchTarget += subroutineLoc[i];
2371          }
2372       }
2373    }
2374
2375    /* append subroutines' instructions after main's instructions */
2376    mainP->Instructions = _mesa_realloc_instructions(mainP->Instructions,
2377                                                     mainP->NumInstructions,
2378                                                     total);
2379    mainP->NumInstructions = total;
2380    for (i = 0; i < emitInfo->NumSubroutines; i++) {
2381       struct gl_program *sub = emitInfo->Subroutines[i];
2382       _mesa_copy_instructions(mainP->Instructions + subroutineLoc[i],
2383                               sub->Instructions,
2384                               sub->NumInstructions);
2385       /* delete subroutine code */
2386       sub->Parameters = NULL; /* prevent double-free */
2387       _mesa_reference_program(ctx, &emitInfo->Subroutines[i], NULL);
2388    }
2389
2390    /* free subroutine list */
2391    if (emitInfo->Subroutines) {
2392       _mesa_free(emitInfo->Subroutines);
2393       emitInfo->Subroutines = NULL;
2394    }
2395    emitInfo->NumSubroutines = 0;
2396
2397    /* Examine CAL instructions.
2398     * At this point, the BranchTarget field of the CAL instruction is
2399     * the number/id of the subroutine to call (an index into the
2400     * emitInfo->Subroutines list).
2401     * Translate that into an actual instruction location now.
2402     */
2403    for (i = 0; i < mainP->NumInstructions; i++) {
2404       struct prog_instruction *inst = mainP->Instructions + i;
2405       if (inst->Opcode == OPCODE_CAL) {
2406          const GLuint f = inst->BranchTarget;
2407          inst->BranchTarget = subroutineLoc[f];
2408       }
2409    }
2410
2411    _mesa_free(subroutineLoc);
2412 }
2413
2414
2415
2416 /**
2417  * Convert the IR tree into GPU instructions.
2418  * \param n  root of IR tree
2419  * \param vt  variable table
2420  * \param prog  program to put GPU instructions into
2421  * \param pragmas  controls codegen options
2422  * \param withEnd  if true, emit END opcode at end
2423  * \param log  log for emitting errors/warnings/info
2424  */
2425 GLboolean
2426 _slang_emit_code(slang_ir_node *n, slang_var_table *vt,
2427                  struct gl_program *prog,
2428                  const struct gl_sl_pragmas *pragmas,
2429                  GLboolean withEnd,
2430                  slang_info_log *log)
2431 {
2432    GET_CURRENT_CONTEXT(ctx);
2433    GLboolean success;
2434    slang_emit_info emitInfo;
2435    GLuint maxUniforms;
2436
2437    emitInfo.log = log;
2438    emitInfo.vt = vt;
2439    emitInfo.prog = prog;
2440    emitInfo.Subroutines = NULL;
2441    emitInfo.NumSubroutines = 0;
2442    emitInfo.MaxInstructions = prog->NumInstructions;
2443
2444    emitInfo.EmitHighLevelInstructions = ctx->Shader.EmitHighLevelInstructions;
2445    emitInfo.EmitCondCodes = ctx->Shader.EmitCondCodes;
2446    emitInfo.EmitComments = ctx->Shader.EmitComments || pragmas->Debug;
2447    emitInfo.EmitBeginEndSub = GL_TRUE;
2448
2449    if (!emitInfo.EmitCondCodes) {
2450       emitInfo.EmitHighLevelInstructions = GL_TRUE;
2451    }
2452
2453    /* Check uniform/constant limits */
2454    if (prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
2455       maxUniforms = ctx->Const.FragmentProgram.MaxUniformComponents / 4;
2456    }
2457    else {
2458       assert(prog->Target == GL_VERTEX_PROGRAM_ARB);
2459       maxUniforms = ctx->Const.VertexProgram.MaxUniformComponents / 4;
2460    }
2461    if (prog->Parameters->NumParameters > maxUniforms) {
2462       slang_info_log_error(log, "Constant/uniform register limit exceeded "
2463                            "(max=%u vec4)", maxUniforms);
2464
2465       return GL_FALSE;
2466    }
2467
2468    (void) emit(&emitInfo, n);
2469
2470    /* finish up by adding the END opcode to program */
2471    if (withEnd) {
2472       struct prog_instruction *inst;
2473       inst = new_instruction(&emitInfo, OPCODE_END);
2474    }
2475
2476    _slang_resolve_subroutines(&emitInfo);
2477
2478    success = GL_TRUE;
2479
2480 #if 0
2481    printf("*********** End emit code (%u inst):\n", prog->NumInstructions);
2482    _mesa_print_program(prog);
2483    _mesa_print_program_parameters(ctx,prog);
2484 #endif
2485
2486    return success;
2487 }