2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_glsl_to_tgsi_temprename.h"
58 #include "util/hash_table.h"
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
65 #define MAX_GLSL_TEXTURE_OFFSET 4
68 #include "util/u_atomic.h"
69 #include "util/simple_mtx.h"
73 /* Prepare to make it possible to specify log file */
74 static std::ofstream stats_log
;
76 /* Helper function to check whether we want to write some statistics
77 * of the shader conversion.
80 static simple_mtx_t print_stats_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
82 static inline bool print_stats_enabled ()
84 static int stats_enabled
= 0;
87 simple_mtx_lock(&print_stats_mutex
);
89 const char *stats_filename
= getenv("GLSL_TO_TGSI_PRINT_STATS");
91 bool write_header
= std::ifstream(stats_filename
).fail();
92 stats_log
.open(stats_filename
, std::ios_base::out
| std::ios_base::app
);
93 stats_enabled
= stats_log
.good() ? 1 : -1;
95 stats_log
<< "arrays,temps,temps in arrays,total,instructions\n";
100 simple_mtx_unlock(&print_stats_mutex
);
102 return stats_enabled
> 0;
104 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
106 #define PRINT_STATS(X)
110 static unsigned is_precise(const ir_variable
*ir
)
114 return ir
->data
.precise
|| ir
->data
.invariant
;
117 class variable_storage
{
118 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
121 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
122 unsigned array_id
= 0)
123 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
125 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
128 gl_register_file file
;
131 /* Explicit component location. This is given in terms of the GLSL-style
132 * swizzles where each double is a single component, i.e. for 64-bit types
133 * it can only be 0 or 1.
136 ir_variable
*var
; /* variable that maps to this, if any */
140 class immediate_storage
: public exec_node
{
142 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
144 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
145 this->size32
= size32
;
149 /* doubles are stored across 2 gl_constant_values */
150 gl_constant_value values
[4];
151 int size32
; /**< Number of 32-bit components (1-4) */
152 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
155 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
156 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
160 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
163 unsigned gs_out_streams
;
164 enum glsl_interp_mode interp
;
165 enum glsl_base_type base_type
;
166 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
170 static struct inout_decl
*
171 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
173 assert(array_id
!= 0);
175 for (unsigned i
= 0; i
< count
; i
++) {
176 struct inout_decl
*decl
= &decls
[i
];
178 if (array_id
== decl
->array_id
) {
186 static enum glsl_base_type
187 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
190 return GLSL_TYPE_ERROR
;
191 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
193 return decl
->base_type
;
194 return GLSL_TYPE_ERROR
;
197 struct hwatomic_decl
{
204 struct glsl_to_tgsi_visitor
: public ir_visitor
{
206 glsl_to_tgsi_visitor();
207 ~glsl_to_tgsi_visitor();
209 struct gl_context
*ctx
;
210 struct gl_program
*prog
;
211 struct gl_shader_program
*shader_program
;
212 struct gl_linked_shader
*shader
;
213 struct gl_shader_compiler_options
*options
;
217 unsigned *array_sizes
;
218 unsigned max_num_arrays
;
221 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
223 unsigned num_input_arrays
;
224 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
225 unsigned num_outputs
;
226 unsigned num_output_arrays
;
228 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
229 unsigned num_atomics
;
230 unsigned num_atomic_arrays
;
231 int num_address_regs
;
232 uint32_t samplers_used
;
233 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
234 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
236 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
237 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
238 bool image_wr
[PIPE_MAX_SHADER_IMAGES
];
239 bool indirect_addr_consts
;
240 int wpos_transform_const
;
242 bool native_integers
;
245 bool use_shared_memory
;
249 bool tg4_component_in_swizzle
;
251 variable_storage
*find_variable_storage(ir_variable
*var
);
253 int add_constant(gl_register_file file
, gl_constant_value values
[8],
254 int size
, GLenum datatype
, uint16_t *swizzle_out
);
256 st_src_reg
get_temp(const glsl_type
*type
);
257 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
259 st_src_reg
st_src_reg_for_double(double val
);
260 st_src_reg
st_src_reg_for_float(float val
);
261 st_src_reg
st_src_reg_for_int(int val
);
262 st_src_reg
st_src_reg_for_int64(int64_t val
);
263 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
266 * \name Visit methods
268 * As typical for the visitor pattern, there must be one \c visit method for
269 * each concrete subclass of \c ir_instruction. Virtual base classes within
270 * the hierarchy should not have \c visit methods.
273 virtual void visit(ir_variable
*);
274 virtual void visit(ir_loop
*);
275 virtual void visit(ir_loop_jump
*);
276 virtual void visit(ir_function_signature
*);
277 virtual void visit(ir_function
*);
278 virtual void visit(ir_expression
*);
279 virtual void visit(ir_swizzle
*);
280 virtual void visit(ir_dereference_variable
*);
281 virtual void visit(ir_dereference_array
*);
282 virtual void visit(ir_dereference_record
*);
283 virtual void visit(ir_assignment
*);
284 virtual void visit(ir_constant
*);
285 virtual void visit(ir_call
*);
286 virtual void visit(ir_return
*);
287 virtual void visit(ir_discard
*);
288 virtual void visit(ir_demote
*);
289 virtual void visit(ir_texture
*);
290 virtual void visit(ir_if
*);
291 virtual void visit(ir_emit_vertex
*);
292 virtual void visit(ir_end_primitive
*);
293 virtual void visit(ir_barrier
*);
296 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
298 void visit_atomic_counter_intrinsic(ir_call
*);
299 void visit_ssbo_intrinsic(ir_call
*);
300 void visit_membar_intrinsic(ir_call
*);
301 void visit_shared_intrinsic(ir_call
*);
302 void visit_image_intrinsic(ir_call
*);
303 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
307 /** List of variable_storage */
308 struct hash_table
*variables
;
310 /** List of immediate_storage */
311 exec_list immediates
;
312 unsigned num_immediates
;
314 /** List of glsl_to_tgsi_instruction */
315 exec_list instructions
;
317 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
318 st_dst_reg dst
= undef_dst
,
319 st_src_reg src0
= undef_src
,
320 st_src_reg src1
= undef_src
,
321 st_src_reg src2
= undef_src
,
322 st_src_reg src3
= undef_src
);
324 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
325 st_dst_reg dst
, st_dst_reg dst1
,
326 st_src_reg src0
= undef_src
,
327 st_src_reg src1
= undef_src
,
328 st_src_reg src2
= undef_src
,
329 st_src_reg src3
= undef_src
);
331 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
333 st_src_reg src0
, st_src_reg src1
);
336 * Emit the correct dot-product instruction for the type of arguments
338 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
344 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
345 st_dst_reg dst
, st_src_reg src0
);
347 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
348 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
350 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
352 void get_deref_offsets(ir_dereference
*ir
,
353 unsigned *array_size
,
358 void calc_deref_offsets(ir_dereference
*tail
,
359 unsigned *array_elements
,
361 st_src_reg
*indirect
,
363 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
364 bool handle_bound_deref(ir_dereference
*ir
);
366 bool try_emit_mad(ir_expression
*ir
,
368 bool try_emit_mad_for_and_not(ir_expression
*ir
,
371 void emit_swz(ir_expression
*ir
);
373 bool process_move_condition(ir_rvalue
*ir
);
375 void simplify_cmp(void);
377 void rename_temp_registers(struct rename_reg_pair
*renames
);
378 void get_first_temp_read(int *first_reads
);
379 void get_first_temp_write(int *first_writes
);
380 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
381 void get_last_temp_write(int *last_writes
);
383 void copy_propagate(void);
384 int eliminate_dead_code(void);
386 void split_arrays(void);
387 void merge_two_dsts(void);
388 void merge_registers(void);
389 void renumber_registers(void);
391 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
392 st_dst_reg
*l
, st_src_reg
*r
,
393 st_src_reg
*cond
, bool cond_swap
);
400 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
402 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
404 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
408 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
412 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
416 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
419 prog
->data
->LinkStatus
= LINKING_FAILURE
;
423 swizzle_for_size(int size
)
425 static const int size_swizzles
[4] = {
426 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
427 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
428 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
429 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
432 assert((size
>= 1) && (size
<= 4));
433 return size_swizzles
[size
- 1];
437 glsl_to_tgsi_instruction
*
438 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
439 st_dst_reg dst
, st_dst_reg dst1
,
440 st_src_reg src0
, st_src_reg src1
,
441 st_src_reg src2
, st_src_reg src3
)
443 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
444 int num_reladdr
= 0, i
, j
;
445 bool dst_is_64bit
[2];
447 op
= get_opcode(op
, dst
, src0
, src1
);
449 /* If we have to do relative addressing, we want to load the ARL
450 * reg directly for one of the regs, and preload the other reladdr
451 * sources into temps.
453 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
454 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
455 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
456 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
457 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
458 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
460 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
461 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
462 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
463 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
465 if (dst
.reladdr
|| dst
.reladdr2
) {
467 emit_arl(ir
, address_reg
, *dst
.reladdr
);
469 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
473 assert(num_reladdr
== 0);
475 /* inst->op has only 8 bits. */
476 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
479 inst
->precise
= this->precise
;
480 inst
->info
= tgsi_get_opcode_info(op
);
487 inst
->is_64bit_expanded
= false;
490 inst
->tex_offsets
= NULL
;
491 inst
->tex_offset_num_offset
= 0;
493 inst
->tex_shadow
= 0;
494 /* default to float, for paths where this is not initialized
495 * (since 0==UINT which is likely wrong):
497 inst
->tex_type
= GLSL_TYPE_FLOAT
;
499 /* Update indirect addressing status used by TGSI */
500 if (dst
.reladdr
|| dst
.reladdr2
) {
502 case PROGRAM_STATE_VAR
:
503 case PROGRAM_CONSTANT
:
504 case PROGRAM_UNIFORM
:
505 this->indirect_addr_consts
= true;
507 case PROGRAM_IMMEDIATE
:
508 assert(!"immediates should not have indirect addressing");
515 for (i
= 0; i
< 4; i
++) {
516 if (inst
->src
[i
].reladdr
) {
517 switch (inst
->src
[i
].file
) {
518 case PROGRAM_STATE_VAR
:
519 case PROGRAM_CONSTANT
:
520 case PROGRAM_UNIFORM
:
521 this->indirect_addr_consts
= true;
523 case PROGRAM_IMMEDIATE
:
524 assert(!"immediates should not have indirect addressing");
534 * This section contains the double processing.
535 * GLSL just represents doubles as single channel values,
536 * however most HW and TGSI represent doubles as pairs of register channels.
538 * so we have to fixup destination writemask/index and src swizzle/indexes.
539 * dest writemasks need to translate from single channel write mask
540 * to a dual-channel writemask, but also need to modify the index,
541 * if we are touching the Z,W fields in the pre-translated writemask.
543 * src channels have similiar index modifications along with swizzle
544 * changes to we pick the XY, ZW pairs from the correct index.
546 * GLSL [0].x -> TGSI [0].xy
547 * GLSL [0].y -> TGSI [0].zw
548 * GLSL [0].z -> TGSI [1].xy
549 * GLSL [0].w -> TGSI [1].zw
551 for (j
= 0; j
< 2; j
++) {
552 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
553 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
554 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
555 enum glsl_base_type type
= find_array_type(this->outputs
,
557 inst
->dst
[j
].array_id
);
558 if (glsl_base_type_is_64bit(type
))
559 dst_is_64bit
[j
] = true;
563 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
564 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
565 glsl_to_tgsi_instruction
*dinst
= NULL
;
566 int initial_src_swz
[4], initial_src_idx
[4];
567 int initial_dst_idx
[2], initial_dst_writemask
[2];
568 /* select the writemask for dst0 or dst1 */
569 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
570 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
572 /* copy out the writemask, index and swizzles for all src/dsts. */
573 for (j
= 0; j
< 2; j
++) {
574 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
575 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
578 for (j
= 0; j
< 4; j
++) {
579 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
580 initial_src_idx
[j
] = inst
->src
[j
].index
;
584 * scan all the components in the dst writemask
585 * generate an instruction for each of them if required.
590 int i
= u_bit_scan(&writemask
);
592 /* before emitting the instruction, see if we have to adjust
593 * load / store address */
594 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
595 inst
->op
== TGSI_OPCODE_STORE
) &&
596 addr
.file
== PROGRAM_UNDEFINED
) {
597 /* We have to advance the buffer address by 16 */
598 addr
= get_temp(glsl_type::uint_type
);
599 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
600 inst
->src
[0], st_src_reg_for_int(16));
603 /* first time use previous instruction */
607 /* create a new instructions for subsequent attempts */
608 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
613 this->instructions
.push_tail(dinst
);
614 dinst
->is_64bit_expanded
= true;
616 /* modify the destination if we are splitting */
617 for (j
= 0; j
< 2; j
++) {
618 if (dst_is_64bit
[j
]) {
619 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
620 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
622 if (dinst
->op
== TGSI_OPCODE_LOAD
||
623 dinst
->op
== TGSI_OPCODE_STORE
)
624 dinst
->src
[0] = addr
;
625 if (dinst
->op
!= TGSI_OPCODE_STORE
)
626 dinst
->dst
[j
].index
++;
629 /* if we aren't writing to a double, just get the bit of the
630 * initial writemask for this channel
632 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
636 /* modify the src registers */
637 for (j
= 0; j
< 4; j
++) {
638 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
640 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
641 dinst
->src
[j
].index
= initial_src_idx
[j
];
643 dinst
->src
[j
].double_reg2
= true;
644 dinst
->src
[j
].index
++;
648 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
649 SWIZZLE_Z
, SWIZZLE_W
);
651 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
652 SWIZZLE_X
, SWIZZLE_Y
);
655 /* some opcodes are special case in what they use as sources
656 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
659 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
660 op
== TGSI_OPCODE_I2D
||
661 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
662 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
663 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
664 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
671 this->instructions
.push_tail(inst
);
678 glsl_to_tgsi_instruction
*
679 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
681 st_src_reg src0
, st_src_reg src1
,
682 st_src_reg src2
, st_src_reg src3
)
684 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
688 * Determines whether to use an integer, unsigned integer, or float opcode
689 * based on the operands and input opcode, then emits the result.
692 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
694 st_src_reg src0
, st_src_reg src1
)
696 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
698 if (op
== TGSI_OPCODE_MOV
)
701 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
702 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
703 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
704 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
706 if (is_resource_instruction(op
))
708 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
709 type
= GLSL_TYPE_INT64
;
710 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
711 type
= GLSL_TYPE_UINT64
;
712 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
713 type
= GLSL_TYPE_DOUBLE
;
714 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
715 type
= GLSL_TYPE_FLOAT
;
716 else if (native_integers
)
717 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
719 #define case7(c, f, i, u, d, i64, ui64) \
720 case TGSI_OPCODE_##c: \
721 if (type == GLSL_TYPE_UINT64) \
722 op = TGSI_OPCODE_##ui64; \
723 else if (type == GLSL_TYPE_INT64) \
724 op = TGSI_OPCODE_##i64; \
725 else if (type == GLSL_TYPE_DOUBLE) \
726 op = TGSI_OPCODE_##d; \
727 else if (type == GLSL_TYPE_INT) \
728 op = TGSI_OPCODE_##i; \
729 else if (type == GLSL_TYPE_UINT) \
730 op = TGSI_OPCODE_##u; \
732 op = TGSI_OPCODE_##f; \
735 #define casecomp(c, f, i, u, d, i64, ui64) \
736 case TGSI_OPCODE_##c: \
737 if (type == GLSL_TYPE_INT64) \
738 op = TGSI_OPCODE_##i64; \
739 else if (type == GLSL_TYPE_UINT64) \
740 op = TGSI_OPCODE_##ui64; \
741 else if (type == GLSL_TYPE_DOUBLE) \
742 op = TGSI_OPCODE_##d; \
743 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
744 op = TGSI_OPCODE_##i; \
745 else if (type == GLSL_TYPE_UINT) \
746 op = TGSI_OPCODE_##u; \
747 else if (native_integers) \
748 op = TGSI_OPCODE_##f; \
750 op = TGSI_OPCODE_##c; \
754 /* Some instructions are initially selected without considering the type.
755 * This fixes the type:
757 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
759 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
760 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
761 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
762 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
763 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
764 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
765 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
766 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
767 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
768 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
769 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
770 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
771 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
772 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
773 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
774 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
776 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
777 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
778 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
779 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
780 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
781 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
782 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
783 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
784 case7(ATOMUADD
,ATOMFADD
,ATOMUADD
,ATOMUADD
,LAST
, LAST
, LAST
);
786 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
787 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
788 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
789 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
795 assert(op
!= TGSI_OPCODE_LAST
);
799 glsl_to_tgsi_instruction
*
800 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
801 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
804 static const enum tgsi_opcode dot_opcodes
[] = {
805 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
808 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
812 * Emits TGSI scalar opcodes to produce unique answers across channels.
814 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
815 * channel determines the result across all channels. So to do a vec4
816 * of this operation, we want to emit a scalar per source channel used
817 * to produce dest channels.
820 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
822 st_src_reg orig_src0
, st_src_reg orig_src1
)
825 int done_mask
= ~dst
.writemask
;
827 /* TGSI RCP is a scalar operation splatting results to all channels,
828 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
831 for (i
= 0; i
< 4; i
++) {
832 GLuint this_mask
= (1 << i
);
833 st_src_reg src0
= orig_src0
;
834 st_src_reg src1
= orig_src1
;
836 if (done_mask
& this_mask
)
839 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
840 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
841 for (j
= i
+ 1; j
< 4; j
++) {
842 /* If there is another enabled component in the destination that is
843 * derived from the same inputs, generate its value on this pass as
846 if (!(done_mask
& (1 << j
)) &&
847 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
848 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
849 this_mask
|= (1 << j
);
852 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
853 src0_swiz
, src0_swiz
);
854 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
855 src1_swiz
, src1_swiz
);
857 dst
.writemask
= this_mask
;
858 emit_asm(ir
, op
, dst
, src0
, src1
);
859 done_mask
|= this_mask
;
864 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
865 st_dst_reg dst
, st_src_reg src0
)
867 st_src_reg undef
= undef_src
;
869 undef
.swizzle
= SWIZZLE_XXXX
;
871 emit_scalar(ir
, op
, dst
, src0
, undef
);
875 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
876 st_dst_reg dst
, st_src_reg src0
)
878 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
880 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
881 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
884 op
= TGSI_OPCODE_UARL
;
887 assert(dst
.file
== PROGRAM_ADDRESS
);
888 if (dst
.index
>= this->num_address_regs
)
889 this->num_address_regs
= dst
.index
+ 1;
891 emit_asm(NULL
, op
, dst
, src0
);
895 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
896 gl_constant_value values
[8], int size
,
898 uint16_t *swizzle_out
)
900 if (file
== PROGRAM_CONSTANT
) {
901 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
902 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
903 values
, size
, datatype
,
906 *swizzle_out
= swizzle
;
910 assert(file
== PROGRAM_IMMEDIATE
);
913 immediate_storage
*entry
;
914 int size32
= size
* ((datatype
== GL_DOUBLE
||
915 datatype
== GL_INT64_ARB
||
916 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
919 /* Search immediate storage to see if we already have an identical
920 * immediate that we can use instead of adding a duplicate entry.
922 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
923 immediate_storage
*tmp
= entry
;
925 for (i
= 0; i
* 4 < size32
; i
++) {
926 int slot_size
= MIN2(size32
- (i
* 4), 4);
927 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
929 if (memcmp(tmp
->values
, &values
[i
* 4],
930 slot_size
* sizeof(gl_constant_value
)))
933 /* Everything matches, keep going until the full size is matched */
934 tmp
= (immediate_storage
*)tmp
->next
;
937 /* The full value matched */
944 for (i
= 0; i
* 4 < size32
; i
++) {
945 int slot_size
= MIN2(size32
- (i
* 4), 4);
946 /* Add this immediate to the list. */
947 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
948 slot_size
, datatype
);
949 this->immediates
.push_tail(entry
);
950 this->num_immediates
++;
956 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
958 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
959 union gl_constant_value uval
;
962 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
968 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
970 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
971 union gl_constant_value uval
[2];
973 memcpy(uval
, &val
, sizeof(uval
));
974 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
975 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
980 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
982 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
983 union gl_constant_value uval
;
985 assert(native_integers
);
988 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
994 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
996 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
997 union gl_constant_value uval
[2];
999 memcpy(uval
, &val
, sizeof(uval
));
1000 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1001 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1007 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1009 if (native_integers
)
1010 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1011 st_src_reg_for_int(val
);
1013 return st_src_reg_for_float(val
);
1017 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1019 return type
->count_attribute_slots(is_vs_input
);
1023 type_size(const struct glsl_type
*type
)
1025 return type
->count_attribute_slots(false);
1029 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
1030 exec_list
*instructions
, ir_constant
*access
)
1033 * emit_asm() might have actually split the op into pieces, e.g. for
1034 * double stores. We have to go back and fix up all the generated ops.
1036 enum tgsi_opcode op
= inst
->op
;
1038 inst
->resource
= *buf
;
1040 inst
->buffer_access
= access
->value
.u
[0];
1042 if (inst
== instructions
->get_head_raw())
1044 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1046 if (inst
->op
== TGSI_OPCODE_UADD
) {
1047 if (inst
== instructions
->get_head_raw())
1049 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1051 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1055 * If the given GLSL type is an array or matrix or a structure containing
1056 * an array/matrix member, return true. Else return false.
1058 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1059 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1060 * we have an array that might be indexed with a variable, we need to use
1061 * the later storage type.
1064 type_has_array_or_matrix(const glsl_type
*type
)
1066 if (type
->is_array() || type
->is_matrix())
1069 if (type
->is_struct()) {
1070 for (unsigned i
= 0; i
< type
->length
; i
++) {
1071 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1082 * In the initial pass of codegen, we assign temporary numbers to
1083 * intermediate results. (not SSA -- variable assignments will reuse
1087 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1091 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1096 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1097 if (next_array
>= max_num_arrays
) {
1098 max_num_arrays
+= 32;
1099 array_sizes
= (unsigned*)
1100 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1103 src
.file
= PROGRAM_ARRAY
;
1105 src
.array_id
= next_array
+ 1;
1106 array_sizes
[next_array
] = type_size(type
);
1110 src
.file
= PROGRAM_TEMPORARY
;
1111 src
.index
= next_temp
;
1112 next_temp
+= type_size(type
);
1115 if (type
->is_array() || type
->is_struct()) {
1116 src
.swizzle
= SWIZZLE_NOOP
;
1118 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1125 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1127 struct hash_entry
*entry
;
1129 entry
= _mesa_hash_table_search(this->variables
, var
);
1133 return (variable_storage
*)entry
->data
;
1137 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1139 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1141 const ir_state_slot
*const slots
= ir
->get_state_slots();
1142 assert(slots
!= NULL
);
1144 /* Check if this statevar's setup in the STATE file exactly
1145 * matches how we'll want to reference it as a
1146 * struct/array/whatever. If not, then we need to move it into
1147 * temporary storage and hope that it'll get copy-propagated
1150 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1151 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1156 variable_storage
*storage
;
1158 if (i
== ir
->get_num_state_slots()) {
1159 /* We'll set the index later. */
1160 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1162 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1166 /* The variable_storage constructor allocates slots based on the size
1167 * of the type. However, this had better match the number of state
1168 * elements that we're going to copy into the new temporary.
1170 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1172 dst
= st_dst_reg(get_temp(ir
->type
));
1174 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1177 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1181 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1182 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1185 if (storage
->file
== PROGRAM_STATE_VAR
) {
1186 if (storage
->index
== -1) {
1187 storage
->index
= index
;
1189 assert(index
== storage
->index
+ (int)i
);
1192 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1193 * the data being moved since MOV does not care about the type of
1194 * data it is moving, and we don't want to declare registers with
1195 * array or struct types.
1197 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1198 src
.swizzle
= slots
[i
].swizzle
;
1199 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1200 /* even a float takes up a whole vec4 reg in a struct/array. */
1205 if (storage
->file
== PROGRAM_TEMPORARY
&&
1206 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1207 fail_link(this->shader_program
,
1208 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1209 ir
->name
, dst
.index
- storage
->index
,
1210 type_size(ir
->type
));
1216 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1218 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1220 visit_exec_list(&ir
->body_instructions
, this);
1222 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1226 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1229 case ir_loop_jump::jump_break
:
1230 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1232 case ir_loop_jump::jump_continue
:
1233 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1240 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1247 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1249 /* Ignore function bodies other than main() -- we shouldn't see calls to
1250 * them since they should all be inlined before we get to glsl_to_tgsi.
1252 if (strcmp(ir
->name
, "main") == 0) {
1253 const ir_function_signature
*sig
;
1256 sig
= ir
->matching_signature(NULL
, &empty
, false);
1260 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1267 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1269 int nonmul_operand
= 1 - mul_operand
;
1271 st_dst_reg result_dst
;
1273 // there is no TGSI opcode for this
1274 if (ir
->type
->is_integer_64())
1277 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1278 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1281 expr
->operands
[0]->accept(this);
1283 expr
->operands
[1]->accept(this);
1285 ir
->operands
[nonmul_operand
]->accept(this);
1288 this->result
= get_temp(ir
->type
);
1289 result_dst
= st_dst_reg(this->result
);
1290 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1291 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1297 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1299 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1300 * implemented using multiplication, and logical-or is implemented using
1301 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1302 * As result, the logical expression (a & !b) can be rewritten as:
1306 * - (a * 1) - (a * b)
1310 * This final expression can be implemented as a single MAD(a, -b, a)
1314 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1317 const int other_operand
= 1 - try_operand
;
1320 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1321 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1324 ir
->operands
[other_operand
]->accept(this);
1326 expr
->operands
[0]->accept(this);
1329 b
.negate
= ~b
.negate
;
1331 this->result
= get_temp(ir
->type
);
1332 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1338 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1339 st_src_reg
*reg
, int *num_reladdr
)
1341 if (!reg
->reladdr
&& !reg
->reladdr2
)
1345 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1347 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1349 if (*num_reladdr
!= 1) {
1350 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1352 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1360 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1362 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1364 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1366 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1367 if (try_emit_mad(ir
, 1))
1369 if (try_emit_mad(ir
, 0))
1373 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1375 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1376 if (try_emit_mad_for_and_not(ir
, 1))
1378 if (try_emit_mad_for_and_not(ir
, 0))
1382 if (ir
->operation
== ir_quadop_vector
)
1383 assert(!"ir_quadop_vector should have been lowered");
1385 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1386 this->result
.file
= PROGRAM_UNDEFINED
;
1387 ir
->operands
[operand
]->accept(this);
1388 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1389 printf("Failed to get tree for expression operand:\n");
1390 ir
->operands
[operand
]->print();
1394 op
[operand
] = this->result
;
1396 /* Matrix expression operands should have been broken down to vector
1397 * operations already.
1399 assert(!ir
->operands
[operand
]->type
->is_matrix());
1402 visit_expression(ir
, op
);
1405 /* The non-recursive part of the expression visitor lives in a separate
1406 * function and should be prevented from being inlined, to avoid a stack
1407 * explosion when deeply nested expressions are visited.
1410 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1412 st_src_reg result_src
;
1413 st_dst_reg result_dst
;
1415 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1416 if (ir
->operands
[1] &&
1417 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1418 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1419 st_src_reg
*swz_op
= NULL
;
1420 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1421 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1423 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1424 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1428 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1429 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1430 swizzle_x
, swizzle_x
);
1432 vector_elements
= MAX2(vector_elements
,
1433 ir
->operands
[1]->type
->vector_elements
);
1435 if (ir
->operands
[2] &&
1436 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1437 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1438 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1439 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1440 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1441 swizzle_x
, swizzle_x
);
1444 this->result
.file
= PROGRAM_UNDEFINED
;
1446 /* Storage for our result. Ideally for an assignment we'd be using
1447 * the actual storage for the result here, instead.
1449 result_src
= get_temp(ir
->type
);
1450 /* convenience for the emit functions below. */
1451 result_dst
= st_dst_reg(result_src
);
1452 /* Limit writes to the channels that will be used by result_src later.
1453 * This does limit this temp's use as a temporary for multi-instruction
1456 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1458 switch (ir
->operation
) {
1459 case ir_unop_logic_not
:
1460 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1461 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1463 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1464 * older GPUs implement SEQ using multiple instructions (i915 uses two
1465 * SGE instructions and a MUL instruction). Since our logic values are
1466 * 0.0 and 1.0, 1-x also implements !x.
1468 op
[0].negate
= ~op
[0].negate
;
1469 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1470 st_src_reg_for_float(1.0));
1474 if (result_dst
.type
== GLSL_TYPE_INT64
||
1475 result_dst
.type
== GLSL_TYPE_UINT64
)
1476 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1477 else if (result_dst
.type
== GLSL_TYPE_INT
||
1478 result_dst
.type
== GLSL_TYPE_UINT
)
1479 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1480 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1481 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1483 op
[0].negate
= ~op
[0].negate
;
1487 case ir_unop_subroutine_to_int
:
1488 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1491 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1492 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1493 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1494 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1495 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1496 result_dst
.type
== GLSL_TYPE_UINT64
)
1497 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1499 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1502 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1505 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1509 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1512 assert(!"not reached: should be handled by exp_to_exp2");
1515 assert(!"not reached: should be handled by log_to_log2");
1518 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1521 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1524 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1526 case ir_unop_saturate
: {
1527 glsl_to_tgsi_instruction
*inst
;
1528 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1529 inst
->saturate
= true;
1534 case ir_unop_dFdx_coarse
:
1535 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1537 case ir_unop_dFdx_fine
:
1538 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1541 case ir_unop_dFdy_coarse
:
1542 case ir_unop_dFdy_fine
:
1544 /* The X component contains 1 or -1 depending on whether the framebuffer
1545 * is a FBO or the window system buffer, respectively.
1546 * It is then multiplied with the source operand of DDY.
1548 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1549 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1551 unsigned transform_y_index
=
1552 _mesa_add_state_reference(this->prog
->Parameters
,
1555 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1557 glsl_type::vec4_type
);
1558 transform_y
.swizzle
= SWIZZLE_XXXX
;
1560 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1562 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1563 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1564 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1568 case ir_unop_frexp_sig
:
1569 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1572 case ir_unop_frexp_exp
:
1573 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1576 case ir_unop_noise
: {
1577 /* At some point, a motivated person could add a better
1578 * implementation of noise. Currently not even the nvidia
1579 * binary drivers do anything more than this. In any case, the
1580 * place to do this is in the GL state tracker, not the poor
1583 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1588 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1591 op
[1].negate
= ~op
[1].negate
;
1592 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1596 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1599 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1602 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1603 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1605 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1609 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1611 case ir_binop_gequal
:
1612 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1614 case ir_binop_equal
:
1615 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1617 case ir_binop_nequal
:
1618 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1620 case ir_binop_all_equal
:
1621 /* "==" operator producing a scalar boolean. */
1622 if (ir
->operands
[0]->type
->is_vector() ||
1623 ir
->operands
[1]->type
->is_vector()) {
1624 st_src_reg temp
= get_temp(native_integers
?
1625 glsl_type::uvec4_type
:
1626 glsl_type::vec4_type
);
1628 if (native_integers
) {
1629 st_dst_reg temp_dst
= st_dst_reg(temp
);
1630 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1632 if (ir
->operands
[0]->type
->is_boolean() &&
1633 ir
->operands
[1]->as_constant() &&
1634 ir
->operands
[1]->as_constant()->is_one()) {
1635 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1637 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1640 /* Emit 1-3 AND operations to combine the SEQ results. */
1641 switch (ir
->operands
[0]->type
->vector_elements
) {
1645 temp_dst
.writemask
= WRITEMASK_Y
;
1646 temp1
.swizzle
= SWIZZLE_YYYY
;
1647 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1648 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1651 temp_dst
.writemask
= WRITEMASK_X
;
1652 temp1
.swizzle
= SWIZZLE_XXXX
;
1653 temp2
.swizzle
= SWIZZLE_YYYY
;
1654 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1655 temp_dst
.writemask
= WRITEMASK_Y
;
1656 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1657 temp2
.swizzle
= SWIZZLE_WWWW
;
1658 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1661 temp1
.swizzle
= SWIZZLE_XXXX
;
1662 temp2
.swizzle
= SWIZZLE_YYYY
;
1663 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1665 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1667 /* After the dot-product, the value will be an integer on the
1668 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1670 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1672 /* Negating the result of the dot-product gives values on the range
1673 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1674 * This is achieved using SGE.
1676 st_src_reg sge_src
= result_src
;
1677 sge_src
.negate
= ~sge_src
.negate
;
1678 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1679 st_src_reg_for_float(0.0));
1682 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1685 case ir_binop_any_nequal
:
1686 /* "!=" operator producing a scalar boolean. */
1687 if (ir
->operands
[0]->type
->is_vector() ||
1688 ir
->operands
[1]->type
->is_vector()) {
1689 st_src_reg temp
= get_temp(native_integers
?
1690 glsl_type::uvec4_type
:
1691 glsl_type::vec4_type
);
1692 if (ir
->operands
[0]->type
->is_boolean() &&
1693 ir
->operands
[1]->as_constant() &&
1694 ir
->operands
[1]->as_constant()->is_zero()) {
1695 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1697 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1700 if (native_integers
) {
1701 st_dst_reg temp_dst
= st_dst_reg(temp
);
1702 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1704 /* Emit 1-3 OR operations to combine the SNE results. */
1705 switch (ir
->operands
[0]->type
->vector_elements
) {
1709 temp_dst
.writemask
= WRITEMASK_Y
;
1710 temp1
.swizzle
= SWIZZLE_YYYY
;
1711 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1712 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1715 temp_dst
.writemask
= WRITEMASK_X
;
1716 temp1
.swizzle
= SWIZZLE_XXXX
;
1717 temp2
.swizzle
= SWIZZLE_YYYY
;
1718 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1719 temp_dst
.writemask
= WRITEMASK_Y
;
1720 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1721 temp2
.swizzle
= SWIZZLE_WWWW
;
1722 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1725 temp1
.swizzle
= SWIZZLE_XXXX
;
1726 temp2
.swizzle
= SWIZZLE_YYYY
;
1727 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1729 /* After the dot-product, the value will be an integer on the
1730 * range [0,4]. Zero stays zero, and positive values become 1.0.
1732 glsl_to_tgsi_instruction
*const dp
=
1733 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1734 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1735 /* The clamping to [0,1] can be done for free in the fragment
1736 * shader with a saturate.
1738 dp
->saturate
= true;
1740 /* Negating the result of the dot-product gives values on the
1741 * range [-4, 0]. Zero stays zero, and negative values become
1742 * 1.0. This achieved using SLT.
1744 st_src_reg slt_src
= result_src
;
1745 slt_src
.negate
= ~slt_src
.negate
;
1746 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1747 st_src_reg_for_float(0.0));
1751 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1755 case ir_binop_logic_xor
:
1756 if (native_integers
)
1757 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1759 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1762 case ir_binop_logic_or
: {
1763 if (native_integers
) {
1764 /* If integers are used as booleans, we can use an actual "or"
1767 assert(native_integers
);
1768 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1770 /* After the addition, the value will be an integer on the
1771 * range [0,2]. Zero stays zero, and positive values become 1.0.
1773 glsl_to_tgsi_instruction
*add
=
1774 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1775 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1776 /* The clamping to [0,1] can be done for free in the fragment
1777 * shader with a saturate if floats are being used as boolean
1780 add
->saturate
= true;
1782 /* Negating the result of the addition gives values on the range
1783 * [-2, 0]. Zero stays zero, and negative values become 1.0
1784 * This is achieved using SLT.
1786 st_src_reg slt_src
= result_src
;
1787 slt_src
.negate
= ~slt_src
.negate
;
1788 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1789 st_src_reg_for_float(0.0));
1795 case ir_binop_logic_and
:
1796 /* If native integers are disabled, the bool args are stored as float 0.0
1797 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1798 * actual AND opcode.
1800 if (native_integers
)
1801 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1803 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1807 assert(ir
->operands
[0]->type
->is_vector());
1808 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1809 emit_dp(ir
, result_dst
, op
[0], op
[1],
1810 ir
->operands
[0]->type
->vector_elements
);
1815 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1817 /* This is the only instruction sequence that makes the game "Risen"
1818 * render correctly. ABS is not required for the game, but since GLSL
1819 * declares negative values as "undefined", allowing us to do whatever
1820 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1823 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1824 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1828 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1831 if (native_integers
) {
1832 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1835 /* fallthrough to next case otherwise */
1837 if (native_integers
) {
1838 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1839 st_src_reg_for_float(1.0));
1842 /* fallthrough to next case otherwise */
1845 case ir_unop_i642u64
:
1846 case ir_unop_u642i64
:
1847 /* Converting between signed and unsigned integers is a no-op. */
1849 result_src
.type
= result_dst
.type
;
1852 if (native_integers
) {
1853 /* Booleans are stored as integers using ~0 for true and 0 for false.
1854 * GLSL requires that int(bool) return 1 for true and 0 for false.
1855 * This conversion is done with AND, but it could be done with NEG.
1857 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1858 st_src_reg_for_int(1));
1860 /* Booleans and integers are both stored as floats when native
1861 * integers are disabled.
1867 if (native_integers
)
1868 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1870 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1873 if (native_integers
)
1874 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1876 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1878 case ir_unop_bitcast_f2i
:
1879 case ir_unop_bitcast_f2u
:
1880 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1881 if (op
[0].negate
|| op
[0].abs
)
1882 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1885 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1888 case ir_unop_bitcast_i2f
:
1889 case ir_unop_bitcast_u2f
:
1891 result_src
.type
= GLSL_TYPE_FLOAT
;
1894 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1895 st_src_reg_for_float(0.0));
1898 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1899 st_src_reg_for_double(0.0));
1902 if (native_integers
)
1903 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1904 st_src_reg_for_int(0));
1906 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1907 st_src_reg_for_float(0.0));
1909 case ir_unop_bitcast_u642d
:
1910 case ir_unop_bitcast_i642d
:
1912 result_src
.type
= GLSL_TYPE_DOUBLE
;
1914 case ir_unop_bitcast_d2i64
:
1916 result_src
.type
= GLSL_TYPE_INT64
;
1918 case ir_unop_bitcast_d2u64
:
1920 result_src
.type
= GLSL_TYPE_UINT64
;
1923 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1926 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1929 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1931 case ir_unop_round_even
:
1932 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1935 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1939 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1942 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1945 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1948 case ir_unop_bit_not
:
1949 if (native_integers
) {
1950 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1954 if (native_integers
) {
1955 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1958 case ir_binop_lshift
:
1959 case ir_binop_rshift
:
1960 if (native_integers
) {
1961 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1962 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1965 if (glsl_base_type_is_64bit(op
[0].type
)) {
1966 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1969 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1970 ->type
->components()));
1971 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1976 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1979 case ir_binop_bit_and
:
1980 if (native_integers
) {
1981 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1984 case ir_binop_bit_xor
:
1985 if (native_integers
) {
1986 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1989 case ir_binop_bit_or
:
1990 if (native_integers
) {
1991 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1995 assert(!"GLSL 1.30 features unsupported");
1998 case ir_binop_ubo_load
: {
1999 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
2000 ir_rvalue
*block
= ir
->operands
[0];
2001 ir_rvalue
*offset
= ir
->operands
[1];
2002 ir_constant
*const_block
= block
->as_constant();
2004 st_src_reg
cbuf(PROGRAM_CONSTANT
,
2005 (const_block
? const_block
->value
.u
[0] + 1 : 1),
2006 ir
->type
->base_type
);
2008 cbuf
.has_index2
= true;
2011 block
->accept(this);
2012 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2013 *cbuf
.reladdr
= this->result
;
2014 emit_arl(ir
, sampler_reladdr
, this->result
);
2017 /* Calculate the surface offset */
2018 offset
->accept(this);
2019 st_src_reg off
= this->result
;
2021 glsl_to_tgsi_instruction
*inst
=
2022 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
2024 if (result_dst
.type
== GLSL_TYPE_BOOL
)
2025 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
2026 st_src_reg_for_int(0));
2028 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
2031 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2032 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2033 unsigned const_offset
= const_offset_ir
?
2034 const_offset_ir
->value
.u
[0] : 0;
2035 unsigned const_block
= const_uniform_block
?
2036 const_uniform_block
->value
.u
[0] + 1 : 1;
2037 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2040 cbuf
.type
= ir
->type
->base_type
;
2041 cbuf
.file
= PROGRAM_CONSTANT
;
2043 cbuf
.reladdr
= NULL
;
2046 cbuf
.index2D
= const_block
;
2048 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2050 if (const_offset_ir
) {
2051 /* Constant index into constant buffer */
2052 cbuf
.reladdr
= NULL
;
2053 cbuf
.index
= const_offset
/ 16;
2055 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2056 st_src_reg offset
= op
[1];
2058 /* The OpenGL spec is written in such a way that accesses with
2059 * non-constant offset are almost always vec4-aligned. The only
2060 * exception to this are members of structs in arrays of structs:
2061 * each struct in an array of structs is at least vec4-aligned,
2062 * but single-element and [ui]vec2 members of the struct may be at
2063 * an offset that is not a multiple of 16 bytes.
2065 * Here, we extract that offset, relying on previous passes to
2066 * always generate offset expressions of the form
2067 * (+ expr constant_offset).
2069 * Note that the std430 layout, which allows more cases of
2070 * alignment less than vec4 in arrays, is not supported for
2071 * uniform blocks, so we do not have to deal with it here.
2073 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2074 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2075 if (const_offset_ir
) {
2076 const_offset
= const_offset_ir
->value
.u
[0];
2077 cbuf
.index
= const_offset
/ 16;
2078 offset_expr
->operands
[0]->accept(this);
2079 offset
= this->result
;
2083 /* Relative/variable index into constant buffer */
2084 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2085 st_src_reg_for_int(4));
2086 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2087 *cbuf
.reladdr
= index_reg
;
2090 if (const_uniform_block
) {
2091 /* Constant constant buffer */
2092 cbuf
.reladdr2
= NULL
;
2094 /* Relative/variable constant buffer */
2095 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2096 *cbuf
.reladdr2
= op
[0];
2098 cbuf
.has_index2
= true;
2100 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2101 if (glsl_base_type_is_64bit(cbuf
.type
))
2102 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2103 const_offset
% 16 / 8,
2104 const_offset
% 16 / 8,
2105 const_offset
% 16 / 8);
2107 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2108 const_offset
% 16 / 4,
2109 const_offset
% 16 / 4,
2110 const_offset
% 16 / 4);
2112 if (ir
->type
->is_boolean()) {
2113 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2114 st_src_reg_for_int(0));
2116 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2122 /* note: we have to reorder the three args here */
2123 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2126 if (this->ctx
->Const
.NativeIntegers
)
2127 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2129 op
[0].negate
= ~op
[0].negate
;
2130 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2133 case ir_triop_bitfield_extract
:
2134 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2136 case ir_quadop_bitfield_insert
:
2137 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2139 case ir_unop_bitfield_reverse
:
2140 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2142 case ir_unop_bit_count
:
2143 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2145 case ir_unop_find_msb
:
2146 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2148 case ir_unop_find_lsb
:
2149 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2151 case ir_binop_imul_high
:
2152 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2155 /* In theory, MAD is incorrect here. */
2157 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2159 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2161 case ir_unop_interpolate_at_centroid
:
2162 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2164 case ir_binop_interpolate_at_offset
: {
2165 /* The y coordinate needs to be flipped for the default fb */
2166 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2167 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2169 unsigned transform_y_index
=
2170 _mesa_add_state_reference(this->prog
->Parameters
,
2173 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2175 glsl_type::vec4_type
);
2176 transform_y
.swizzle
= SWIZZLE_XXXX
;
2178 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2179 st_dst_reg temp_dst
= st_dst_reg(temp
);
2181 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2182 temp_dst
.writemask
= WRITEMASK_Y
;
2183 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2184 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2187 case ir_binop_interpolate_at_sample
:
2188 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2192 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2195 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2198 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2201 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2204 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2207 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2209 case ir_unop_unpack_double_2x32
:
2210 case ir_unop_pack_double_2x32
:
2211 case ir_unop_unpack_int_2x32
:
2212 case ir_unop_pack_int_2x32
:
2213 case ir_unop_unpack_uint_2x32
:
2214 case ir_unop_pack_uint_2x32
:
2215 case ir_unop_unpack_sampler_2x32
:
2216 case ir_unop_pack_sampler_2x32
:
2217 case ir_unop_unpack_image_2x32
:
2218 case ir_unop_pack_image_2x32
:
2219 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2222 case ir_binop_ldexp
:
2223 if (ir
->operands
[0]->type
->is_double()) {
2224 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2225 } else if (ir
->operands
[0]->type
->is_float()) {
2226 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2228 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2232 case ir_unop_pack_half_2x16
:
2233 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2235 case ir_unop_unpack_half_2x16
:
2236 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2239 case ir_unop_get_buffer_size
: {
2240 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2241 int buf_base
= ctx
->st
->has_hw_atomics
2242 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
2245 buf_base
+ (const_offset
? const_offset
->value
.u
[0] : 0),
2247 if (!const_offset
) {
2248 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2249 *buffer
.reladdr
= op
[0];
2250 emit_arl(ir
, sampler_reladdr
, op
[0]);
2252 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2258 case ir_unop_b2i64
: {
2259 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2260 st_dst_reg temp_dst
= st_dst_reg(temp
);
2261 unsigned orig_swz
= op
[0].swizzle
;
2263 * To convert unsigned to 64-bit:
2264 * zero Y channel, copy X channel.
2266 temp_dst
.writemask
= WRITEMASK_Y
;
2267 if (vector_elements
> 1)
2268 temp_dst
.writemask
|= WRITEMASK_W
;
2269 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2270 temp_dst
.writemask
= WRITEMASK_X
;
2271 if (vector_elements
> 1)
2272 temp_dst
.writemask
|= WRITEMASK_Z
;
2273 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2274 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2275 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2276 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2278 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2280 result_src
.type
= GLSL_TYPE_UINT64
;
2281 if (vector_elements
> 2) {
2282 /* Subtle: We rely on the fact that get_temp here returns the next
2283 * TGSI temporary register directly after the temp register used for
2284 * the first two components, so that the result gets picked up
2287 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2288 st_dst_reg temp_dst
= st_dst_reg(temp
);
2289 temp_dst
.writemask
= WRITEMASK_Y
;
2290 if (vector_elements
> 3)
2291 temp_dst
.writemask
|= WRITEMASK_W
;
2292 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2294 temp_dst
.writemask
= WRITEMASK_X
;
2295 if (vector_elements
> 3)
2296 temp_dst
.writemask
|= WRITEMASK_Z
;
2297 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2298 GET_SWZ(orig_swz
, 2),
2299 GET_SWZ(orig_swz
, 3),
2300 GET_SWZ(orig_swz
, 3));
2301 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2302 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2304 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2305 st_src_reg_for_int(1));
2312 case ir_unop_i642u
: {
2313 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2314 st_dst_reg temp_dst
= st_dst_reg(temp
);
2315 unsigned orig_swz
= op
[0].swizzle
;
2316 unsigned orig_idx
= op
[0].index
;
2318 temp_dst
.writemask
= WRITEMASK_X
;
2320 for (el
= 0; el
< vector_elements
; el
++) {
2321 unsigned swz
= GET_SWZ(orig_swz
, el
);
2323 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2324 SWIZZLE_Z
, SWIZZLE_Z
);
2326 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2327 SWIZZLE_X
, SWIZZLE_X
);
2329 op
[0].index
= orig_idx
+ 1;
2330 op
[0].type
= GLSL_TYPE_UINT
;
2331 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2332 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2335 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2336 result_src
.type
= GLSL_TYPE_UINT
;
2338 result_src
.type
= GLSL_TYPE_INT
;
2342 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2343 st_src_reg_for_int64(0));
2346 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2349 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2352 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2355 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2358 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2361 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2364 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2367 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2370 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2373 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2375 /* these might be needed */
2376 case ir_unop_pack_snorm_2x16
:
2377 case ir_unop_pack_unorm_2x16
:
2378 case ir_unop_pack_snorm_4x8
:
2379 case ir_unop_pack_unorm_4x8
:
2381 case ir_unop_unpack_snorm_2x16
:
2382 case ir_unop_unpack_unorm_2x16
:
2383 case ir_unop_unpack_snorm_4x8
:
2384 case ir_unop_unpack_unorm_4x8
:
2386 case ir_quadop_vector
:
2387 case ir_binop_vector_extract
:
2388 case ir_triop_vector_insert
:
2389 case ir_binop_carry
:
2390 case ir_binop_borrow
:
2391 case ir_unop_ssbo_unsized_array_length
:
2393 case ir_binop_atan2
:
2394 /* This operation is not supported, or should have already been handled.
2396 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2400 this->result
= result_src
;
2405 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2411 /* Note that this is only swizzles in expressions, not those on the left
2412 * hand side of an assignment, which do write masking. See ir_assignment
2416 ir
->val
->accept(this);
2418 assert(src
.file
!= PROGRAM_UNDEFINED
);
2419 assert(ir
->type
->vector_elements
> 0);
2421 for (i
= 0; i
< 4; i
++) {
2422 if (i
< ir
->type
->vector_elements
) {
2425 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2428 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2431 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2434 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2438 /* If the type is smaller than a vec4, replicate the last
2441 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2445 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2450 /* Test if the variable is an array. Note that geometry and
2451 * tessellation shader inputs are outputs are always arrays (except
2452 * for patch inputs), so only the array element type is considered.
2455 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2457 const glsl_type
*type
= var
->type
;
2459 *remove_array
= false;
2461 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2462 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2465 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2466 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2467 stage
== MESA_SHADER_TESS_CTRL
) &&
2469 if (!var
->type
->is_array())
2470 return false; /* a system value probably */
2472 type
= var
->type
->fields
.array
;
2473 *remove_array
= true;
2476 return type
->is_array() || type
->is_matrix();
2480 st_translate_interp_loc(ir_variable
*var
)
2482 if (var
->data
.centroid
)
2483 return TGSI_INTERPOLATE_LOC_CENTROID
;
2484 else if (var
->data
.sample
)
2485 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2487 return TGSI_INTERPOLATE_LOC_CENTER
;
2491 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2493 variable_storage
*entry
;
2494 ir_variable
*var
= ir
->var
;
2497 if (handle_bound_deref(ir
->as_dereference()))
2500 entry
= find_variable_storage(ir
->var
);
2503 switch (var
->data
.mode
) {
2504 case ir_var_uniform
:
2505 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2506 var
->data
.param_index
);
2507 _mesa_hash_table_insert(this->variables
, var
, entry
);
2509 case ir_var_shader_in
: {
2510 /* The linker assigns locations for varyings and attributes,
2511 * including deprecated builtins (like gl_Color), user-assign
2512 * generic attributes (glBindVertexLocation), and
2513 * user-defined varyings.
2515 assert(var
->data
.location
!= -1);
2517 const glsl_type
*type_without_array
= var
->type
->without_array();
2518 struct inout_decl
*decl
= &inputs
[num_inputs
];
2519 unsigned component
= var
->data
.location_frac
;
2520 unsigned num_components
;
2523 if (type_without_array
->is_64bit())
2524 component
= component
/ 2;
2525 if (type_without_array
->vector_elements
)
2526 num_components
= type_without_array
->vector_elements
;
2530 decl
->mesa_index
= var
->data
.location
;
2531 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2532 decl
->interp_loc
= st_translate_interp_loc(var
);
2533 decl
->base_type
= type_without_array
->base_type
;
2534 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2536 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2537 decl
->array_id
= num_input_arrays
+ 1;
2544 decl
->size
= type_size(var
->type
->fields
.array
);
2546 decl
->size
= type_size(var
->type
);
2548 entry
= new(mem_ctx
) variable_storage(var
,
2552 entry
->component
= component
;
2554 _mesa_hash_table_insert(this->variables
, var
, entry
);
2558 case ir_var_shader_out
: {
2559 assert(var
->data
.location
!= -1);
2561 const glsl_type
*type_without_array
= var
->type
->without_array();
2562 struct inout_decl
*decl
= &outputs
[num_outputs
];
2563 unsigned component
= var
->data
.location_frac
;
2564 unsigned num_components
;
2567 decl
->invariant
= var
->data
.invariant
;
2569 if (type_without_array
->is_64bit())
2570 component
= component
/ 2;
2571 if (type_without_array
->vector_elements
)
2572 num_components
= type_without_array
->vector_elements
;
2576 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2577 decl
->base_type
= type_without_array
->base_type
;
2578 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2579 if (var
->data
.stream
& (1u << 31)) {
2580 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2582 assert(var
->data
.stream
< 4);
2583 decl
->gs_out_streams
= 0;
2584 for (unsigned i
= 0; i
< num_components
; ++i
)
2585 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2588 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2589 decl
->array_id
= num_output_arrays
+ 1;
2590 num_output_arrays
++;
2596 decl
->size
= type_size(var
->type
->fields
.array
);
2598 decl
->size
= type_size(var
->type
);
2600 if (var
->data
.fb_fetch_output
) {
2601 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2602 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2603 var
->type
, component
, decl
->array_id
);
2604 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2605 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2608 entry
= new(mem_ctx
) variable_storage(var
,
2613 entry
->component
= component
;
2615 _mesa_hash_table_insert(this->variables
, var
, entry
);
2619 case ir_var_system_value
:
2620 entry
= new(mem_ctx
) variable_storage(var
,
2621 PROGRAM_SYSTEM_VALUE
,
2622 var
->data
.location
);
2625 case ir_var_temporary
:
2626 st_src_reg src
= get_temp(var
->type
);
2628 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2630 _mesa_hash_table_insert(this->variables
, var
, entry
);
2636 printf("Failed to make storage for %s\n", var
->name
);
2641 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2642 entry
->component
, entry
->array_id
);
2643 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2644 var
->data
.mode
== ir_var_shader_in
&&
2645 var
->type
->without_array()->is_double())
2646 this->result
.is_double_vertex_input
= true;
2647 if (!native_integers
)
2648 this->result
.type
= GLSL_TYPE_FLOAT
;
2652 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2653 GLbitfield64
* usage_mask
,
2654 GLbitfield64 double_usage_mask
,
2655 GLbitfield
* patch_usage_mask
)
2660 /* Fix array declarations by removing unused array elements at both ends
2661 * of the arrays. For example, mat4[3] where only mat[1] is used.
2663 for (i
= 0; i
< count
; i
++) {
2664 struct inout_decl
*decl
= &decls
[i
];
2665 if (!decl
->array_id
)
2668 /* Shrink the beginning. */
2669 for (j
= 0; j
< (int)decl
->size
; j
++) {
2670 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2671 if (*patch_usage_mask
&
2672 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2676 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2678 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2687 /* Shrink the end. */
2688 for (j
= decl
->size
-1; j
>= 0; j
--) {
2689 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2690 if (*patch_usage_mask
&
2691 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2695 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2697 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2704 /* When not all entries of an array are accessed, we mark them as used
2705 * here anyway, to ensure that the input/output mapping logic doesn't get
2708 * TODO This happens when an array isn't used via indirect access, which
2709 * some game ports do (at least eON-based). There is an optimization
2710 * opportunity here by replacing the array declaration with non-array
2711 * declarations of those slots that are actually used.
2713 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2714 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2715 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2717 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2724 mark_array_io(struct inout_decl
*decls
, unsigned count
,
2725 GLbitfield64
* usage_mask
,
2726 GLbitfield64 double_usage_mask
,
2727 GLbitfield
* patch_usage_mask
)
2732 /* Fix array declarations by removing unused array elements at both ends
2733 * of the arrays. For example, mat4[3] where only mat[1] is used.
2735 for (i
= 0; i
< count
; i
++) {
2736 struct inout_decl
*decl
= &decls
[i
];
2737 if (!decl
->array_id
)
2740 /* When not all entries of an array are accessed, we mark them as used
2741 * here anyway, to ensure that the input/output mapping logic doesn't get
2744 * TODO This happens when an array isn't used via indirect access, which
2745 * some game ports do (at least eON-based). There is an optimization
2746 * opportunity here by replacing the array declaration with non-array
2747 * declarations of those slots that are actually used.
2749 for (j
= 0; j
< (int)decl
->size
; ++j
) {
2750 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2751 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2753 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2759 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2764 ir_variable
*var
= ir
->variable_referenced();
2766 if (handle_bound_deref(ir
->as_dereference()))
2769 /* We only need the logic provided by st_glsl_storage_type_size()
2770 * for arrays of structs. Indirect sampler and image indexing is handled
2773 int element_size
= ir
->type
->without_array()->is_struct() ?
2774 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2775 type_size(ir
->type
);
2777 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2779 ir
->array
->accept(this);
2782 if (!src
.has_index2
) {
2783 switch (this->prog
->Target
) {
2784 case GL_TESS_CONTROL_PROGRAM_NV
:
2785 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2786 !ir
->variable_referenced()->data
.patch
;
2788 case GL_TESS_EVALUATION_PROGRAM_NV
:
2789 is_2D
= src
.file
== PROGRAM_INPUT
&&
2790 !ir
->variable_referenced()->data
.patch
;
2792 case GL_GEOMETRY_PROGRAM_NV
:
2793 is_2D
= src
.file
== PROGRAM_INPUT
;
2803 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2804 src
.file
== PROGRAM_INPUT
)
2805 element_size
= attrib_type_size(ir
->type
, true);
2807 src
.index2D
= index
->value
.i
[0];
2808 src
.has_index2
= true;
2810 src
.index
+= index
->value
.i
[0] * element_size
;
2812 /* Variable index array dereference. It eats the "vec4" of the
2813 * base of the array and an index that offsets the TGSI register
2816 ir
->array_index
->accept(this);
2818 st_src_reg index_reg
;
2820 if (element_size
== 1) {
2821 index_reg
= this->result
;
2823 index_reg
= get_temp(native_integers
?
2824 glsl_type::int_type
: glsl_type::float_type
);
2826 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2827 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2830 /* If there was already a relative address register involved, add the
2831 * new and the old together to get the new offset.
2833 if (!is_2D
&& src
.reladdr
!= NULL
) {
2834 st_src_reg accum_reg
= get_temp(native_integers
?
2835 glsl_type::int_type
: glsl_type::float_type
);
2837 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2838 index_reg
, *src
.reladdr
);
2840 index_reg
= accum_reg
;
2844 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2845 *src
.reladdr2
= index_reg
;
2847 src
.has_index2
= true;
2849 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2850 *src
.reladdr
= index_reg
;
2854 /* Change the register type to the element type of the array. */
2855 src
.type
= ir
->type
->base_type
;
2861 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2864 const glsl_type
*struct_type
= ir
->record
->type
;
2865 ir_variable
*var
= ir
->record
->variable_referenced();
2868 if (handle_bound_deref(ir
->as_dereference()))
2871 ir
->record
->accept(this);
2873 assert(ir
->field_idx
>= 0);
2875 for (i
= 0; i
< struct_type
->length
; i
++) {
2876 if (i
== (unsigned) ir
->field_idx
)
2878 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2879 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2882 /* If the type is smaller than a vec4, replicate the last channel out. */
2883 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2884 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2886 this->result
.swizzle
= SWIZZLE_NOOP
;
2888 this->result
.index
+= offset
;
2889 this->result
.type
= ir
->type
->base_type
;
2893 * We want to be careful in assignment setup to hit the actual storage
2894 * instead of potentially using a temporary like we might with the
2895 * ir_dereference handler.
2898 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2900 /* The LHS must be a dereference. If the LHS is a variable indexed array
2901 * access of a vector, it must be separated into a series conditional moves
2902 * before reaching this point (see ir_vec_index_to_cond_assign).
2904 assert(ir
->as_dereference());
2905 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2907 assert(!deref_array
->array
->type
->is_vector());
2910 /* Use the rvalue deref handler for the most part. We write swizzles using
2911 * the writemask, but we do extract the base component for enhanced layouts
2912 * from the source swizzle.
2915 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2916 return st_dst_reg(v
->result
);
2920 * Process the condition of a conditional assignment
2922 * Examines the condition of a conditional assignment to generate the optimal
2923 * first operand of a \c CMP instruction. If the condition is a relational
2924 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2925 * used as the source for the \c CMP instruction. Otherwise the comparison
2926 * is processed to a boolean result, and the boolean result is used as the
2927 * operand to the CMP instruction.
2930 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2932 ir_rvalue
*src_ir
= ir
;
2934 bool switch_order
= false;
2936 ir_expression
*const expr
= ir
->as_expression();
2938 if (native_integers
) {
2939 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2940 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2941 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2942 type
== GLSL_TYPE_BOOL
) {
2943 if (expr
->operation
== ir_binop_equal
) {
2944 if (expr
->operands
[0]->is_zero()) {
2945 src_ir
= expr
->operands
[1];
2946 switch_order
= true;
2948 else if (expr
->operands
[1]->is_zero()) {
2949 src_ir
= expr
->operands
[0];
2950 switch_order
= true;
2953 else if (expr
->operation
== ir_binop_nequal
) {
2954 if (expr
->operands
[0]->is_zero()) {
2955 src_ir
= expr
->operands
[1];
2957 else if (expr
->operands
[1]->is_zero()) {
2958 src_ir
= expr
->operands
[0];
2964 src_ir
->accept(this);
2965 return switch_order
;
2968 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2969 bool zero_on_left
= false;
2971 if (expr
->operands
[0]->is_zero()) {
2972 src_ir
= expr
->operands
[1];
2973 zero_on_left
= true;
2974 } else if (expr
->operands
[1]->is_zero()) {
2975 src_ir
= expr
->operands
[0];
2976 zero_on_left
= false;
2980 * (a < 0) T F F ( a < 0) T F F
2981 * (0 < a) F F T (-a < 0) F F T
2982 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2983 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2985 * Note that exchanging the order of 0 and 'a' in the comparison simply
2986 * means that the value of 'a' should be negated.
2989 switch (expr
->operation
) {
2991 switch_order
= false;
2992 negate
= zero_on_left
;
2995 case ir_binop_gequal
:
2996 switch_order
= true;
2997 negate
= zero_on_left
;
3001 /* This isn't the right kind of comparison afterall, so make sure
3002 * the whole condition is visited.
3010 src_ir
->accept(this);
3012 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3013 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3014 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3015 * computing the condition.
3018 this->result
.negate
= ~this->result
.negate
;
3020 return switch_order
;
3024 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3025 st_dst_reg
*l
, st_src_reg
*r
,
3026 st_src_reg
*cond
, bool cond_swap
)
3028 if (type
->is_struct()) {
3029 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3030 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3036 if (type
->is_array()) {
3037 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3038 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3043 if (type
->is_matrix()) {
3044 const struct glsl_type
*vec_type
;
3046 vec_type
= glsl_type::get_instance(type
->is_double()
3047 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3048 type
->vector_elements
, 1);
3050 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3051 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3056 assert(type
->is_scalar() || type
->is_vector());
3058 l
->type
= type
->base_type
;
3059 r
->type
= type
->base_type
;
3061 st_src_reg l_src
= st_src_reg(*l
);
3063 if (l_src
.file
== PROGRAM_OUTPUT
&&
3064 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
3065 (l_src
.index
== FRAG_RESULT_DEPTH
||
3066 l_src
.index
== FRAG_RESULT_STENCIL
)) {
3067 /* This is a special case because the source swizzles will be shifted
3068 * later to account for the difference between GLSL (where they're
3069 * plain floats) and TGSI (where they're Z and Y components). */
3070 l_src
.swizzle
= SWIZZLE_XXXX
;
3073 if (native_integers
) {
3074 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3075 cond_swap
? l_src
: *r
,
3076 cond_swap
? *r
: l_src
);
3078 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3079 cond_swap
? l_src
: *r
,
3080 cond_swap
? *r
: l_src
);
3083 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3087 if (type
->is_dual_slot()) {
3089 if (r
->is_double_vertex_input
== false)
3095 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3101 /* all generated instructions need to be flaged as precise */
3102 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3103 ir
->rhs
->accept(this);
3106 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3110 int first_enabled_chan
= 0;
3112 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3114 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3115 variable
->data
.mode
== ir_var_shader_out
&&
3116 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3117 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3118 assert(ir
->lhs
->type
->is_scalar());
3119 assert(ir
->write_mask
== WRITEMASK_X
);
3121 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3122 l
.writemask
= WRITEMASK_Z
;
3124 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3125 l
.writemask
= WRITEMASK_Y
;
3127 } else if (ir
->write_mask
== 0) {
3128 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3130 unsigned num_elements
=
3131 ir
->lhs
->type
->without_array()->vector_elements
;
3134 l
.writemask
= u_bit_consecutive(0, num_elements
);
3136 /* The type is a struct or an array of (array of) structs. */
3137 l
.writemask
= WRITEMASK_XYZW
;
3140 l
.writemask
= ir
->write_mask
;
3143 for (int i
= 0; i
< 4; i
++) {
3144 if (l
.writemask
& (1 << i
)) {
3145 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3150 l
.writemask
= l
.writemask
<< dst_component
;
3152 /* Swizzle a small RHS vector into the channels being written.
3154 * glsl ir treats write_mask as dictating how many channels are
3155 * present on the RHS while TGSI treats write_mask as just
3156 * showing which channels of the vec4 RHS get written.
3158 for (int i
= 0; i
< 4; i
++) {
3159 if (l
.writemask
& (1 << i
))
3160 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3162 swizzles
[i
] = first_enabled_chan
;
3164 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3165 swizzles
[2], swizzles
[3]);
3168 assert(l
.file
!= PROGRAM_UNDEFINED
);
3169 assert(r
.file
!= PROGRAM_UNDEFINED
);
3171 if (ir
->condition
) {
3172 const bool switch_order
= this->process_move_condition(ir
->condition
);
3173 st_src_reg condition
= this->result
;
3175 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3176 } else if (ir
->rhs
->as_expression() &&
3177 this->instructions
.get_tail() &&
3178 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3179 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3180 type_size(ir
->lhs
->type
) == 1 &&
3181 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3182 /* To avoid emitting an extra MOV when assigning an expression to a
3183 * variable, emit the last instruction of the expression again, but
3184 * replace the destination register with the target of the assignment.
3185 * Dead code elimination will remove the original instruction.
3187 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3188 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3189 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3190 new_inst
->saturate
= inst
->saturate
;
3191 new_inst
->resource
= inst
->resource
;
3192 inst
->dead_mask
= inst
->dst
[0].writemask
;
3194 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3201 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3204 GLdouble stack_vals
[4] = { 0 };
3205 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3206 GLenum gl_type
= GL_NONE
;
3207 unsigned int i
, elements
;
3208 static int in_array
= 0;
3209 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3211 /* Unfortunately, 4 floats is all we can get into
3212 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3213 * aggregate constant and move each constant value into it. If we
3214 * get lucky, copy propagation will eliminate the extra moves.
3216 if (ir
->type
->is_struct()) {
3217 st_src_reg temp_base
= get_temp(ir
->type
);
3218 st_dst_reg temp
= st_dst_reg(temp_base
);
3220 for (i
= 0; i
< ir
->type
->length
; i
++) {
3221 ir_constant
*const field_value
= ir
->get_record_field(i
);
3222 int size
= type_size(field_value
->type
);
3226 field_value
->accept(this);
3229 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3230 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3236 this->result
= temp_base
;
3240 if (ir
->type
->is_array()) {
3241 st_src_reg temp_base
= get_temp(ir
->type
);
3242 st_dst_reg temp
= st_dst_reg(temp_base
);
3243 int size
= type_size(ir
->type
->fields
.array
);
3248 for (i
= 0; i
< ir
->type
->length
; i
++) {
3249 ir
->const_elements
[i
]->accept(this);
3251 for (int j
= 0; j
< size
; j
++) {
3252 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3258 this->result
= temp_base
;
3263 if (ir
->type
->is_matrix()) {
3264 st_src_reg mat
= get_temp(ir
->type
);
3265 st_dst_reg mat_column
= st_dst_reg(mat
);
3267 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3268 switch (ir
->type
->base_type
) {
3269 case GLSL_TYPE_FLOAT
:
3270 values
= (gl_constant_value
*)
3271 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3273 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3274 src
.index
= add_constant(file
,
3276 ir
->type
->vector_elements
,
3279 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3281 case GLSL_TYPE_DOUBLE
:
3282 values
= (gl_constant_value
*)
3283 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3284 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3285 src
.index
= add_constant(file
,
3287 ir
->type
->vector_elements
,
3290 if (ir
->type
->vector_elements
>= 2) {
3291 mat_column
.writemask
= WRITEMASK_XY
;
3292 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3293 SWIZZLE_X
, SWIZZLE_Y
);
3294 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3296 mat_column
.writemask
= WRITEMASK_X
;
3297 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3298 SWIZZLE_X
, SWIZZLE_X
);
3299 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3302 if (ir
->type
->vector_elements
> 2) {
3303 if (ir
->type
->vector_elements
== 4) {
3304 mat_column
.writemask
= WRITEMASK_ZW
;
3305 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3306 SWIZZLE_X
, SWIZZLE_Y
);
3307 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3309 mat_column
.writemask
= WRITEMASK_Z
;
3310 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3311 SWIZZLE_Y
, SWIZZLE_Y
);
3312 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3313 mat_column
.writemask
= WRITEMASK_XYZW
;
3314 src
.swizzle
= SWIZZLE_XYZW
;
3320 unreachable("Illegal matrix constant type.\n");
3329 elements
= ir
->type
->vector_elements
;
3330 switch (ir
->type
->base_type
) {
3331 case GLSL_TYPE_FLOAT
:
3333 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3334 values
[i
].f
= ir
->value
.f
[i
];
3337 case GLSL_TYPE_DOUBLE
:
3338 gl_type
= GL_DOUBLE
;
3339 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3340 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3343 case GLSL_TYPE_INT64
:
3344 gl_type
= GL_INT64_ARB
;
3345 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3346 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3349 case GLSL_TYPE_UINT64
:
3350 gl_type
= GL_UNSIGNED_INT64_ARB
;
3351 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3352 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3355 case GLSL_TYPE_UINT
:
3356 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3357 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3358 if (native_integers
)
3359 values
[i
].u
= ir
->value
.u
[i
];
3361 values
[i
].f
= ir
->value
.u
[i
];
3365 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3366 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3367 if (native_integers
)
3368 values
[i
].i
= ir
->value
.i
[i
];
3370 values
[i
].f
= ir
->value
.i
[i
];
3373 case GLSL_TYPE_BOOL
:
3374 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3375 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3376 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3379 case GLSL_TYPE_SAMPLER
:
3380 case GLSL_TYPE_IMAGE
:
3381 gl_type
= GL_UNSIGNED_INT
;
3383 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3384 values
[1].u
= ir
->value
.u64
[0] >> 32;
3387 assert(!"Non-float/uint/int/bool/sampler/image constant");
3390 this->result
= st_src_reg(file
, -1, ir
->type
);
3391 this->result
.index
= add_constant(file
,
3395 &this->result
.swizzle
);
3399 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3401 exec_node
*param
= ir
->actual_parameters
.get_head();
3402 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3403 ir_variable
*location
= deref
->variable_referenced();
3404 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3405 /* Calculate the surface offset */
3407 unsigned array_size
= 0, base
= 0;
3409 st_src_reg resource
;
3411 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3413 if (has_hw_atomics
) {
3414 variable_storage
*entry
= find_variable_storage(location
);
3415 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3416 location
->data
.binding
);
3419 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3421 _mesa_hash_table_insert(this->variables
, location
, entry
);
3423 atomic_info
[num_atomics
].location
= location
->data
.location
;
3424 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3425 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3426 if (atomic_info
[num_atomics
].size
== 0)
3427 atomic_info
[num_atomics
].size
= 1;
3428 atomic_info
[num_atomics
].array_id
= 0;
3432 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3433 if (atomic_info
[entry
->index
].array_id
== 0) {
3434 num_atomic_arrays
++;
3435 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3437 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3440 buffer
.index
= index
;
3441 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3442 buffer
.has_index2
= true;
3444 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3445 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3446 *buffer
.reladdr
= offset
;
3447 emit_arl(ir
, sampler_reladdr
, offset
);
3449 offset
= st_src_reg_for_int(0);
3453 st_src_reg
buffer(PROGRAM_BUFFER
, location
->data
.binding
,
3454 GLSL_TYPE_ATOMIC_UINT
);
3456 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3457 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3458 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3459 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3460 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3462 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3467 ir
->return_deref
->accept(this);
3468 st_dst_reg
dst(this->result
);
3469 dst
.writemask
= WRITEMASK_X
;
3471 glsl_to_tgsi_instruction
*inst
;
3473 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3474 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3475 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3476 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3477 st_src_reg_for_int(1));
3478 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3479 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3480 st_src_reg_for_int(-1));
3481 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3483 param
= param
->get_next();
3484 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3487 st_src_reg data
= this->result
, data2
= undef_src
;
3488 enum tgsi_opcode opcode
;
3489 switch (ir
->callee
->intrinsic_id
) {
3490 case ir_intrinsic_atomic_counter_add
:
3491 opcode
= TGSI_OPCODE_ATOMUADD
;
3493 case ir_intrinsic_atomic_counter_min
:
3494 opcode
= TGSI_OPCODE_ATOMIMIN
;
3496 case ir_intrinsic_atomic_counter_max
:
3497 opcode
= TGSI_OPCODE_ATOMIMAX
;
3499 case ir_intrinsic_atomic_counter_and
:
3500 opcode
= TGSI_OPCODE_ATOMAND
;
3502 case ir_intrinsic_atomic_counter_or
:
3503 opcode
= TGSI_OPCODE_ATOMOR
;
3505 case ir_intrinsic_atomic_counter_xor
:
3506 opcode
= TGSI_OPCODE_ATOMXOR
;
3508 case ir_intrinsic_atomic_counter_exchange
:
3509 opcode
= TGSI_OPCODE_ATOMXCHG
;
3511 case ir_intrinsic_atomic_counter_comp_swap
: {
3512 opcode
= TGSI_OPCODE_ATOMCAS
;
3513 param
= param
->get_next();
3514 val
= ((ir_instruction
*)param
)->as_rvalue();
3516 data2
= this->result
;
3520 assert(!"Unexpected intrinsic");
3524 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3527 inst
->resource
= resource
;
3531 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3533 exec_node
*param
= ir
->actual_parameters
.get_head();
3535 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3537 param
= param
->get_next();
3538 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3540 ir_constant
*const_block
= block
->as_constant();
3541 int buf_base
= st_context(ctx
)->has_hw_atomics
3542 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
3545 buf_base
+ (const_block
? const_block
->value
.u
[0] : 0),
3549 block
->accept(this);
3550 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3551 *buffer
.reladdr
= this->result
;
3552 emit_arl(ir
, sampler_reladdr
, this->result
);
3555 /* Calculate the surface offset */
3556 offset
->accept(this);
3557 st_src_reg off
= this->result
;
3559 st_dst_reg dst
= undef_dst
;
3560 if (ir
->return_deref
) {
3561 ir
->return_deref
->accept(this);
3562 dst
= st_dst_reg(this->result
);
3563 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3566 glsl_to_tgsi_instruction
*inst
;
3568 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3569 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3570 if (dst
.type
== GLSL_TYPE_BOOL
)
3571 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3572 st_src_reg_for_int(0));
3573 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3574 param
= param
->get_next();
3575 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3578 param
= param
->get_next();
3579 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3581 dst
.writemask
= write_mask
->value
.u
[0];
3583 dst
.type
= this->result
.type
;
3584 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3586 param
= param
->get_next();
3587 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3590 st_src_reg data
= this->result
, data2
= undef_src
;
3591 enum tgsi_opcode opcode
;
3592 switch (ir
->callee
->intrinsic_id
) {
3593 case ir_intrinsic_ssbo_atomic_add
:
3594 opcode
= TGSI_OPCODE_ATOMUADD
;
3596 case ir_intrinsic_ssbo_atomic_min
:
3597 opcode
= TGSI_OPCODE_ATOMIMIN
;
3599 case ir_intrinsic_ssbo_atomic_max
:
3600 opcode
= TGSI_OPCODE_ATOMIMAX
;
3602 case ir_intrinsic_ssbo_atomic_and
:
3603 opcode
= TGSI_OPCODE_ATOMAND
;
3605 case ir_intrinsic_ssbo_atomic_or
:
3606 opcode
= TGSI_OPCODE_ATOMOR
;
3608 case ir_intrinsic_ssbo_atomic_xor
:
3609 opcode
= TGSI_OPCODE_ATOMXOR
;
3611 case ir_intrinsic_ssbo_atomic_exchange
:
3612 opcode
= TGSI_OPCODE_ATOMXCHG
;
3614 case ir_intrinsic_ssbo_atomic_comp_swap
:
3615 opcode
= TGSI_OPCODE_ATOMCAS
;
3616 param
= param
->get_next();
3617 val
= ((ir_instruction
*)param
)->as_rvalue();
3619 data2
= this->result
;
3622 assert(!"Unexpected intrinsic");
3626 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3629 param
= param
->get_next();
3630 ir_constant
*access
= NULL
;
3631 if (!param
->is_tail_sentinel()) {
3632 access
= ((ir_instruction
*)param
)->as_constant();
3636 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3640 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3642 switch (ir
->callee
->intrinsic_id
) {
3643 case ir_intrinsic_memory_barrier
:
3644 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3645 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3646 TGSI_MEMBAR_ATOMIC_BUFFER
|
3647 TGSI_MEMBAR_SHADER_IMAGE
|
3648 TGSI_MEMBAR_SHARED
));
3650 case ir_intrinsic_memory_barrier_atomic_counter
:
3651 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3652 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3654 case ir_intrinsic_memory_barrier_buffer
:
3655 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3656 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3658 case ir_intrinsic_memory_barrier_image
:
3659 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3660 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3662 case ir_intrinsic_memory_barrier_shared
:
3663 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3664 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3666 case ir_intrinsic_group_memory_barrier
:
3667 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3668 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3669 TGSI_MEMBAR_ATOMIC_BUFFER
|
3670 TGSI_MEMBAR_SHADER_IMAGE
|
3671 TGSI_MEMBAR_SHARED
|
3672 TGSI_MEMBAR_THREAD_GROUP
));
3675 assert(!"Unexpected memory barrier intrinsic");
3680 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3682 exec_node
*param
= ir
->actual_parameters
.get_head();
3684 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3686 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3688 /* Calculate the surface offset */
3689 offset
->accept(this);
3690 st_src_reg off
= this->result
;
3692 st_dst_reg dst
= undef_dst
;
3693 if (ir
->return_deref
) {
3694 ir
->return_deref
->accept(this);
3695 dst
= st_dst_reg(this->result
);
3696 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3699 glsl_to_tgsi_instruction
*inst
;
3701 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3702 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3703 inst
->resource
= buffer
;
3704 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3705 param
= param
->get_next();
3706 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3709 param
= param
->get_next();
3710 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3712 dst
.writemask
= write_mask
->value
.u
[0];
3714 dst
.type
= this->result
.type
;
3715 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3716 inst
->resource
= buffer
;
3718 param
= param
->get_next();
3719 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3722 st_src_reg data
= this->result
, data2
= undef_src
;
3723 enum tgsi_opcode opcode
;
3724 switch (ir
->callee
->intrinsic_id
) {
3725 case ir_intrinsic_shared_atomic_add
:
3726 opcode
= TGSI_OPCODE_ATOMUADD
;
3728 case ir_intrinsic_shared_atomic_min
:
3729 opcode
= TGSI_OPCODE_ATOMIMIN
;
3731 case ir_intrinsic_shared_atomic_max
:
3732 opcode
= TGSI_OPCODE_ATOMIMAX
;
3734 case ir_intrinsic_shared_atomic_and
:
3735 opcode
= TGSI_OPCODE_ATOMAND
;
3737 case ir_intrinsic_shared_atomic_or
:
3738 opcode
= TGSI_OPCODE_ATOMOR
;
3740 case ir_intrinsic_shared_atomic_xor
:
3741 opcode
= TGSI_OPCODE_ATOMXOR
;
3743 case ir_intrinsic_shared_atomic_exchange
:
3744 opcode
= TGSI_OPCODE_ATOMXCHG
;
3746 case ir_intrinsic_shared_atomic_comp_swap
:
3747 opcode
= TGSI_OPCODE_ATOMCAS
;
3748 param
= param
->get_next();
3749 val
= ((ir_instruction
*)param
)->as_rvalue();
3751 data2
= this->result
;
3754 assert(!"Unexpected intrinsic");
3758 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3759 inst
->resource
= buffer
;
3764 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3765 bool *memory_coherent
, bool *memory_volatile
,
3766 bool *memory_restrict
, bool *memory_read_only
,
3767 unsigned *image_format
)
3770 switch (ir
->ir_type
) {
3771 case ir_type_dereference_record
: {
3772 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3773 const glsl_type
*struct_type
= deref_record
->record
->type
;
3774 int fild_idx
= deref_record
->field_idx
;
3776 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3778 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3780 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3782 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3784 struct_type
->fields
.structure
[fild_idx
].memory_read_only
;
3786 struct_type
->fields
.structure
[fild_idx
].image_format
;
3790 case ir_type_dereference_array
: {
3791 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3792 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3793 memory_coherent
, memory_volatile
, memory_restrict
,
3794 memory_read_only
, image_format
);
3798 case ir_type_dereference_variable
: {
3799 ir_variable
*var
= ir
->variable_referenced();
3801 *type
= var
->type
->without_array();
3802 *memory_coherent
= var
->data
.memory_coherent
;
3803 *memory_volatile
= var
->data
.memory_volatile
;
3804 *memory_restrict
= var
->data
.memory_restrict
;
3805 *memory_read_only
= var
->data
.memory_read_only
;
3806 *image_format
= var
->data
.image_format
;
3816 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3818 exec_node
*param
= ir
->actual_parameters
.get_head();
3820 ir_dereference
*img
= (ir_dereference
*)param
;
3821 const ir_variable
*imgvar
= img
->variable_referenced();
3822 unsigned sampler_array_size
= 1, sampler_base
= 0;
3823 bool memory_coherent
= false, memory_volatile
= false,
3824 memory_restrict
= false, memory_read_only
= false;
3825 unsigned image_format
= 0;
3826 const glsl_type
*type
= NULL
;
3828 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3829 &memory_restrict
, &memory_read_only
, &image_format
);
3832 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3834 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3835 &index
, &reladdr
, !imgvar
->contains_bindless());
3837 image
.index
= index
;
3838 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3839 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3840 *image
.reladdr
= reladdr
;
3841 emit_arl(ir
, sampler_reladdr
, reladdr
);
3844 st_dst_reg dst
= undef_dst
;
3845 if (ir
->return_deref
) {
3846 ir
->return_deref
->accept(this);
3847 dst
= st_dst_reg(this->result
);
3848 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3851 glsl_to_tgsi_instruction
*inst
;
3853 st_src_reg bindless
;
3854 if (imgvar
->contains_bindless()) {
3856 bindless
= this->result
;
3859 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3860 dst
.writemask
= WRITEMASK_XYZ
;
3861 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3862 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3863 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3864 st_dst_reg dstres
= st_dst_reg(res
);
3865 dstres
.writemask
= WRITEMASK_W
;
3866 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3867 res
.swizzle
= SWIZZLE_WWWW
;
3868 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3870 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3872 st_dst_reg coord_dst
;
3873 coord
= get_temp(glsl_type::ivec4_type
);
3874 coord_dst
= st_dst_reg(coord
);
3875 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3876 param
= param
->get_next();
3877 ((ir_dereference
*)param
)->accept(this);
3878 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3879 coord
.swizzle
= SWIZZLE_XXXX
;
3880 switch (type
->coordinate_components()) {
3881 case 4: assert(!"unexpected coord count");
3883 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3885 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3888 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3889 param
= param
->get_next();
3890 ((ir_dereference
*)param
)->accept(this);
3891 st_src_reg sample
= this->result
;
3892 sample
.swizzle
= SWIZZLE_XXXX
;
3893 coord_dst
.writemask
= WRITEMASK_W
;
3894 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3895 coord
.swizzle
|= SWIZZLE_W
<< 9;
3898 param
= param
->get_next();
3899 if (!param
->is_tail_sentinel()) {
3900 ((ir_dereference
*)param
)->accept(this);
3901 arg1
= this->result
;
3902 param
= param
->get_next();
3905 if (!param
->is_tail_sentinel()) {
3906 ((ir_dereference
*)param
)->accept(this);
3907 arg2
= this->result
;
3908 param
= param
->get_next();
3911 assert(param
->is_tail_sentinel());
3913 enum tgsi_opcode opcode
;
3914 switch (ir
->callee
->intrinsic_id
) {
3915 case ir_intrinsic_image_load
:
3916 opcode
= TGSI_OPCODE_LOAD
;
3918 case ir_intrinsic_image_store
:
3919 opcode
= TGSI_OPCODE_STORE
;
3921 case ir_intrinsic_image_atomic_add
:
3922 opcode
= TGSI_OPCODE_ATOMUADD
;
3924 case ir_intrinsic_image_atomic_min
:
3925 opcode
= TGSI_OPCODE_ATOMIMIN
;
3927 case ir_intrinsic_image_atomic_max
:
3928 opcode
= TGSI_OPCODE_ATOMIMAX
;
3930 case ir_intrinsic_image_atomic_and
:
3931 opcode
= TGSI_OPCODE_ATOMAND
;
3933 case ir_intrinsic_image_atomic_or
:
3934 opcode
= TGSI_OPCODE_ATOMOR
;
3936 case ir_intrinsic_image_atomic_xor
:
3937 opcode
= TGSI_OPCODE_ATOMXOR
;
3939 case ir_intrinsic_image_atomic_exchange
:
3940 opcode
= TGSI_OPCODE_ATOMXCHG
;
3942 case ir_intrinsic_image_atomic_comp_swap
:
3943 opcode
= TGSI_OPCODE_ATOMCAS
;
3945 case ir_intrinsic_image_atomic_inc_wrap
: {
3946 /* There's a bit of disagreement between GLSL and the hardware. The
3947 * hardware wants to wrap after the given wrap value, while GLSL
3948 * wants to wrap at the value. Subtract 1 to make up the difference.
3950 st_src_reg wrap
= get_temp(glsl_type::uint_type
);
3951 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(wrap
),
3952 arg1
, st_src_reg_for_int(-1));
3954 opcode
= TGSI_OPCODE_ATOMINC_WRAP
;
3957 case ir_intrinsic_image_atomic_dec_wrap
:
3958 opcode
= TGSI_OPCODE_ATOMDEC_WRAP
;
3961 assert(!"Unexpected intrinsic");
3965 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3966 if (opcode
== TGSI_OPCODE_STORE
)
3967 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3970 if (imgvar
->contains_bindless()) {
3971 inst
->resource
= bindless
;
3972 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3973 SWIZZLE_X
, SWIZZLE_Y
);
3975 inst
->resource
= image
;
3976 inst
->sampler_array_size
= sampler_array_size
;
3977 inst
->sampler_base
= sampler_base
;
3980 inst
->tex_target
= type
->sampler_index();
3981 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3982 _mesa_get_shader_image_format(image_format
));
3983 inst
->read_only
= memory_read_only
;
3985 if (memory_coherent
)
3986 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3987 if (memory_restrict
)
3988 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3989 if (memory_volatile
)
3990 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3994 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
3996 ir
->return_deref
->accept(this);
3997 st_dst_reg dst
= st_dst_reg(this->result
);
3999 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
4001 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
4002 unsigned num_src
= 0;
4003 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
4004 assert(num_src
< ARRAY_SIZE(src
));
4006 this->result
.file
= PROGRAM_UNDEFINED
;
4007 param
->accept(this);
4008 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4010 src
[num_src
] = this->result
;
4014 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
4018 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
4020 ir_function_signature
*sig
= ir
->callee
;
4022 /* Filter out intrinsics */
4023 switch (sig
->intrinsic_id
) {
4024 case ir_intrinsic_atomic_counter_read
:
4025 case ir_intrinsic_atomic_counter_increment
:
4026 case ir_intrinsic_atomic_counter_predecrement
:
4027 case ir_intrinsic_atomic_counter_add
:
4028 case ir_intrinsic_atomic_counter_min
:
4029 case ir_intrinsic_atomic_counter_max
:
4030 case ir_intrinsic_atomic_counter_and
:
4031 case ir_intrinsic_atomic_counter_or
:
4032 case ir_intrinsic_atomic_counter_xor
:
4033 case ir_intrinsic_atomic_counter_exchange
:
4034 case ir_intrinsic_atomic_counter_comp_swap
:
4035 visit_atomic_counter_intrinsic(ir
);
4038 case ir_intrinsic_ssbo_load
:
4039 case ir_intrinsic_ssbo_store
:
4040 case ir_intrinsic_ssbo_atomic_add
:
4041 case ir_intrinsic_ssbo_atomic_min
:
4042 case ir_intrinsic_ssbo_atomic_max
:
4043 case ir_intrinsic_ssbo_atomic_and
:
4044 case ir_intrinsic_ssbo_atomic_or
:
4045 case ir_intrinsic_ssbo_atomic_xor
:
4046 case ir_intrinsic_ssbo_atomic_exchange
:
4047 case ir_intrinsic_ssbo_atomic_comp_swap
:
4048 visit_ssbo_intrinsic(ir
);
4051 case ir_intrinsic_memory_barrier
:
4052 case ir_intrinsic_memory_barrier_atomic_counter
:
4053 case ir_intrinsic_memory_barrier_buffer
:
4054 case ir_intrinsic_memory_barrier_image
:
4055 case ir_intrinsic_memory_barrier_shared
:
4056 case ir_intrinsic_group_memory_barrier
:
4057 visit_membar_intrinsic(ir
);
4060 case ir_intrinsic_shared_load
:
4061 case ir_intrinsic_shared_store
:
4062 case ir_intrinsic_shared_atomic_add
:
4063 case ir_intrinsic_shared_atomic_min
:
4064 case ir_intrinsic_shared_atomic_max
:
4065 case ir_intrinsic_shared_atomic_and
:
4066 case ir_intrinsic_shared_atomic_or
:
4067 case ir_intrinsic_shared_atomic_xor
:
4068 case ir_intrinsic_shared_atomic_exchange
:
4069 case ir_intrinsic_shared_atomic_comp_swap
:
4070 visit_shared_intrinsic(ir
);
4073 case ir_intrinsic_image_load
:
4074 case ir_intrinsic_image_store
:
4075 case ir_intrinsic_image_atomic_add
:
4076 case ir_intrinsic_image_atomic_min
:
4077 case ir_intrinsic_image_atomic_max
:
4078 case ir_intrinsic_image_atomic_and
:
4079 case ir_intrinsic_image_atomic_or
:
4080 case ir_intrinsic_image_atomic_xor
:
4081 case ir_intrinsic_image_atomic_exchange
:
4082 case ir_intrinsic_image_atomic_comp_swap
:
4083 case ir_intrinsic_image_size
:
4084 case ir_intrinsic_image_samples
:
4085 case ir_intrinsic_image_atomic_inc_wrap
:
4086 case ir_intrinsic_image_atomic_dec_wrap
:
4087 visit_image_intrinsic(ir
);
4090 case ir_intrinsic_shader_clock
:
4091 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4094 case ir_intrinsic_vote_all
:
4095 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4097 case ir_intrinsic_vote_any
:
4098 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4100 case ir_intrinsic_vote_eq
:
4101 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4103 case ir_intrinsic_ballot
:
4104 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4106 case ir_intrinsic_read_first_invocation
:
4107 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4109 case ir_intrinsic_read_invocation
:
4110 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4113 case ir_intrinsic_helper_invocation
:
4114 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_HELPER
);
4117 case ir_intrinsic_invalid
:
4118 case ir_intrinsic_generic_load
:
4119 case ir_intrinsic_generic_store
:
4120 case ir_intrinsic_generic_atomic_add
:
4121 case ir_intrinsic_generic_atomic_and
:
4122 case ir_intrinsic_generic_atomic_or
:
4123 case ir_intrinsic_generic_atomic_xor
:
4124 case ir_intrinsic_generic_atomic_min
:
4125 case ir_intrinsic_generic_atomic_max
:
4126 case ir_intrinsic_generic_atomic_exchange
:
4127 case ir_intrinsic_generic_atomic_comp_swap
:
4128 case ir_intrinsic_begin_invocation_interlock
:
4129 case ir_intrinsic_end_invocation_interlock
:
4130 unreachable("Invalid intrinsic");
4135 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4136 unsigned *array_elements
,
4138 st_src_reg
*indirect
,
4141 switch (tail
->ir_type
) {
4142 case ir_type_dereference_record
: {
4143 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4144 const glsl_type
*struct_type
= deref_record
->record
->type
;
4145 int field_index
= deref_record
->field_idx
;
4147 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4149 assert(field_index
>= 0);
4150 *location
+= struct_type
->struct_location_offset(field_index
);
4154 case ir_type_dereference_array
: {
4155 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4157 void *mem_ctx
= ralloc_parent(deref_arr
);
4158 ir_constant
*array_index
=
4159 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4162 st_src_reg temp_reg
;
4163 st_dst_reg temp_dst
;
4165 temp_reg
= get_temp(glsl_type::uint_type
);
4166 temp_dst
= st_dst_reg(temp_reg
);
4167 temp_dst
.writemask
= 1;
4169 deref_arr
->array_index
->accept(this);
4170 if (*array_elements
!= 1)
4171 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4173 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4175 if (indirect
->file
== PROGRAM_UNDEFINED
)
4176 *indirect
= temp_reg
;
4178 temp_dst
= st_dst_reg(*indirect
);
4179 temp_dst
.writemask
= 1;
4180 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4183 *index
+= array_index
->value
.u
[0] * *array_elements
;
4185 *array_elements
*= deref_arr
->array
->type
->length
;
4187 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4196 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4197 unsigned *array_size
,
4200 st_src_reg
*reladdr
,
4203 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4204 unsigned location
= 0;
4205 ir_variable
*var
= ir
->variable_referenced();
4213 location
= var
->data
.location
;
4214 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4217 * If we end up with no indirect then adjust the base to the index,
4218 * and set the array size to 1.
4220 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4226 assert(location
!= 0xffffffff);
4227 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4228 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4233 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4235 if (offset
.reladdr
|| offset
.reladdr2
||
4236 offset
.has_index2
||
4237 offset
.file
== PROGRAM_UNIFORM
||
4238 offset
.file
== PROGRAM_CONSTANT
||
4239 offset
.file
== PROGRAM_STATE_VAR
) {
4240 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4241 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4242 tmp_dst
.writemask
= WRITEMASK_XY
;
4243 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4251 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4253 ir_variable
*var
= ir
->variable_referenced();
4255 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4256 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4259 /* Convert from bound sampler/image to bindless handle. */
4260 bool is_image
= ir
->type
->is_image();
4261 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4263 unsigned array_size
= 1, base
= 0;
4265 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4267 resource
.index
= index
;
4268 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4269 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4270 *resource
.reladdr
= reladdr
;
4271 emit_arl(ir
, sampler_reladdr
, reladdr
);
4274 this->result
= get_temp(glsl_type::uvec2_type
);
4275 st_dst_reg
dst(this->result
);
4276 dst
.writemask
= WRITEMASK_XY
;
4278 glsl_to_tgsi_instruction
*inst
= emit_asm(
4279 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4281 inst
->tex_target
= ir
->type
->sampler_index();
4282 inst
->resource
= resource
;
4283 inst
->sampler_array_size
= array_size
;
4284 inst
->sampler_base
= base
;
4290 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4292 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4293 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4294 st_src_reg levels_src
, reladdr
;
4295 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4296 glsl_to_tgsi_instruction
*inst
= NULL
;
4297 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4298 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4299 unsigned sampler_array_size
= 1, sampler_base
= 0;
4300 bool is_cube_array
= false, is_cube_shadow
= false;
4301 ir_variable
*var
= ir
->sampler
->variable_referenced();
4304 /* if we are a cube array sampler or a cube shadow */
4305 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4306 is_cube_array
= sampler_type
->sampler_array
;
4307 is_cube_shadow
= sampler_type
->sampler_shadow
;
4310 if (ir
->coordinate
) {
4311 ir
->coordinate
->accept(this);
4313 /* Put our coords in a temp. We'll need to modify them for shadow,
4314 * projection, or LOD, so the only case we'd use it as-is is if
4315 * we're doing plain old texturing. The optimization passes on
4316 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4318 coord
= get_temp(glsl_type::vec4_type
);
4319 coord_dst
= st_dst_reg(coord
);
4320 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4321 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4324 if (ir
->projector
) {
4325 ir
->projector
->accept(this);
4326 projector
= this->result
;
4329 /* Storage for our result. Ideally for an assignment we'd be using
4330 * the actual storage for the result here, instead.
4332 result_src
= get_temp(ir
->type
);
4333 result_dst
= st_dst_reg(result_src
);
4334 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4338 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4340 ir
->offset
->accept(this);
4341 offset
[0] = this->result
;
4345 if (is_cube_array
|| is_cube_shadow
) {
4346 opcode
= TGSI_OPCODE_TXB2
;
4349 opcode
= TGSI_OPCODE_TXB
;
4351 ir
->lod_info
.bias
->accept(this);
4352 lod_info
= this->result
;
4354 ir
->offset
->accept(this);
4355 offset
[0] = this->result
;
4359 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4360 opcode
= TGSI_OPCODE_TEX_LZ
;
4362 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4363 ir
->lod_info
.lod
->accept(this);
4364 lod_info
= this->result
;
4367 ir
->offset
->accept(this);
4368 offset
[0] = this->result
;
4372 opcode
= TGSI_OPCODE_TXD
;
4373 ir
->lod_info
.grad
.dPdx
->accept(this);
4375 ir
->lod_info
.grad
.dPdy
->accept(this);
4378 ir
->offset
->accept(this);
4379 offset
[0] = this->result
;
4383 opcode
= TGSI_OPCODE_TXQ
;
4384 ir
->lod_info
.lod
->accept(this);
4385 lod_info
= this->result
;
4387 case ir_query_levels
:
4388 opcode
= TGSI_OPCODE_TXQ
;
4389 lod_info
= undef_src
;
4390 levels_src
= get_temp(ir
->type
);
4393 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4394 opcode
= TGSI_OPCODE_TXF_LZ
;
4396 opcode
= TGSI_OPCODE_TXF
;
4397 ir
->lod_info
.lod
->accept(this);
4398 lod_info
= this->result
;
4401 ir
->offset
->accept(this);
4402 offset
[0] = this->result
;
4406 opcode
= TGSI_OPCODE_TXF
;
4407 ir
->lod_info
.sample_index
->accept(this);
4408 sample_index
= this->result
;
4411 opcode
= TGSI_OPCODE_TG4
;
4412 ir
->lod_info
.component
->accept(this);
4413 component
= this->result
;
4415 ir
->offset
->accept(this);
4416 if (ir
->offset
->type
->is_array()) {
4417 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4418 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4419 offset
[i
] = this->result
;
4420 offset
[i
].index
+= i
* type_size(elt_type
);
4421 offset
[i
].type
= elt_type
->base_type
;
4422 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4423 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4426 offset
[0] = canonicalize_gather_offset(this->result
);
4431 opcode
= TGSI_OPCODE_LODQ
;
4433 case ir_texture_samples
:
4434 opcode
= TGSI_OPCODE_TXQS
;
4436 case ir_samples_identical
:
4437 unreachable("Unexpected ir_samples_identical opcode");
4440 if (ir
->projector
) {
4441 if (opcode
== TGSI_OPCODE_TEX
) {
4442 /* Slot the projector in as the last component of the coord. */
4443 coord_dst
.writemask
= WRITEMASK_W
;
4444 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4445 coord_dst
.writemask
= WRITEMASK_XYZW
;
4446 opcode
= TGSI_OPCODE_TXP
;
4448 st_src_reg coord_w
= coord
;
4449 coord_w
.swizzle
= SWIZZLE_WWWW
;
4451 /* For the other TEX opcodes there's no projective version
4452 * since the last slot is taken up by LOD info. Do the
4453 * projective divide now.
4455 coord_dst
.writemask
= WRITEMASK_W
;
4456 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4458 /* In the case where we have to project the coordinates "by hand,"
4459 * the shadow comparator value must also be projected.
4461 st_src_reg tmp_src
= coord
;
4462 if (ir
->shadow_comparator
) {
4463 /* Slot the shadow value in as the second to last component of the
4466 ir
->shadow_comparator
->accept(this);
4468 tmp_src
= get_temp(glsl_type::vec4_type
);
4469 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4471 /* Projective division not allowed for array samplers. */
4472 assert(!sampler_type
->sampler_array
);
4474 tmp_dst
.writemask
= WRITEMASK_Z
;
4475 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4477 tmp_dst
.writemask
= WRITEMASK_XY
;
4478 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4481 coord_dst
.writemask
= WRITEMASK_XYZ
;
4482 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4484 coord_dst
.writemask
= WRITEMASK_XYZW
;
4485 coord
.swizzle
= SWIZZLE_XYZW
;
4489 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4490 * shadow comparator was put in the correct place (and projected) by the
4491 * code, above, that handles by-hand projection.
4493 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4494 /* Slot the shadow value in as the second to last component of the
4497 ir
->shadow_comparator
->accept(this);
4499 if (is_cube_array
) {
4500 cube_sc
= get_temp(glsl_type::float_type
);
4501 cube_sc_dst
= st_dst_reg(cube_sc
);
4502 cube_sc_dst
.writemask
= WRITEMASK_X
;
4503 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4504 cube_sc_dst
.writemask
= WRITEMASK_X
;
4507 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4508 sampler_type
->sampler_array
) ||
4509 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4510 coord_dst
.writemask
= WRITEMASK_W
;
4512 coord_dst
.writemask
= WRITEMASK_Z
;
4514 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4515 coord_dst
.writemask
= WRITEMASK_XYZW
;
4519 if (ir
->op
== ir_txf_ms
) {
4520 coord_dst
.writemask
= WRITEMASK_W
;
4521 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4522 coord_dst
.writemask
= WRITEMASK_XYZW
;
4523 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4524 opcode
== TGSI_OPCODE_TXF
) {
4525 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4526 coord_dst
.writemask
= WRITEMASK_W
;
4527 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4528 coord_dst
.writemask
= WRITEMASK_XYZW
;
4531 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4534 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4535 &index
, &reladdr
, !var
->contains_bindless());
4537 sampler
.index
= index
;
4538 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4539 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4540 *sampler
.reladdr
= reladdr
;
4541 emit_arl(ir
, sampler_reladdr
, reladdr
);
4544 st_src_reg bindless
;
4545 if (var
->contains_bindless()) {
4546 ir
->sampler
->accept(this);
4547 bindless
= this->result
;
4550 if (opcode
== TGSI_OPCODE_TXD
)
4551 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4552 else if (opcode
== TGSI_OPCODE_TXQ
) {
4553 if (ir
->op
== ir_query_levels
) {
4554 /* the level is stored in W */
4555 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4556 result_dst
.writemask
= WRITEMASK_X
;
4557 levels_src
.swizzle
= SWIZZLE_WWWW
;
4558 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4560 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4561 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4562 inst
= emit_asm(ir
, opcode
, result_dst
);
4563 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4564 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4565 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4566 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4567 } else if (opcode
== TGSI_OPCODE_TG4
) {
4568 if (is_cube_array
&& ir
->shadow_comparator
) {
4569 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4571 if (this->tg4_component_in_swizzle
) {
4572 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4574 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
4575 if (component
.index
== idx
) {
4576 gl_constant_value value
= entry
->values
[component
.swizzle
];
4577 inst
->gather_component
= value
.i
;
4583 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4587 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4589 if (ir
->shadow_comparator
)
4590 inst
->tex_shadow
= GL_TRUE
;
4592 if (var
->contains_bindless()) {
4593 inst
->resource
= bindless
;
4594 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4595 SWIZZLE_X
, SWIZZLE_Y
);
4597 inst
->resource
= sampler
;
4598 inst
->sampler_array_size
= sampler_array_size
;
4599 inst
->sampler_base
= sampler_base
;
4603 if (!inst
->tex_offsets
)
4604 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4605 MAX_GLSL_TEXTURE_OFFSET
);
4607 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4608 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4609 inst
->tex_offsets
[i
] = offset
[i
];
4610 inst
->tex_offset_num_offset
= i
;
4613 inst
->tex_target
= sampler_type
->sampler_index();
4614 inst
->tex_type
= ir
->type
->base_type
;
4616 this->result
= result_src
;
4620 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4622 assert(!ir
->get_value());
4624 emit_asm(ir
, TGSI_OPCODE_RET
);
4628 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4630 if (ir
->condition
) {
4631 ir
->condition
->accept(this);
4632 st_src_reg condition
= this->result
;
4634 /* Convert the bool condition to a float so we can negate. */
4635 if (native_integers
) {
4636 st_src_reg temp
= get_temp(ir
->condition
->type
);
4637 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4638 condition
, st_src_reg_for_float(1.0));
4642 condition
.negate
= ~condition
.negate
;
4643 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4645 /* unconditional kil */
4646 emit_asm(ir
, TGSI_OPCODE_KILL
);
4651 glsl_to_tgsi_visitor::visit(ir_demote
*ir
)
4653 emit_asm(ir
, TGSI_OPCODE_DEMOTE
);
4657 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4659 enum tgsi_opcode if_opcode
;
4660 glsl_to_tgsi_instruction
*if_inst
;
4662 ir
->condition
->accept(this);
4663 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4665 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4667 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4669 this->instructions
.push_tail(if_inst
);
4671 visit_exec_list(&ir
->then_instructions
, this);
4673 if (!ir
->else_instructions
.is_empty()) {
4674 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4675 visit_exec_list(&ir
->else_instructions
, this);
4678 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4683 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4685 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4687 ir
->stream
->accept(this);
4688 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4692 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4694 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4696 ir
->stream
->accept(this);
4697 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4701 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4703 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4704 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4706 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4709 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4711 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4713 result
.file
= PROGRAM_UNDEFINED
;
4720 num_input_arrays
= 0;
4721 num_output_arrays
= 0;
4723 num_atomic_arrays
= 0;
4725 num_address_regs
= 0;
4728 indirect_addr_consts
= false;
4729 wpos_transform_const
= -1;
4730 native_integers
= false;
4731 mem_ctx
= ralloc_context(NULL
);
4736 tg4_component_in_swizzle
= false;
4737 shader_program
= NULL
;
4742 use_shared_memory
= false;
4743 has_tex_txf_lz
= false;
4747 static void var_destroy(struct hash_entry
*entry
)
4749 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4754 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4756 _mesa_hash_table_destroy(variables
, var_destroy
);
4758 ralloc_free(mem_ctx
);
4761 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4768 * Count resources used by the given gpu program (number of texture
4772 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4774 v
->samplers_used
= 0;
4776 prog
->info
.textures_used_by_txf
= 0;
4778 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4779 if (inst
->info
->is_tex
) {
4780 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4781 unsigned idx
= inst
->sampler_base
+ i
;
4782 v
->samplers_used
|= 1u << idx
;
4784 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4785 v
->sampler_types
[idx
] = inst
->tex_type
;
4786 v
->sampler_targets
[idx
] =
4787 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4789 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4790 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4795 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4796 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4798 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4799 is_resource_instruction(inst
->op
) ||
4800 inst
->op
== TGSI_OPCODE_STORE
)) {
4801 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4802 v
->use_shared_memory
= true;
4803 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4804 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4805 unsigned idx
= inst
->sampler_base
+ i
;
4806 v
->images_used
|= 1 << idx
;
4807 v
->image_targets
[idx
] =
4808 st_translate_texture_target(inst
->tex_target
, false);
4809 v
->image_formats
[idx
] = inst
->image_format
;
4810 v
->image_wr
[idx
] = !inst
->read_only
;
4815 prog
->SamplersUsed
= v
->samplers_used
;
4817 if (v
->shader_program
!= NULL
)
4818 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4822 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4823 * are read from the given src in this instruction
4826 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4828 int read_mask
= 0, comp
;
4830 /* Now, given the src swizzle and the written channels, find which
4831 * components are actually read
4833 for (comp
= 0; comp
< 4; ++comp
) {
4834 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4836 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4837 read_mask
|= 1 << coord
;
4844 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4845 * instruction is the first instruction to write to register T0. There are
4846 * several lowering passes done in GLSL IR (e.g. branches and
4847 * relative addressing) that create a large number of conditional assignments
4848 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4850 * Here is why this conversion is safe:
4851 * CMP T0, T1 T2 T0 can be expanded to:
4857 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4858 * as the original program. If (T1 < 0.0) evaluates to false, executing
4859 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4860 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4861 * because any instruction that was going to read from T0 after this was going
4862 * to read a garbage value anyway.
4865 glsl_to_tgsi_visitor::simplify_cmp(void)
4867 int tempWritesSize
= 0;
4868 unsigned *tempWrites
= NULL
;
4869 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4871 memset(outputWrites
, 0, sizeof(outputWrites
));
4873 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4874 unsigned prevWriteMask
= 0;
4876 /* Give up if we encounter relative addressing or flow control. */
4877 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4878 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4879 inst
->info
->is_branch
||
4880 inst
->op
== TGSI_OPCODE_CONT
||
4881 inst
->op
== TGSI_OPCODE_END
||
4882 inst
->op
== TGSI_OPCODE_RET
) {
4886 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4887 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4888 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4889 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4890 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4891 if (inst
->dst
[0].index
>= tempWritesSize
) {
4892 const int inc
= 4096;
4894 tempWrites
= (unsigned*)
4896 (tempWritesSize
+ inc
) * sizeof(unsigned));
4900 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4901 tempWritesSize
+= inc
;
4904 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4905 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4909 /* For a CMP to be considered a conditional write, the destination
4910 * register and source register two must be the same. */
4911 if (inst
->op
== TGSI_OPCODE_CMP
4912 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4913 && inst
->src
[2].file
== inst
->dst
[0].file
4914 && inst
->src
[2].index
== inst
->dst
[0].index
4915 && inst
->dst
[0].writemask
==
4916 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4918 inst
->op
= TGSI_OPCODE_MOV
;
4919 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4920 inst
->src
[0] = inst
->src
[1];
4928 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4930 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4931 int old_idx
= src
->index
;
4932 if (renames
[old_idx
].valid
)
4933 src
->index
= renames
[old_idx
].new_reg
;
4937 /* Replaces all references to a temporary register index with another index. */
4939 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4941 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4943 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4944 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4945 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4946 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4949 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4950 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4951 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4952 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4955 rename_temp_handle_src(renames
, &inst
->resource
);
4956 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4957 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4959 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4960 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4961 int old_idx
= inst
->dst
[j
].index
;
4962 if (renames
[old_idx
].valid
)
4963 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4965 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4966 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4972 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4974 int depth
= 0; /* loop depth */
4975 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4978 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4979 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4980 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4981 if (first_writes
[inst
->dst
[j
].index
] == -1)
4982 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4986 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4989 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4999 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
5001 int depth
= 0; /* loop depth */
5002 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5005 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5006 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5007 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
5008 if (first_reads
[inst
->src
[j
].index
] == -1)
5009 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5012 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5013 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
5014 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
5015 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5018 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5021 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5031 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
5033 int depth
= 0; /* loop depth */
5034 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5037 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5038 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5039 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
5040 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
5042 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5043 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
5044 if (first_writes
[inst
->dst
[j
].index
] == -1)
5045 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5046 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5049 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5050 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
5051 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
5053 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5056 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5059 for (k
= 0; k
< this->next_temp
; k
++) {
5060 if (last_reads
[k
] == -2) {
5072 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
5074 int depth
= 0; /* loop depth */
5078 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5079 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5080 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
5081 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5084 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
5086 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
5088 for (k
= 0; k
< this->next_temp
; k
++) {
5089 if (last_writes
[k
] == -2) {
5100 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5101 * channels for copy propagation and updates following instructions to
5102 * use the original versions.
5104 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5105 * will occur. As an example, a TXP production before this pass:
5107 * 0: MOV TEMP[1], INPUT[4].xyyy;
5108 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5109 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5113 * 0: MOV TEMP[1], INPUT[4].xyyy;
5114 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5115 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5117 * which allows for dead code elimination on TEMP[1]'s writes.
5120 glsl_to_tgsi_visitor::copy_propagate(void)
5122 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5123 glsl_to_tgsi_instruction
*,
5124 this->next_temp
* 4);
5125 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5128 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5129 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5130 || inst
->dst
[0].index
< this->next_temp
);
5132 /* First, do any copy propagation possible into the src regs. */
5133 for (int r
= 0; r
< 3; r
++) {
5134 glsl_to_tgsi_instruction
*first
= NULL
;
5136 int acp_base
= inst
->src
[r
].index
* 4;
5138 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5139 inst
->src
[r
].reladdr
||
5140 inst
->src
[r
].reladdr2
)
5143 /* See if we can find entries in the ACP consisting of MOVs
5144 * from the same src register for all the swizzled channels
5145 * of this src register reference.
5147 for (int i
= 0; i
< 4; i
++) {
5148 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5149 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5156 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5161 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5162 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5163 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5164 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5172 /* We've now validated that we can copy-propagate to
5173 * replace this src register reference. Do it.
5175 inst
->src
[r
].file
= first
->src
[0].file
;
5176 inst
->src
[r
].index
= first
->src
[0].index
;
5177 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5178 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5179 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5180 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5183 for (int i
= 0; i
< 4; i
++) {
5184 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5185 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5186 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5188 inst
->src
[r
].swizzle
= swizzle
;
5193 case TGSI_OPCODE_BGNLOOP
:
5194 case TGSI_OPCODE_ENDLOOP
:
5195 /* End of a basic block, clear the ACP entirely. */
5196 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5199 case TGSI_OPCODE_IF
:
5200 case TGSI_OPCODE_UIF
:
5204 case TGSI_OPCODE_ENDIF
:
5205 case TGSI_OPCODE_ELSE
:
5206 /* Clear all channels written inside the block from the ACP, but
5207 * leaving those that were not touched.
5209 for (int r
= 0; r
< this->next_temp
; r
++) {
5210 for (int c
= 0; c
< 4; c
++) {
5211 if (!acp
[4 * r
+ c
])
5214 if (acp_level
[4 * r
+ c
] >= level
)
5215 acp
[4 * r
+ c
] = NULL
;
5218 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5223 /* Continuing the block, clear any written channels from
5226 for (int d
= 0; d
< 2; d
++) {
5227 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5228 /* Any temporary might be written, so no copy propagation
5229 * across this instruction.
5231 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5232 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5233 inst
->dst
[d
].reladdr
) {
5234 /* Any output might be written, so no copy propagation
5235 * from outputs across this instruction.
5237 for (int r
= 0; r
< this->next_temp
; r
++) {
5238 for (int c
= 0; c
< 4; c
++) {
5239 if (!acp
[4 * r
+ c
])
5242 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5243 acp
[4 * r
+ c
] = NULL
;
5246 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5247 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5248 /* Clear where it's used as dst. */
5249 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5250 for (int c
= 0; c
< 4; c
++) {
5251 if (inst
->dst
[d
].writemask
& (1 << c
))
5252 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5256 /* Clear where it's used as src. */
5257 for (int r
= 0; r
< this->next_temp
; r
++) {
5258 for (int c
= 0; c
< 4; c
++) {
5259 if (!acp
[4 * r
+ c
])
5262 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5264 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5265 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5266 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5267 acp
[4 * r
+ c
] = NULL
;
5276 /* If this is a copy, add it to the ACP. */
5277 if (inst
->op
== TGSI_OPCODE_MOV
&&
5278 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5279 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5280 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5281 !inst
->dst
[0].reladdr
&&
5282 !inst
->dst
[0].reladdr2
&&
5284 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5285 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5286 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5287 !inst
->src
[0].reladdr
&&
5288 !inst
->src
[0].reladdr2
&&
5289 !inst
->src
[0].negate
&&
5290 !inst
->src
[0].abs
) {
5291 for (int i
= 0; i
< 4; i
++) {
5292 if (inst
->dst
[0].writemask
& (1 << i
)) {
5293 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5294 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5300 ralloc_free(acp_level
);
5305 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5307 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5308 /* Clear where it's used as src. */
5309 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5310 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5315 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5318 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5319 * will occur. As an example, a TXP production after copy propagation but
5322 * 0: MOV TEMP[1], INPUT[4].xyyy;
5323 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5324 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5326 * and after this pass:
5328 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5331 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5333 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5334 glsl_to_tgsi_instruction
*,
5335 this->next_temp
* 4);
5336 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5340 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5341 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5342 || inst
->dst
[0].index
< this->next_temp
);
5345 case TGSI_OPCODE_BGNLOOP
:
5346 case TGSI_OPCODE_ENDLOOP
:
5347 case TGSI_OPCODE_CONT
:
5348 case TGSI_OPCODE_BRK
:
5349 /* End of a basic block, clear the write array entirely.
5351 * This keeps us from killing dead code when the writes are
5352 * on either side of a loop, even when the register isn't touched
5353 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5354 * dead code of this type, so it shouldn't make a difference as long as
5355 * the dead code elimination pass in the GLSL compiler does its job.
5357 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5360 case TGSI_OPCODE_ENDIF
:
5361 case TGSI_OPCODE_ELSE
:
5362 /* Promote the recorded level of all channels written inside the
5363 * preceding if or else block to the level above the if/else block.
5365 for (int r
= 0; r
< this->next_temp
; r
++) {
5366 for (int c
= 0; c
< 4; c
++) {
5367 if (!writes
[4 * r
+ c
])
5370 if (write_level
[4 * r
+ c
] == level
)
5371 write_level
[4 * r
+ c
] = level
-1;
5374 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5378 case TGSI_OPCODE_IF
:
5379 case TGSI_OPCODE_UIF
:
5381 /* fallthrough to default case to mark the condition as read */
5383 /* Continuing the block, clear any channels from the write array that
5384 * are read by this instruction.
5386 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5387 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5388 /* Any temporary might be read, so no dead code elimination
5389 * across this instruction.
5391 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5392 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5393 /* Clear where it's used as src. */
5394 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5395 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5396 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5397 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5399 for (int c
= 0; c
< 4; c
++) {
5400 if (src_chans
& (1 << c
))
5401 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5404 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5405 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5407 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5408 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5409 /* Any temporary might be read, so no dead code elimination
5410 * across this instruction.
5412 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5413 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5414 /* Clear where it's used as src. */
5415 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5416 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5417 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5418 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5420 for (int c
= 0; c
< 4; c
++) {
5421 if (src_chans
& (1 << c
))
5422 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5425 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5426 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5429 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5432 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5433 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5434 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5435 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5437 for (int c
= 0; c
< 4; c
++) {
5438 if (src_chans
& (1 << c
))
5439 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5442 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5443 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5445 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5446 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5447 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5452 /* If this instruction writes to a temporary, add it to the write array.
5453 * If there is already an instruction in the write array for one or more
5454 * of the channels, flag that channel write as dead.
5456 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5457 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5458 !inst
->dst
[i
].reladdr
) {
5459 for (int c
= 0; c
< 4; c
++) {
5460 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5461 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5462 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5465 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5467 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5468 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5475 /* Anything still in the write array at this point is dead code. */
5476 for (int r
= 0; r
< this->next_temp
; r
++) {
5477 for (int c
= 0; c
< 4; c
++) {
5478 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5480 inst
->dead_mask
|= (1 << c
);
5484 /* Now actually remove the instructions that are completely dead and update
5485 * the writemask of other instructions with dead channels.
5487 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5488 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5490 /* No amount of dead masks should remove memory stores */
5491 if (inst
->info
->is_store
)
5494 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5499 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5500 if (inst
->dead_mask
== WRITEMASK_XY
||
5501 inst
->dead_mask
== WRITEMASK_ZW
)
5502 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5504 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5508 ralloc_free(write_level
);
5509 ralloc_free(writes
);
5514 /* merge DFRACEXP instructions into one. */
5516 glsl_to_tgsi_visitor::merge_two_dsts(void)
5518 /* We never delete inst, but we may delete its successor. */
5519 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5520 glsl_to_tgsi_instruction
*inst2
;
5523 if (num_inst_dst_regs(inst
) != 2)
5526 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5527 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5530 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5531 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5533 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5538 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5539 while (!inst2
->is_tail_sentinel()) {
5540 if (inst
->op
== inst2
->op
&&
5541 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5542 inst
->src
[0].file
== inst2
->src
[0].file
&&
5543 inst
->src
[0].index
== inst2
->src
[0].index
&&
5544 inst
->src
[0].type
== inst2
->src
[0].type
&&
5545 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5547 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5550 if (inst2
->is_tail_sentinel()) {
5551 /* Undefined destinations are not allowed, substitute with an unused
5552 * temporary register.
5554 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5555 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5556 inst
->dst
[defined
^ 1].writemask
= 0;
5560 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5566 template <typename st_reg
>
5567 void test_indirect_access(const st_reg
& reg
, bool *has_indirect_access
)
5569 if (reg
.file
== PROGRAM_ARRAY
) {
5570 if (reg
.reladdr
|| reg
.reladdr2
|| reg
.has_index2
) {
5571 has_indirect_access
[reg
.array_id
] = true;
5573 test_indirect_access(*reg
.reladdr
, has_indirect_access
);
5575 test_indirect_access(*reg
.reladdr2
, has_indirect_access
);
5580 template <typename st_reg
>
5581 void remap_array(st_reg
& reg
, const int *array_remap_info
,
5582 const bool *has_indirect_access
)
5584 if (reg
.file
== PROGRAM_ARRAY
) {
5585 if (!has_indirect_access
[reg
.array_id
]) {
5586 reg
.file
= PROGRAM_TEMPORARY
;
5587 reg
.index
= reg
.index
+ array_remap_info
[reg
.array_id
];
5590 reg
.array_id
= array_remap_info
[reg
.array_id
];
5594 remap_array(*reg
.reladdr
, array_remap_info
, has_indirect_access
);
5597 remap_array(*reg
.reladdr2
, array_remap_info
, has_indirect_access
);
5601 /* One-dimensional arrays whose elements are only accessed directly are
5602 * replaced by an according set of temporary registers that then can become
5603 * subject to further optimization steps like copy propagation and
5607 glsl_to_tgsi_visitor::split_arrays(void)
5612 bool *has_indirect_access
= rzalloc_array(mem_ctx
, bool, next_array
+ 1);
5614 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5615 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5616 test_indirect_access(inst
->src
[j
], has_indirect_access
);
5618 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5619 test_indirect_access(inst
->tex_offsets
[j
], has_indirect_access
);
5621 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++)
5622 test_indirect_access(inst
->dst
[j
], has_indirect_access
);
5624 test_indirect_access(inst
->resource
, has_indirect_access
);
5627 unsigned array_offset
= 0;
5628 unsigned n_remaining_arrays
= 0;
5630 /* Double use: For arrays that get split this value will contain
5631 * the base index of the temporary registers this array is replaced
5632 * with. For arrays that remain it contains the new array ID.
5634 int *array_remap_info
= rzalloc_array(has_indirect_access
, int,
5637 for (unsigned i
= 1; i
<= next_array
; ++i
) {
5638 if (!has_indirect_access
[i
]) {
5639 array_remap_info
[i
] = this->next_temp
+ array_offset
;
5640 array_offset
+= array_sizes
[i
- 1];
5642 array_sizes
[n_remaining_arrays
] = array_sizes
[i
-1];
5643 array_remap_info
[i
] = ++n_remaining_arrays
;
5647 if (next_array
!= n_remaining_arrays
) {
5648 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5649 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5650 remap_array(inst
->src
[j
], array_remap_info
, has_indirect_access
);
5652 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5653 remap_array(inst
->tex_offsets
[j
], array_remap_info
, has_indirect_access
);
5655 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5656 remap_array(inst
->dst
[j
], array_remap_info
, has_indirect_access
);
5658 remap_array(inst
->resource
, array_remap_info
, has_indirect_access
);
5662 ralloc_free(has_indirect_access
);
5663 this->next_temp
+= array_offset
;
5664 next_array
= n_remaining_arrays
;
5667 /* Merges temporary registers together where possible to reduce the number of
5668 * registers needed to run a program.
5670 * Produces optimal code only after copy propagation and dead code elimination
5673 glsl_to_tgsi_visitor::merge_registers(void)
5675 class array_live_range
*arr_live_ranges
= NULL
;
5677 struct register_live_range
*reg_live_ranges
=
5678 rzalloc_array(mem_ctx
, struct register_live_range
, this->next_temp
);
5680 if (this->next_array
> 0) {
5681 arr_live_ranges
= new array_live_range
[this->next_array
];
5682 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5683 arr_live_ranges
[i
] = array_live_range(i
+1, this->array_sizes
[i
]);
5687 if (get_temp_registers_required_live_ranges(reg_live_ranges
, &this->instructions
,
5688 this->next_temp
, reg_live_ranges
,
5689 this->next_array
, arr_live_ranges
)) {
5690 struct rename_reg_pair
*renames
=
5691 rzalloc_array(reg_live_ranges
, struct rename_reg_pair
, this->next_temp
);
5692 get_temp_registers_remapping(reg_live_ranges
, this->next_temp
,
5693 reg_live_ranges
, renames
);
5694 rename_temp_registers(renames
);
5696 this->next_array
= merge_arrays(this->next_array
, this->array_sizes
,
5697 &this->instructions
, arr_live_ranges
);
5700 if (arr_live_ranges
)
5701 delete[] arr_live_ranges
;
5703 ralloc_free(reg_live_ranges
);
5706 /* Reassign indices to temporary registers by reusing unused indices created
5707 * by optimization passes. */
5709 glsl_to_tgsi_visitor::renumber_registers(void)
5713 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5714 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5716 for (i
= 0; i
< this->next_temp
; i
++) {
5717 first_writes
[i
] = -1;
5719 get_first_temp_write(first_writes
);
5721 for (i
= 0; i
< this->next_temp
; i
++) {
5722 if (first_writes
[i
] < 0) continue;
5723 if (i
!= new_index
) {
5724 renames
[i
].new_reg
= new_index
;
5725 renames
[i
].valid
= true;
5730 rename_temp_registers(renames
);
5731 this->next_temp
= new_index
;
5732 ralloc_free(renames
);
5733 ralloc_free(first_writes
);
5737 void glsl_to_tgsi_visitor::print_stats()
5739 int narray_registers
= 0;
5740 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5741 narray_registers
+= this->array_sizes
[i
];
5743 int ninstructions
= 0;
5744 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &instructions
) {
5748 simple_mtx_lock(&print_stats_mutex
);
5749 stats_log
<< next_array
<< ", "
5750 << next_temp
<< ", "
5751 << narray_registers
<< ", "
5752 << next_temp
+ narray_registers
<< ", "
5753 << ninstructions
<< "\n";
5754 simple_mtx_unlock(&print_stats_mutex
);
5757 /* ------------------------- TGSI conversion stuff -------------------------- */
5760 * Intermediate state used during shader translation.
5762 struct st_translate
{
5763 struct ureg_program
*ureg
;
5765 unsigned temps_size
;
5766 struct ureg_dst
*temps
;
5768 struct ureg_dst
*arrays
;
5769 unsigned num_temp_arrays
;
5770 struct ureg_src
*constants
;
5772 struct ureg_src
*immediates
;
5774 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5775 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5776 struct ureg_dst address
[3];
5777 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5778 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5779 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5780 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5781 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5782 struct ureg_src shared_memory
;
5783 unsigned *array_sizes
;
5784 struct inout_decl
*input_decls
;
5785 unsigned num_input_decls
;
5786 struct inout_decl
*output_decls
;
5787 unsigned num_output_decls
;
5789 const ubyte
*inputMapping
;
5790 const ubyte
*outputMapping
;
5792 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5794 bool tg4_component_in_swizzle
;
5797 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5799 _mesa_sysval_to_semantic(unsigned sysval
)
5803 case SYSTEM_VALUE_VERTEX_ID
:
5804 return TGSI_SEMANTIC_VERTEXID
;
5805 case SYSTEM_VALUE_INSTANCE_ID
:
5806 return TGSI_SEMANTIC_INSTANCEID
;
5807 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5808 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5809 case SYSTEM_VALUE_BASE_VERTEX
:
5810 return TGSI_SEMANTIC_BASEVERTEX
;
5811 case SYSTEM_VALUE_BASE_INSTANCE
:
5812 return TGSI_SEMANTIC_BASEINSTANCE
;
5813 case SYSTEM_VALUE_DRAW_ID
:
5814 return TGSI_SEMANTIC_DRAWID
;
5816 /* Geometry shader */
5817 case SYSTEM_VALUE_INVOCATION_ID
:
5818 return TGSI_SEMANTIC_INVOCATIONID
;
5820 /* Fragment shader */
5821 case SYSTEM_VALUE_FRAG_COORD
:
5822 return TGSI_SEMANTIC_POSITION
;
5823 case SYSTEM_VALUE_POINT_COORD
:
5824 return TGSI_SEMANTIC_PCOORD
;
5825 case SYSTEM_VALUE_FRONT_FACE
:
5826 return TGSI_SEMANTIC_FACE
;
5827 case SYSTEM_VALUE_SAMPLE_ID
:
5828 return TGSI_SEMANTIC_SAMPLEID
;
5829 case SYSTEM_VALUE_SAMPLE_POS
:
5830 return TGSI_SEMANTIC_SAMPLEPOS
;
5831 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5832 return TGSI_SEMANTIC_SAMPLEMASK
;
5833 case SYSTEM_VALUE_HELPER_INVOCATION
:
5834 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5836 /* Tessellation shader */
5837 case SYSTEM_VALUE_TESS_COORD
:
5838 return TGSI_SEMANTIC_TESSCOORD
;
5839 case SYSTEM_VALUE_VERTICES_IN
:
5840 return TGSI_SEMANTIC_VERTICESIN
;
5841 case SYSTEM_VALUE_PRIMITIVE_ID
:
5842 return TGSI_SEMANTIC_PRIMID
;
5843 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5844 return TGSI_SEMANTIC_TESSOUTER
;
5845 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5846 return TGSI_SEMANTIC_TESSINNER
;
5848 /* Compute shader */
5849 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5850 return TGSI_SEMANTIC_THREAD_ID
;
5851 case SYSTEM_VALUE_WORK_GROUP_ID
:
5852 return TGSI_SEMANTIC_BLOCK_ID
;
5853 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5854 return TGSI_SEMANTIC_GRID_SIZE
;
5855 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5856 return TGSI_SEMANTIC_BLOCK_SIZE
;
5858 /* ARB_shader_ballot */
5859 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5860 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5861 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5862 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5863 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5864 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5865 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5866 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5867 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5868 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5869 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5870 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5871 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5872 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5875 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5876 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5877 case SYSTEM_VALUE_VERTEX_CNT
:
5878 case SYSTEM_VALUE_BARYCENTRIC_PIXEL
:
5879 case SYSTEM_VALUE_BARYCENTRIC_SAMPLE
:
5880 case SYSTEM_VALUE_BARYCENTRIC_CENTROID
:
5881 case SYSTEM_VALUE_BARYCENTRIC_SIZE
:
5883 assert(!"Unexpected SYSTEM_VALUE_ enum");
5884 return TGSI_SEMANTIC_COUNT
;
5889 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5891 static struct ureg_src
5892 emit_immediate(struct st_translate
*t
,
5893 gl_constant_value values
[4],
5894 GLenum type
, int size
)
5896 struct ureg_program
*ureg
= t
->ureg
;
5900 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5902 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5904 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5905 case GL_UNSIGNED_INT64_ARB
:
5906 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5908 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5909 case GL_UNSIGNED_INT
:
5911 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5913 assert(!"should not get here - type must be float, int, uint, or bool");
5914 return ureg_src_undef();
5919 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5921 static struct ureg_dst
5922 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5928 case PROGRAM_UNDEFINED
:
5929 return ureg_dst_undef();
5931 case PROGRAM_TEMPORARY
:
5932 /* Allocate space for temporaries on demand. */
5933 if (index
>= t
->temps_size
) {
5934 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5936 t
->temps
= (struct ureg_dst
*)
5938 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5940 return ureg_dst_undef();
5942 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5943 t
->temps_size
+= inc
;
5946 if (ureg_dst_is_undef(t
->temps
[index
]))
5947 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5949 return t
->temps
[index
];
5952 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5953 array
= array_id
- 1;
5955 if (ureg_dst_is_undef(t
->arrays
[array
]))
5956 t
->arrays
[array
] = ureg_DECL_array_temporary(
5957 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5959 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5961 case PROGRAM_OUTPUT
:
5963 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5964 assert(index
< 2 * FRAG_RESULT_MAX
);
5965 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5966 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5967 assert(index
< VARYING_SLOT_TESS_MAX
);
5969 assert(index
< VARYING_SLOT_MAX
);
5971 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5972 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5973 return t
->outputs
[t
->outputMapping
[index
]];
5976 struct inout_decl
*decl
=
5977 find_inout_array(t
->output_decls
,
5978 t
->num_output_decls
, array_id
);
5979 unsigned mesa_index
= decl
->mesa_index
;
5980 int slot
= t
->outputMapping
[mesa_index
];
5982 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5984 struct ureg_dst dst
= t
->outputs
[slot
];
5985 dst
.ArrayID
= array_id
;
5986 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5989 case PROGRAM_ADDRESS
:
5990 return t
->address
[index
];
5993 assert(!"unknown dst register file");
5994 return ureg_dst_undef();
5998 static struct ureg_src
5999 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
6001 static struct ureg_src
6002 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
6003 unsigned addr_index
)
6005 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
6006 return ureg_src(t
->address
[addr_index
]);
6008 return translate_src(t
, reladdr
);
6012 * Create a TGSI ureg_dst register from an st_dst_reg.
6014 static struct ureg_dst
6015 translate_dst(struct st_translate
*t
,
6016 const st_dst_reg
*dst_reg
,
6019 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
6022 if (dst
.File
== TGSI_FILE_NULL
)
6025 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
6028 dst
= ureg_saturate(dst
);
6030 if (dst_reg
->reladdr
!= NULL
) {
6031 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
6032 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
6035 if (dst_reg
->has_index2
) {
6036 if (dst_reg
->reladdr2
)
6037 dst
= ureg_dst_dimension_indirect(dst
,
6038 translate_addr(t
, dst_reg
->reladdr2
, 1),
6041 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
6048 * Create a TGSI ureg_src register from an st_src_reg.
6050 static struct ureg_src
6051 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
6053 struct ureg_src src
;
6054 int index
= src_reg
->index
;
6055 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
6057 switch (src_reg
->file
) {
6058 case PROGRAM_UNDEFINED
:
6059 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6062 case PROGRAM_TEMPORARY
:
6064 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
6065 src_reg
->array_id
));
6068 case PROGRAM_OUTPUT
: {
6069 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
6071 assert(dst
.WriteMask
!= 0);
6072 unsigned shift
= ffs(dst
.WriteMask
) - 1;
6073 src
= ureg_swizzle(ureg_src(dst
),
6077 MIN2(shift
+ 3, 3));
6081 case PROGRAM_UNIFORM
:
6082 assert(src_reg
->index
>= 0);
6083 src
= src_reg
->index
< t
->num_constants
?
6084 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6086 case PROGRAM_STATE_VAR
:
6087 case PROGRAM_CONSTANT
: /* ie, immediate */
6088 if (src_reg
->has_index2
)
6089 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
6091 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
6092 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6095 case PROGRAM_IMMEDIATE
:
6096 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
6097 src
= t
->immediates
[src_reg
->index
];
6101 /* GLSL inputs are 64-bit containers, so we have to
6102 * map back to the original index and add the offset after
6104 index
-= double_reg2
;
6105 if (!src_reg
->array_id
) {
6106 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
6107 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
6108 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
6111 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
6114 unsigned mesa_index
= decl
->mesa_index
;
6115 int slot
= t
->inputMapping
[mesa_index
];
6117 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
6119 src
= t
->inputs
[slot
];
6120 src
.ArrayID
= src_reg
->array_id
;
6121 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
6125 case PROGRAM_ADDRESS
:
6126 src
= ureg_src(t
->address
[src_reg
->index
]);
6129 case PROGRAM_SYSTEM_VALUE
:
6130 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
6131 src
= t
->systemValues
[src_reg
->index
];
6134 case PROGRAM_HW_ATOMIC
:
6135 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
6140 assert(!"unknown src register file");
6141 return ureg_src_undef();
6144 if (src_reg
->has_index2
) {
6145 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6146 * and UBO constant buffers (buffer, position).
6148 if (src_reg
->reladdr2
)
6149 src
= ureg_src_dimension_indirect(src
,
6150 translate_addr(t
, src_reg
->reladdr2
, 1),
6153 src
= ureg_src_dimension(src
, src_reg
->index2D
);
6156 src
= ureg_swizzle(src
,
6157 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
6158 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
6159 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
6160 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
6163 src
= ureg_abs(src
);
6165 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
6166 src
= ureg_negate(src
);
6168 if (src_reg
->reladdr
!= NULL
) {
6169 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
6170 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
6176 static struct tgsi_texture_offset
6177 translate_tex_offset(struct st_translate
*t
,
6178 const st_src_reg
*in_offset
)
6180 struct tgsi_texture_offset offset
;
6181 struct ureg_src src
= translate_src(t
, in_offset
);
6183 offset
.File
= src
.File
;
6184 offset
.Index
= src
.Index
;
6185 offset
.SwizzleX
= src
.SwizzleX
;
6186 offset
.SwizzleY
= src
.SwizzleY
;
6187 offset
.SwizzleZ
= src
.SwizzleZ
;
6190 assert(!src
.Indirect
);
6191 assert(!src
.DimIndirect
);
6192 assert(!src
.Dimension
);
6193 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
6194 assert(!src
.Negate
);
6200 compile_tgsi_instruction(struct st_translate
*t
,
6201 const glsl_to_tgsi_instruction
*inst
)
6203 struct ureg_program
*ureg
= t
->ureg
;
6205 struct ureg_dst dst
[2];
6206 struct ureg_src src
[4];
6207 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
6211 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
6213 num_dst
= num_inst_dst_regs(inst
);
6214 num_src
= num_inst_src_regs(inst
);
6216 for (i
= 0; i
< num_dst
; i
++)
6217 dst
[i
] = translate_dst(t
,
6221 for (i
= 0; i
< num_src
; i
++)
6222 src
[i
] = translate_src(t
, &inst
->src
[i
]);
6225 case TGSI_OPCODE_BGNLOOP
:
6226 case TGSI_OPCODE_ELSE
:
6227 case TGSI_OPCODE_ENDLOOP
:
6228 case TGSI_OPCODE_IF
:
6229 case TGSI_OPCODE_UIF
:
6230 assert(num_dst
== 0);
6231 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
6234 case TGSI_OPCODE_TEX
:
6235 case TGSI_OPCODE_TEX_LZ
:
6236 case TGSI_OPCODE_TXB
:
6237 case TGSI_OPCODE_TXD
:
6238 case TGSI_OPCODE_TXL
:
6239 case TGSI_OPCODE_TXP
:
6240 case TGSI_OPCODE_TXQ
:
6241 case TGSI_OPCODE_TXQS
:
6242 case TGSI_OPCODE_TXF
:
6243 case TGSI_OPCODE_TXF_LZ
:
6244 case TGSI_OPCODE_TEX2
:
6245 case TGSI_OPCODE_TXB2
:
6246 case TGSI_OPCODE_TXL2
:
6247 case TGSI_OPCODE_TG4
:
6248 case TGSI_OPCODE_LODQ
:
6249 case TGSI_OPCODE_SAMP2HND
:
6250 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
6251 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
6252 if (t
->tg4_component_in_swizzle
&& inst
->op
== TGSI_OPCODE_TG4
)
6253 src
[num_src
].SwizzleX
= inst
->gather_component
;
6255 /* Bindless samplers. */
6256 src
[num_src
] = translate_src(t
, &inst
->resource
);
6258 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
6259 if (inst
->resource
.reladdr
)
6261 ureg_src_indirect(src
[num_src
],
6262 translate_addr(t
, inst
->resource
.reladdr
, 2));
6264 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
6265 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
6267 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6273 st_translate_texture_type(inst
->tex_type
),
6274 texoffsets
, inst
->tex_offset_num_offset
,
6278 case TGSI_OPCODE_RESQ
:
6279 case TGSI_OPCODE_LOAD
:
6280 case TGSI_OPCODE_ATOMUADD
:
6281 case TGSI_OPCODE_ATOMXCHG
:
6282 case TGSI_OPCODE_ATOMCAS
:
6283 case TGSI_OPCODE_ATOMAND
:
6284 case TGSI_OPCODE_ATOMOR
:
6285 case TGSI_OPCODE_ATOMXOR
:
6286 case TGSI_OPCODE_ATOMUMIN
:
6287 case TGSI_OPCODE_ATOMUMAX
:
6288 case TGSI_OPCODE_ATOMIMIN
:
6289 case TGSI_OPCODE_ATOMIMAX
:
6290 case TGSI_OPCODE_ATOMFADD
:
6291 case TGSI_OPCODE_IMG2HND
:
6292 case TGSI_OPCODE_ATOMINC_WRAP
:
6293 case TGSI_OPCODE_ATOMDEC_WRAP
:
6294 for (i
= num_src
- 1; i
>= 0; i
--)
6295 src
[i
+ 1] = src
[i
];
6297 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6298 src
[0] = t
->shared_memory
;
6299 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6300 src
[0] = t
->buffers
[inst
->resource
.index
];
6301 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6302 src
[0] = translate_src(t
, &inst
->resource
);
6303 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6304 assert(inst
->resource
.has_index2
);
6305 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6307 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6308 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6309 src
[0] = t
->images
[inst
->resource
.index
];
6311 /* Bindless images. */
6312 src
[0] = translate_src(t
, &inst
->resource
);
6314 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6316 if (inst
->resource
.reladdr
)
6317 src
[0] = ureg_src_indirect(src
[0],
6318 translate_addr(t
, inst
->resource
.reladdr
, 2));
6319 assert(src
[0].File
!= TGSI_FILE_NULL
);
6320 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6321 inst
->buffer_access
,
6322 tex_target
, inst
->image_format
);
6325 case TGSI_OPCODE_STORE
:
6326 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6327 dst
[0] = ureg_dst(t
->shared_memory
);
6328 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6329 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6331 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6332 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6334 /* Bindless images. */
6335 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6337 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6339 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6340 if (inst
->resource
.reladdr
)
6341 dst
[0] = ureg_dst_indirect(dst
[0],
6342 translate_addr(t
, inst
->resource
.reladdr
, 2));
6343 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6344 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6345 inst
->buffer_access
,
6346 tex_target
, inst
->image_format
);
6353 src
, num_src
, inst
->precise
);
6358 /* Invert SamplePos.y when rendering to the default framebuffer. */
6360 emit_samplepos_adjustment(struct st_translate
*t
, int wpos_y_transform
)
6362 struct ureg_program
*ureg
= t
->ureg
;
6364 assert(wpos_y_transform
>= 0);
6365 struct ureg_src trans_const
= ureg_DECL_constant(ureg
, wpos_y_transform
);
6366 struct ureg_src samplepos_sysval
= t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
];
6367 struct ureg_dst samplepos_flipped
= ureg_DECL_temporary(ureg
);
6368 struct ureg_dst is_fbo
= ureg_DECL_temporary(ureg
);
6370 ureg_ADD(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6371 ureg_imm1f(ureg
, 1), ureg_negate(samplepos_sysval
));
6373 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6374 ureg_FSEQ(ureg
, ureg_writemask(is_fbo
, TGSI_WRITEMASK_Y
),
6375 ureg_scalar(trans_const
, TGSI_SWIZZLE_X
), ureg_imm1f(ureg
, 1));
6376 ureg_UCMP(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6377 ureg_src(is_fbo
), samplepos_sysval
, ureg_src(samplepos_flipped
));
6378 ureg_MOV(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_X
),
6381 /* Use the result in place of the system value. */
6382 t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
] = ureg_src(samplepos_flipped
);
6387 * Emit the TGSI instructions for inverting and adjusting WPOS.
6388 * This code is unavoidable because it also depends on whether
6389 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6392 emit_wpos_adjustment(struct gl_context
*ctx
,
6393 struct st_translate
*t
,
6394 int wpos_transform_const
,
6396 GLfloat adjX
, GLfloat adjY
[2])
6398 struct ureg_program
*ureg
= t
->ureg
;
6400 assert(wpos_transform_const
>= 0);
6402 /* Fragment program uses fragment position input.
6403 * Need to replace instances of INPUT[WPOS] with temp T
6404 * where T = INPUT[WPOS] is inverted by Y.
6406 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6407 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6408 struct ureg_src
*wpos
=
6409 ctx
->Const
.GLSLFragCoordIsSysVal
?
6410 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6411 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6412 struct ureg_src wpos_input
= *wpos
;
6414 /* First, apply the coordinate shift: */
6415 if (adjX
|| adjY
[0] || adjY
[1]) {
6416 if (adjY
[0] != adjY
[1]) {
6417 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6418 * depending on whether inversion is actually going to be applied
6419 * or not, which is determined by testing against the inversion
6420 * state variable used below, which will be either +1 or -1.
6422 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6424 ureg_CMP(ureg
, adj_temp
,
6425 ureg_scalar(wpostrans
, invert
? 2 : 0),
6426 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6427 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6428 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6430 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6431 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6433 wpos_input
= ureg_src(wpos_temp
);
6435 /* MOV wpos_temp, input[wpos]
6437 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6440 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6441 * inversion/identity, or the other way around if we're drawing to an FBO.
6444 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6447 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6449 ureg_scalar(wpostrans
, 0),
6450 ureg_scalar(wpostrans
, 1));
6452 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6455 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6457 ureg_scalar(wpostrans
, 2),
6458 ureg_scalar(wpostrans
, 3));
6461 /* Use wpos_temp as position input from here on:
6463 *wpos
= ureg_src(wpos_temp
);
6468 * Emit fragment position/ooordinate code.
6471 emit_wpos(struct st_context
*st
,
6472 struct st_translate
*t
,
6473 const struct gl_program
*program
,
6474 struct ureg_program
*ureg
,
6475 int wpos_transform_const
)
6477 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6478 GLfloat adjX
= 0.0f
;
6479 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6480 boolean invert
= FALSE
;
6482 /* Query the pixel center conventions supported by the pipe driver and set
6483 * adjX, adjY to help out if it cannot handle the requested one internally.
6485 * The bias of the y-coordinate depends on whether y-inversion takes place
6486 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6487 * drawing to an FBO (causes additional inversion), and whether the pipe
6488 * driver origin and the requested origin differ (the latter condition is
6489 * stored in the 'invert' variable).
6491 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6493 * center shift only:
6498 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6499 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6500 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6501 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6503 * inversion and center shift:
6504 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6505 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6506 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6507 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6509 if (program
->info
.fs
.origin_upper_left
) {
6510 /* Fragment shader wants origin in upper-left */
6511 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6512 /* the driver supports upper-left origin */
6514 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6515 /* the driver supports lower-left origin, need to invert Y */
6516 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6517 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6524 /* Fragment shader wants origin in lower-left */
6525 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6526 /* the driver supports lower-left origin */
6527 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6528 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6529 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6530 /* the driver supports upper-left origin, need to invert Y */
6536 if (program
->info
.fs
.pixel_center_integer
) {
6537 /* Fragment shader wants pixel center integer */
6538 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6539 /* the driver supports pixel center integer */
6541 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6542 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6544 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6545 /* the driver supports pixel center half integer, need to bias X,Y */
6554 /* Fragment shader wants pixel center half integer */
6555 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6556 /* the driver supports pixel center half integer */
6558 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6559 /* the driver supports pixel center integer, need to bias X,Y */
6560 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6561 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6562 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6568 /* we invert after adjustment so that we avoid the MOV to temporary,
6569 * and reuse the adjustment ADD instead */
6570 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6574 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6575 * TGSI uses +1 for front, -1 for back.
6576 * This function converts the TGSI value to the GL value. Simply clamping/
6577 * saturating the value to [0,1] does the job.
6580 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6582 struct ureg_program
*ureg
= t
->ureg
;
6583 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6584 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6586 if (ctx
->Const
.NativeIntegers
) {
6587 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6590 /* MOV_SAT face_temp, input[face] */
6591 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6594 /* Use face_temp as face input from here on: */
6595 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6599 emit_compute_block_size(const struct gl_program
*prog
,
6600 struct ureg_program
*ureg
) {
6601 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6602 prog
->info
.cs
.local_size
[0]);
6603 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6604 prog
->info
.cs
.local_size
[1]);
6605 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6606 prog
->info
.cs
.local_size
[2]);
6609 struct sort_inout_decls
{
6610 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6611 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6614 const ubyte
*mapping
;
6617 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6619 * This is for the benefit of older drivers which are broken when the
6620 * declarations aren't sorted in this way.
6623 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6625 const ubyte mapping
[])
6627 sort_inout_decls sorter
;
6628 sorter
.mapping
= mapping
;
6629 std::sort(decls
, decls
+ count
, sorter
);
6632 static enum tgsi_interpolate_mode
6633 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6635 switch (glsl_qual
) {
6636 case INTERP_MODE_NONE
:
6637 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6638 return TGSI_INTERPOLATE_COLOR
;
6639 return TGSI_INTERPOLATE_PERSPECTIVE
;
6640 case INTERP_MODE_SMOOTH
:
6641 return TGSI_INTERPOLATE_PERSPECTIVE
;
6642 case INTERP_MODE_FLAT
:
6643 return TGSI_INTERPOLATE_CONSTANT
;
6644 case INTERP_MODE_NOPERSPECTIVE
:
6645 return TGSI_INTERPOLATE_LINEAR
;
6647 assert(0 && "unexpected interp mode in st_translate_interp()");
6648 return TGSI_INTERPOLATE_PERSPECTIVE
;
6653 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6654 * \param program the program to translate
6655 * \param numInputs number of input registers used
6656 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6658 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6659 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6661 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6662 * \param numOutputs number of output registers used
6663 * \param outputMapping maps Mesa fragment program outputs to TGSI
6665 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6666 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6669 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6671 extern "C" enum pipe_error
6672 st_translate_program(
6673 struct gl_context
*ctx
,
6674 enum pipe_shader_type procType
,
6675 struct ureg_program
*ureg
,
6676 glsl_to_tgsi_visitor
*program
,
6677 const struct gl_program
*proginfo
,
6679 const ubyte inputMapping
[],
6680 const ubyte inputSlotToAttr
[],
6681 const ubyte inputSemanticName
[],
6682 const ubyte inputSemanticIndex
[],
6683 const ubyte interpMode
[],
6685 const ubyte outputMapping
[],
6686 const ubyte outputSemanticName
[],
6687 const ubyte outputSemanticIndex
[])
6689 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6690 struct st_translate
*t
;
6692 struct gl_program_constants
*frag_const
=
6693 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6694 enum pipe_error ret
= PIPE_OK
;
6696 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6697 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6699 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6700 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6701 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6702 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6703 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6704 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6705 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6706 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6707 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6708 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6710 t
= CALLOC_STRUCT(st_translate
);
6712 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6716 t
->procType
= procType
;
6717 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6718 t
->tg4_component_in_swizzle
= screen
->get_param(screen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
6719 t
->inputMapping
= inputMapping
;
6720 t
->outputMapping
= outputMapping
;
6722 t
->num_temp_arrays
= program
->next_array
;
6723 if (t
->num_temp_arrays
)
6724 t
->arrays
= (struct ureg_dst
*)
6725 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6728 * Declare input attributes.
6731 case PIPE_SHADER_FRAGMENT
:
6732 case PIPE_SHADER_GEOMETRY
:
6733 case PIPE_SHADER_TESS_EVAL
:
6734 case PIPE_SHADER_TESS_CTRL
:
6735 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6737 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6738 struct inout_decl
*decl
= &program
->inputs
[i
];
6739 unsigned slot
= inputMapping
[decl
->mesa_index
];
6740 struct ureg_src src
;
6741 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6743 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6744 if (tgsi_usage_mask
== 1)
6745 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6746 else if (tgsi_usage_mask
== 2)
6747 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6749 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6752 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6753 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6754 if (procType
== PIPE_SHADER_FRAGMENT
) {
6756 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6757 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6758 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6760 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6763 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6764 (enum tgsi_semantic
) inputSemanticName
[slot
],
6765 inputSemanticIndex
[slot
],
6766 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6767 decl
->array_id
, decl
->size
);
6769 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6770 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6771 /* The ArrayID is set up in dst_register */
6772 t
->inputs
[slot
+ j
] = src
;
6773 t
->inputs
[slot
+ j
].ArrayID
= 0;
6774 t
->inputs
[slot
+ j
].Index
+= j
;
6779 case PIPE_SHADER_VERTEX
:
6780 for (i
= 0; i
< numInputs
; i
++) {
6781 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6784 case PIPE_SHADER_COMPUTE
:
6791 * Declare output attributes.
6794 case PIPE_SHADER_FRAGMENT
:
6795 case PIPE_SHADER_COMPUTE
:
6797 case PIPE_SHADER_GEOMETRY
:
6798 case PIPE_SHADER_TESS_EVAL
:
6799 case PIPE_SHADER_TESS_CTRL
:
6800 case PIPE_SHADER_VERTEX
:
6801 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6803 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6804 struct inout_decl
*decl
= &program
->outputs
[i
];
6805 unsigned slot
= outputMapping
[decl
->mesa_index
];
6806 struct ureg_dst dst
;
6807 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6809 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6810 if (tgsi_usage_mask
== 1)
6811 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6812 else if (tgsi_usage_mask
== 2)
6813 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6815 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6818 dst
= ureg_DECL_output_layout(ureg
,
6819 (enum tgsi_semantic
) outputSemanticName
[slot
],
6820 outputSemanticIndex
[slot
],
6821 decl
->gs_out_streams
,
6822 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6823 dst
.Invariant
= decl
->invariant
;
6824 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6825 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6826 /* The ArrayID is set up in dst_register */
6827 t
->outputs
[slot
+ j
] = dst
;
6828 t
->outputs
[slot
+ j
].ArrayID
= 0;
6829 t
->outputs
[slot
+ j
].Index
+= j
;
6830 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6839 if (procType
== PIPE_SHADER_FRAGMENT
) {
6840 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6841 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6842 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6844 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6845 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6848 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6849 /* Must do this after setting up t->inputs. */
6850 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6851 program
->wpos_transform_const
);
6854 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6855 emit_face_var(ctx
, t
);
6857 for (i
= 0; i
< numOutputs
; i
++) {
6858 switch (outputSemanticName
[i
]) {
6859 case TGSI_SEMANTIC_POSITION
:
6860 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6861 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6862 outputSemanticIndex
[i
]);
6863 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6865 case TGSI_SEMANTIC_STENCIL
:
6866 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6867 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6868 outputSemanticIndex
[i
]);
6869 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6871 case TGSI_SEMANTIC_COLOR
:
6872 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6873 TGSI_SEMANTIC_COLOR
,
6874 outputSemanticIndex
[i
]);
6876 case TGSI_SEMANTIC_SAMPLEMASK
:
6877 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6878 TGSI_SEMANTIC_SAMPLEMASK
,
6879 outputSemanticIndex
[i
]);
6880 /* TODO: If we ever support more than 32 samples, this will have
6881 * to become an array.
6883 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6886 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6887 ret
= PIPE_ERROR_BAD_INPUT
;
6892 else if (procType
== PIPE_SHADER_VERTEX
) {
6893 for (i
= 0; i
< numOutputs
; i
++) {
6894 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6895 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6897 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6898 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6899 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6904 if (procType
== PIPE_SHADER_COMPUTE
) {
6905 emit_compute_block_size(proginfo
, ureg
);
6908 /* Declare address register.
6910 if (program
->num_address_regs
> 0) {
6911 assert(program
->num_address_regs
<= 3);
6912 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6913 t
->address
[i
] = ureg_DECL_address(ureg
);
6916 /* Declare misc input registers
6919 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6921 for (i
= 0; sysInputs
; i
++) {
6922 if (sysInputs
& (1ull << i
)) {
6923 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6925 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6927 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6928 semName
== TGSI_SEMANTIC_VERTEXID
) {
6929 /* From Gallium perspective, these system values are always
6930 * integer, and require native integer support. However, if
6931 * native integer is supported on the vertex stage but not the
6932 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6933 * assumes these system values are floats. To resolve the
6934 * inconsistency, we insert a U2F.
6936 struct st_context
*st
= st_context(ctx
);
6937 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6938 assert(procType
== PIPE_SHADER_VERTEX
);
6939 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6941 if (!ctx
->Const
.NativeIntegers
) {
6942 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6943 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6944 t
->systemValues
[i
]);
6945 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6949 if (procType
== PIPE_SHADER_FRAGMENT
&&
6950 semName
== TGSI_SEMANTIC_POSITION
)
6951 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6952 program
->wpos_transform_const
);
6954 if (procType
== PIPE_SHADER_FRAGMENT
&&
6955 semName
== TGSI_SEMANTIC_SAMPLEPOS
)
6956 emit_samplepos_adjustment(t
, program
->wpos_transform_const
);
6958 sysInputs
&= ~(1ull << i
);
6963 t
->array_sizes
= program
->array_sizes
;
6964 t
->input_decls
= program
->inputs
;
6965 t
->num_input_decls
= program
->num_inputs
;
6966 t
->output_decls
= program
->outputs
;
6967 t
->num_output_decls
= program
->num_outputs
;
6969 /* Emit constants and uniforms. TGSI uses a single index space for these,
6970 * so we put all the translated regs in t->constants.
6972 if (proginfo
->Parameters
) {
6973 t
->constants
= (struct ureg_src
*)
6974 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6975 if (t
->constants
== NULL
) {
6976 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6979 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6981 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6982 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6984 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6985 case PROGRAM_STATE_VAR
:
6986 case PROGRAM_UNIFORM
:
6987 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6990 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6991 * addressing of the const buffer.
6992 * FIXME: Be smarter and recognize param arrays:
6993 * indirect addressing is only valid within the referenced
6996 case PROGRAM_CONSTANT
:
6997 if (program
->indirect_addr_consts
)
6998 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
7000 t
->constants
[i
] = emit_immediate(t
,
7001 proginfo
->Parameters
->ParameterValues
+ pvo
,
7002 proginfo
->Parameters
->Parameters
[i
].DataType
,
7011 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
7012 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
7013 unsigned num_const_vecs
= (size
+ 15) / 16;
7014 unsigned first
, last
;
7015 assert(num_const_vecs
> 0);
7017 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
7018 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
7021 /* Emit immediate values.
7023 t
->immediates
= (struct ureg_src
*)
7024 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
7025 if (t
->immediates
== NULL
) {
7026 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
7029 t
->num_immediates
= program
->num_immediates
;
7032 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
7033 assert(i
< program
->num_immediates
);
7034 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
7036 assert(i
== program
->num_immediates
);
7038 /* texture samplers */
7039 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
7040 if (program
->samplers_used
& (1u << i
)) {
7041 enum tgsi_return_type type
=
7042 st_translate_texture_type(program
->sampler_types
[i
]);
7044 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
7046 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
7047 type
, type
, type
, type
);
7051 /* Declare atomic and shader storage buffers. */
7053 struct gl_program
*prog
= program
->prog
;
7055 if (!st_context(ctx
)->has_hw_atomics
) {
7056 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
7057 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
7058 assert(index
< frag_const
->MaxAtomicBuffers
);
7059 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
7062 for (i
= 0; i
< program
->num_atomics
; i
++) {
7063 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
7064 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
7065 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
7066 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
7071 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
7072 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
7074 if (!st_context(ctx
)->has_hw_atomics
)
7075 index
+= frag_const
->MaxAtomicBuffers
;
7077 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
7081 if (program
->use_shared_memory
)
7082 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
7084 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
7085 if (program
->images_used
& (1 << i
)) {
7086 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
7087 program
->image_targets
[i
],
7088 program
->image_formats
[i
],
7089 program
->image_wr
[i
],
7094 /* Emit each instruction in turn:
7096 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
7097 compile_tgsi_instruction(t
, inst
);
7099 /* Set the next shader stage hint for VS and TES. */
7101 case PIPE_SHADER_VERTEX
:
7102 case PIPE_SHADER_TESS_EVAL
:
7103 if (program
->shader_program
->SeparateShader
)
7106 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
7107 if (program
->shader_program
->_LinkedShaders
[i
]) {
7108 ureg_set_next_shader_processor(
7109 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
7115 ; /* nothing - silence compiler warning */
7123 t
->num_constants
= 0;
7124 free(t
->immediates
);
7125 t
->num_immediates
= 0;
7131 /* ----------------------------- End TGSI code ------------------------------ */
7135 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7136 * generating Mesa IR.
7138 static struct gl_program
*
7139 get_mesa_program_tgsi(struct gl_context
*ctx
,
7140 struct gl_shader_program
*shader_program
,
7141 struct gl_linked_shader
*shader
)
7143 glsl_to_tgsi_visitor
* v
;
7144 struct gl_program
*prog
;
7145 struct gl_shader_compiler_options
*options
=
7146 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
7147 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7148 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
7149 unsigned skip_merge_registers
;
7151 validate_ir_tree(shader
->ir
);
7153 prog
= shader
->Program
;
7155 prog
->Parameters
= _mesa_new_parameter_list();
7156 v
= new glsl_to_tgsi_visitor();
7159 v
->shader_program
= shader_program
;
7161 v
->options
= options
;
7162 v
->native_integers
= ctx
->Const
.NativeIntegers
;
7164 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
7165 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
7166 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
7167 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
7168 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
7169 PIPE_CAP_TGSI_TEX_TXF_LZ
);
7170 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
7172 v
->tg4_component_in_swizzle
= pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
7173 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
7174 _mesa_key_pointer_equal
);
7175 skip_merge_registers
=
7176 pscreen
->get_shader_param(pscreen
, ptarget
,
7177 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
7179 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
7182 /* Remove reads from output registers. */
7183 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
7184 lower_output_reads(shader
->Stage
, shader
->ir
);
7186 /* Emit intermediate IR for main(). */
7187 visit_exec_list(shader
->ir
, v
);
7190 /* Print out some information (for debugging purposes) used by the
7191 * optimization passes. */
7194 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7195 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7196 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7197 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7199 for (i
= 0; i
< v
->next_temp
; i
++) {
7200 first_writes
[i
] = -1;
7201 first_reads
[i
] = -1;
7202 last_writes
[i
] = -1;
7205 v
->get_first_temp_read(first_reads
);
7206 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
7207 v
->get_last_temp_write(last_writes
);
7208 for (i
= 0; i
< v
->next_temp
; i
++)
7209 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
7213 ralloc_free(first_writes
);
7214 ralloc_free(first_reads
);
7215 ralloc_free(last_writes
);
7216 ralloc_free(last_reads
);
7220 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7222 v
->copy_propagate();
7224 while (v
->eliminate_dead_code());
7226 v
->merge_two_dsts();
7228 if (!skip_merge_registers
) {
7230 v
->copy_propagate();
7231 while (v
->eliminate_dead_code());
7233 v
->merge_registers();
7234 v
->copy_propagate();
7235 while (v
->eliminate_dead_code());
7238 v
->renumber_registers();
7240 /* Write the END instruction. */
7241 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
7243 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
7245 _mesa_log("GLSL IR for linked %s program %d:\n",
7246 _mesa_shader_stage_to_string(shader
->Stage
),
7247 shader_program
->Name
);
7248 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
7252 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
7254 _mesa_copy_linked_program_data(shader_program
, shader
);
7256 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
)) {
7257 mark_array_io(v
->inputs
, v
->num_inputs
,
7258 &prog
->info
.inputs_read
,
7259 prog
->DualSlotInputs
,
7260 &prog
->info
.patch_inputs_read
);
7262 mark_array_io(v
->outputs
, v
->num_outputs
,
7263 &prog
->info
.outputs_written
, 0ULL,
7264 &prog
->info
.patch_outputs_written
);
7266 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
7267 &prog
->info
.inputs_read
,
7268 prog
->DualSlotInputs
,
7269 &prog
->info
.patch_inputs_read
);
7270 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
7271 &prog
->info
.outputs_written
, 0ULL,
7272 &prog
->info
.patch_outputs_written
);
7275 count_resources(v
, prog
);
7277 /* The GLSL IR won't be needed anymore. */
7278 ralloc_free(shader
->ir
);
7281 /* This must be done before the uniform storage is associated. */
7282 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
7283 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
7284 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
) ||
7285 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_SAMPLE_POS
))) {
7286 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
7287 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
7290 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
7291 wposTransformState
);
7294 /* Avoid reallocation of the program parameter list, because the uniform
7295 * storage is only associated with the original parameter list.
7296 * This should be enough for Bitmap and DrawPixels constants.
7298 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
7300 /* This has to be done last. Any operation the can cause
7301 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7302 * program constant) has to happen before creating this linkage.
7304 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
);
7305 if (!shader_program
->data
->LinkStatus
) {
7306 free_glsl_to_tgsi_visitor(v
);
7307 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7311 struct st_common_program
*stvp
;
7312 struct st_common_program
*stp
;
7314 switch (shader
->Stage
) {
7315 case MESA_SHADER_VERTEX
:
7316 stvp
= (struct st_common_program
*)prog
;
7317 stvp
->glsl_to_tgsi
= v
;
7319 case MESA_SHADER_FRAGMENT
:
7320 case MESA_SHADER_TESS_CTRL
:
7321 case MESA_SHADER_TESS_EVAL
:
7322 case MESA_SHADER_GEOMETRY
:
7323 case MESA_SHADER_COMPUTE
:
7324 stp
= st_common_program(prog
);
7325 stp
->glsl_to_tgsi
= v
;
7328 assert(!"should not be reached");
7332 PRINT_STATS(v
->print_stats());
7337 /* See if there are unsupported control flow statements. */
7338 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7340 const struct gl_shader_compiler_options
*options
;
7342 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7348 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7350 /* Other functions are skipped (same as glsl_to_tgsi). */
7351 if (strcmp(ir
->name
, "main") == 0)
7352 return visit_continue
;
7354 return visit_continue_with_parent
;
7357 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7359 if (!ir
->callee
->is_intrinsic()) {
7360 unsupported
= true; /* it's a function call */
7363 return visit_continue
;
7366 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7368 if (options
->EmitNoMainReturn
) {
7372 return visit_continue
;
7379 has_unsupported_control_flow(exec_list
*ir
,
7380 const struct gl_shader_compiler_options
*options
)
7382 ir_control_flow_info_visitor
visitor(options
);
7383 visit_list_elements(&visitor
, ir
);
7384 return visitor
.unsupported
;
7389 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7390 * with code lowering and other optimizations.
7393 st_link_tgsi(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7395 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7397 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7398 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7402 exec_list
*ir
= shader
->ir
;
7403 gl_shader_stage stage
= shader
->Stage
;
7404 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7405 const struct gl_shader_compiler_options
*options
=
7406 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7408 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7409 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7410 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7411 /* Do it once and repeat only if there's unsupported control flow. */
7413 do_common_optimization(ir
, true, true, options
,
7414 ctx
->Const
.NativeIntegers
);
7415 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7416 options
->MaxIfDepth
, if_threshold
);
7417 } while (has_unsupported_control_flow(ir
, options
));
7419 /* Repeat it until it stops making changes. */
7422 progress
= do_common_optimization(ir
, true, true, options
,
7423 ctx
->Const
.NativeIntegers
);
7424 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7425 options
->MaxIfDepth
, if_threshold
);
7429 /* Do this again to lower ir_binop_vector_extract introduced
7430 * by optimization passes.
7432 do_vec_index_to_cond_assign(ir
);
7434 validate_ir_tree(ir
);
7436 struct gl_program
*linked_prog
=
7437 get_mesa_program_tgsi(ctx
, prog
, shader
);
7438 st_set_prog_affected_state_flags(linked_prog
);
7441 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7442 _mesa_shader_stage_to_program(i
),
7444 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);