2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
128 static struct inout_decl
*
129 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
131 assert(array_id
!= 0);
133 for (unsigned i
= 0; i
< count
; i
++) {
134 struct inout_decl
*decl
= &decls
[i
];
136 if (array_id
== decl
->array_id
) {
144 static enum glsl_base_type
145 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
148 return GLSL_TYPE_ERROR
;
149 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
151 return decl
->base_type
;
152 return GLSL_TYPE_ERROR
;
155 struct glsl_to_tgsi_visitor
: public ir_visitor
{
157 glsl_to_tgsi_visitor();
158 ~glsl_to_tgsi_visitor();
160 struct gl_context
*ctx
;
161 struct gl_program
*prog
;
162 struct gl_shader_program
*shader_program
;
163 struct gl_linked_shader
*shader
;
164 struct gl_shader_compiler_options
*options
;
168 unsigned *array_sizes
;
169 unsigned max_num_arrays
;
172 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
174 unsigned num_input_arrays
;
175 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
176 unsigned num_outputs
;
177 unsigned num_output_arrays
;
179 int num_address_regs
;
180 uint32_t samplers_used
;
181 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
182 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
184 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
185 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
186 bool indirect_addr_consts
;
187 int wpos_transform_const
;
189 bool native_integers
;
192 bool use_shared_memory
;
197 variable_storage
*find_variable_storage(ir_variable
*var
);
199 int add_constant(gl_register_file file
, gl_constant_value values
[8],
200 int size
, int datatype
, uint16_t *swizzle_out
);
202 st_src_reg
get_temp(const glsl_type
*type
);
203 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
205 st_src_reg
st_src_reg_for_double(double val
);
206 st_src_reg
st_src_reg_for_float(float val
);
207 st_src_reg
st_src_reg_for_int(int val
);
208 st_src_reg
st_src_reg_for_int64(int64_t val
);
209 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
212 * \name Visit methods
214 * As typical for the visitor pattern, there must be one \c visit method for
215 * each concrete subclass of \c ir_instruction. Virtual base classes within
216 * the hierarchy should not have \c visit methods.
219 virtual void visit(ir_variable
*);
220 virtual void visit(ir_loop
*);
221 virtual void visit(ir_loop_jump
*);
222 virtual void visit(ir_function_signature
*);
223 virtual void visit(ir_function
*);
224 virtual void visit(ir_expression
*);
225 virtual void visit(ir_swizzle
*);
226 virtual void visit(ir_dereference_variable
*);
227 virtual void visit(ir_dereference_array
*);
228 virtual void visit(ir_dereference_record
*);
229 virtual void visit(ir_assignment
*);
230 virtual void visit(ir_constant
*);
231 virtual void visit(ir_call
*);
232 virtual void visit(ir_return
*);
233 virtual void visit(ir_discard
*);
234 virtual void visit(ir_texture
*);
235 virtual void visit(ir_if
*);
236 virtual void visit(ir_emit_vertex
*);
237 virtual void visit(ir_end_primitive
*);
238 virtual void visit(ir_barrier
*);
241 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
243 void visit_atomic_counter_intrinsic(ir_call
*);
244 void visit_ssbo_intrinsic(ir_call
*);
245 void visit_membar_intrinsic(ir_call
*);
246 void visit_shared_intrinsic(ir_call
*);
247 void visit_image_intrinsic(ir_call
*);
248 void visit_generic_intrinsic(ir_call
*, unsigned op
);
252 /** List of variable_storage */
253 struct hash_table
*variables
;
255 /** List of immediate_storage */
256 exec_list immediates
;
257 unsigned num_immediates
;
259 /** List of glsl_to_tgsi_instruction */
260 exec_list instructions
;
262 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
263 st_dst_reg dst
= undef_dst
,
264 st_src_reg src0
= undef_src
,
265 st_src_reg src1
= undef_src
,
266 st_src_reg src2
= undef_src
,
267 st_src_reg src3
= undef_src
);
269 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
270 st_dst_reg dst
, st_dst_reg dst1
,
271 st_src_reg src0
= undef_src
,
272 st_src_reg src1
= undef_src
,
273 st_src_reg src2
= undef_src
,
274 st_src_reg src3
= undef_src
);
276 unsigned get_opcode(unsigned op
,
278 st_src_reg src0
, st_src_reg src1
);
281 * Emit the correct dot-product instruction for the type of arguments
283 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
289 void emit_scalar(ir_instruction
*ir
, unsigned op
,
290 st_dst_reg dst
, st_src_reg src0
);
292 void emit_scalar(ir_instruction
*ir
, unsigned op
,
293 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
295 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
297 void get_deref_offsets(ir_dereference
*ir
,
298 unsigned *array_size
,
303 void calc_deref_offsets(ir_dereference
*tail
,
304 unsigned *array_elements
,
306 st_src_reg
*indirect
,
308 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
315 void emit_swz(ir_expression
*ir
);
317 bool process_move_condition(ir_rvalue
*ir
);
319 void simplify_cmp(void);
321 void rename_temp_registers(struct rename_reg_pair
*renames
);
322 void get_first_temp_read(int *first_reads
);
323 void get_first_temp_write(int *first_writes
);
324 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
325 void get_last_temp_write(int *last_writes
);
327 void copy_propagate(void);
328 int eliminate_dead_code(void);
330 void merge_two_dsts(void);
331 void merge_registers(void);
332 void renumber_registers(void);
334 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
335 st_dst_reg
*l
, st_src_reg
*r
,
336 st_src_reg
*cond
, bool cond_swap
);
341 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
342 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
343 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
346 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
349 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
353 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
356 prog
->data
->LinkStatus
= linking_failure
;
360 swizzle_for_size(int size
)
362 static const int size_swizzles
[4] = {
363 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
364 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
365 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
366 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
369 assert((size
>= 1) && (size
<= 4));
370 return size_swizzles
[size
- 1];
374 glsl_to_tgsi_instruction
*
375 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
376 st_dst_reg dst
, st_dst_reg dst1
,
377 st_src_reg src0
, st_src_reg src1
,
378 st_src_reg src2
, st_src_reg src3
)
380 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
381 int num_reladdr
= 0, i
, j
;
382 bool dst_is_64bit
[2];
384 op
= get_opcode(op
, dst
, src0
, src1
);
386 /* If we have to do relative addressing, we want to load the ARL
387 * reg directly for one of the regs, and preload the other reladdr
388 * sources into temps.
390 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
391 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
392 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
393 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
394 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
395 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
397 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
398 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
399 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
400 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
402 if (dst
.reladdr
|| dst
.reladdr2
) {
404 emit_arl(ir
, address_reg
, *dst
.reladdr
);
406 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
410 assert(num_reladdr
== 0);
412 /* inst->op has only 8 bits. */
413 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
416 inst
->precise
= this->precise
;
417 inst
->info
= tgsi_get_opcode_info(op
);
424 inst
->is_64bit_expanded
= false;
427 inst
->tex_offsets
= NULL
;
428 inst
->tex_offset_num_offset
= 0;
430 inst
->tex_shadow
= 0;
431 /* default to float, for paths where this is not initialized
432 * (since 0==UINT which is likely wrong):
434 inst
->tex_type
= GLSL_TYPE_FLOAT
;
436 /* Update indirect addressing status used by TGSI */
437 if (dst
.reladdr
|| dst
.reladdr2
) {
439 case PROGRAM_STATE_VAR
:
440 case PROGRAM_CONSTANT
:
441 case PROGRAM_UNIFORM
:
442 this->indirect_addr_consts
= true;
444 case PROGRAM_IMMEDIATE
:
445 assert(!"immediates should not have indirect addressing");
452 for (i
= 0; i
< 4; i
++) {
453 if(inst
->src
[i
].reladdr
) {
454 switch(inst
->src
[i
].file
) {
455 case PROGRAM_STATE_VAR
:
456 case PROGRAM_CONSTANT
:
457 case PROGRAM_UNIFORM
:
458 this->indirect_addr_consts
= true;
460 case PROGRAM_IMMEDIATE
:
461 assert(!"immediates should not have indirect addressing");
471 * This section contains the double processing.
472 * GLSL just represents doubles as single channel values,
473 * however most HW and TGSI represent doubles as pairs of register channels.
475 * so we have to fixup destination writemask/index and src swizzle/indexes.
476 * dest writemasks need to translate from single channel write mask
477 * to a dual-channel writemask, but also need to modify the index,
478 * if we are touching the Z,W fields in the pre-translated writemask.
480 * src channels have similiar index modifications along with swizzle
481 * changes to we pick the XY, ZW pairs from the correct index.
483 * GLSL [0].x -> TGSI [0].xy
484 * GLSL [0].y -> TGSI [0].zw
485 * GLSL [0].z -> TGSI [1].xy
486 * GLSL [0].w -> TGSI [1].zw
488 for (j
= 0; j
< 2; j
++) {
489 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
490 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
491 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
492 if (glsl_base_type_is_64bit(type
))
493 dst_is_64bit
[j
] = true;
497 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
498 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
499 glsl_to_tgsi_instruction
*dinst
= NULL
;
500 int initial_src_swz
[4], initial_src_idx
[4];
501 int initial_dst_idx
[2], initial_dst_writemask
[2];
502 /* select the writemask for dst0 or dst1 */
503 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
505 /* copy out the writemask, index and swizzles for all src/dsts. */
506 for (j
= 0; j
< 2; j
++) {
507 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
508 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
511 for (j
= 0; j
< 4; j
++) {
512 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
513 initial_src_idx
[j
] = inst
->src
[j
].index
;
517 * scan all the components in the dst writemask
518 * generate an instruction for each of them if required.
523 int i
= u_bit_scan(&writemask
);
525 /* before emitting the instruction, see if we have to adjust load / store
527 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
528 addr
.file
== PROGRAM_UNDEFINED
) {
529 /* We have to advance the buffer address by 16 */
530 addr
= get_temp(glsl_type::uint_type
);
531 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
532 inst
->src
[0], st_src_reg_for_int(16));
535 /* first time use previous instruction */
539 /* create a new instructions for subsequent attempts */
540 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
545 this->instructions
.push_tail(dinst
);
546 dinst
->is_64bit_expanded
= true;
548 /* modify the destination if we are splitting */
549 for (j
= 0; j
< 2; j
++) {
550 if (dst_is_64bit
[j
]) {
551 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
552 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
554 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
555 dinst
->src
[0] = addr
;
556 if (dinst
->op
!= TGSI_OPCODE_STORE
)
557 dinst
->dst
[j
].index
++;
560 /* if we aren't writing to a double, just get the bit of the initial writemask
562 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
566 /* modify the src registers */
567 for (j
= 0; j
< 4; j
++) {
568 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
570 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
571 dinst
->src
[j
].index
= initial_src_idx
[j
];
573 dinst
->src
[j
].double_reg2
= true;
574 dinst
->src
[j
].index
++;
578 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
580 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
583 /* some opcodes are special case in what they use as sources
584 - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
585 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
586 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
587 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
588 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
589 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
596 this->instructions
.push_tail(inst
);
603 glsl_to_tgsi_instruction
*
604 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
606 st_src_reg src0
, st_src_reg src1
,
607 st_src_reg src2
, st_src_reg src3
)
609 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
613 * Determines whether to use an integer, unsigned integer, or float opcode
614 * based on the operands and input opcode, then emits the result.
617 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
619 st_src_reg src0
, st_src_reg src1
)
621 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
623 if (op
== TGSI_OPCODE_MOV
)
626 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
627 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
628 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
629 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
631 if (is_resource_instruction(op
))
633 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
634 type
= GLSL_TYPE_INT64
;
635 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
636 type
= GLSL_TYPE_UINT64
;
637 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
638 type
= GLSL_TYPE_DOUBLE
;
639 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
640 type
= GLSL_TYPE_FLOAT
;
641 else if (native_integers
)
642 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
644 #define case7(c, f, i, u, d, i64, ui64) \
645 case TGSI_OPCODE_##c: \
646 if (type == GLSL_TYPE_UINT64) \
647 op = TGSI_OPCODE_##ui64; \
648 else if (type == GLSL_TYPE_INT64) \
649 op = TGSI_OPCODE_##i64; \
650 else if (type == GLSL_TYPE_DOUBLE) \
651 op = TGSI_OPCODE_##d; \
652 else if (type == GLSL_TYPE_INT) \
653 op = TGSI_OPCODE_##i; \
654 else if (type == GLSL_TYPE_UINT) \
655 op = TGSI_OPCODE_##u; \
657 op = TGSI_OPCODE_##f; \
660 #define casecomp(c, f, i, u, d, i64, ui64) \
661 case TGSI_OPCODE_##c: \
662 if (type == GLSL_TYPE_INT64) \
663 op = TGSI_OPCODE_##i64; \
664 else if (type == GLSL_TYPE_UINT64) \
665 op = TGSI_OPCODE_##ui64; \
666 else if (type == GLSL_TYPE_DOUBLE) \
667 op = TGSI_OPCODE_##d; \
668 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
669 op = TGSI_OPCODE_##i; \
670 else if (type == GLSL_TYPE_UINT) \
671 op = TGSI_OPCODE_##u; \
672 else if (native_integers) \
673 op = TGSI_OPCODE_##f; \
675 op = TGSI_OPCODE_##c; \
679 /* Some instructions are initially selected without considering the type.
680 * This fixes the type:
682 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
684 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
685 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
686 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
687 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
688 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
689 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
690 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
691 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
692 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
693 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
694 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
695 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
696 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
697 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
698 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
699 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
701 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
702 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
703 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
704 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
705 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
706 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
707 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
708 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
710 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
711 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
712 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
713 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
718 assert(op
!= TGSI_OPCODE_LAST
);
722 glsl_to_tgsi_instruction
*
723 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
724 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
727 static const unsigned dot_opcodes
[] = {
728 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
731 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
735 * Emits TGSI scalar opcodes to produce unique answers across channels.
737 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
738 * channel determines the result across all channels. So to do a vec4
739 * of this operation, we want to emit a scalar per source channel used
740 * to produce dest channels.
743 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
745 st_src_reg orig_src0
, st_src_reg orig_src1
)
748 int done_mask
= ~dst
.writemask
;
750 /* TGSI RCP is a scalar operation splatting results to all channels,
751 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
754 for (i
= 0; i
< 4; i
++) {
755 GLuint this_mask
= (1 << i
);
756 st_src_reg src0
= orig_src0
;
757 st_src_reg src1
= orig_src1
;
759 if (done_mask
& this_mask
)
762 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
763 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
764 for (j
= i
+ 1; j
< 4; j
++) {
765 /* If there is another enabled component in the destination that is
766 * derived from the same inputs, generate its value on this pass as
769 if (!(done_mask
& (1 << j
)) &&
770 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
771 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
772 this_mask
|= (1 << j
);
775 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
776 src0_swiz
, src0_swiz
);
777 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
778 src1_swiz
, src1_swiz
);
780 dst
.writemask
= this_mask
;
781 emit_asm(ir
, op
, dst
, src0
, src1
);
782 done_mask
|= this_mask
;
787 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
788 st_dst_reg dst
, st_src_reg src0
)
790 st_src_reg undef
= undef_src
;
792 undef
.swizzle
= SWIZZLE_XXXX
;
794 emit_scalar(ir
, op
, dst
, src0
, undef
);
798 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
799 st_dst_reg dst
, st_src_reg src0
)
801 int op
= TGSI_OPCODE_ARL
;
803 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
804 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
807 op
= TGSI_OPCODE_UARL
;
810 assert(dst
.file
== PROGRAM_ADDRESS
);
811 if (dst
.index
>= this->num_address_regs
)
812 this->num_address_regs
= dst
.index
+ 1;
814 emit_asm(NULL
, op
, dst
, src0
);
818 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
819 gl_constant_value values
[8], int size
, int datatype
,
820 uint16_t *swizzle_out
)
822 if (file
== PROGRAM_CONSTANT
) {
823 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
824 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
825 size
, datatype
, &swizzle
);
827 *swizzle_out
= swizzle
;
831 assert(file
== PROGRAM_IMMEDIATE
);
834 immediate_storage
*entry
;
835 int size32
= size
* ((datatype
== GL_DOUBLE
||
836 datatype
== GL_INT64_ARB
||
837 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
840 /* Search immediate storage to see if we already have an identical
841 * immediate that we can use instead of adding a duplicate entry.
843 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
844 immediate_storage
*tmp
= entry
;
846 for (i
= 0; i
* 4 < size32
; i
++) {
847 int slot_size
= MIN2(size32
- (i
* 4), 4);
848 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
850 if (memcmp(tmp
->values
, &values
[i
* 4],
851 slot_size
* sizeof(gl_constant_value
)))
854 /* Everything matches, keep going until the full size is matched */
855 tmp
= (immediate_storage
*)tmp
->next
;
858 /* The full value matched */
865 for (i
= 0; i
* 4 < size32
; i
++) {
866 int slot_size
= MIN2(size32
- (i
* 4), 4);
867 /* Add this immediate to the list. */
868 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
869 this->immediates
.push_tail(entry
);
870 this->num_immediates
++;
876 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
878 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
879 union gl_constant_value uval
;
882 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
888 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
890 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
891 union gl_constant_value uval
[2];
893 memcpy(uval
, &val
, sizeof(uval
));
894 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
895 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
900 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
902 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
903 union gl_constant_value uval
;
905 assert(native_integers
);
908 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
914 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
916 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
917 union gl_constant_value uval
[2];
919 memcpy(uval
, &val
, sizeof(uval
));
920 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
921 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
927 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
930 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
931 st_src_reg_for_int(val
);
933 return st_src_reg_for_float(val
);
937 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
939 return type
->count_attribute_slots(is_vs_input
);
943 type_size(const struct glsl_type
*type
)
945 return type
->count_attribute_slots(false);
949 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
950 exec_list
*instructions
, ir_constant
*access
)
953 * emit_asm() might have actually split the op into pieces, e.g. for
954 * double stores. We have to go back and fix up all the generated ops.
956 unsigned op
= inst
->op
;
958 inst
->resource
= *buf
;
960 inst
->buffer_access
= access
->value
.u
[0];
962 if (inst
== instructions
->get_head_raw())
964 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
966 if (inst
->op
== TGSI_OPCODE_UADD
) {
967 if (inst
== instructions
->get_head_raw())
969 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
971 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
975 * If the given GLSL type is an array or matrix or a structure containing
976 * an array/matrix member, return true. Else return false.
978 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
979 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
980 * we have an array that might be indexed with a variable, we need to use
981 * the later storage type.
984 type_has_array_or_matrix(const glsl_type
*type
)
986 if (type
->is_array() || type
->is_matrix())
989 if (type
->is_record()) {
990 for (unsigned i
= 0; i
< type
->length
; i
++) {
991 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1002 * In the initial pass of codegen, we assign temporary numbers to
1003 * intermediate results. (not SSA -- variable assignments will reuse
1007 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1011 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1016 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1017 if (next_array
>= max_num_arrays
) {
1018 max_num_arrays
+= 32;
1019 array_sizes
= (unsigned*)
1020 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1023 src
.file
= PROGRAM_ARRAY
;
1025 src
.array_id
= next_array
+ 1;
1026 array_sizes
[next_array
] = type_size(type
);
1030 src
.file
= PROGRAM_TEMPORARY
;
1031 src
.index
= next_temp
;
1032 next_temp
+= type_size(type
);
1035 if (type
->is_array() || type
->is_record()) {
1036 src
.swizzle
= SWIZZLE_NOOP
;
1038 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1045 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1047 struct hash_entry
*entry
;
1049 entry
= _mesa_hash_table_search(this->variables
, var
);
1053 return (variable_storage
*)entry
->data
;
1057 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1059 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1060 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1061 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1064 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1066 const ir_state_slot
*const slots
= ir
->get_state_slots();
1067 assert(slots
!= NULL
);
1069 /* Check if this statevar's setup in the STATE file exactly
1070 * matches how we'll want to reference it as a
1071 * struct/array/whatever. If not, then we need to move it into
1072 * temporary storage and hope that it'll get copy-propagated
1075 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1076 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1081 variable_storage
*storage
;
1083 if (i
== ir
->get_num_state_slots()) {
1084 /* We'll set the index later. */
1085 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1087 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1091 /* The variable_storage constructor allocates slots based on the size
1092 * of the type. However, this had better match the number of state
1093 * elements that we're going to copy into the new temporary.
1095 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1097 dst
= st_dst_reg(get_temp(ir
->type
));
1099 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1102 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1106 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1107 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1108 (gl_state_index
*)slots
[i
].tokens
);
1110 if (storage
->file
== PROGRAM_STATE_VAR
) {
1111 if (storage
->index
== -1) {
1112 storage
->index
= index
;
1114 assert(index
== storage
->index
+ (int)i
);
1117 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1118 * the data being moved since MOV does not care about the type of
1119 * data it is moving, and we don't want to declare registers with
1120 * array or struct types.
1122 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1123 src
.swizzle
= slots
[i
].swizzle
;
1124 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1125 /* even a float takes up a whole vec4 reg in a struct/array. */
1130 if (storage
->file
== PROGRAM_TEMPORARY
&&
1131 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1132 fail_link(this->shader_program
,
1133 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1134 ir
->name
, dst
.index
- storage
->index
,
1135 type_size(ir
->type
));
1141 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1143 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1145 visit_exec_list(&ir
->body_instructions
, this);
1147 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1151 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1154 case ir_loop_jump::jump_break
:
1155 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1157 case ir_loop_jump::jump_continue
:
1158 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1165 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1172 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1174 /* Ignore function bodies other than main() -- we shouldn't see calls to
1175 * them since they should all be inlined before we get to glsl_to_tgsi.
1177 if (strcmp(ir
->name
, "main") == 0) {
1178 const ir_function_signature
*sig
;
1181 sig
= ir
->matching_signature(NULL
, &empty
, false);
1185 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1192 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1194 int nonmul_operand
= 1 - mul_operand
;
1196 st_dst_reg result_dst
;
1198 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1199 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1202 expr
->operands
[0]->accept(this);
1204 expr
->operands
[1]->accept(this);
1206 ir
->operands
[nonmul_operand
]->accept(this);
1209 this->result
= get_temp(ir
->type
);
1210 result_dst
= st_dst_reg(this->result
);
1211 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1212 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1218 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1220 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1221 * implemented using multiplication, and logical-or is implemented using
1222 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1223 * As result, the logical expression (a & !b) can be rewritten as:
1227 * - (a * 1) - (a * b)
1231 * This final expression can be implemented as a single MAD(a, -b, a)
1235 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1237 const int other_operand
= 1 - try_operand
;
1240 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1241 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1244 ir
->operands
[other_operand
]->accept(this);
1246 expr
->operands
[0]->accept(this);
1249 b
.negate
= ~b
.negate
;
1251 this->result
= get_temp(ir
->type
);
1252 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1258 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1259 st_src_reg
*reg
, int *num_reladdr
)
1261 if (!reg
->reladdr
&& !reg
->reladdr2
)
1264 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1265 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1267 if (*num_reladdr
!= 1) {
1268 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1270 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1278 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1280 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1282 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1284 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1285 if (try_emit_mad(ir
, 1))
1287 if (try_emit_mad(ir
, 0))
1291 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1293 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1294 if (try_emit_mad_for_and_not(ir
, 1))
1296 if (try_emit_mad_for_and_not(ir
, 0))
1300 if (ir
->operation
== ir_quadop_vector
)
1301 assert(!"ir_quadop_vector should have been lowered");
1303 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1304 this->result
.file
= PROGRAM_UNDEFINED
;
1305 ir
->operands
[operand
]->accept(this);
1306 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1307 printf("Failed to get tree for expression operand:\n");
1308 ir
->operands
[operand
]->print();
1312 op
[operand
] = this->result
;
1314 /* Matrix expression operands should have been broken down to vector
1315 * operations already.
1317 assert(!ir
->operands
[operand
]->type
->is_matrix());
1320 visit_expression(ir
, op
);
1323 /* The non-recursive part of the expression visitor lives in a separate
1324 * function and should be prevented from being inlined, to avoid a stack
1325 * explosion when deeply nested expressions are visited.
1328 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1330 st_src_reg result_src
;
1331 st_dst_reg result_dst
;
1333 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1334 if (ir
->operands
[1]) {
1335 vector_elements
= MAX2(vector_elements
,
1336 ir
->operands
[1]->type
->vector_elements
);
1339 this->result
.file
= PROGRAM_UNDEFINED
;
1341 /* Storage for our result. Ideally for an assignment we'd be using
1342 * the actual storage for the result here, instead.
1344 result_src
= get_temp(ir
->type
);
1345 /* convenience for the emit functions below. */
1346 result_dst
= st_dst_reg(result_src
);
1347 /* Limit writes to the channels that will be used by result_src later.
1348 * This does limit this temp's use as a temporary for multi-instruction
1351 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1353 switch (ir
->operation
) {
1354 case ir_unop_logic_not
:
1355 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1356 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1358 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1359 * older GPUs implement SEQ using multiple instructions (i915 uses two
1360 * SGE instructions and a MUL instruction). Since our logic values are
1361 * 0.0 and 1.0, 1-x also implements !x.
1363 op
[0].negate
= ~op
[0].negate
;
1364 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1368 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1369 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1370 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1371 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1372 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1373 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1375 op
[0].negate
= ~op
[0].negate
;
1379 case ir_unop_subroutine_to_int
:
1380 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1383 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1384 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1385 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1386 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1387 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1388 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1390 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1393 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1396 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1400 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1403 assert(!"not reached: should be handled by exp_to_exp2");
1406 assert(!"not reached: should be handled by log_to_log2");
1409 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1412 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1415 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1417 case ir_unop_saturate
: {
1418 glsl_to_tgsi_instruction
*inst
;
1419 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1420 inst
->saturate
= true;
1425 case ir_unop_dFdx_coarse
:
1426 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1428 case ir_unop_dFdx_fine
:
1429 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1432 case ir_unop_dFdy_coarse
:
1433 case ir_unop_dFdy_fine
:
1435 /* The X component contains 1 or -1 depending on whether the framebuffer
1436 * is a FBO or the window system buffer, respectively.
1437 * It is then multiplied with the source operand of DDY.
1439 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1440 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1442 unsigned transform_y_index
=
1443 _mesa_add_state_reference(this->prog
->Parameters
,
1446 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1448 glsl_type::vec4_type
);
1449 transform_y
.swizzle
= SWIZZLE_XXXX
;
1451 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1453 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1454 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1455 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1459 case ir_unop_frexp_sig
:
1460 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1463 case ir_unop_frexp_exp
:
1464 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1467 case ir_unop_noise
: {
1468 /* At some point, a motivated person could add a better
1469 * implementation of noise. Currently not even the nvidia
1470 * binary drivers do anything more than this. In any case, the
1471 * place to do this is in the GL state tracker, not the poor
1474 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1479 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1482 op
[1].negate
= ~op
[1].negate
;
1483 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1487 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1490 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1493 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1494 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1496 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1500 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1502 case ir_binop_gequal
:
1503 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1505 case ir_binop_equal
:
1506 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1508 case ir_binop_nequal
:
1509 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1511 case ir_binop_all_equal
:
1512 /* "==" operator producing a scalar boolean. */
1513 if (ir
->operands
[0]->type
->is_vector() ||
1514 ir
->operands
[1]->type
->is_vector()) {
1515 st_src_reg temp
= get_temp(native_integers
?
1516 glsl_type::uvec4_type
:
1517 glsl_type::vec4_type
);
1519 if (native_integers
) {
1520 st_dst_reg temp_dst
= st_dst_reg(temp
);
1521 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1523 if (ir
->operands
[0]->type
->is_boolean() &&
1524 ir
->operands
[1]->as_constant() &&
1525 ir
->operands
[1]->as_constant()->is_one()) {
1526 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1528 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1531 /* Emit 1-3 AND operations to combine the SEQ results. */
1532 switch (ir
->operands
[0]->type
->vector_elements
) {
1536 temp_dst
.writemask
= WRITEMASK_Y
;
1537 temp1
.swizzle
= SWIZZLE_YYYY
;
1538 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1539 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1542 temp_dst
.writemask
= WRITEMASK_X
;
1543 temp1
.swizzle
= SWIZZLE_XXXX
;
1544 temp2
.swizzle
= SWIZZLE_YYYY
;
1545 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1546 temp_dst
.writemask
= WRITEMASK_Y
;
1547 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1548 temp2
.swizzle
= SWIZZLE_WWWW
;
1549 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1552 temp1
.swizzle
= SWIZZLE_XXXX
;
1553 temp2
.swizzle
= SWIZZLE_YYYY
;
1554 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1556 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1558 /* After the dot-product, the value will be an integer on the
1559 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1561 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1563 /* Negating the result of the dot-product gives values on the range
1564 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1565 * This is achieved using SGE.
1567 st_src_reg sge_src
= result_src
;
1568 sge_src
.negate
= ~sge_src
.negate
;
1569 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1572 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1575 case ir_binop_any_nequal
:
1576 /* "!=" operator producing a scalar boolean. */
1577 if (ir
->operands
[0]->type
->is_vector() ||
1578 ir
->operands
[1]->type
->is_vector()) {
1579 st_src_reg temp
= get_temp(native_integers
?
1580 glsl_type::uvec4_type
:
1581 glsl_type::vec4_type
);
1582 if (ir
->operands
[0]->type
->is_boolean() &&
1583 ir
->operands
[1]->as_constant() &&
1584 ir
->operands
[1]->as_constant()->is_zero()) {
1585 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1587 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1590 if (native_integers
) {
1591 st_dst_reg temp_dst
= st_dst_reg(temp
);
1592 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1594 /* Emit 1-3 OR operations to combine the SNE results. */
1595 switch (ir
->operands
[0]->type
->vector_elements
) {
1599 temp_dst
.writemask
= WRITEMASK_Y
;
1600 temp1
.swizzle
= SWIZZLE_YYYY
;
1601 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1602 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1605 temp_dst
.writemask
= WRITEMASK_X
;
1606 temp1
.swizzle
= SWIZZLE_XXXX
;
1607 temp2
.swizzle
= SWIZZLE_YYYY
;
1608 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1609 temp_dst
.writemask
= WRITEMASK_Y
;
1610 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1611 temp2
.swizzle
= SWIZZLE_WWWW
;
1612 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1615 temp1
.swizzle
= SWIZZLE_XXXX
;
1616 temp2
.swizzle
= SWIZZLE_YYYY
;
1617 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1619 /* After the dot-product, the value will be an integer on the
1620 * range [0,4]. Zero stays zero, and positive values become 1.0.
1622 glsl_to_tgsi_instruction
*const dp
=
1623 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1624 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1625 /* The clamping to [0,1] can be done for free in the fragment
1626 * shader with a saturate.
1628 dp
->saturate
= true;
1630 /* Negating the result of the dot-product gives values on the range
1631 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1632 * achieved using SLT.
1634 st_src_reg slt_src
= result_src
;
1635 slt_src
.negate
= ~slt_src
.negate
;
1636 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1640 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1644 case ir_binop_logic_xor
:
1645 if (native_integers
)
1646 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1648 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1651 case ir_binop_logic_or
: {
1652 if (native_integers
) {
1653 /* If integers are used as booleans, we can use an actual "or"
1656 assert(native_integers
);
1657 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1659 /* After the addition, the value will be an integer on the
1660 * range [0,2]. Zero stays zero, and positive values become 1.0.
1662 glsl_to_tgsi_instruction
*add
=
1663 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1664 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1665 /* The clamping to [0,1] can be done for free in the fragment
1666 * shader with a saturate if floats are being used as boolean values.
1668 add
->saturate
= true;
1670 /* Negating the result of the addition gives values on the range
1671 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1672 * is achieved using SLT.
1674 st_src_reg slt_src
= result_src
;
1675 slt_src
.negate
= ~slt_src
.negate
;
1676 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1682 case ir_binop_logic_and
:
1683 /* If native integers are disabled, the bool args are stored as float 0.0
1684 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1685 * actual AND opcode.
1687 if (native_integers
)
1688 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1690 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1694 assert(ir
->operands
[0]->type
->is_vector());
1695 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1696 emit_dp(ir
, result_dst
, op
[0], op
[1],
1697 ir
->operands
[0]->type
->vector_elements
);
1702 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1704 /* This is the only instruction sequence that makes the game "Risen"
1705 * render correctly. ABS is not required for the game, but since GLSL
1706 * declares negative values as "undefined", allowing us to do whatever
1707 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1710 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1711 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1715 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1718 if (native_integers
) {
1719 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1722 /* fallthrough to next case otherwise */
1724 if (native_integers
) {
1725 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1728 /* fallthrough to next case otherwise */
1731 case ir_unop_i642u64
:
1732 case ir_unop_u642i64
:
1733 /* Converting between signed and unsigned integers is a no-op. */
1735 result_src
.type
= result_dst
.type
;
1738 if (native_integers
) {
1739 /* Booleans are stored as integers using ~0 for true and 0 for false.
1740 * GLSL requires that int(bool) return 1 for true and 0 for false.
1741 * This conversion is done with AND, but it could be done with NEG.
1743 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1745 /* Booleans and integers are both stored as floats when native
1746 * integers are disabled.
1752 if (native_integers
)
1753 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1755 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1758 if (native_integers
)
1759 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1761 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1763 case ir_unop_bitcast_f2i
:
1764 case ir_unop_bitcast_f2u
:
1765 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1766 if (op
[0].negate
|| op
[0].abs
)
1767 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1770 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1773 case ir_unop_bitcast_i2f
:
1774 case ir_unop_bitcast_u2f
:
1776 result_src
.type
= GLSL_TYPE_FLOAT
;
1779 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1782 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1785 if (native_integers
)
1786 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1788 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1790 case ir_unop_bitcast_u642d
:
1791 case ir_unop_bitcast_i642d
:
1793 result_src
.type
= GLSL_TYPE_DOUBLE
;
1795 case ir_unop_bitcast_d2i64
:
1797 result_src
.type
= GLSL_TYPE_INT64
;
1799 case ir_unop_bitcast_d2u64
:
1801 result_src
.type
= GLSL_TYPE_UINT64
;
1804 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1807 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1810 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1812 case ir_unop_round_even
:
1813 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1816 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1820 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1823 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1826 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1829 case ir_unop_bit_not
:
1830 if (native_integers
) {
1831 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1835 if (native_integers
) {
1836 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1839 case ir_binop_lshift
:
1840 case ir_binop_rshift
:
1841 if (native_integers
) {
1842 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
1846 if (glsl_base_type_is_64bit(op
[0].type
)) {
1847 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1850 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
1851 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1856 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1859 case ir_binop_bit_and
:
1860 if (native_integers
) {
1861 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1864 case ir_binop_bit_xor
:
1865 if (native_integers
) {
1866 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1869 case ir_binop_bit_or
:
1870 if (native_integers
) {
1871 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1875 assert(!"GLSL 1.30 features unsupported");
1878 case ir_binop_ubo_load
: {
1879 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1880 ir_rvalue
*block
= ir
->operands
[0];
1881 ir_rvalue
*offset
= ir
->operands
[1];
1882 ir_constant
*const_block
= block
->as_constant();
1884 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1885 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1886 ir
->type
->base_type
);
1888 cbuf
.has_index2
= true;
1891 block
->accept(this);
1892 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1893 *cbuf
.reladdr
= this->result
;
1894 emit_arl(ir
, sampler_reladdr
, this->result
);
1897 /* Calculate the surface offset */
1898 offset
->accept(this);
1899 st_src_reg off
= this->result
;
1901 glsl_to_tgsi_instruction
*inst
=
1902 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1904 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1905 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1906 st_src_reg_for_int(0));
1908 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1911 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1912 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1913 unsigned const_offset
= const_offset_ir
?
1914 const_offset_ir
->value
.u
[0] : 0;
1915 unsigned const_block
= const_uniform_block
?
1916 const_uniform_block
->value
.u
[0] + 1 : 1;
1917 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1920 cbuf
.type
= ir
->type
->base_type
;
1921 cbuf
.file
= PROGRAM_CONSTANT
;
1923 cbuf
.reladdr
= NULL
;
1926 cbuf
.index2D
= const_block
;
1928 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1930 if (const_offset_ir
) {
1931 /* Constant index into constant buffer */
1932 cbuf
.reladdr
= NULL
;
1933 cbuf
.index
= const_offset
/ 16;
1935 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
1936 st_src_reg offset
= op
[1];
1938 /* The OpenGL spec is written in such a way that accesses with
1939 * non-constant offset are almost always vec4-aligned. The only
1940 * exception to this are members of structs in arrays of structs:
1941 * each struct in an array of structs is at least vec4-aligned,
1942 * but single-element and [ui]vec2 members of the struct may be at
1943 * an offset that is not a multiple of 16 bytes.
1945 * Here, we extract that offset, relying on previous passes to
1946 * always generate offset expressions of the form
1947 * (+ expr constant_offset).
1949 * Note that the std430 layout, which allows more cases of
1950 * alignment less than vec4 in arrays, is not supported for
1951 * uniform blocks, so we do not have to deal with it here.
1953 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
1954 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
1955 if (const_offset_ir
) {
1956 const_offset
= const_offset_ir
->value
.u
[0];
1957 cbuf
.index
= const_offset
/ 16;
1958 offset_expr
->operands
[0]->accept(this);
1959 offset
= this->result
;
1963 /* Relative/variable index into constant buffer */
1964 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
1965 st_src_reg_for_int(4));
1966 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1967 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
1970 if (const_uniform_block
) {
1971 /* Constant constant buffer */
1972 cbuf
.reladdr2
= NULL
;
1974 /* Relative/variable constant buffer */
1975 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
1976 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
1978 cbuf
.has_index2
= true;
1980 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1981 if (glsl_base_type_is_64bit(cbuf
.type
))
1982 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
1983 const_offset
% 16 / 8,
1984 const_offset
% 16 / 8,
1985 const_offset
% 16 / 8);
1987 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
1988 const_offset
% 16 / 4,
1989 const_offset
% 16 / 4,
1990 const_offset
% 16 / 4);
1992 if (ir
->type
->is_boolean()) {
1993 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
1994 st_src_reg_for_int(0));
1996 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2002 /* note: we have to reorder the three args here */
2003 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2006 if (this->ctx
->Const
.NativeIntegers
)
2007 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2009 op
[0].negate
= ~op
[0].negate
;
2010 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2013 case ir_triop_bitfield_extract
:
2014 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2016 case ir_quadop_bitfield_insert
:
2017 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2019 case ir_unop_bitfield_reverse
:
2020 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2022 case ir_unop_bit_count
:
2023 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2025 case ir_unop_find_msb
:
2026 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2028 case ir_unop_find_lsb
:
2029 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2031 case ir_binop_imul_high
:
2032 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2035 /* In theory, MAD is incorrect here. */
2037 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2039 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2041 case ir_unop_interpolate_at_centroid
:
2042 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2044 case ir_binop_interpolate_at_offset
: {
2045 /* The y coordinate needs to be flipped for the default fb */
2046 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2047 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2049 unsigned transform_y_index
=
2050 _mesa_add_state_reference(this->prog
->Parameters
,
2053 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2055 glsl_type::vec4_type
);
2056 transform_y
.swizzle
= SWIZZLE_XXXX
;
2058 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2059 st_dst_reg temp_dst
= st_dst_reg(temp
);
2061 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2062 temp_dst
.writemask
= WRITEMASK_Y
;
2063 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2064 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2067 case ir_binop_interpolate_at_sample
:
2068 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2072 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2075 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2078 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2081 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2084 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2087 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2089 case ir_unop_unpack_double_2x32
:
2090 case ir_unop_pack_double_2x32
:
2091 case ir_unop_unpack_int_2x32
:
2092 case ir_unop_pack_int_2x32
:
2093 case ir_unop_unpack_uint_2x32
:
2094 case ir_unop_pack_uint_2x32
:
2095 case ir_unop_unpack_sampler_2x32
:
2096 case ir_unop_pack_sampler_2x32
:
2097 case ir_unop_unpack_image_2x32
:
2098 case ir_unop_pack_image_2x32
:
2099 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2102 case ir_binop_ldexp
:
2103 if (ir
->operands
[0]->type
->is_double()) {
2104 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2105 } else if (ir
->operands
[0]->type
->is_float()) {
2106 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2108 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2112 case ir_unop_pack_half_2x16
:
2113 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2115 case ir_unop_unpack_half_2x16
:
2116 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2119 case ir_unop_get_buffer_size
: {
2120 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2123 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2124 (const_offset
? const_offset
->value
.u
[0] : 0),
2126 if (!const_offset
) {
2127 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2128 *buffer
.reladdr
= op
[0];
2129 emit_arl(ir
, sampler_reladdr
, op
[0]);
2131 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2137 case ir_unop_b2i64
: {
2138 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2139 st_dst_reg temp_dst
= st_dst_reg(temp
);
2140 unsigned orig_swz
= op
[0].swizzle
;
2142 * To convert unsigned to 64-bit:
2143 * zero Y channel, copy X channel.
2145 temp_dst
.writemask
= WRITEMASK_Y
;
2146 if (vector_elements
> 1)
2147 temp_dst
.writemask
|= WRITEMASK_W
;
2148 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2149 temp_dst
.writemask
= WRITEMASK_X
;
2150 if (vector_elements
> 1)
2151 temp_dst
.writemask
|= WRITEMASK_Z
;
2152 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2153 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2154 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2155 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2157 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2159 result_src
.type
= GLSL_TYPE_UINT64
;
2160 if (vector_elements
> 2) {
2161 /* Subtle: We rely on the fact that get_temp here returns the next
2162 * TGSI temporary register directly after the temp register used for
2163 * the first two components, so that the result gets picked up
2166 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2167 st_dst_reg temp_dst
= st_dst_reg(temp
);
2168 temp_dst
.writemask
= WRITEMASK_Y
;
2169 if (vector_elements
> 3)
2170 temp_dst
.writemask
|= WRITEMASK_W
;
2171 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2173 temp_dst
.writemask
= WRITEMASK_X
;
2174 if (vector_elements
> 3)
2175 temp_dst
.writemask
|= WRITEMASK_Z
;
2176 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2177 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2178 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2179 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2181 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2188 case ir_unop_i642u
: {
2189 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2190 st_dst_reg temp_dst
= st_dst_reg(temp
);
2191 unsigned orig_swz
= op
[0].swizzle
;
2192 unsigned orig_idx
= op
[0].index
;
2194 temp_dst
.writemask
= WRITEMASK_X
;
2196 for (el
= 0; el
< vector_elements
; el
++) {
2197 unsigned swz
= GET_SWZ(orig_swz
, el
);
2199 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2201 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2203 op
[0].index
= orig_idx
+ 1;
2204 op
[0].type
= GLSL_TYPE_UINT
;
2205 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2206 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2209 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2210 result_src
.type
= GLSL_TYPE_UINT
;
2212 result_src
.type
= GLSL_TYPE_INT
;
2216 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int64(0));
2219 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2222 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2225 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2228 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2231 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2234 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2237 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2240 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2243 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2246 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2248 /* these might be needed */
2249 case ir_unop_pack_snorm_2x16
:
2250 case ir_unop_pack_unorm_2x16
:
2251 case ir_unop_pack_snorm_4x8
:
2252 case ir_unop_pack_unorm_4x8
:
2254 case ir_unop_unpack_snorm_2x16
:
2255 case ir_unop_unpack_unorm_2x16
:
2256 case ir_unop_unpack_snorm_4x8
:
2257 case ir_unop_unpack_unorm_4x8
:
2259 case ir_quadop_vector
:
2260 case ir_binop_vector_extract
:
2261 case ir_triop_vector_insert
:
2262 case ir_binop_carry
:
2263 case ir_binop_borrow
:
2264 case ir_unop_ssbo_unsized_array_length
:
2265 /* This operation is not supported, or should have already been handled.
2267 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2271 this->result
= result_src
;
2276 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2282 /* Note that this is only swizzles in expressions, not those on the left
2283 * hand side of an assignment, which do write masking. See ir_assignment
2287 ir
->val
->accept(this);
2289 assert(src
.file
!= PROGRAM_UNDEFINED
);
2290 assert(ir
->type
->vector_elements
> 0);
2292 for (i
= 0; i
< 4; i
++) {
2293 if (i
< ir
->type
->vector_elements
) {
2296 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2299 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2302 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2305 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2309 /* If the type is smaller than a vec4, replicate the last
2312 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2316 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2321 /* Test if the variable is an array. Note that geometry and
2322 * tessellation shader inputs are outputs are always arrays (except
2323 * for patch inputs), so only the array element type is considered.
2326 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2328 const glsl_type
*type
= var
->type
;
2330 *remove_array
= false;
2332 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2333 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2336 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2337 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2338 stage
== MESA_SHADER_TESS_CTRL
) &&
2340 if (!var
->type
->is_array())
2341 return false; /* a system value probably */
2343 type
= var
->type
->fields
.array
;
2344 *remove_array
= true;
2347 return type
->is_array() || type
->is_matrix();
2351 st_translate_interp_loc(ir_variable
*var
)
2353 if (var
->data
.centroid
)
2354 return TGSI_INTERPOLATE_LOC_CENTROID
;
2355 else if (var
->data
.sample
)
2356 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2358 return TGSI_INTERPOLATE_LOC_CENTER
;
2362 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2364 variable_storage
*entry
= find_variable_storage(ir
->var
);
2365 ir_variable
*var
= ir
->var
;
2369 switch (var
->data
.mode
) {
2370 case ir_var_uniform
:
2371 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2372 var
->data
.param_index
);
2373 _mesa_hash_table_insert(this->variables
, var
, entry
);
2375 case ir_var_shader_in
: {
2376 /* The linker assigns locations for varyings and attributes,
2377 * including deprecated builtins (like gl_Color), user-assign
2378 * generic attributes (glBindVertexLocation), and
2379 * user-defined varyings.
2381 assert(var
->data
.location
!= -1);
2383 const glsl_type
*type_without_array
= var
->type
->without_array();
2384 struct inout_decl
*decl
= &inputs
[num_inputs
];
2385 unsigned component
= var
->data
.location_frac
;
2386 unsigned num_components
;
2389 if (type_without_array
->is_64bit())
2390 component
= component
/ 2;
2391 if (type_without_array
->vector_elements
)
2392 num_components
= type_without_array
->vector_elements
;
2396 decl
->mesa_index
= var
->data
.location
;
2397 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2398 decl
->interp_loc
= st_translate_interp_loc(var
);
2399 decl
->base_type
= type_without_array
->base_type
;
2400 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2402 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2403 decl
->array_id
= num_input_arrays
+ 1;
2410 decl
->size
= type_size(var
->type
->fields
.array
);
2412 decl
->size
= type_size(var
->type
);
2414 entry
= new(mem_ctx
) variable_storage(var
,
2418 entry
->component
= component
;
2420 _mesa_hash_table_insert(this->variables
, var
, entry
);
2424 case ir_var_shader_out
: {
2425 assert(var
->data
.location
!= -1);
2427 const glsl_type
*type_without_array
= var
->type
->without_array();
2428 struct inout_decl
*decl
= &outputs
[num_outputs
];
2429 unsigned component
= var
->data
.location_frac
;
2430 unsigned num_components
;
2433 if (type_without_array
->is_64bit())
2434 component
= component
/ 2;
2435 if (type_without_array
->vector_elements
)
2436 num_components
= type_without_array
->vector_elements
;
2440 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2441 decl
->base_type
= type_without_array
->base_type
;
2442 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2443 if (var
->data
.stream
& (1u << 31)) {
2444 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2446 assert(var
->data
.stream
< 4);
2447 decl
->gs_out_streams
= 0;
2448 for (unsigned i
= 0; i
< num_components
; ++i
)
2449 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2452 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2453 decl
->array_id
= num_output_arrays
+ 1;
2454 num_output_arrays
++;
2460 decl
->size
= type_size(var
->type
->fields
.array
);
2462 decl
->size
= type_size(var
->type
);
2464 if (var
->data
.fb_fetch_output
) {
2465 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2466 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2467 var
->type
, component
, decl
->array_id
);
2468 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2469 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2472 entry
= new(mem_ctx
) variable_storage(var
,
2477 entry
->component
= component
;
2479 _mesa_hash_table_insert(this->variables
, var
, entry
);
2483 case ir_var_system_value
:
2484 entry
= new(mem_ctx
) variable_storage(var
,
2485 PROGRAM_SYSTEM_VALUE
,
2486 var
->data
.location
);
2489 case ir_var_temporary
:
2490 st_src_reg src
= get_temp(var
->type
);
2492 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2494 _mesa_hash_table_insert(this->variables
, var
, entry
);
2500 printf("Failed to make storage for %s\n", var
->name
);
2505 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2506 entry
->component
, entry
->array_id
);
2507 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2508 var
->data
.mode
== ir_var_shader_in
&&
2509 var
->type
->without_array()->is_double())
2510 this->result
.is_double_vertex_input
= true;
2511 if (!native_integers
)
2512 this->result
.type
= GLSL_TYPE_FLOAT
;
2516 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2517 GLbitfield64
* usage_mask
,
2518 GLbitfield64 double_usage_mask
,
2519 GLbitfield
* patch_usage_mask
)
2524 /* Fix array declarations by removing unused array elements at both ends
2525 * of the arrays. For example, mat4[3] where only mat[1] is used.
2527 for (i
= 0; i
< count
; i
++) {
2528 struct inout_decl
*decl
= &decls
[i
];
2529 if (!decl
->array_id
)
2532 /* Shrink the beginning. */
2533 for (j
= 0; j
< (int)decl
->size
; j
++) {
2534 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2535 if (*patch_usage_mask
&
2536 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2540 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2542 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2551 /* Shrink the end. */
2552 for (j
= decl
->size
-1; j
>= 0; j
--) {
2553 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2554 if (*patch_usage_mask
&
2555 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2559 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2561 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2568 /* When not all entries of an array are accessed, we mark them as used
2569 * here anyway, to ensure that the input/output mapping logic doesn't get
2572 * TODO This happens when an array isn't used via indirect access, which
2573 * some game ports do (at least eON-based). There is an optimization
2574 * opportunity here by replacing the array declaration with non-array
2575 * declarations of those slots that are actually used.
2577 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2578 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2579 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2581 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2587 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2592 ir_variable
*var
= ir
->variable_referenced();
2594 /* We only need the logic provided by st_glsl_storage_type_size()
2595 * for arrays of structs. Indirect sampler and image indexing is handled
2598 int element_size
= ir
->type
->without_array()->is_record() ?
2599 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2600 type_size(ir
->type
);
2602 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2604 ir
->array
->accept(this);
2607 if (!src
.has_index2
) {
2608 switch (this->prog
->Target
) {
2609 case GL_TESS_CONTROL_PROGRAM_NV
:
2610 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2611 !ir
->variable_referenced()->data
.patch
;
2613 case GL_TESS_EVALUATION_PROGRAM_NV
:
2614 is_2D
= src
.file
== PROGRAM_INPUT
&&
2615 !ir
->variable_referenced()->data
.patch
;
2617 case GL_GEOMETRY_PROGRAM_NV
:
2618 is_2D
= src
.file
== PROGRAM_INPUT
;
2628 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2629 src
.file
== PROGRAM_INPUT
)
2630 element_size
= attrib_type_size(ir
->type
, true);
2632 src
.index2D
= index
->value
.i
[0];
2633 src
.has_index2
= true;
2635 src
.index
+= index
->value
.i
[0] * element_size
;
2637 /* Variable index array dereference. It eats the "vec4" of the
2638 * base of the array and an index that offsets the TGSI register
2641 ir
->array_index
->accept(this);
2643 st_src_reg index_reg
;
2645 if (element_size
== 1) {
2646 index_reg
= this->result
;
2648 index_reg
= get_temp(native_integers
?
2649 glsl_type::int_type
: glsl_type::float_type
);
2651 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2652 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2655 /* If there was already a relative address register involved, add the
2656 * new and the old together to get the new offset.
2658 if (!is_2D
&& src
.reladdr
!= NULL
) {
2659 st_src_reg accum_reg
= get_temp(native_integers
?
2660 glsl_type::int_type
: glsl_type::float_type
);
2662 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2663 index_reg
, *src
.reladdr
);
2665 index_reg
= accum_reg
;
2669 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2670 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2672 src
.has_index2
= true;
2674 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2675 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2679 /* Change the register type to the element type of the array. */
2680 src
.type
= ir
->type
->base_type
;
2686 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2689 const glsl_type
*struct_type
= ir
->record
->type
;
2690 ir_variable
*var
= ir
->record
->variable_referenced();
2693 ir
->record
->accept(this);
2695 assert(ir
->field_idx
>= 0);
2697 for (i
= 0; i
< struct_type
->length
; i
++) {
2698 if (i
== (unsigned) ir
->field_idx
)
2700 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2701 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2704 /* If the type is smaller than a vec4, replicate the last channel out. */
2705 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2706 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2708 this->result
.swizzle
= SWIZZLE_NOOP
;
2710 this->result
.index
+= offset
;
2711 this->result
.type
= ir
->type
->base_type
;
2715 * We want to be careful in assignment setup to hit the actual storage
2716 * instead of potentially using a temporary like we might with the
2717 * ir_dereference handler.
2720 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2722 /* The LHS must be a dereference. If the LHS is a variable indexed array
2723 * access of a vector, it must be separated into a series conditional moves
2724 * before reaching this point (see ir_vec_index_to_cond_assign).
2726 assert(ir
->as_dereference());
2727 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2729 assert(!deref_array
->array
->type
->is_vector());
2732 /* Use the rvalue deref handler for the most part. We write swizzles using
2733 * the writemask, but we do extract the base component for enhanced layouts
2734 * from the source swizzle.
2737 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2738 return st_dst_reg(v
->result
);
2742 * Process the condition of a conditional assignment
2744 * Examines the condition of a conditional assignment to generate the optimal
2745 * first operand of a \c CMP instruction. If the condition is a relational
2746 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2747 * used as the source for the \c CMP instruction. Otherwise the comparison
2748 * is processed to a boolean result, and the boolean result is used as the
2749 * operand to the CMP instruction.
2752 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2754 ir_rvalue
*src_ir
= ir
;
2756 bool switch_order
= false;
2758 ir_expression
*const expr
= ir
->as_expression();
2760 if (native_integers
) {
2761 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2762 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2763 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2764 type
== GLSL_TYPE_BOOL
) {
2765 if (expr
->operation
== ir_binop_equal
) {
2766 if (expr
->operands
[0]->is_zero()) {
2767 src_ir
= expr
->operands
[1];
2768 switch_order
= true;
2770 else if (expr
->operands
[1]->is_zero()) {
2771 src_ir
= expr
->operands
[0];
2772 switch_order
= true;
2775 else if (expr
->operation
== ir_binop_nequal
) {
2776 if (expr
->operands
[0]->is_zero()) {
2777 src_ir
= expr
->operands
[1];
2779 else if (expr
->operands
[1]->is_zero()) {
2780 src_ir
= expr
->operands
[0];
2786 src_ir
->accept(this);
2787 return switch_order
;
2790 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2791 bool zero_on_left
= false;
2793 if (expr
->operands
[0]->is_zero()) {
2794 src_ir
= expr
->operands
[1];
2795 zero_on_left
= true;
2796 } else if (expr
->operands
[1]->is_zero()) {
2797 src_ir
= expr
->operands
[0];
2798 zero_on_left
= false;
2802 * (a < 0) T F F ( a < 0) T F F
2803 * (0 < a) F F T (-a < 0) F F T
2804 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2805 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2807 * Note that exchanging the order of 0 and 'a' in the comparison simply
2808 * means that the value of 'a' should be negated.
2811 switch (expr
->operation
) {
2813 switch_order
= false;
2814 negate
= zero_on_left
;
2817 case ir_binop_gequal
:
2818 switch_order
= true;
2819 negate
= zero_on_left
;
2823 /* This isn't the right kind of comparison afterall, so make sure
2824 * the whole condition is visited.
2832 src_ir
->accept(this);
2834 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2835 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2836 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2837 * computing the condition.
2840 this->result
.negate
= ~this->result
.negate
;
2842 return switch_order
;
2846 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2847 st_dst_reg
*l
, st_src_reg
*r
,
2848 st_src_reg
*cond
, bool cond_swap
)
2850 if (type
->is_record()) {
2851 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2852 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2858 if (type
->is_array()) {
2859 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2860 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2865 if (type
->is_matrix()) {
2866 const struct glsl_type
*vec_type
;
2868 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2869 type
->vector_elements
, 1);
2871 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2872 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2877 assert(type
->is_scalar() || type
->is_vector());
2879 l
->type
= type
->base_type
;
2880 r
->type
= type
->base_type
;
2882 st_src_reg l_src
= st_src_reg(*l
);
2884 if (l_src
.file
== PROGRAM_OUTPUT
&&
2885 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
2886 (l_src
.index
== FRAG_RESULT_DEPTH
|| l_src
.index
== FRAG_RESULT_STENCIL
)) {
2887 /* This is a special case because the source swizzles will be shifted
2888 * later to account for the difference between GLSL (where they're
2889 * plain floats) and TGSI (where they're Z and Y components). */
2890 l_src
.swizzle
= SWIZZLE_XXXX
;
2893 if (native_integers
) {
2894 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2895 cond_swap
? l_src
: *r
,
2896 cond_swap
? *r
: l_src
);
2898 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2899 cond_swap
? l_src
: *r
,
2900 cond_swap
? *r
: l_src
);
2903 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2907 if (type
->is_dual_slot()) {
2909 if (r
->is_double_vertex_input
== false)
2915 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2921 /* all generated instructions need to be flaged as precise */
2922 this->precise
= is_precise(ir
->lhs
->variable_referenced());
2923 ir
->rhs
->accept(this);
2926 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2930 int first_enabled_chan
= 0;
2932 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2934 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2935 variable
->data
.mode
== ir_var_shader_out
&&
2936 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2937 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2938 assert(ir
->lhs
->type
->is_scalar());
2939 assert(ir
->write_mask
== WRITEMASK_X
);
2941 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2942 l
.writemask
= WRITEMASK_Z
;
2944 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2945 l
.writemask
= WRITEMASK_Y
;
2947 } else if (ir
->write_mask
== 0) {
2948 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2950 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2953 l
.writemask
= u_bit_consecutive(0, num_elements
);
2955 /* The type is a struct or an array of (array of) structs. */
2956 l
.writemask
= WRITEMASK_XYZW
;
2959 l
.writemask
= ir
->write_mask
;
2962 for (int i
= 0; i
< 4; i
++) {
2963 if (l
.writemask
& (1 << i
)) {
2964 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2969 l
.writemask
= l
.writemask
<< dst_component
;
2971 /* Swizzle a small RHS vector into the channels being written.
2973 * glsl ir treats write_mask as dictating how many channels are
2974 * present on the RHS while TGSI treats write_mask as just
2975 * showing which channels of the vec4 RHS get written.
2977 for (int i
= 0; i
< 4; i
++) {
2978 if (l
.writemask
& (1 << i
))
2979 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2981 swizzles
[i
] = first_enabled_chan
;
2983 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2984 swizzles
[2], swizzles
[3]);
2987 assert(l
.file
!= PROGRAM_UNDEFINED
);
2988 assert(r
.file
!= PROGRAM_UNDEFINED
);
2990 if (ir
->condition
) {
2991 const bool switch_order
= this->process_move_condition(ir
->condition
);
2992 st_src_reg condition
= this->result
;
2994 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2995 } else if (ir
->rhs
->as_expression() &&
2996 this->instructions
.get_tail() &&
2997 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2998 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
2999 type_size(ir
->lhs
->type
) == 1 &&
3000 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3001 /* To avoid emitting an extra MOV when assigning an expression to a
3002 * variable, emit the last instruction of the expression again, but
3003 * replace the destination register with the target of the assignment.
3004 * Dead code elimination will remove the original instruction.
3006 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3007 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3008 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3009 new_inst
->saturate
= inst
->saturate
;
3010 new_inst
->resource
= inst
->resource
;
3011 inst
->dead_mask
= inst
->dst
[0].writemask
;
3013 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3020 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3023 GLdouble stack_vals
[4] = { 0 };
3024 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3025 GLenum gl_type
= GL_NONE
;
3027 static int in_array
= 0;
3028 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3030 /* Unfortunately, 4 floats is all we can get into
3031 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3032 * aggregate constant and move each constant value into it. If we
3033 * get lucky, copy propagation will eliminate the extra moves.
3035 if (ir
->type
->is_record()) {
3036 st_src_reg temp_base
= get_temp(ir
->type
);
3037 st_dst_reg temp
= st_dst_reg(temp_base
);
3039 for (i
= 0; i
< ir
->type
->length
; i
++) {
3040 ir_constant
*const field_value
= ir
->get_record_field(i
);
3041 int size
= type_size(field_value
->type
);
3045 field_value
->accept(this);
3048 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3049 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3055 this->result
= temp_base
;
3059 if (ir
->type
->is_array()) {
3060 st_src_reg temp_base
= get_temp(ir
->type
);
3061 st_dst_reg temp
= st_dst_reg(temp_base
);
3062 int size
= type_size(ir
->type
->fields
.array
);
3067 for (i
= 0; i
< ir
->type
->length
; i
++) {
3068 ir
->const_elements
[i
]->accept(this);
3070 for (int j
= 0; j
< size
; j
++) {
3071 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3077 this->result
= temp_base
;
3082 if (ir
->type
->is_matrix()) {
3083 st_src_reg mat
= get_temp(ir
->type
);
3084 st_dst_reg mat_column
= st_dst_reg(mat
);
3086 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3087 switch (ir
->type
->base_type
) {
3088 case GLSL_TYPE_FLOAT
:
3089 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3091 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3092 src
.index
= add_constant(file
,
3094 ir
->type
->vector_elements
,
3097 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3099 case GLSL_TYPE_DOUBLE
:
3100 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3101 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3102 src
.index
= add_constant(file
,
3104 ir
->type
->vector_elements
,
3107 if (ir
->type
->vector_elements
>= 2) {
3108 mat_column
.writemask
= WRITEMASK_XY
;
3109 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3110 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3112 mat_column
.writemask
= WRITEMASK_X
;
3113 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3114 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3117 if (ir
->type
->vector_elements
> 2) {
3118 if (ir
->type
->vector_elements
== 4) {
3119 mat_column
.writemask
= WRITEMASK_ZW
;
3120 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3121 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3123 mat_column
.writemask
= WRITEMASK_Z
;
3124 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3125 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3126 mat_column
.writemask
= WRITEMASK_XYZW
;
3127 src
.swizzle
= SWIZZLE_XYZW
;
3133 unreachable("Illegal matrix constant type.\n");
3142 switch (ir
->type
->base_type
) {
3143 case GLSL_TYPE_FLOAT
:
3145 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3146 values
[i
].f
= ir
->value
.f
[i
];
3149 case GLSL_TYPE_DOUBLE
:
3150 gl_type
= GL_DOUBLE
;
3151 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3152 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3155 case GLSL_TYPE_INT64
:
3156 gl_type
= GL_INT64_ARB
;
3157 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3158 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3161 case GLSL_TYPE_UINT64
:
3162 gl_type
= GL_UNSIGNED_INT64_ARB
;
3163 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3164 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3167 case GLSL_TYPE_UINT
:
3168 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3169 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3170 if (native_integers
)
3171 values
[i
].u
= ir
->value
.u
[i
];
3173 values
[i
].f
= ir
->value
.u
[i
];
3177 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3178 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3179 if (native_integers
)
3180 values
[i
].i
= ir
->value
.i
[i
];
3182 values
[i
].f
= ir
->value
.i
[i
];
3185 case GLSL_TYPE_BOOL
:
3186 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3187 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3188 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3192 assert(!"Non-float/uint/int/bool constant");
3195 this->result
= st_src_reg(file
, -1, ir
->type
);
3196 this->result
.index
= add_constant(file
,
3198 ir
->type
->vector_elements
,
3200 &this->result
.swizzle
);
3204 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3206 exec_node
*param
= ir
->actual_parameters
.get_head();
3207 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3208 ir_variable
*location
= deref
->variable_referenced();
3211 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3213 /* Calculate the surface offset */
3215 unsigned array_size
= 0, base
= 0;
3218 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3220 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3221 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3222 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3223 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3224 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3226 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3229 ir
->return_deref
->accept(this);
3230 st_dst_reg
dst(this->result
);
3231 dst
.writemask
= WRITEMASK_X
;
3233 glsl_to_tgsi_instruction
*inst
;
3235 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3236 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3237 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3238 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3239 st_src_reg_for_int(1));
3240 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3241 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3242 st_src_reg_for_int(-1));
3243 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3245 param
= param
->get_next();
3246 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3249 st_src_reg data
= this->result
, data2
= undef_src
;
3251 switch (ir
->callee
->intrinsic_id
) {
3252 case ir_intrinsic_atomic_counter_add
:
3253 opcode
= TGSI_OPCODE_ATOMUADD
;
3255 case ir_intrinsic_atomic_counter_min
:
3256 opcode
= TGSI_OPCODE_ATOMIMIN
;
3258 case ir_intrinsic_atomic_counter_max
:
3259 opcode
= TGSI_OPCODE_ATOMIMAX
;
3261 case ir_intrinsic_atomic_counter_and
:
3262 opcode
= TGSI_OPCODE_ATOMAND
;
3264 case ir_intrinsic_atomic_counter_or
:
3265 opcode
= TGSI_OPCODE_ATOMOR
;
3267 case ir_intrinsic_atomic_counter_xor
:
3268 opcode
= TGSI_OPCODE_ATOMXOR
;
3270 case ir_intrinsic_atomic_counter_exchange
:
3271 opcode
= TGSI_OPCODE_ATOMXCHG
;
3273 case ir_intrinsic_atomic_counter_comp_swap
: {
3274 opcode
= TGSI_OPCODE_ATOMCAS
;
3275 param
= param
->get_next();
3276 val
= ((ir_instruction
*)param
)->as_rvalue();
3278 data2
= this->result
;
3282 assert(!"Unexpected intrinsic");
3286 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3289 inst
->resource
= buffer
;
3293 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3295 exec_node
*param
= ir
->actual_parameters
.get_head();
3297 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3299 param
= param
->get_next();
3300 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3302 ir_constant
*const_block
= block
->as_constant();
3306 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3307 (const_block
? const_block
->value
.u
[0] : 0),
3311 block
->accept(this);
3312 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3313 *buffer
.reladdr
= this->result
;
3314 emit_arl(ir
, sampler_reladdr
, this->result
);
3317 /* Calculate the surface offset */
3318 offset
->accept(this);
3319 st_src_reg off
= this->result
;
3321 st_dst_reg dst
= undef_dst
;
3322 if (ir
->return_deref
) {
3323 ir
->return_deref
->accept(this);
3324 dst
= st_dst_reg(this->result
);
3325 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3328 glsl_to_tgsi_instruction
*inst
;
3330 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3331 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3332 if (dst
.type
== GLSL_TYPE_BOOL
)
3333 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3334 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3335 param
= param
->get_next();
3336 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3339 param
= param
->get_next();
3340 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3342 dst
.writemask
= write_mask
->value
.u
[0];
3344 dst
.type
= this->result
.type
;
3345 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3347 param
= param
->get_next();
3348 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3351 st_src_reg data
= this->result
, data2
= undef_src
;
3353 switch (ir
->callee
->intrinsic_id
) {
3354 case ir_intrinsic_ssbo_atomic_add
:
3355 opcode
= TGSI_OPCODE_ATOMUADD
;
3357 case ir_intrinsic_ssbo_atomic_min
:
3358 opcode
= TGSI_OPCODE_ATOMIMIN
;
3360 case ir_intrinsic_ssbo_atomic_max
:
3361 opcode
= TGSI_OPCODE_ATOMIMAX
;
3363 case ir_intrinsic_ssbo_atomic_and
:
3364 opcode
= TGSI_OPCODE_ATOMAND
;
3366 case ir_intrinsic_ssbo_atomic_or
:
3367 opcode
= TGSI_OPCODE_ATOMOR
;
3369 case ir_intrinsic_ssbo_atomic_xor
:
3370 opcode
= TGSI_OPCODE_ATOMXOR
;
3372 case ir_intrinsic_ssbo_atomic_exchange
:
3373 opcode
= TGSI_OPCODE_ATOMXCHG
;
3375 case ir_intrinsic_ssbo_atomic_comp_swap
:
3376 opcode
= TGSI_OPCODE_ATOMCAS
;
3377 param
= param
->get_next();
3378 val
= ((ir_instruction
*)param
)->as_rvalue();
3380 data2
= this->result
;
3383 assert(!"Unexpected intrinsic");
3387 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3390 param
= param
->get_next();
3391 ir_constant
*access
= NULL
;
3392 if (!param
->is_tail_sentinel()) {
3393 access
= ((ir_instruction
*)param
)->as_constant();
3397 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3401 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3403 switch (ir
->callee
->intrinsic_id
) {
3404 case ir_intrinsic_memory_barrier
:
3405 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3406 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3407 TGSI_MEMBAR_ATOMIC_BUFFER
|
3408 TGSI_MEMBAR_SHADER_IMAGE
|
3409 TGSI_MEMBAR_SHARED
));
3411 case ir_intrinsic_memory_barrier_atomic_counter
:
3412 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3413 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3415 case ir_intrinsic_memory_barrier_buffer
:
3416 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3417 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3419 case ir_intrinsic_memory_barrier_image
:
3420 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3421 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3423 case ir_intrinsic_memory_barrier_shared
:
3424 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3425 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3427 case ir_intrinsic_group_memory_barrier
:
3428 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3429 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3430 TGSI_MEMBAR_ATOMIC_BUFFER
|
3431 TGSI_MEMBAR_SHADER_IMAGE
|
3432 TGSI_MEMBAR_SHARED
|
3433 TGSI_MEMBAR_THREAD_GROUP
));
3436 assert(!"Unexpected memory barrier intrinsic");
3441 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3443 exec_node
*param
= ir
->actual_parameters
.get_head();
3445 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3447 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3449 /* Calculate the surface offset */
3450 offset
->accept(this);
3451 st_src_reg off
= this->result
;
3453 st_dst_reg dst
= undef_dst
;
3454 if (ir
->return_deref
) {
3455 ir
->return_deref
->accept(this);
3456 dst
= st_dst_reg(this->result
);
3457 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3460 glsl_to_tgsi_instruction
*inst
;
3462 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3463 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3464 inst
->resource
= buffer
;
3465 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3466 param
= param
->get_next();
3467 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3470 param
= param
->get_next();
3471 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3473 dst
.writemask
= write_mask
->value
.u
[0];
3475 dst
.type
= this->result
.type
;
3476 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3477 inst
->resource
= buffer
;
3479 param
= param
->get_next();
3480 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3483 st_src_reg data
= this->result
, data2
= undef_src
;
3485 switch (ir
->callee
->intrinsic_id
) {
3486 case ir_intrinsic_shared_atomic_add
:
3487 opcode
= TGSI_OPCODE_ATOMUADD
;
3489 case ir_intrinsic_shared_atomic_min
:
3490 opcode
= TGSI_OPCODE_ATOMIMIN
;
3492 case ir_intrinsic_shared_atomic_max
:
3493 opcode
= TGSI_OPCODE_ATOMIMAX
;
3495 case ir_intrinsic_shared_atomic_and
:
3496 opcode
= TGSI_OPCODE_ATOMAND
;
3498 case ir_intrinsic_shared_atomic_or
:
3499 opcode
= TGSI_OPCODE_ATOMOR
;
3501 case ir_intrinsic_shared_atomic_xor
:
3502 opcode
= TGSI_OPCODE_ATOMXOR
;
3504 case ir_intrinsic_shared_atomic_exchange
:
3505 opcode
= TGSI_OPCODE_ATOMXCHG
;
3507 case ir_intrinsic_shared_atomic_comp_swap
:
3508 opcode
= TGSI_OPCODE_ATOMCAS
;
3509 param
= param
->get_next();
3510 val
= ((ir_instruction
*)param
)->as_rvalue();
3512 data2
= this->result
;
3515 assert(!"Unexpected intrinsic");
3519 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3520 inst
->resource
= buffer
;
3525 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3526 bool *memory_coherent
, bool *memory_volatile
,
3527 bool *memory_restrict
, unsigned *image_format
)
3530 switch (ir
->ir_type
) {
3531 case ir_type_dereference_record
: {
3532 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3533 const glsl_type
*struct_type
= deref_record
->record
->type
;
3534 int fild_idx
= deref_record
->field_idx
;
3536 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3538 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3540 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3542 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3544 struct_type
->fields
.structure
[fild_idx
].image_format
;
3548 case ir_type_dereference_array
: {
3549 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3550 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3551 memory_coherent
, memory_volatile
, memory_restrict
,
3556 case ir_type_dereference_variable
: {
3557 ir_variable
*var
= ir
->variable_referenced();
3559 *type
= var
->type
->without_array();
3560 *memory_coherent
= var
->data
.memory_coherent
;
3561 *memory_volatile
= var
->data
.memory_volatile
;
3562 *memory_restrict
= var
->data
.memory_restrict
;
3563 *image_format
= var
->data
.image_format
;
3573 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3575 exec_node
*param
= ir
->actual_parameters
.get_head();
3577 ir_dereference
*img
= (ir_dereference
*)param
;
3578 const ir_variable
*imgvar
= img
->variable_referenced();
3579 unsigned sampler_array_size
= 1, sampler_base
= 0;
3580 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3581 unsigned image_format
= 0;
3582 const glsl_type
*type
= NULL
;
3584 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3585 &memory_restrict
, &image_format
);
3588 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3590 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3591 &index
, &reladdr
, !imgvar
->contains_bindless());
3593 image
.index
= index
;
3594 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3595 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3596 *image
.reladdr
= reladdr
;
3597 emit_arl(ir
, sampler_reladdr
, reladdr
);
3600 st_dst_reg dst
= undef_dst
;
3601 if (ir
->return_deref
) {
3602 ir
->return_deref
->accept(this);
3603 dst
= st_dst_reg(this->result
);
3604 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3607 glsl_to_tgsi_instruction
*inst
;
3609 st_src_reg bindless
;
3610 if (imgvar
->contains_bindless()) {
3612 bindless
= this->result
;
3615 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3616 dst
.writemask
= WRITEMASK_XYZ
;
3617 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3618 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3619 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3620 st_dst_reg dstres
= st_dst_reg(res
);
3621 dstres
.writemask
= WRITEMASK_W
;
3622 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3623 res
.swizzle
= SWIZZLE_WWWW
;
3624 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3626 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3628 st_dst_reg coord_dst
;
3629 coord
= get_temp(glsl_type::ivec4_type
);
3630 coord_dst
= st_dst_reg(coord
);
3631 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3632 param
= param
->get_next();
3633 ((ir_dereference
*)param
)->accept(this);
3634 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3635 coord
.swizzle
= SWIZZLE_XXXX
;
3636 switch (type
->coordinate_components()) {
3637 case 4: assert(!"unexpected coord count");
3639 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3641 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3644 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3645 param
= param
->get_next();
3646 ((ir_dereference
*)param
)->accept(this);
3647 st_src_reg sample
= this->result
;
3648 sample
.swizzle
= SWIZZLE_XXXX
;
3649 coord_dst
.writemask
= WRITEMASK_W
;
3650 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3651 coord
.swizzle
|= SWIZZLE_W
<< 9;
3654 param
= param
->get_next();
3655 if (!param
->is_tail_sentinel()) {
3656 ((ir_dereference
*)param
)->accept(this);
3657 arg1
= this->result
;
3658 param
= param
->get_next();
3661 if (!param
->is_tail_sentinel()) {
3662 ((ir_dereference
*)param
)->accept(this);
3663 arg2
= this->result
;
3664 param
= param
->get_next();
3667 assert(param
->is_tail_sentinel());
3670 switch (ir
->callee
->intrinsic_id
) {
3671 case ir_intrinsic_image_load
:
3672 opcode
= TGSI_OPCODE_LOAD
;
3674 case ir_intrinsic_image_store
:
3675 opcode
= TGSI_OPCODE_STORE
;
3677 case ir_intrinsic_image_atomic_add
:
3678 opcode
= TGSI_OPCODE_ATOMUADD
;
3680 case ir_intrinsic_image_atomic_min
:
3681 opcode
= TGSI_OPCODE_ATOMIMIN
;
3683 case ir_intrinsic_image_atomic_max
:
3684 opcode
= TGSI_OPCODE_ATOMIMAX
;
3686 case ir_intrinsic_image_atomic_and
:
3687 opcode
= TGSI_OPCODE_ATOMAND
;
3689 case ir_intrinsic_image_atomic_or
:
3690 opcode
= TGSI_OPCODE_ATOMOR
;
3692 case ir_intrinsic_image_atomic_xor
:
3693 opcode
= TGSI_OPCODE_ATOMXOR
;
3695 case ir_intrinsic_image_atomic_exchange
:
3696 opcode
= TGSI_OPCODE_ATOMXCHG
;
3698 case ir_intrinsic_image_atomic_comp_swap
:
3699 opcode
= TGSI_OPCODE_ATOMCAS
;
3702 assert(!"Unexpected intrinsic");
3706 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3707 if (opcode
== TGSI_OPCODE_STORE
)
3708 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3711 if (imgvar
->contains_bindless()) {
3712 inst
->resource
= bindless
;
3713 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3714 SWIZZLE_X
, SWIZZLE_Y
);
3716 inst
->resource
= image
;
3717 inst
->sampler_array_size
= sampler_array_size
;
3718 inst
->sampler_base
= sampler_base
;
3721 inst
->tex_target
= type
->sampler_index();
3722 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3723 _mesa_get_shader_image_format(image_format
));
3725 if (memory_coherent
)
3726 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3727 if (memory_restrict
)
3728 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3729 if (memory_volatile
)
3730 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3734 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3736 ir
->return_deref
->accept(this);
3737 st_dst_reg dst
= st_dst_reg(this->result
);
3739 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3741 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3742 unsigned num_src
= 0;
3743 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3744 assert(num_src
< ARRAY_SIZE(src
));
3746 this->result
.file
= PROGRAM_UNDEFINED
;
3747 param
->accept(this);
3748 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3750 src
[num_src
] = this->result
;
3754 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3758 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3760 ir_function_signature
*sig
= ir
->callee
;
3762 /* Filter out intrinsics */
3763 switch (sig
->intrinsic_id
) {
3764 case ir_intrinsic_atomic_counter_read
:
3765 case ir_intrinsic_atomic_counter_increment
:
3766 case ir_intrinsic_atomic_counter_predecrement
:
3767 case ir_intrinsic_atomic_counter_add
:
3768 case ir_intrinsic_atomic_counter_min
:
3769 case ir_intrinsic_atomic_counter_max
:
3770 case ir_intrinsic_atomic_counter_and
:
3771 case ir_intrinsic_atomic_counter_or
:
3772 case ir_intrinsic_atomic_counter_xor
:
3773 case ir_intrinsic_atomic_counter_exchange
:
3774 case ir_intrinsic_atomic_counter_comp_swap
:
3775 visit_atomic_counter_intrinsic(ir
);
3778 case ir_intrinsic_ssbo_load
:
3779 case ir_intrinsic_ssbo_store
:
3780 case ir_intrinsic_ssbo_atomic_add
:
3781 case ir_intrinsic_ssbo_atomic_min
:
3782 case ir_intrinsic_ssbo_atomic_max
:
3783 case ir_intrinsic_ssbo_atomic_and
:
3784 case ir_intrinsic_ssbo_atomic_or
:
3785 case ir_intrinsic_ssbo_atomic_xor
:
3786 case ir_intrinsic_ssbo_atomic_exchange
:
3787 case ir_intrinsic_ssbo_atomic_comp_swap
:
3788 visit_ssbo_intrinsic(ir
);
3791 case ir_intrinsic_memory_barrier
:
3792 case ir_intrinsic_memory_barrier_atomic_counter
:
3793 case ir_intrinsic_memory_barrier_buffer
:
3794 case ir_intrinsic_memory_barrier_image
:
3795 case ir_intrinsic_memory_barrier_shared
:
3796 case ir_intrinsic_group_memory_barrier
:
3797 visit_membar_intrinsic(ir
);
3800 case ir_intrinsic_shared_load
:
3801 case ir_intrinsic_shared_store
:
3802 case ir_intrinsic_shared_atomic_add
:
3803 case ir_intrinsic_shared_atomic_min
:
3804 case ir_intrinsic_shared_atomic_max
:
3805 case ir_intrinsic_shared_atomic_and
:
3806 case ir_intrinsic_shared_atomic_or
:
3807 case ir_intrinsic_shared_atomic_xor
:
3808 case ir_intrinsic_shared_atomic_exchange
:
3809 case ir_intrinsic_shared_atomic_comp_swap
:
3810 visit_shared_intrinsic(ir
);
3813 case ir_intrinsic_image_load
:
3814 case ir_intrinsic_image_store
:
3815 case ir_intrinsic_image_atomic_add
:
3816 case ir_intrinsic_image_atomic_min
:
3817 case ir_intrinsic_image_atomic_max
:
3818 case ir_intrinsic_image_atomic_and
:
3819 case ir_intrinsic_image_atomic_or
:
3820 case ir_intrinsic_image_atomic_xor
:
3821 case ir_intrinsic_image_atomic_exchange
:
3822 case ir_intrinsic_image_atomic_comp_swap
:
3823 case ir_intrinsic_image_size
:
3824 case ir_intrinsic_image_samples
:
3825 visit_image_intrinsic(ir
);
3828 case ir_intrinsic_shader_clock
:
3829 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3832 case ir_intrinsic_vote_all
:
3833 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3835 case ir_intrinsic_vote_any
:
3836 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3838 case ir_intrinsic_vote_eq
:
3839 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3841 case ir_intrinsic_ballot
:
3842 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3844 case ir_intrinsic_read_first_invocation
:
3845 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
3847 case ir_intrinsic_read_invocation
:
3848 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
3851 case ir_intrinsic_invalid
:
3852 case ir_intrinsic_generic_load
:
3853 case ir_intrinsic_generic_store
:
3854 case ir_intrinsic_generic_atomic_add
:
3855 case ir_intrinsic_generic_atomic_and
:
3856 case ir_intrinsic_generic_atomic_or
:
3857 case ir_intrinsic_generic_atomic_xor
:
3858 case ir_intrinsic_generic_atomic_min
:
3859 case ir_intrinsic_generic_atomic_max
:
3860 case ir_intrinsic_generic_atomic_exchange
:
3861 case ir_intrinsic_generic_atomic_comp_swap
:
3862 unreachable("Invalid intrinsic");
3867 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3868 unsigned *array_elements
,
3870 st_src_reg
*indirect
,
3873 switch (tail
->ir_type
) {
3874 case ir_type_dereference_record
: {
3875 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3876 const glsl_type
*struct_type
= deref_record
->record
->type
;
3877 int field_index
= deref_record
->field_idx
;
3879 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3881 assert(field_index
>= 0);
3882 *location
+= struct_type
->record_location_offset(field_index
);
3886 case ir_type_dereference_array
: {
3887 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3889 void *mem_ctx
= ralloc_parent(deref_arr
);
3890 ir_constant
*array_index
=
3891 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
3894 st_src_reg temp_reg
;
3895 st_dst_reg temp_dst
;
3897 temp_reg
= get_temp(glsl_type::uint_type
);
3898 temp_dst
= st_dst_reg(temp_reg
);
3899 temp_dst
.writemask
= 1;
3901 deref_arr
->array_index
->accept(this);
3902 if (*array_elements
!= 1)
3903 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3905 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3907 if (indirect
->file
== PROGRAM_UNDEFINED
)
3908 *indirect
= temp_reg
;
3910 temp_dst
= st_dst_reg(*indirect
);
3911 temp_dst
.writemask
= 1;
3912 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3915 *index
+= array_index
->value
.u
[0] * *array_elements
;
3917 *array_elements
*= deref_arr
->array
->type
->length
;
3919 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3928 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3929 unsigned *array_size
,
3932 st_src_reg
*reladdr
,
3935 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3936 unsigned location
= 0;
3937 ir_variable
*var
= ir
->variable_referenced();
3939 memset(reladdr
, 0, sizeof(*reladdr
));
3940 reladdr
->file
= PROGRAM_UNDEFINED
;
3946 location
= var
->data
.location
;
3947 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3950 * If we end up with no indirect then adjust the base to the index,
3951 * and set the array size to 1.
3953 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3959 assert(location
!= 0xffffffff);
3960 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3961 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3966 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3968 if (offset
.reladdr
|| offset
.reladdr2
) {
3969 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3970 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3971 tmp_dst
.writemask
= WRITEMASK_XY
;
3972 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
3980 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3982 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3983 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3984 st_src_reg levels_src
, reladdr
;
3985 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3986 glsl_to_tgsi_instruction
*inst
= NULL
;
3987 unsigned opcode
= TGSI_OPCODE_NOP
;
3988 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3989 unsigned sampler_array_size
= 1, sampler_base
= 0;
3990 bool is_cube_array
= false, is_cube_shadow
= false;
3991 ir_variable
*var
= ir
->sampler
->variable_referenced();
3994 /* if we are a cube array sampler or a cube shadow */
3995 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3996 is_cube_array
= sampler_type
->sampler_array
;
3997 is_cube_shadow
= sampler_type
->sampler_shadow
;
4000 if (ir
->coordinate
) {
4001 ir
->coordinate
->accept(this);
4003 /* Put our coords in a temp. We'll need to modify them for shadow,
4004 * projection, or LOD, so the only case we'd use it as-is is if
4005 * we're doing plain old texturing. The optimization passes on
4006 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4008 coord
= get_temp(glsl_type::vec4_type
);
4009 coord_dst
= st_dst_reg(coord
);
4010 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4011 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4014 if (ir
->projector
) {
4015 ir
->projector
->accept(this);
4016 projector
= this->result
;
4019 /* Storage for our result. Ideally for an assignment we'd be using
4020 * the actual storage for the result here, instead.
4022 result_src
= get_temp(ir
->type
);
4023 result_dst
= st_dst_reg(result_src
);
4024 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4028 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4030 ir
->offset
->accept(this);
4031 offset
[0] = this->result
;
4035 if (is_cube_array
|| is_cube_shadow
) {
4036 opcode
= TGSI_OPCODE_TXB2
;
4039 opcode
= TGSI_OPCODE_TXB
;
4041 ir
->lod_info
.bias
->accept(this);
4042 lod_info
= this->result
;
4044 ir
->offset
->accept(this);
4045 offset
[0] = this->result
;
4049 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4050 opcode
= TGSI_OPCODE_TEX_LZ
;
4052 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4053 ir
->lod_info
.lod
->accept(this);
4054 lod_info
= this->result
;
4057 ir
->offset
->accept(this);
4058 offset
[0] = this->result
;
4062 opcode
= TGSI_OPCODE_TXD
;
4063 ir
->lod_info
.grad
.dPdx
->accept(this);
4065 ir
->lod_info
.grad
.dPdy
->accept(this);
4068 ir
->offset
->accept(this);
4069 offset
[0] = this->result
;
4073 opcode
= TGSI_OPCODE_TXQ
;
4074 ir
->lod_info
.lod
->accept(this);
4075 lod_info
= this->result
;
4077 case ir_query_levels
:
4078 opcode
= TGSI_OPCODE_TXQ
;
4079 lod_info
= undef_src
;
4080 levels_src
= get_temp(ir
->type
);
4083 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4084 opcode
= TGSI_OPCODE_TXF_LZ
;
4086 opcode
= TGSI_OPCODE_TXF
;
4087 ir
->lod_info
.lod
->accept(this);
4088 lod_info
= this->result
;
4091 ir
->offset
->accept(this);
4092 offset
[0] = this->result
;
4096 opcode
= TGSI_OPCODE_TXF
;
4097 ir
->lod_info
.sample_index
->accept(this);
4098 sample_index
= this->result
;
4101 opcode
= TGSI_OPCODE_TG4
;
4102 ir
->lod_info
.component
->accept(this);
4103 component
= this->result
;
4105 ir
->offset
->accept(this);
4106 if (ir
->offset
->type
->is_array()) {
4107 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4108 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4109 offset
[i
] = this->result
;
4110 offset
[i
].index
+= i
* type_size(elt_type
);
4111 offset
[i
].type
= elt_type
->base_type
;
4112 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4113 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4116 offset
[0] = canonicalize_gather_offset(this->result
);
4121 opcode
= TGSI_OPCODE_LODQ
;
4123 case ir_texture_samples
:
4124 opcode
= TGSI_OPCODE_TXQS
;
4126 case ir_samples_identical
:
4127 unreachable("Unexpected ir_samples_identical opcode");
4130 if (ir
->projector
) {
4131 if (opcode
== TGSI_OPCODE_TEX
) {
4132 /* Slot the projector in as the last component of the coord. */
4133 coord_dst
.writemask
= WRITEMASK_W
;
4134 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4135 coord_dst
.writemask
= WRITEMASK_XYZW
;
4136 opcode
= TGSI_OPCODE_TXP
;
4138 st_src_reg coord_w
= coord
;
4139 coord_w
.swizzle
= SWIZZLE_WWWW
;
4141 /* For the other TEX opcodes there's no projective version
4142 * since the last slot is taken up by LOD info. Do the
4143 * projective divide now.
4145 coord_dst
.writemask
= WRITEMASK_W
;
4146 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4148 /* In the case where we have to project the coordinates "by hand,"
4149 * the shadow comparator value must also be projected.
4151 st_src_reg tmp_src
= coord
;
4152 if (ir
->shadow_comparator
) {
4153 /* Slot the shadow value in as the second to last component of the
4156 ir
->shadow_comparator
->accept(this);
4158 tmp_src
= get_temp(glsl_type::vec4_type
);
4159 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4161 /* Projective division not allowed for array samplers. */
4162 assert(!sampler_type
->sampler_array
);
4164 tmp_dst
.writemask
= WRITEMASK_Z
;
4165 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4167 tmp_dst
.writemask
= WRITEMASK_XY
;
4168 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4171 coord_dst
.writemask
= WRITEMASK_XYZ
;
4172 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4174 coord_dst
.writemask
= WRITEMASK_XYZW
;
4175 coord
.swizzle
= SWIZZLE_XYZW
;
4179 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4180 * comparator was put in the correct place (and projected) by the code,
4181 * above, that handles by-hand projection.
4183 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4184 /* Slot the shadow value in as the second to last component of the
4187 ir
->shadow_comparator
->accept(this);
4189 if (is_cube_array
) {
4190 cube_sc
= get_temp(glsl_type::float_type
);
4191 cube_sc_dst
= st_dst_reg(cube_sc
);
4192 cube_sc_dst
.writemask
= WRITEMASK_X
;
4193 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4194 cube_sc_dst
.writemask
= WRITEMASK_X
;
4197 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4198 sampler_type
->sampler_array
) ||
4199 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4200 coord_dst
.writemask
= WRITEMASK_W
;
4202 coord_dst
.writemask
= WRITEMASK_Z
;
4204 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4205 coord_dst
.writemask
= WRITEMASK_XYZW
;
4209 if (ir
->op
== ir_txf_ms
) {
4210 coord_dst
.writemask
= WRITEMASK_W
;
4211 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4212 coord_dst
.writemask
= WRITEMASK_XYZW
;
4213 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4214 opcode
== TGSI_OPCODE_TXF
) {
4215 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4216 coord_dst
.writemask
= WRITEMASK_W
;
4217 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4218 coord_dst
.writemask
= WRITEMASK_XYZW
;
4221 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4224 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4225 &index
, &reladdr
, !var
->contains_bindless());
4227 sampler
.index
= index
;
4228 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4229 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4230 *sampler
.reladdr
= reladdr
;
4231 emit_arl(ir
, sampler_reladdr
, reladdr
);
4234 st_src_reg bindless
;
4235 if (var
->contains_bindless()) {
4236 ir
->sampler
->accept(this);
4237 bindless
= this->result
;
4240 if (opcode
== TGSI_OPCODE_TXD
)
4241 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4242 else if (opcode
== TGSI_OPCODE_TXQ
) {
4243 if (ir
->op
== ir_query_levels
) {
4244 /* the level is stored in W */
4245 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4246 result_dst
.writemask
= WRITEMASK_X
;
4247 levels_src
.swizzle
= SWIZZLE_WWWW
;
4248 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4250 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4251 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4252 inst
= emit_asm(ir
, opcode
, result_dst
);
4253 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4254 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4255 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4256 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4257 } else if (opcode
== TGSI_OPCODE_TG4
) {
4258 if (is_cube_array
&& ir
->shadow_comparator
) {
4259 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4261 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4264 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4266 if (ir
->shadow_comparator
)
4267 inst
->tex_shadow
= GL_TRUE
;
4269 if (var
->contains_bindless()) {
4270 inst
->resource
= bindless
;
4271 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4272 SWIZZLE_X
, SWIZZLE_Y
);
4274 inst
->resource
= sampler
;
4275 inst
->sampler_array_size
= sampler_array_size
;
4276 inst
->sampler_base
= sampler_base
;
4280 if (!inst
->tex_offsets
)
4281 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4283 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4284 inst
->tex_offsets
[i
] = offset
[i
];
4285 inst
->tex_offset_num_offset
= i
;
4288 inst
->tex_target
= sampler_type
->sampler_index();
4289 inst
->tex_type
= ir
->type
->base_type
;
4291 this->result
= result_src
;
4295 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4297 assert(!ir
->get_value());
4299 emit_asm(ir
, TGSI_OPCODE_RET
);
4303 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4305 if (ir
->condition
) {
4306 ir
->condition
->accept(this);
4307 st_src_reg condition
= this->result
;
4309 /* Convert the bool condition to a float so we can negate. */
4310 if (native_integers
) {
4311 st_src_reg temp
= get_temp(ir
->condition
->type
);
4312 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4313 condition
, st_src_reg_for_float(1.0));
4317 condition
.negate
= ~condition
.negate
;
4318 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4320 /* unconditional kil */
4321 emit_asm(ir
, TGSI_OPCODE_KILL
);
4326 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4329 glsl_to_tgsi_instruction
*if_inst
;
4331 ir
->condition
->accept(this);
4332 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4334 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4336 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4338 this->instructions
.push_tail(if_inst
);
4340 visit_exec_list(&ir
->then_instructions
, this);
4342 if (!ir
->else_instructions
.is_empty()) {
4343 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4344 visit_exec_list(&ir
->else_instructions
, this);
4347 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4352 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4354 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4356 ir
->stream
->accept(this);
4357 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4361 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4363 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4365 ir
->stream
->accept(this);
4366 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4370 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4372 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4373 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4375 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4378 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4380 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4382 result
.file
= PROGRAM_UNDEFINED
;
4389 num_input_arrays
= 0;
4390 num_output_arrays
= 0;
4392 num_address_regs
= 0;
4395 indirect_addr_consts
= false;
4396 wpos_transform_const
= -1;
4397 native_integers
= false;
4398 mem_ctx
= ralloc_context(NULL
);
4402 shader_program
= NULL
;
4407 use_shared_memory
= false;
4408 has_tex_txf_lz
= false;
4412 static void var_destroy(struct hash_entry
*entry
)
4414 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4419 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4421 _mesa_hash_table_destroy(variables
, var_destroy
);
4423 ralloc_free(mem_ctx
);
4426 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4433 * Count resources used by the given gpu program (number of texture
4437 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4439 v
->samplers_used
= 0;
4441 prog
->info
.textures_used_by_txf
= 0;
4443 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4444 if (inst
->info
->is_tex
) {
4445 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4446 unsigned idx
= inst
->sampler_base
+ i
;
4447 v
->samplers_used
|= 1u << idx
;
4449 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4450 v
->sampler_types
[idx
] = inst
->tex_type
;
4451 v
->sampler_targets
[idx
] =
4452 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4454 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4455 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4460 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4461 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4463 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4464 is_resource_instruction(inst
->op
) ||
4465 inst
->op
== TGSI_OPCODE_STORE
)) {
4466 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4467 v
->use_shared_memory
= true;
4468 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4469 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4470 unsigned idx
= inst
->sampler_base
+ i
;
4471 v
->images_used
|= 1 << idx
;
4472 v
->image_targets
[idx
] =
4473 st_translate_texture_target(inst
->tex_target
, false);
4474 v
->image_formats
[idx
] = inst
->image_format
;
4479 prog
->SamplersUsed
= v
->samplers_used
;
4481 if (v
->shader_program
!= NULL
)
4482 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4486 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4487 * are read from the given src in this instruction
4490 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4492 int read_mask
= 0, comp
;
4494 /* Now, given the src swizzle and the written channels, find which
4495 * components are actually read
4497 for (comp
= 0; comp
< 4; ++comp
) {
4498 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4500 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4501 read_mask
|= 1 << coord
;
4508 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4509 * instruction is the first instruction to write to register T0. There are
4510 * several lowering passes done in GLSL IR (e.g. branches and
4511 * relative addressing) that create a large number of conditional assignments
4512 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4514 * Here is why this conversion is safe:
4515 * CMP T0, T1 T2 T0 can be expanded to:
4521 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4522 * as the original program. If (T1 < 0.0) evaluates to false, executing
4523 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4524 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4525 * because any instruction that was going to read from T0 after this was going
4526 * to read a garbage value anyway.
4529 glsl_to_tgsi_visitor::simplify_cmp(void)
4531 int tempWritesSize
= 0;
4532 unsigned *tempWrites
= NULL
;
4533 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4535 memset(outputWrites
, 0, sizeof(outputWrites
));
4537 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4538 unsigned prevWriteMask
= 0;
4540 /* Give up if we encounter relative addressing or flow control. */
4541 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4542 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4543 inst
->info
->is_branch
||
4544 inst
->op
== TGSI_OPCODE_CONT
||
4545 inst
->op
== TGSI_OPCODE_END
||
4546 inst
->op
== TGSI_OPCODE_RET
) {
4550 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4551 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4552 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4553 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4554 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4555 if (inst
->dst
[0].index
>= tempWritesSize
) {
4556 const int inc
= 4096;
4558 tempWrites
= (unsigned*)
4560 (tempWritesSize
+ inc
) * sizeof(unsigned));
4564 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4565 tempWritesSize
+= inc
;
4568 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4569 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4573 /* For a CMP to be considered a conditional write, the destination
4574 * register and source register two must be the same. */
4575 if (inst
->op
== TGSI_OPCODE_CMP
4576 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4577 && inst
->src
[2].file
== inst
->dst
[0].file
4578 && inst
->src
[2].index
== inst
->dst
[0].index
4579 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4581 inst
->op
= TGSI_OPCODE_MOV
;
4582 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4583 inst
->src
[0] = inst
->src
[1];
4591 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4593 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4594 int old_idx
= src
->index
;
4595 if (renames
[old_idx
].valid
)
4596 src
->index
= renames
[old_idx
].new_reg
;
4600 /* Replaces all references to a temporary register index with another index. */
4602 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4604 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4606 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4607 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4608 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4609 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4612 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4613 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4614 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4615 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4618 rename_temp_handle_src(renames
, &inst
->resource
);
4619 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4620 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4622 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4623 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4624 int old_idx
= inst
->dst
[j
].index
;
4625 if (renames
[old_idx
].valid
)
4626 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4628 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4629 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4635 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4637 int depth
= 0; /* loop depth */
4638 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4641 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4642 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4643 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4644 if (first_writes
[inst
->dst
[j
].index
] == -1)
4645 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4649 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4652 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4662 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4664 int depth
= 0; /* loop depth */
4665 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4668 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4669 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4670 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4671 if (first_reads
[inst
->src
[j
].index
] == -1)
4672 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4675 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4676 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4677 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4678 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4681 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4684 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4694 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4696 int depth
= 0; /* loop depth */
4697 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4700 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4701 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4702 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4703 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4705 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4706 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4707 if (first_writes
[inst
->dst
[j
].index
] == -1)
4708 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4709 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4712 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4713 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4714 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4716 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4719 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4722 for (k
= 0; k
< this->next_temp
; k
++) {
4723 if (last_reads
[k
] == -2) {
4735 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4737 int depth
= 0; /* loop depth */
4741 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4742 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4743 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4744 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4747 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4749 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4751 for (k
= 0; k
< this->next_temp
; k
++) {
4752 if (last_writes
[k
] == -2) {
4763 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4764 * channels for copy propagation and updates following instructions to
4765 * use the original versions.
4767 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4768 * will occur. As an example, a TXP production before this pass:
4770 * 0: MOV TEMP[1], INPUT[4].xyyy;
4771 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4772 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4776 * 0: MOV TEMP[1], INPUT[4].xyyy;
4777 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4778 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4780 * which allows for dead code elimination on TEMP[1]'s writes.
4783 glsl_to_tgsi_visitor::copy_propagate(void)
4785 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4786 glsl_to_tgsi_instruction
*,
4787 this->next_temp
* 4);
4788 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4791 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4792 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4793 || inst
->dst
[0].index
< this->next_temp
);
4795 /* First, do any copy propagation possible into the src regs. */
4796 for (int r
= 0; r
< 3; r
++) {
4797 glsl_to_tgsi_instruction
*first
= NULL
;
4799 int acp_base
= inst
->src
[r
].index
* 4;
4801 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4802 inst
->src
[r
].reladdr
||
4803 inst
->src
[r
].reladdr2
)
4806 /* See if we can find entries in the ACP consisting of MOVs
4807 * from the same src register for all the swizzled channels
4808 * of this src register reference.
4810 for (int i
= 0; i
< 4; i
++) {
4811 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4812 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4819 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4824 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4825 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4826 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4827 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4835 /* We've now validated that we can copy-propagate to
4836 * replace this src register reference. Do it.
4838 inst
->src
[r
].file
= first
->src
[0].file
;
4839 inst
->src
[r
].index
= first
->src
[0].index
;
4840 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4841 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4842 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4843 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4846 for (int i
= 0; i
< 4; i
++) {
4847 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4848 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4849 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4851 inst
->src
[r
].swizzle
= swizzle
;
4856 case TGSI_OPCODE_BGNLOOP
:
4857 case TGSI_OPCODE_ENDLOOP
:
4858 /* End of a basic block, clear the ACP entirely. */
4859 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4862 case TGSI_OPCODE_IF
:
4863 case TGSI_OPCODE_UIF
:
4867 case TGSI_OPCODE_ENDIF
:
4868 case TGSI_OPCODE_ELSE
:
4869 /* Clear all channels written inside the block from the ACP, but
4870 * leaving those that were not touched.
4872 for (int r
= 0; r
< this->next_temp
; r
++) {
4873 for (int c
= 0; c
< 4; c
++) {
4874 if (!acp
[4 * r
+ c
])
4877 if (acp_level
[4 * r
+ c
] >= level
)
4878 acp
[4 * r
+ c
] = NULL
;
4881 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4886 /* Continuing the block, clear any written channels from
4889 for (int d
= 0; d
< 2; d
++) {
4890 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4891 /* Any temporary might be written, so no copy propagation
4892 * across this instruction.
4894 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4895 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4896 inst
->dst
[d
].reladdr
) {
4897 /* Any output might be written, so no copy propagation
4898 * from outputs across this instruction.
4900 for (int r
= 0; r
< this->next_temp
; r
++) {
4901 for (int c
= 0; c
< 4; c
++) {
4902 if (!acp
[4 * r
+ c
])
4905 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4906 acp
[4 * r
+ c
] = NULL
;
4909 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4910 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4911 /* Clear where it's used as dst. */
4912 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4913 for (int c
= 0; c
< 4; c
++) {
4914 if (inst
->dst
[d
].writemask
& (1 << c
))
4915 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4919 /* Clear where it's used as src. */
4920 for (int r
= 0; r
< this->next_temp
; r
++) {
4921 for (int c
= 0; c
< 4; c
++) {
4922 if (!acp
[4 * r
+ c
])
4925 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4927 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4928 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4929 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4930 acp
[4 * r
+ c
] = NULL
;
4939 /* If this is a copy, add it to the ACP. */
4940 if (inst
->op
== TGSI_OPCODE_MOV
&&
4941 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4942 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4943 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4944 !inst
->dst
[0].reladdr
&&
4945 !inst
->dst
[0].reladdr2
&&
4947 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4948 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
4949 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
4950 !inst
->src
[0].reladdr
&&
4951 !inst
->src
[0].reladdr2
&&
4952 !inst
->src
[0].negate
&&
4953 !inst
->src
[0].abs
) {
4954 for (int i
= 0; i
< 4; i
++) {
4955 if (inst
->dst
[0].writemask
& (1 << i
)) {
4956 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4957 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4963 ralloc_free(acp_level
);
4968 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
4970 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
4971 /* Clear where it's used as src. */
4972 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
4973 writes
[4 * reladdr
->index
+ swz
] = NULL
;
4978 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4981 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4982 * will occur. As an example, a TXP production after copy propagation but
4985 * 0: MOV TEMP[1], INPUT[4].xyyy;
4986 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4987 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4989 * and after this pass:
4991 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4994 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4996 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4997 glsl_to_tgsi_instruction
*,
4998 this->next_temp
* 4);
4999 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5003 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5004 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5005 || inst
->dst
[0].index
< this->next_temp
);
5008 case TGSI_OPCODE_BGNLOOP
:
5009 case TGSI_OPCODE_ENDLOOP
:
5010 case TGSI_OPCODE_CONT
:
5011 case TGSI_OPCODE_BRK
:
5012 /* End of a basic block, clear the write array entirely.
5014 * This keeps us from killing dead code when the writes are
5015 * on either side of a loop, even when the register isn't touched
5016 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5017 * dead code of this type, so it shouldn't make a difference as long as
5018 * the dead code elimination pass in the GLSL compiler does its job.
5020 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5023 case TGSI_OPCODE_ENDIF
:
5024 case TGSI_OPCODE_ELSE
:
5025 /* Promote the recorded level of all channels written inside the
5026 * preceding if or else block to the level above the if/else block.
5028 for (int r
= 0; r
< this->next_temp
; r
++) {
5029 for (int c
= 0; c
< 4; c
++) {
5030 if (!writes
[4 * r
+ c
])
5033 if (write_level
[4 * r
+ c
] == level
)
5034 write_level
[4 * r
+ c
] = level
-1;
5037 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5041 case TGSI_OPCODE_IF
:
5042 case TGSI_OPCODE_UIF
:
5044 /* fallthrough to default case to mark the condition as read */
5046 /* Continuing the block, clear any channels from the write array that
5047 * are read by this instruction.
5049 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5050 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5051 /* Any temporary might be read, so no dead code elimination
5052 * across this instruction.
5054 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5055 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5056 /* Clear where it's used as src. */
5057 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5058 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5059 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5060 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5062 for (int c
= 0; c
< 4; c
++) {
5063 if (src_chans
& (1 << c
))
5064 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5067 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5068 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5070 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5071 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5072 /* Any temporary might be read, so no dead code elimination
5073 * across this instruction.
5075 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5076 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5077 /* Clear where it's used as src. */
5078 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5079 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5080 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5081 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5083 for (int c
= 0; c
< 4; c
++) {
5084 if (src_chans
& (1 << c
))
5085 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5088 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5089 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5092 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5095 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5096 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5097 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5098 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5100 for (int c
= 0; c
< 4; c
++) {
5101 if (src_chans
& (1 << c
))
5102 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5105 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5106 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5108 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5109 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5110 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5115 /* If this instruction writes to a temporary, add it to the write array.
5116 * If there is already an instruction in the write array for one or more
5117 * of the channels, flag that channel write as dead.
5119 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5120 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5121 !inst
->dst
[i
].reladdr
) {
5122 for (int c
= 0; c
< 4; c
++) {
5123 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5124 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5125 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5128 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5130 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5131 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5138 /* Anything still in the write array at this point is dead code. */
5139 for (int r
= 0; r
< this->next_temp
; r
++) {
5140 for (int c
= 0; c
< 4; c
++) {
5141 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5143 inst
->dead_mask
|= (1 << c
);
5147 /* Now actually remove the instructions that are completely dead and update
5148 * the writemask of other instructions with dead channels.
5150 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5151 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5153 /* No amount of dead masks should remove memory stores */
5154 if (inst
->info
->is_store
)
5157 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5162 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5163 if (inst
->dead_mask
== WRITEMASK_XY
||
5164 inst
->dead_mask
== WRITEMASK_ZW
)
5165 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5167 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5171 ralloc_free(write_level
);
5172 ralloc_free(writes
);
5177 /* merge DFRACEXP instructions into one. */
5179 glsl_to_tgsi_visitor::merge_two_dsts(void)
5181 /* We never delete inst, but we may delete its successor. */
5182 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5183 glsl_to_tgsi_instruction
*inst2
;
5186 if (num_inst_dst_regs(inst
) != 2)
5189 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5190 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5193 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5194 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5196 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5201 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5203 if (inst
->op
== inst2
->op
&&
5204 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5205 inst
->src
[0].file
== inst2
->src
[0].file
&&
5206 inst
->src
[0].index
== inst2
->src
[0].index
&&
5207 inst
->src
[0].type
== inst2
->src
[0].type
&&
5208 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5210 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5214 /* Undefined destinations are not allowed, substitute with an unused
5215 * temporary register.
5217 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5218 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5219 inst
->dst
[defined
^ 1].writemask
= 0;
5223 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5229 /* Merges temporary registers together where possible to reduce the number of
5230 * registers needed to run a program.
5232 * Produces optimal code only after copy propagation and dead code elimination
5235 glsl_to_tgsi_visitor::merge_registers(void)
5238 struct lifetime
*lifetimes
=
5239 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5241 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5242 this->next_temp
, lifetimes
)) {
5243 struct rename_reg_pair
*renames
=
5244 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5245 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5246 rename_temp_registers(renames
);
5247 ralloc_free(renames
);
5250 ralloc_free(lifetimes
);
5253 /* Reassign indices to temporary registers by reusing unused indices created
5254 * by optimization passes. */
5256 glsl_to_tgsi_visitor::renumber_registers(void)
5260 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5261 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5263 for (i
= 0; i
< this->next_temp
; i
++) {
5264 first_writes
[i
] = -1;
5266 get_first_temp_write(first_writes
);
5268 for (i
= 0; i
< this->next_temp
; i
++) {
5269 if (first_writes
[i
] < 0) continue;
5270 if (i
!= new_index
) {
5271 renames
[i
].new_reg
= new_index
;
5272 renames
[i
].valid
= true;
5277 rename_temp_registers(renames
);
5278 this->next_temp
= new_index
;
5279 ralloc_free(renames
);
5280 ralloc_free(first_writes
);
5283 /* ------------------------- TGSI conversion stuff -------------------------- */
5286 * Intermediate state used during shader translation.
5288 struct st_translate
{
5289 struct ureg_program
*ureg
;
5291 unsigned temps_size
;
5292 struct ureg_dst
*temps
;
5294 struct ureg_dst
*arrays
;
5295 unsigned num_temp_arrays
;
5296 struct ureg_src
*constants
;
5298 struct ureg_src
*immediates
;
5300 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5301 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5302 struct ureg_dst address
[3];
5303 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5304 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5305 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5306 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5307 struct ureg_src shared_memory
;
5308 unsigned *array_sizes
;
5309 struct inout_decl
*input_decls
;
5310 unsigned num_input_decls
;
5311 struct inout_decl
*output_decls
;
5312 unsigned num_output_decls
;
5314 const ubyte
*inputMapping
;
5315 const ubyte
*outputMapping
;
5317 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5321 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5323 _mesa_sysval_to_semantic(unsigned sysval
)
5327 case SYSTEM_VALUE_VERTEX_ID
:
5328 return TGSI_SEMANTIC_VERTEXID
;
5329 case SYSTEM_VALUE_INSTANCE_ID
:
5330 return TGSI_SEMANTIC_INSTANCEID
;
5331 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5332 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5333 case SYSTEM_VALUE_BASE_VERTEX
:
5334 return TGSI_SEMANTIC_BASEVERTEX
;
5335 case SYSTEM_VALUE_BASE_INSTANCE
:
5336 return TGSI_SEMANTIC_BASEINSTANCE
;
5337 case SYSTEM_VALUE_DRAW_ID
:
5338 return TGSI_SEMANTIC_DRAWID
;
5340 /* Geometry shader */
5341 case SYSTEM_VALUE_INVOCATION_ID
:
5342 return TGSI_SEMANTIC_INVOCATIONID
;
5344 /* Fragment shader */
5345 case SYSTEM_VALUE_FRAG_COORD
:
5346 return TGSI_SEMANTIC_POSITION
;
5347 case SYSTEM_VALUE_FRONT_FACE
:
5348 return TGSI_SEMANTIC_FACE
;
5349 case SYSTEM_VALUE_SAMPLE_ID
:
5350 return TGSI_SEMANTIC_SAMPLEID
;
5351 case SYSTEM_VALUE_SAMPLE_POS
:
5352 return TGSI_SEMANTIC_SAMPLEPOS
;
5353 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5354 return TGSI_SEMANTIC_SAMPLEMASK
;
5355 case SYSTEM_VALUE_HELPER_INVOCATION
:
5356 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5358 /* Tessellation shader */
5359 case SYSTEM_VALUE_TESS_COORD
:
5360 return TGSI_SEMANTIC_TESSCOORD
;
5361 case SYSTEM_VALUE_VERTICES_IN
:
5362 return TGSI_SEMANTIC_VERTICESIN
;
5363 case SYSTEM_VALUE_PRIMITIVE_ID
:
5364 return TGSI_SEMANTIC_PRIMID
;
5365 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5366 return TGSI_SEMANTIC_TESSOUTER
;
5367 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5368 return TGSI_SEMANTIC_TESSINNER
;
5370 /* Compute shader */
5371 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5372 return TGSI_SEMANTIC_THREAD_ID
;
5373 case SYSTEM_VALUE_WORK_GROUP_ID
:
5374 return TGSI_SEMANTIC_BLOCK_ID
;
5375 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5376 return TGSI_SEMANTIC_GRID_SIZE
;
5377 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5378 return TGSI_SEMANTIC_BLOCK_SIZE
;
5380 /* ARB_shader_ballot */
5381 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5382 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5383 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5384 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5385 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5386 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5387 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5388 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5389 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5390 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5391 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5392 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5393 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5394 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5397 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5398 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5399 case SYSTEM_VALUE_VERTEX_CNT
:
5401 assert(!"Unexpected SYSTEM_VALUE_ enum");
5402 return TGSI_SEMANTIC_COUNT
;
5407 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5409 static struct ureg_src
5410 emit_immediate(struct st_translate
*t
,
5411 gl_constant_value values
[4],
5414 struct ureg_program
*ureg
= t
->ureg
;
5419 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5421 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5423 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5424 case GL_UNSIGNED_INT64_ARB
:
5425 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5427 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5428 case GL_UNSIGNED_INT
:
5430 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5432 assert(!"should not get here - type must be float, int, uint, or bool");
5433 return ureg_src_undef();
5438 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5440 static struct ureg_dst
5441 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5447 case PROGRAM_UNDEFINED
:
5448 return ureg_dst_undef();
5450 case PROGRAM_TEMPORARY
:
5451 /* Allocate space for temporaries on demand. */
5452 if (index
>= t
->temps_size
) {
5453 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5455 t
->temps
= (struct ureg_dst
*)
5457 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5459 return ureg_dst_undef();
5461 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5462 t
->temps_size
+= inc
;
5465 if (ureg_dst_is_undef(t
->temps
[index
]))
5466 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5468 return t
->temps
[index
];
5471 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5472 array
= array_id
- 1;
5474 if (ureg_dst_is_undef(t
->arrays
[array
]))
5475 t
->arrays
[array
] = ureg_DECL_array_temporary(
5476 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5478 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5480 case PROGRAM_OUTPUT
:
5482 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5483 assert(index
< 2 * FRAG_RESULT_MAX
);
5484 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5485 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5486 assert(index
< VARYING_SLOT_TESS_MAX
);
5488 assert(index
< VARYING_SLOT_MAX
);
5490 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5491 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5492 return t
->outputs
[t
->outputMapping
[index
]];
5495 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5496 unsigned mesa_index
= decl
->mesa_index
;
5497 int slot
= t
->outputMapping
[mesa_index
];
5499 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5501 struct ureg_dst dst
= t
->outputs
[slot
];
5502 dst
.ArrayID
= array_id
;
5503 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5506 case PROGRAM_ADDRESS
:
5507 return t
->address
[index
];
5510 assert(!"unknown dst register file");
5511 return ureg_dst_undef();
5515 static struct ureg_src
5516 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5518 static struct ureg_src
5519 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5520 unsigned addr_index
)
5522 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5523 return ureg_src(t
->address
[addr_index
]);
5525 return translate_src(t
, reladdr
);
5529 * Create a TGSI ureg_dst register from an st_dst_reg.
5531 static struct ureg_dst
5532 translate_dst(struct st_translate
*t
,
5533 const st_dst_reg
*dst_reg
,
5536 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5539 if (dst
.File
== TGSI_FILE_NULL
)
5542 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5545 dst
= ureg_saturate(dst
);
5547 if (dst_reg
->reladdr
!= NULL
) {
5548 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5549 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5552 if (dst_reg
->has_index2
) {
5553 if (dst_reg
->reladdr2
)
5554 dst
= ureg_dst_dimension_indirect(dst
,
5555 translate_addr(t
, dst_reg
->reladdr2
, 1),
5558 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5565 * Create a TGSI ureg_src register from an st_src_reg.
5567 static struct ureg_src
5568 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5570 struct ureg_src src
;
5571 int index
= src_reg
->index
;
5572 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5574 switch(src_reg
->file
) {
5575 case PROGRAM_UNDEFINED
:
5576 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5579 case PROGRAM_TEMPORARY
:
5581 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
));
5584 case PROGRAM_OUTPUT
: {
5585 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
);
5586 assert(dst
.WriteMask
!= 0);
5587 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5588 src
= ureg_swizzle(ureg_src(dst
),
5592 MIN2(shift
+ 3, 3));
5596 case PROGRAM_UNIFORM
:
5597 assert(src_reg
->index
>= 0);
5598 src
= src_reg
->index
< t
->num_constants
?
5599 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5601 case PROGRAM_STATE_VAR
:
5602 case PROGRAM_CONSTANT
: /* ie, immediate */
5603 if (src_reg
->has_index2
)
5604 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5606 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5607 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5610 case PROGRAM_IMMEDIATE
:
5611 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5612 src
= t
->immediates
[src_reg
->index
];
5616 /* GLSL inputs are 64-bit containers, so we have to
5617 * map back to the original index and add the offset after
5619 index
-= double_reg2
;
5620 if (!src_reg
->array_id
) {
5621 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5622 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5623 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5626 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
,
5628 unsigned mesa_index
= decl
->mesa_index
;
5629 int slot
= t
->inputMapping
[mesa_index
];
5631 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5633 src
= t
->inputs
[slot
];
5634 src
.ArrayID
= src_reg
->array_id
;
5635 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5639 case PROGRAM_ADDRESS
:
5640 src
= ureg_src(t
->address
[src_reg
->index
]);
5643 case PROGRAM_SYSTEM_VALUE
:
5644 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5645 src
= t
->systemValues
[src_reg
->index
];
5649 assert(!"unknown src register file");
5650 return ureg_src_undef();
5653 if (src_reg
->has_index2
) {
5654 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5655 * and UBO constant buffers (buffer, position).
5657 if (src_reg
->reladdr2
)
5658 src
= ureg_src_dimension_indirect(src
,
5659 translate_addr(t
, src_reg
->reladdr2
, 1),
5662 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5665 src
= ureg_swizzle(src
,
5666 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5667 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5668 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5669 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5672 src
= ureg_abs(src
);
5674 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5675 src
= ureg_negate(src
);
5677 if (src_reg
->reladdr
!= NULL
) {
5678 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5679 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5685 static struct tgsi_texture_offset
5686 translate_tex_offset(struct st_translate
*t
,
5687 const st_src_reg
*in_offset
)
5689 struct tgsi_texture_offset offset
;
5690 struct ureg_src src
= translate_src(t
, in_offset
);
5692 offset
.File
= src
.File
;
5693 offset
.Index
= src
.Index
;
5694 offset
.SwizzleX
= src
.SwizzleX
;
5695 offset
.SwizzleY
= src
.SwizzleY
;
5696 offset
.SwizzleZ
= src
.SwizzleZ
;
5699 assert(!src
.Indirect
);
5700 assert(!src
.DimIndirect
);
5701 assert(!src
.Dimension
);
5702 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5703 assert(!src
.Negate
);
5709 compile_tgsi_instruction(struct st_translate
*t
,
5710 const glsl_to_tgsi_instruction
*inst
)
5712 struct ureg_program
*ureg
= t
->ureg
;
5714 struct ureg_dst dst
[2];
5715 struct ureg_src src
[4];
5716 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5720 unsigned tex_target
= 0;
5722 num_dst
= num_inst_dst_regs(inst
);
5723 num_src
= num_inst_src_regs(inst
);
5725 for (i
= 0; i
< num_dst
; i
++)
5726 dst
[i
] = translate_dst(t
,
5730 for (i
= 0; i
< num_src
; i
++)
5731 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5734 case TGSI_OPCODE_BGNLOOP
:
5735 case TGSI_OPCODE_ELSE
:
5736 case TGSI_OPCODE_ENDLOOP
:
5737 case TGSI_OPCODE_IF
:
5738 case TGSI_OPCODE_UIF
:
5739 assert(num_dst
== 0);
5740 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5743 case TGSI_OPCODE_TEX
:
5744 case TGSI_OPCODE_TEX_LZ
:
5745 case TGSI_OPCODE_TXB
:
5746 case TGSI_OPCODE_TXD
:
5747 case TGSI_OPCODE_TXL
:
5748 case TGSI_OPCODE_TXP
:
5749 case TGSI_OPCODE_TXQ
:
5750 case TGSI_OPCODE_TXQS
:
5751 case TGSI_OPCODE_TXF
:
5752 case TGSI_OPCODE_TXF_LZ
:
5753 case TGSI_OPCODE_TEX2
:
5754 case TGSI_OPCODE_TXB2
:
5755 case TGSI_OPCODE_TXL2
:
5756 case TGSI_OPCODE_TG4
:
5757 case TGSI_OPCODE_LODQ
:
5758 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5759 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5761 /* Bindless samplers. */
5762 src
[num_src
] = translate_src(t
, &inst
->resource
);
5764 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5765 if (inst
->resource
.reladdr
)
5767 ureg_src_indirect(src
[num_src
],
5768 translate_addr(t
, inst
->resource
.reladdr
, 2));
5770 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5771 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5773 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5779 st_translate_texture_type(inst
->tex_type
),
5780 texoffsets
, inst
->tex_offset_num_offset
,
5784 case TGSI_OPCODE_RESQ
:
5785 case TGSI_OPCODE_LOAD
:
5786 case TGSI_OPCODE_ATOMUADD
:
5787 case TGSI_OPCODE_ATOMXCHG
:
5788 case TGSI_OPCODE_ATOMCAS
:
5789 case TGSI_OPCODE_ATOMAND
:
5790 case TGSI_OPCODE_ATOMOR
:
5791 case TGSI_OPCODE_ATOMXOR
:
5792 case TGSI_OPCODE_ATOMUMIN
:
5793 case TGSI_OPCODE_ATOMUMAX
:
5794 case TGSI_OPCODE_ATOMIMIN
:
5795 case TGSI_OPCODE_ATOMIMAX
:
5796 for (i
= num_src
- 1; i
>= 0; i
--)
5797 src
[i
+ 1] = src
[i
];
5799 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5800 src
[0] = t
->shared_memory
;
5801 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5802 src
[0] = t
->buffers
[inst
->resource
.index
];
5803 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
5804 assert(inst
->resource
.has_index2
);
5805 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
5807 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
5808 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5809 src
[0] = t
->images
[inst
->resource
.index
];
5811 /* Bindless images. */
5812 src
[0] = translate_src(t
, &inst
->resource
);
5814 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5816 if (inst
->resource
.reladdr
)
5817 src
[0] = ureg_src_indirect(src
[0],
5818 translate_addr(t
, inst
->resource
.reladdr
, 2));
5819 assert(src
[0].File
!= TGSI_FILE_NULL
);
5820 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5821 inst
->buffer_access
,
5822 tex_target
, inst
->image_format
);
5825 case TGSI_OPCODE_STORE
:
5826 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5827 dst
[0] = ureg_dst(t
->shared_memory
);
5828 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5829 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5831 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5832 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5834 /* Bindless images. */
5835 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
5837 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5839 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5840 if (inst
->resource
.reladdr
)
5841 dst
[0] = ureg_dst_indirect(dst
[0],
5842 translate_addr(t
, inst
->resource
.reladdr
, 2));
5843 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5844 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5845 inst
->buffer_access
,
5846 tex_target
, inst
->image_format
);
5853 src
, num_src
, inst
->precise
);
5859 * Emit the TGSI instructions for inverting and adjusting WPOS.
5860 * This code is unavoidable because it also depends on whether
5861 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5864 emit_wpos_adjustment(struct gl_context
*ctx
,
5865 struct st_translate
*t
,
5866 int wpos_transform_const
,
5868 GLfloat adjX
, GLfloat adjY
[2])
5870 struct ureg_program
*ureg
= t
->ureg
;
5872 assert(wpos_transform_const
>= 0);
5874 /* Fragment program uses fragment position input.
5875 * Need to replace instances of INPUT[WPOS] with temp T
5876 * where T = INPUT[WPOS] is inverted by Y.
5878 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5879 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5880 struct ureg_src
*wpos
=
5881 ctx
->Const
.GLSLFragCoordIsSysVal
?
5882 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5883 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5884 struct ureg_src wpos_input
= *wpos
;
5886 /* First, apply the coordinate shift: */
5887 if (adjX
|| adjY
[0] || adjY
[1]) {
5888 if (adjY
[0] != adjY
[1]) {
5889 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5890 * depending on whether inversion is actually going to be applied
5891 * or not, which is determined by testing against the inversion
5892 * state variable used below, which will be either +1 or -1.
5894 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5896 ureg_CMP(ureg
, adj_temp
,
5897 ureg_scalar(wpostrans
, invert
? 2 : 0),
5898 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5899 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5900 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5902 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5903 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5905 wpos_input
= ureg_src(wpos_temp
);
5907 /* MOV wpos_temp, input[wpos]
5909 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5912 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5913 * inversion/identity, or the other way around if we're drawing to an FBO.
5916 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5919 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5921 ureg_scalar(wpostrans
, 0),
5922 ureg_scalar(wpostrans
, 1));
5924 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5927 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5929 ureg_scalar(wpostrans
, 2),
5930 ureg_scalar(wpostrans
, 3));
5933 /* Use wpos_temp as position input from here on:
5935 *wpos
= ureg_src(wpos_temp
);
5940 * Emit fragment position/ooordinate code.
5943 emit_wpos(struct st_context
*st
,
5944 struct st_translate
*t
,
5945 const struct gl_program
*program
,
5946 struct ureg_program
*ureg
,
5947 int wpos_transform_const
)
5949 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5950 GLfloat adjX
= 0.0f
;
5951 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5952 boolean invert
= FALSE
;
5954 /* Query the pixel center conventions supported by the pipe driver and set
5955 * adjX, adjY to help out if it cannot handle the requested one internally.
5957 * The bias of the y-coordinate depends on whether y-inversion takes place
5958 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5959 * drawing to an FBO (causes additional inversion), and whether the pipe
5960 * driver origin and the requested origin differ (the latter condition is
5961 * stored in the 'invert' variable).
5963 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5965 * center shift only:
5970 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5971 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5972 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5973 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5975 * inversion and center shift:
5976 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5977 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5978 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5979 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5981 if (program
->OriginUpperLeft
) {
5982 /* Fragment shader wants origin in upper-left */
5983 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5984 /* the driver supports upper-left origin */
5986 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5987 /* the driver supports lower-left origin, need to invert Y */
5988 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5989 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5996 /* Fragment shader wants origin in lower-left */
5997 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5998 /* the driver supports lower-left origin */
5999 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6000 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6001 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6002 /* the driver supports upper-left origin, need to invert Y */
6008 if (program
->PixelCenterInteger
) {
6009 /* Fragment shader wants pixel center integer */
6010 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6011 /* the driver supports pixel center integer */
6013 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6014 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6016 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6017 /* the driver supports pixel center half integer, need to bias X,Y */
6026 /* Fragment shader wants pixel center half integer */
6027 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6028 /* the driver supports pixel center half integer */
6030 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6031 /* the driver supports pixel center integer, need to bias X,Y */
6032 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6033 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6034 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6040 /* we invert after adjustment so that we avoid the MOV to temporary,
6041 * and reuse the adjustment ADD instead */
6042 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6046 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6047 * TGSI uses +1 for front, -1 for back.
6048 * This function converts the TGSI value to the GL value. Simply clamping/
6049 * saturating the value to [0,1] does the job.
6052 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6054 struct ureg_program
*ureg
= t
->ureg
;
6055 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6056 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6058 if (ctx
->Const
.NativeIntegers
) {
6059 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6062 /* MOV_SAT face_temp, input[face] */
6063 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6066 /* Use face_temp as face input from here on: */
6067 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6071 emit_compute_block_size(const struct gl_program
*prog
,
6072 struct ureg_program
*ureg
) {
6073 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6074 prog
->info
.cs
.local_size
[0]);
6075 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6076 prog
->info
.cs
.local_size
[1]);
6077 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6078 prog
->info
.cs
.local_size
[2]);
6081 struct sort_inout_decls
{
6082 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6083 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6086 const ubyte
*mapping
;
6089 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6091 * This is for the benefit of older drivers which are broken when the
6092 * declarations aren't sorted in this way.
6095 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6097 const ubyte mapping
[])
6099 sort_inout_decls sorter
;
6100 sorter
.mapping
= mapping
;
6101 std::sort(decls
, decls
+ count
, sorter
);
6105 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6107 switch (glsl_qual
) {
6108 case INTERP_MODE_NONE
:
6109 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6110 return TGSI_INTERPOLATE_COLOR
;
6111 return TGSI_INTERPOLATE_PERSPECTIVE
;
6112 case INTERP_MODE_SMOOTH
:
6113 return TGSI_INTERPOLATE_PERSPECTIVE
;
6114 case INTERP_MODE_FLAT
:
6115 return TGSI_INTERPOLATE_CONSTANT
;
6116 case INTERP_MODE_NOPERSPECTIVE
:
6117 return TGSI_INTERPOLATE_LINEAR
;
6119 assert(0 && "unexpected interp mode in st_translate_interp()");
6120 return TGSI_INTERPOLATE_PERSPECTIVE
;
6125 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6126 * \param program the program to translate
6127 * \param numInputs number of input registers used
6128 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6130 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6131 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6133 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6134 * \param numOutputs number of output registers used
6135 * \param outputMapping maps Mesa fragment program outputs to TGSI
6137 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6138 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6141 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6143 extern "C" enum pipe_error
6144 st_translate_program(
6145 struct gl_context
*ctx
,
6147 struct ureg_program
*ureg
,
6148 glsl_to_tgsi_visitor
*program
,
6149 const struct gl_program
*proginfo
,
6151 const ubyte inputMapping
[],
6152 const ubyte inputSlotToAttr
[],
6153 const ubyte inputSemanticName
[],
6154 const ubyte inputSemanticIndex
[],
6155 const ubyte interpMode
[],
6157 const ubyte outputMapping
[],
6158 const ubyte outputSemanticName
[],
6159 const ubyte outputSemanticIndex
[])
6161 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6162 struct st_translate
*t
;
6164 struct gl_program_constants
*frag_const
=
6165 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6166 enum pipe_error ret
= PIPE_OK
;
6168 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6169 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6171 t
= CALLOC_STRUCT(st_translate
);
6173 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6177 t
->procType
= procType
;
6178 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6179 t
->inputMapping
= inputMapping
;
6180 t
->outputMapping
= outputMapping
;
6182 t
->num_temp_arrays
= program
->next_array
;
6183 if (t
->num_temp_arrays
)
6184 t
->arrays
= (struct ureg_dst
*)
6185 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6188 * Declare input attributes.
6191 case PIPE_SHADER_FRAGMENT
:
6192 case PIPE_SHADER_GEOMETRY
:
6193 case PIPE_SHADER_TESS_EVAL
:
6194 case PIPE_SHADER_TESS_CTRL
:
6195 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6197 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6198 struct inout_decl
*decl
= &program
->inputs
[i
];
6199 unsigned slot
= inputMapping
[decl
->mesa_index
];
6200 struct ureg_src src
;
6201 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6203 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6204 if (tgsi_usage_mask
== 1)
6205 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6206 else if (tgsi_usage_mask
== 2)
6207 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6209 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6212 unsigned interp_mode
= 0;
6213 unsigned interp_location
= 0;
6214 if (procType
== PIPE_SHADER_FRAGMENT
) {
6216 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6218 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6220 interp_location
= decl
->interp_loc
;
6223 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6224 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6225 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6226 decl
->array_id
, decl
->size
);
6228 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6229 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6230 /* The ArrayID is set up in dst_register */
6231 t
->inputs
[slot
+ j
] = src
;
6232 t
->inputs
[slot
+ j
].ArrayID
= 0;
6233 t
->inputs
[slot
+ j
].Index
+= j
;
6238 case PIPE_SHADER_VERTEX
:
6239 for (i
= 0; i
< numInputs
; i
++) {
6240 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6243 case PIPE_SHADER_COMPUTE
:
6250 * Declare output attributes.
6253 case PIPE_SHADER_FRAGMENT
:
6254 case PIPE_SHADER_COMPUTE
:
6256 case PIPE_SHADER_GEOMETRY
:
6257 case PIPE_SHADER_TESS_EVAL
:
6258 case PIPE_SHADER_TESS_CTRL
:
6259 case PIPE_SHADER_VERTEX
:
6260 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6262 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6263 struct inout_decl
*decl
= &program
->outputs
[i
];
6264 unsigned slot
= outputMapping
[decl
->mesa_index
];
6265 struct ureg_dst dst
;
6266 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6268 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6269 if (tgsi_usage_mask
== 1)
6270 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6271 else if (tgsi_usage_mask
== 2)
6272 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6274 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6277 dst
= ureg_DECL_output_layout(ureg
,
6278 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6279 decl
->gs_out_streams
,
6280 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6282 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6283 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6284 /* The ArrayID is set up in dst_register */
6285 t
->outputs
[slot
+ j
] = dst
;
6286 t
->outputs
[slot
+ j
].ArrayID
= 0;
6287 t
->outputs
[slot
+ j
].Index
+= j
;
6296 if (procType
== PIPE_SHADER_FRAGMENT
) {
6297 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6298 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6299 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6301 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6302 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6305 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6306 /* Must do this after setting up t->inputs. */
6307 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6308 program
->wpos_transform_const
);
6311 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6312 emit_face_var(ctx
, t
);
6314 for (i
= 0; i
< numOutputs
; i
++) {
6315 switch (outputSemanticName
[i
]) {
6316 case TGSI_SEMANTIC_POSITION
:
6317 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6318 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6319 outputSemanticIndex
[i
]);
6320 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6322 case TGSI_SEMANTIC_STENCIL
:
6323 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6324 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6325 outputSemanticIndex
[i
]);
6326 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6328 case TGSI_SEMANTIC_COLOR
:
6329 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6330 TGSI_SEMANTIC_COLOR
,
6331 outputSemanticIndex
[i
]);
6333 case TGSI_SEMANTIC_SAMPLEMASK
:
6334 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6335 TGSI_SEMANTIC_SAMPLEMASK
,
6336 outputSemanticIndex
[i
]);
6337 /* TODO: If we ever support more than 32 samples, this will have
6338 * to become an array.
6340 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6343 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6344 ret
= PIPE_ERROR_BAD_INPUT
;
6349 else if (procType
== PIPE_SHADER_VERTEX
) {
6350 for (i
= 0; i
< numOutputs
; i
++) {
6351 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6352 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6354 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6355 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6356 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6361 if (procType
== PIPE_SHADER_COMPUTE
) {
6362 emit_compute_block_size(proginfo
, ureg
);
6365 /* Declare address register.
6367 if (program
->num_address_regs
> 0) {
6368 assert(program
->num_address_regs
<= 3);
6369 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6370 t
->address
[i
] = ureg_DECL_address(ureg
);
6373 /* Declare misc input registers
6376 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6378 for (i
= 0; sysInputs
; i
++) {
6379 if (sysInputs
& (1 << i
)) {
6380 unsigned semName
= _mesa_sysval_to_semantic(i
);
6382 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6384 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6385 semName
== TGSI_SEMANTIC_VERTEXID
) {
6386 /* From Gallium perspective, these system values are always
6387 * integer, and require native integer support. However, if
6388 * native integer is supported on the vertex stage but not the
6389 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6390 * assumes these system values are floats. To resolve the
6391 * inconsistency, we insert a U2F.
6393 struct st_context
*st
= st_context(ctx
);
6394 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6395 assert(procType
== PIPE_SHADER_VERTEX
);
6396 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6398 if (!ctx
->Const
.NativeIntegers
) {
6399 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6400 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6401 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6405 if (procType
== PIPE_SHADER_FRAGMENT
&&
6406 semName
== TGSI_SEMANTIC_POSITION
)
6407 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6408 program
->wpos_transform_const
);
6410 sysInputs
&= ~(1 << i
);
6415 t
->array_sizes
= program
->array_sizes
;
6416 t
->input_decls
= program
->inputs
;
6417 t
->num_input_decls
= program
->num_inputs
;
6418 t
->output_decls
= program
->outputs
;
6419 t
->num_output_decls
= program
->num_outputs
;
6421 /* Emit constants and uniforms. TGSI uses a single index space for these,
6422 * so we put all the translated regs in t->constants.
6424 if (proginfo
->Parameters
) {
6425 t
->constants
= (struct ureg_src
*)
6426 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6427 if (t
->constants
== NULL
) {
6428 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6431 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6433 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6434 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6435 case PROGRAM_STATE_VAR
:
6436 case PROGRAM_UNIFORM
:
6437 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6440 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6441 * addressing of the const buffer.
6442 * FIXME: Be smarter and recognize param arrays:
6443 * indirect addressing is only valid within the referenced
6446 case PROGRAM_CONSTANT
:
6447 if (program
->indirect_addr_consts
)
6448 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6450 t
->constants
[i
] = emit_immediate(t
,
6451 proginfo
->Parameters
->ParameterValues
[i
],
6452 proginfo
->Parameters
->Parameters
[i
].DataType
,
6461 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6462 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6463 unsigned num_const_vecs
= (size
+ 15) / 16;
6464 unsigned first
, last
;
6465 assert(num_const_vecs
> 0);
6467 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6468 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6471 /* Emit immediate values.
6473 t
->immediates
= (struct ureg_src
*)
6474 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6475 if (t
->immediates
== NULL
) {
6476 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6479 t
->num_immediates
= program
->num_immediates
;
6482 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6483 assert(i
< program
->num_immediates
);
6484 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6486 assert(i
== program
->num_immediates
);
6488 /* texture samplers */
6489 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6490 if (program
->samplers_used
& (1u << i
)) {
6491 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6493 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6495 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6496 type
, type
, type
, type
);
6500 /* Declare atomic and shader storage buffers. */
6502 struct gl_program
*prog
= program
->prog
;
6504 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6505 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6506 assert(index
< frag_const
->MaxAtomicBuffers
);
6507 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6510 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6511 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6512 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6513 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6517 if (program
->use_shared_memory
)
6518 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6520 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6521 if (program
->images_used
& (1 << i
)) {
6522 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6523 program
->image_targets
[i
],
6524 program
->image_formats
[i
],
6529 /* Emit each instruction in turn:
6531 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6532 compile_tgsi_instruction(t
, inst
);
6534 /* Set the next shader stage hint for VS and TES. */
6536 case PIPE_SHADER_VERTEX
:
6537 case PIPE_SHADER_TESS_EVAL
:
6538 if (program
->shader_program
->SeparateShader
)
6541 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6542 if (program
->shader_program
->_LinkedShaders
[i
]) {
6543 ureg_set_next_shader_processor(
6544 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6556 t
->num_constants
= 0;
6557 free(t
->immediates
);
6558 t
->num_immediates
= 0;
6564 /* ----------------------------- End TGSI code ------------------------------ */
6568 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6569 * generating Mesa IR.
6571 static struct gl_program
*
6572 get_mesa_program_tgsi(struct gl_context
*ctx
,
6573 struct gl_shader_program
*shader_program
,
6574 struct gl_linked_shader
*shader
)
6576 glsl_to_tgsi_visitor
* v
;
6577 struct gl_program
*prog
;
6578 struct gl_shader_compiler_options
*options
=
6579 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6580 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6581 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6582 unsigned skip_merge_registers
;
6584 validate_ir_tree(shader
->ir
);
6586 prog
= shader
->Program
;
6588 prog
->Parameters
= _mesa_new_parameter_list();
6589 v
= new glsl_to_tgsi_visitor();
6592 v
->shader_program
= shader_program
;
6594 v
->options
= options
;
6595 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6597 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6598 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6599 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6600 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6601 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6602 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6603 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6605 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6606 _mesa_key_pointer_equal
);
6607 skip_merge_registers
=
6608 pscreen
->get_shader_param(pscreen
, ptarget
,
6609 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6611 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6614 /* Remove reads from output registers. */
6615 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6616 lower_output_reads(shader
->Stage
, shader
->ir
);
6618 /* Emit intermediate IR for main(). */
6619 visit_exec_list(shader
->ir
, v
);
6622 /* Print out some information (for debugging purposes) used by the
6623 * optimization passes. */
6626 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6627 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6628 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6629 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6631 for (i
= 0; i
< v
->next_temp
; i
++) {
6632 first_writes
[i
] = -1;
6633 first_reads
[i
] = -1;
6634 last_writes
[i
] = -1;
6637 v
->get_first_temp_read(first_reads
);
6638 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6639 v
->get_last_temp_write(last_writes
);
6640 for (i
= 0; i
< v
->next_temp
; i
++)
6641 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6645 ralloc_free(first_writes
);
6646 ralloc_free(first_reads
);
6647 ralloc_free(last_writes
);
6648 ralloc_free(last_reads
);
6652 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6654 v
->copy_propagate();
6656 while (v
->eliminate_dead_code());
6658 v
->merge_two_dsts();
6659 if (!skip_merge_registers
)
6660 v
->merge_registers();
6661 v
->renumber_registers();
6663 /* Write the END instruction. */
6664 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6666 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6668 _mesa_log("GLSL IR for linked %s program %d:\n",
6669 _mesa_shader_stage_to_string(shader
->Stage
),
6670 shader_program
->Name
);
6671 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6675 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6676 _mesa_copy_linked_program_data(shader_program
, shader
);
6677 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6678 &prog
->info
.inputs_read
,
6679 prog
->info
.double_inputs_read
,
6680 &prog
->info
.patch_inputs_read
);
6681 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6682 &prog
->info
.outputs_written
, 0ULL,
6683 &prog
->info
.patch_outputs_written
);
6684 count_resources(v
, prog
);
6686 /* The GLSL IR won't be needed anymore. */
6687 ralloc_free(shader
->ir
);
6690 /* This must be done before the uniform storage is associated. */
6691 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6692 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6693 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6694 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6695 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6698 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6699 wposTransformState
);
6702 /* Avoid reallocation of the program parameter list, because the uniform
6703 * storage is only associated with the original parameter list.
6704 * This should be enough for Bitmap and DrawPixels constants.
6706 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6708 /* This has to be done last. Any operation the can cause
6709 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6710 * program constant) has to happen before creating this linkage.
6712 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6713 if (!shader_program
->data
->LinkStatus
) {
6714 free_glsl_to_tgsi_visitor(v
);
6715 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6719 struct st_vertex_program
*stvp
;
6720 struct st_fragment_program
*stfp
;
6721 struct st_common_program
*stp
;
6722 struct st_compute_program
*stcp
;
6724 switch (shader
->Stage
) {
6725 case MESA_SHADER_VERTEX
:
6726 stvp
= (struct st_vertex_program
*)prog
;
6727 stvp
->glsl_to_tgsi
= v
;
6729 case MESA_SHADER_FRAGMENT
:
6730 stfp
= (struct st_fragment_program
*)prog
;
6731 stfp
->glsl_to_tgsi
= v
;
6733 case MESA_SHADER_TESS_CTRL
:
6734 case MESA_SHADER_TESS_EVAL
:
6735 case MESA_SHADER_GEOMETRY
:
6736 stp
= st_common_program(prog
);
6737 stp
->glsl_to_tgsi
= v
;
6739 case MESA_SHADER_COMPUTE
:
6740 stcp
= (struct st_compute_program
*)prog
;
6741 stcp
->glsl_to_tgsi
= v
;
6744 assert(!"should not be reached");
6751 /* See if there are unsupported control flow statements. */
6752 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6754 const struct gl_shader_compiler_options
*options
;
6756 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6762 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6764 /* Other functions are skipped (same as glsl_to_tgsi). */
6765 if (strcmp(ir
->name
, "main") == 0)
6766 return visit_continue
;
6768 return visit_continue_with_parent
;
6771 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6773 if (!ir
->callee
->is_intrinsic()) {
6774 unsupported
= true; /* it's a function call */
6777 return visit_continue
;
6780 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6782 if (options
->EmitNoMainReturn
) {
6786 return visit_continue
;
6793 has_unsupported_control_flow(exec_list
*ir
,
6794 const struct gl_shader_compiler_options
*options
)
6796 ir_control_flow_info_visitor
visitor(options
);
6797 visit_list_elements(&visitor
, ir
);
6798 return visitor
.unsupported
;
6805 * Called via ctx->Driver.LinkShader()
6806 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6807 * with code lowering and other optimizations.
6810 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6812 /* Return early if we are loading the shader from on-disk cache */
6813 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6817 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6818 assert(prog
->data
->LinkStatus
);
6820 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6821 if (prog
->_LinkedShaders
[i
] == NULL
)
6824 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6825 exec_list
*ir
= shader
->ir
;
6826 gl_shader_stage stage
= shader
->Stage
;
6827 const struct gl_shader_compiler_options
*options
=
6828 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6829 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
6830 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6831 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6832 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6833 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6834 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6835 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
6836 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6837 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6839 /* If there are forms of indirect addressing that the driver
6840 * cannot handle, perform the lowering pass.
6842 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6843 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6844 lower_variable_index_to_cond_assign(stage
, ir
,
6845 options
->EmitNoIndirectInput
,
6846 options
->EmitNoIndirectOutput
,
6847 options
->EmitNoIndirectTemp
,
6848 options
->EmitNoIndirectUniform
);
6851 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6852 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6854 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6855 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6856 LOWER_UNPACK_SNORM_2x16
|
6857 LOWER_PACK_UNORM_2x16
|
6858 LOWER_UNPACK_UNORM_2x16
|
6859 LOWER_PACK_SNORM_4x8
|
6860 LOWER_UNPACK_SNORM_4x8
|
6861 LOWER_UNPACK_UNORM_4x8
|
6862 LOWER_PACK_UNORM_4x8
;
6864 if (ctx
->Extensions
.ARB_gpu_shader5
)
6865 lower_inst
|= LOWER_PACK_USE_BFI
|
6867 if (!ctx
->st
->has_half_float_packing
)
6868 lower_inst
|= LOWER_PACK_HALF_2x16
|
6869 LOWER_UNPACK_HALF_2x16
;
6871 lower_packing_builtins(ir
, lower_inst
);
6874 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6875 lower_offset_arrays(ir
);
6876 do_mat_op_to_vec(ir
);
6878 if (stage
== MESA_SHADER_FRAGMENT
)
6879 lower_blend_equation_advanced(shader
);
6881 lower_instructions(ir
,
6886 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
6887 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6890 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6891 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6892 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6893 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6894 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6895 /* Assume that if ARB_gpu_shader5 is not supported
6896 * then all of the extended integer functions need
6897 * lowering. It may be necessary to add some caps
6898 * for individual instructions.
6900 (!ctx
->Extensions
.ARB_gpu_shader5
6901 ? BIT_COUNT_TO_MATH
|
6905 FIND_LSB_TO_FLOAT_CAST
|
6906 FIND_MSB_TO_FLOAT_CAST
|
6910 do_vec_index_to_cond_assign(ir
);
6911 lower_vector_insert(ir
, true);
6912 lower_quadop_vector(ir
, false);
6914 if (options
->MaxIfDepth
== 0) {
6918 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6919 /* Do it once and repeat only if there's unsupported control flow. */
6921 do_common_optimization(ir
, true, true, options
,
6922 ctx
->Const
.NativeIntegers
);
6923 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6924 options
->MaxIfDepth
, if_threshold
);
6925 } while (has_unsupported_control_flow(ir
, options
));
6927 /* Repeat it until it stops making changes. */
6930 progress
= do_common_optimization(ir
, true, true, options
,
6931 ctx
->Const
.NativeIntegers
);
6932 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6933 options
->MaxIfDepth
, if_threshold
);
6937 validate_ir_tree(ir
);
6940 build_program_resource_list(ctx
, prog
);
6942 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6943 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6947 enum pipe_shader_type ptarget
=
6948 pipe_shader_type_from_mesa(shader
->Stage
);
6949 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6950 pscreen
->get_shader_param(pscreen
, ptarget
,
6951 PIPE_SHADER_CAP_PREFERRED_IR
);
6953 struct gl_program
*linked_prog
= NULL
;
6954 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6955 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6957 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6958 st_set_prog_affected_state_flags(linked_prog
);
6962 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6963 _mesa_shader_stage_to_program(i
),
6965 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6975 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6976 const ubyte outputMapping
[],
6977 struct pipe_stream_output_info
*so
)
6979 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
6982 struct gl_transform_feedback_info
*info
=
6983 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
6984 st_translate_stream_output_info2(info
, outputMapping
, so
);
6988 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
6989 const ubyte outputMapping
[],
6990 struct pipe_stream_output_info
*so
)
6994 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6995 so
->output
[i
].register_index
=
6996 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6997 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6998 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6999 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7000 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7001 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7004 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7005 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7007 so
->num_outputs
= info
->NumOutputs
;