2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
56 #include "st_shader_cache.h"
58 #include "util/hash_table.h"
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
65 #define MAX_GLSL_TEXTURE_OFFSET 4
70 static int swizzle_for_size(int size
);
72 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
74 unsigned num_elements
= 4;
77 type
= type
->without_array();
78 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
79 num_elements
= type
->vector_elements
;
82 int swizzle
= swizzle_for_size(num_elements
);
83 assert(num_elements
+ component
<= 4);
85 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
89 static unsigned is_precise(const ir_variable
*ir
)
93 return ir
->data
.precise
|| ir
->data
.invariant
;
97 * This struct is a corresponding struct to TGSI ureg_src.
101 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
102 int component
= 0, unsigned array_id
= 0)
104 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
107 this->swizzle
= swizzle_for_type(type
, component
);
111 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
112 this->reladdr
= NULL
;
113 this->reladdr2
= NULL
;
114 this->has_index2
= false;
115 this->double_reg2
= false;
116 this->array_id
= array_id
;
117 this->is_double_vertex_input
= false;
120 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
122 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
127 this->swizzle
= SWIZZLE_XYZW
;
130 this->reladdr
= NULL
;
131 this->reladdr2
= NULL
;
132 this->has_index2
= false;
133 this->double_reg2
= false;
135 this->is_double_vertex_input
= false;
138 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
140 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
144 this->index2D
= index2D
;
145 this->swizzle
= SWIZZLE_XYZW
;
148 this->reladdr
= NULL
;
149 this->reladdr2
= NULL
;
150 this->has_index2
= false;
151 this->double_reg2
= false;
153 this->is_double_vertex_input
= false;
158 this->type
= GLSL_TYPE_ERROR
;
159 this->file
= PROGRAM_UNDEFINED
;
165 this->reladdr
= NULL
;
166 this->reladdr2
= NULL
;
167 this->has_index2
= false;
168 this->double_reg2
= false;
170 this->is_double_vertex_input
= false;
173 explicit st_src_reg(st_dst_reg reg
);
175 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
177 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
178 int negate
:4; /**< NEGATE_XYZW mask from mesa */
180 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
181 unsigned has_index2
:1;
182 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
184 * Is this the second half of a double register pair?
185 * currently used for input mapping only.
187 unsigned double_reg2
:1;
188 unsigned is_double_vertex_input
:1;
189 unsigned array_id
:10;
191 /** Register index should be offset by the integer in this reg. */
193 st_src_reg
*reladdr2
;
197 st_src_reg reg
= *this;
206 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
208 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
212 this->writemask
= writemask
;
213 this->reladdr
= NULL
;
214 this->reladdr2
= NULL
;
215 this->has_index2
= false;
220 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
222 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
226 this->writemask
= writemask
;
227 this->reladdr
= NULL
;
228 this->reladdr2
= NULL
;
229 this->has_index2
= false;
236 this->type
= GLSL_TYPE_ERROR
;
237 this->file
= PROGRAM_UNDEFINED
;
241 this->reladdr
= NULL
;
242 this->reladdr2
= NULL
;
243 this->has_index2
= false;
247 explicit st_dst_reg(st_src_reg reg
);
249 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
251 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
252 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
253 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
254 unsigned has_index2
:1;
255 unsigned array_id
:10;
257 /** Register index should be offset by the integer in this reg. */
259 st_src_reg
*reladdr2
;
262 st_src_reg::st_src_reg(st_dst_reg reg
)
264 this->type
= reg
.type
;
265 this->file
= reg
.file
;
266 this->index
= reg
.index
;
267 this->swizzle
= SWIZZLE_XYZW
;
270 this->reladdr
= reg
.reladdr
;
271 this->index2D
= reg
.index2D
;
272 this->reladdr2
= reg
.reladdr2
;
273 this->has_index2
= reg
.has_index2
;
274 this->double_reg2
= false;
275 this->array_id
= reg
.array_id
;
276 this->is_double_vertex_input
= false;
279 st_dst_reg::st_dst_reg(st_src_reg reg
)
281 this->type
= reg
.type
;
282 this->file
= reg
.file
;
283 this->index
= reg
.index
;
284 this->writemask
= WRITEMASK_XYZW
;
285 this->reladdr
= reg
.reladdr
;
286 this->index2D
= reg
.index2D
;
287 this->reladdr2
= reg
.reladdr2
;
288 this->has_index2
= reg
.has_index2
;
289 this->array_id
= reg
.array_id
;
292 class glsl_to_tgsi_instruction
: public exec_node
{
294 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
298 st_src_reg resource
; /**< sampler, image or buffer register */
299 st_src_reg
*tex_offsets
;
301 /** Pointer to the ir source this tree came from for debugging */
304 unsigned op
:8; /**< TGSI opcode */
307 unsigned is_64bit_expanded
:1;
308 unsigned sampler_base
:5;
309 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
310 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
311 glsl_base_type tex_type
:5;
312 unsigned tex_shadow
:1;
313 unsigned image_format
:9;
314 unsigned tex_offset_num_offset
:3;
315 unsigned dead_mask
:4; /**< Used in dead code elimination */
316 unsigned buffer_access
:3; /**< buffer access type */
318 const struct tgsi_opcode_info
*info
;
321 class variable_storage
{
322 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
325 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
326 unsigned array_id
= 0)
327 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
329 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
332 gl_register_file file
;
335 /* Explicit component location. This is given in terms of the GLSL-style
336 * swizzles where each double is a single component, i.e. for 64-bit types
337 * it can only be 0 or 1.
340 ir_variable
*var
; /* variable that maps to this, if any */
344 class immediate_storage
: public exec_node
{
346 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
348 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
349 this->size32
= size32
;
353 /* doubles are stored across 2 gl_constant_values */
354 gl_constant_value values
[4];
355 int size32
; /**< Number of 32-bit components (1-4) */
356 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
359 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
360 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
364 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
367 unsigned gs_out_streams
;
368 enum glsl_interp_mode interp
;
369 enum glsl_base_type base_type
;
370 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
373 static struct inout_decl
*
374 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
376 assert(array_id
!= 0);
378 for (unsigned i
= 0; i
< count
; i
++) {
379 struct inout_decl
*decl
= &decls
[i
];
381 if (array_id
== decl
->array_id
) {
389 static enum glsl_base_type
390 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
393 return GLSL_TYPE_ERROR
;
394 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
396 return decl
->base_type
;
397 return GLSL_TYPE_ERROR
;
400 struct rename_reg_pair
{
405 struct glsl_to_tgsi_visitor
: public ir_visitor
{
407 glsl_to_tgsi_visitor();
408 ~glsl_to_tgsi_visitor();
410 struct gl_context
*ctx
;
411 struct gl_program
*prog
;
412 struct gl_shader_program
*shader_program
;
413 struct gl_linked_shader
*shader
;
414 struct gl_shader_compiler_options
*options
;
418 unsigned *array_sizes
;
419 unsigned max_num_arrays
;
422 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
424 unsigned num_input_arrays
;
425 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
426 unsigned num_outputs
;
427 unsigned num_output_arrays
;
429 int num_address_regs
;
430 uint32_t samplers_used
;
431 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
432 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
434 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
435 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
436 bool indirect_addr_consts
;
437 int wpos_transform_const
;
440 bool native_integers
;
443 bool use_shared_memory
;
447 variable_storage
*find_variable_storage(ir_variable
*var
);
449 int add_constant(gl_register_file file
, gl_constant_value values
[8],
450 int size
, int datatype
, uint16_t *swizzle_out
);
452 st_src_reg
get_temp(const glsl_type
*type
);
453 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
455 st_src_reg
st_src_reg_for_double(double val
);
456 st_src_reg
st_src_reg_for_float(float val
);
457 st_src_reg
st_src_reg_for_int(int val
);
458 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
461 * \name Visit methods
463 * As typical for the visitor pattern, there must be one \c visit method for
464 * each concrete subclass of \c ir_instruction. Virtual base classes within
465 * the hierarchy should not have \c visit methods.
468 virtual void visit(ir_variable
*);
469 virtual void visit(ir_loop
*);
470 virtual void visit(ir_loop_jump
*);
471 virtual void visit(ir_function_signature
*);
472 virtual void visit(ir_function
*);
473 virtual void visit(ir_expression
*);
474 virtual void visit(ir_swizzle
*);
475 virtual void visit(ir_dereference_variable
*);
476 virtual void visit(ir_dereference_array
*);
477 virtual void visit(ir_dereference_record
*);
478 virtual void visit(ir_assignment
*);
479 virtual void visit(ir_constant
*);
480 virtual void visit(ir_call
*);
481 virtual void visit(ir_return
*);
482 virtual void visit(ir_discard
*);
483 virtual void visit(ir_texture
*);
484 virtual void visit(ir_if
*);
485 virtual void visit(ir_emit_vertex
*);
486 virtual void visit(ir_end_primitive
*);
487 virtual void visit(ir_barrier
*);
490 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
492 void visit_atomic_counter_intrinsic(ir_call
*);
493 void visit_ssbo_intrinsic(ir_call
*);
494 void visit_membar_intrinsic(ir_call
*);
495 void visit_shared_intrinsic(ir_call
*);
496 void visit_image_intrinsic(ir_call
*);
497 void visit_generic_intrinsic(ir_call
*, unsigned op
);
501 /** List of variable_storage */
502 struct hash_table
*variables
;
504 /** List of immediate_storage */
505 exec_list immediates
;
506 unsigned num_immediates
;
508 /** List of glsl_to_tgsi_instruction */
509 exec_list instructions
;
511 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
512 st_dst_reg dst
= undef_dst
,
513 st_src_reg src0
= undef_src
,
514 st_src_reg src1
= undef_src
,
515 st_src_reg src2
= undef_src
,
516 st_src_reg src3
= undef_src
);
518 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
519 st_dst_reg dst
, st_dst_reg dst1
,
520 st_src_reg src0
= undef_src
,
521 st_src_reg src1
= undef_src
,
522 st_src_reg src2
= undef_src
,
523 st_src_reg src3
= undef_src
);
525 unsigned get_opcode(unsigned op
,
527 st_src_reg src0
, st_src_reg src1
);
530 * Emit the correct dot-product instruction for the type of arguments
532 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
538 void emit_scalar(ir_instruction
*ir
, unsigned op
,
539 st_dst_reg dst
, st_src_reg src0
);
541 void emit_scalar(ir_instruction
*ir
, unsigned op
,
542 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
544 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
546 void get_deref_offsets(ir_dereference
*ir
,
547 unsigned *array_size
,
552 void calc_deref_offsets(ir_dereference
*tail
,
553 unsigned *array_elements
,
555 st_src_reg
*indirect
,
557 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
559 bool try_emit_mad(ir_expression
*ir
,
561 bool try_emit_mad_for_and_not(ir_expression
*ir
,
564 void emit_swz(ir_expression
*ir
);
566 bool process_move_condition(ir_rvalue
*ir
);
568 void simplify_cmp(void);
570 void rename_temp_registers(struct rename_reg_pair
*renames
);
571 void get_first_temp_read(int *first_reads
);
572 void get_first_temp_write(int *first_writes
);
573 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
574 void get_last_temp_write(int *last_writes
);
576 void copy_propagate(void);
577 int eliminate_dead_code(void);
579 void merge_two_dsts(void);
580 void merge_registers(void);
581 void renumber_registers(void);
583 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
584 st_dst_reg
*l
, st_src_reg
*r
,
585 st_src_reg
*cond
, bool cond_swap
);
590 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
591 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
592 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
595 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
598 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
602 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
605 prog
->data
->LinkStatus
= linking_failure
;
609 swizzle_for_size(int size
)
611 static const int size_swizzles
[4] = {
612 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
613 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
614 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
615 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
618 assert((size
>= 1) && (size
<= 4));
619 return size_swizzles
[size
- 1];
623 is_resource_instruction(unsigned opcode
)
626 case TGSI_OPCODE_RESQ
:
627 case TGSI_OPCODE_LOAD
:
628 case TGSI_OPCODE_ATOMUADD
:
629 case TGSI_OPCODE_ATOMXCHG
:
630 case TGSI_OPCODE_ATOMCAS
:
631 case TGSI_OPCODE_ATOMAND
:
632 case TGSI_OPCODE_ATOMOR
:
633 case TGSI_OPCODE_ATOMXOR
:
634 case TGSI_OPCODE_ATOMUMIN
:
635 case TGSI_OPCODE_ATOMUMAX
:
636 case TGSI_OPCODE_ATOMIMIN
:
637 case TGSI_OPCODE_ATOMIMAX
:
645 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
647 return op
->info
->num_dst
;
651 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
653 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
654 op
->info
->num_src
- 1 : op
->info
->num_src
;
657 glsl_to_tgsi_instruction
*
658 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
659 st_dst_reg dst
, st_dst_reg dst1
,
660 st_src_reg src0
, st_src_reg src1
,
661 st_src_reg src2
, st_src_reg src3
)
663 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
664 int num_reladdr
= 0, i
, j
;
665 bool dst_is_64bit
[2];
667 op
= get_opcode(op
, dst
, src0
, src1
);
669 /* If we have to do relative addressing, we want to load the ARL
670 * reg directly for one of the regs, and preload the other reladdr
671 * sources into temps.
673 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
674 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
675 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
676 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
677 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
678 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
680 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
681 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
682 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
683 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
685 if (dst
.reladdr
|| dst
.reladdr2
) {
687 emit_arl(ir
, address_reg
, *dst
.reladdr
);
689 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
693 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
696 assert(num_reladdr
== 0);
698 /* inst->op has only 8 bits. */
699 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
702 inst
->precise
= this->precise
;
703 inst
->info
= tgsi_get_opcode_info(op
);
710 inst
->is_64bit_expanded
= false;
713 inst
->tex_offsets
= NULL
;
714 inst
->tex_offset_num_offset
= 0;
716 inst
->tex_shadow
= 0;
717 /* default to float, for paths where this is not initialized
718 * (since 0==UINT which is likely wrong):
720 inst
->tex_type
= GLSL_TYPE_FLOAT
;
722 /* Update indirect addressing status used by TGSI */
723 if (dst
.reladdr
|| dst
.reladdr2
) {
725 case PROGRAM_STATE_VAR
:
726 case PROGRAM_CONSTANT
:
727 case PROGRAM_UNIFORM
:
728 this->indirect_addr_consts
= true;
730 case PROGRAM_IMMEDIATE
:
731 assert(!"immediates should not have indirect addressing");
738 for (i
= 0; i
< 4; i
++) {
739 if(inst
->src
[i
].reladdr
) {
740 switch(inst
->src
[i
].file
) {
741 case PROGRAM_STATE_VAR
:
742 case PROGRAM_CONSTANT
:
743 case PROGRAM_UNIFORM
:
744 this->indirect_addr_consts
= true;
746 case PROGRAM_IMMEDIATE
:
747 assert(!"immediates should not have indirect addressing");
757 * This section contains the double processing.
758 * GLSL just represents doubles as single channel values,
759 * however most HW and TGSI represent doubles as pairs of register channels.
761 * so we have to fixup destination writemask/index and src swizzle/indexes.
762 * dest writemasks need to translate from single channel write mask
763 * to a dual-channel writemask, but also need to modify the index,
764 * if we are touching the Z,W fields in the pre-translated writemask.
766 * src channels have similiar index modifications along with swizzle
767 * changes to we pick the XY, ZW pairs from the correct index.
769 * GLSL [0].x -> TGSI [0].xy
770 * GLSL [0].y -> TGSI [0].zw
771 * GLSL [0].z -> TGSI [1].xy
772 * GLSL [0].w -> TGSI [1].zw
774 for (j
= 0; j
< 2; j
++) {
775 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
776 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
777 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
778 if (glsl_base_type_is_64bit(type
))
779 dst_is_64bit
[j
] = true;
783 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
784 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
785 glsl_to_tgsi_instruction
*dinst
= NULL
;
786 int initial_src_swz
[4], initial_src_idx
[4];
787 int initial_dst_idx
[2], initial_dst_writemask
[2];
788 /* select the writemask for dst0 or dst1 */
789 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
791 /* copy out the writemask, index and swizzles for all src/dsts. */
792 for (j
= 0; j
< 2; j
++) {
793 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
794 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
797 for (j
= 0; j
< 4; j
++) {
798 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
799 initial_src_idx
[j
] = inst
->src
[j
].index
;
803 * scan all the components in the dst writemask
804 * generate an instruction for each of them if required.
809 int i
= u_bit_scan(&writemask
);
811 /* before emitting the instruction, see if we have to adjust load / store
813 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
814 addr
.file
== PROGRAM_UNDEFINED
) {
815 /* We have to advance the buffer address by 16 */
816 addr
= get_temp(glsl_type::uint_type
);
817 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
818 inst
->src
[0], st_src_reg_for_int(16));
821 /* first time use previous instruction */
825 /* create a new instructions for subsequent attempts */
826 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
831 this->instructions
.push_tail(dinst
);
832 dinst
->is_64bit_expanded
= true;
834 /* modify the destination if we are splitting */
835 for (j
= 0; j
< 2; j
++) {
836 if (dst_is_64bit
[j
]) {
837 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
838 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
840 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
841 dinst
->src
[0] = addr
;
842 if (dinst
->op
!= TGSI_OPCODE_STORE
)
843 dinst
->dst
[j
].index
++;
846 /* if we aren't writing to a double, just get the bit of the initial writemask
848 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
852 /* modify the src registers */
853 for (j
= 0; j
< 4; j
++) {
854 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
856 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
857 dinst
->src
[j
].index
= initial_src_idx
[j
];
859 dinst
->src
[j
].double_reg2
= true;
860 dinst
->src
[j
].index
++;
864 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
866 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
869 /* some opcodes are special case in what they use as sources
870 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
871 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
872 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
873 op
== TGSI_OPCODE_DLDEXP
||
874 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
875 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
882 this->instructions
.push_tail(inst
);
889 glsl_to_tgsi_instruction
*
890 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
892 st_src_reg src0
, st_src_reg src1
,
893 st_src_reg src2
, st_src_reg src3
)
895 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
899 * Determines whether to use an integer, unsigned integer, or float opcode
900 * based on the operands and input opcode, then emits the result.
903 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
905 st_src_reg src0
, st_src_reg src1
)
907 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
909 if (op
== TGSI_OPCODE_MOV
)
912 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
913 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
914 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
915 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
917 if (is_resource_instruction(op
))
919 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
920 type
= GLSL_TYPE_INT64
;
921 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
922 type
= GLSL_TYPE_UINT64
;
923 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
924 type
= GLSL_TYPE_DOUBLE
;
925 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
926 type
= GLSL_TYPE_FLOAT
;
927 else if (native_integers
)
928 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
930 #define case7(c, f, i, u, d, i64, ui64) \
931 case TGSI_OPCODE_##c: \
932 if (type == GLSL_TYPE_UINT64) \
933 op = TGSI_OPCODE_##ui64; \
934 else if (type == GLSL_TYPE_INT64) \
935 op = TGSI_OPCODE_##i64; \
936 else if (type == GLSL_TYPE_DOUBLE) \
937 op = TGSI_OPCODE_##d; \
938 else if (type == GLSL_TYPE_INT) \
939 op = TGSI_OPCODE_##i; \
940 else if (type == GLSL_TYPE_UINT) \
941 op = TGSI_OPCODE_##u; \
943 op = TGSI_OPCODE_##f; \
945 #define case5(c, f, i, u, d) \
946 case TGSI_OPCODE_##c: \
947 if (type == GLSL_TYPE_DOUBLE) \
948 op = TGSI_OPCODE_##d; \
949 else if (type == GLSL_TYPE_INT) \
950 op = TGSI_OPCODE_##i; \
951 else if (type == GLSL_TYPE_UINT) \
952 op = TGSI_OPCODE_##u; \
954 op = TGSI_OPCODE_##f; \
957 #define case4(c, f, i, u) \
958 case TGSI_OPCODE_##c: \
959 if (type == GLSL_TYPE_INT) \
960 op = TGSI_OPCODE_##i; \
961 else if (type == GLSL_TYPE_UINT) \
962 op = TGSI_OPCODE_##u; \
964 op = TGSI_OPCODE_##f; \
967 #define case3(f, i, u) case4(f, f, i, u)
968 #define case6d(f, i, u, d, i64, u64) case7(f, f, i, u, d, i64, u64)
969 #define case3fid(f, i, d) case5(f, f, i, i, d)
970 #define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
971 #define case2fi(f, i) case4(f, f, i, i)
972 #define case2iu(i, u) case4(i, LAST, i, u)
974 #define case2iu64(i, i64) case7(i, LAST, i, i, LAST, i64, i64)
975 #define case4iu64(i, u, i64, u64) case7(i, LAST, i, u, LAST, i64, u64)
977 #define casecomp(c, f, i, u, d, i64, ui64) \
978 case TGSI_OPCODE_##c: \
979 if (type == GLSL_TYPE_INT64) \
980 op = TGSI_OPCODE_##i64; \
981 else if (type == GLSL_TYPE_UINT64) \
982 op = TGSI_OPCODE_##ui64; \
983 else if (type == GLSL_TYPE_DOUBLE) \
984 op = TGSI_OPCODE_##d; \
985 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
986 op = TGSI_OPCODE_##i; \
987 else if (type == GLSL_TYPE_UINT) \
988 op = TGSI_OPCODE_##u; \
989 else if (native_integers) \
990 op = TGSI_OPCODE_##f; \
992 op = TGSI_OPCODE_##c; \
996 case3fid64(ADD
, UADD
, DADD
, U64ADD
);
997 case3fid64(MUL
, UMUL
, DMUL
, U64MUL
);
998 case3fid(MAD
, UMAD
, DMAD
);
999 case3fid(FMA
, UMAD
, DFMA
);
1000 case6d(DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
1001 case6d(MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
1002 case6d(MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
1003 case4iu64(MOD
, UMOD
, I64MOD
, U64MOD
);
1005 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
1006 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
1007 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
1008 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
1010 case2iu64(SHL
, U64SHL
);
1011 case4iu64(ISHR
, USHR
, I64SHR
, U64SHR
);
1013 case3fid64(SSG
, ISSG
, DSSG
, I64SSG
);
1015 case2iu(IBFE
, UBFE
);
1016 case2iu(IMSB
, UMSB
);
1017 case2iu(IMUL_HI
, UMUL_HI
);
1019 case3fid(SQRT
, SQRT
, DSQRT
);
1021 case3fid(RCP
, RCP
, DRCP
);
1022 case3fid(RSQ
, RSQ
, DRSQ
);
1024 case3fid(FRC
, FRC
, DFRAC
);
1025 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1026 case3fid(CEIL
, CEIL
, DCEIL
);
1027 case3fid(FLR
, FLR
, DFLR
);
1028 case3fid(ROUND
, ROUND
, DROUND
);
1030 case2iu(ATOMIMAX
, ATOMUMAX
);
1031 case2iu(ATOMIMIN
, ATOMUMIN
);
1036 assert(op
!= TGSI_OPCODE_LAST
);
1040 glsl_to_tgsi_instruction
*
1041 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1042 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1045 static const unsigned dot_opcodes
[] = {
1046 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1049 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1053 * Emits TGSI scalar opcodes to produce unique answers across channels.
1055 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1056 * channel determines the result across all channels. So to do a vec4
1057 * of this operation, we want to emit a scalar per source channel used
1058 * to produce dest channels.
1061 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1063 st_src_reg orig_src0
, st_src_reg orig_src1
)
1066 int done_mask
= ~dst
.writemask
;
1068 /* TGSI RCP is a scalar operation splatting results to all channels,
1069 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1072 for (i
= 0; i
< 4; i
++) {
1073 GLuint this_mask
= (1 << i
);
1074 st_src_reg src0
= orig_src0
;
1075 st_src_reg src1
= orig_src1
;
1077 if (done_mask
& this_mask
)
1080 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1081 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1082 for (j
= i
+ 1; j
< 4; j
++) {
1083 /* If there is another enabled component in the destination that is
1084 * derived from the same inputs, generate its value on this pass as
1087 if (!(done_mask
& (1 << j
)) &&
1088 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1089 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1090 this_mask
|= (1 << j
);
1093 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1094 src0_swiz
, src0_swiz
);
1095 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1096 src1_swiz
, src1_swiz
);
1098 dst
.writemask
= this_mask
;
1099 emit_asm(ir
, op
, dst
, src0
, src1
);
1100 done_mask
|= this_mask
;
1105 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1106 st_dst_reg dst
, st_src_reg src0
)
1108 st_src_reg undef
= undef_src
;
1110 undef
.swizzle
= SWIZZLE_XXXX
;
1112 emit_scalar(ir
, op
, dst
, src0
, undef
);
1116 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1117 st_dst_reg dst
, st_src_reg src0
)
1119 int op
= TGSI_OPCODE_ARL
;
1121 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1122 op
= TGSI_OPCODE_UARL
;
1124 assert(dst
.file
== PROGRAM_ADDRESS
);
1125 if (dst
.index
>= this->num_address_regs
)
1126 this->num_address_regs
= dst
.index
+ 1;
1128 emit_asm(NULL
, op
, dst
, src0
);
1132 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1133 gl_constant_value values
[8], int size
, int datatype
,
1134 uint16_t *swizzle_out
)
1136 if (file
== PROGRAM_CONSTANT
) {
1137 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1138 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1139 size
, datatype
, &swizzle
);
1141 *swizzle_out
= swizzle
;
1145 assert(file
== PROGRAM_IMMEDIATE
);
1148 immediate_storage
*entry
;
1149 int size32
= size
* ((datatype
== GL_DOUBLE
||
1150 datatype
== GL_INT64_ARB
||
1151 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1154 /* Search immediate storage to see if we already have an identical
1155 * immediate that we can use instead of adding a duplicate entry.
1157 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1158 immediate_storage
*tmp
= entry
;
1160 for (i
= 0; i
* 4 < size32
; i
++) {
1161 int slot_size
= MIN2(size32
- (i
* 4), 4);
1162 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1164 if (memcmp(tmp
->values
, &values
[i
* 4],
1165 slot_size
* sizeof(gl_constant_value
)))
1168 /* Everything matches, keep going until the full size is matched */
1169 tmp
= (immediate_storage
*)tmp
->next
;
1172 /* The full value matched */
1173 if (i
* 4 >= size32
)
1179 for (i
= 0; i
* 4 < size32
; i
++) {
1180 int slot_size
= MIN2(size32
- (i
* 4), 4);
1181 /* Add this immediate to the list. */
1182 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1183 this->immediates
.push_tail(entry
);
1184 this->num_immediates
++;
1190 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1192 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1193 union gl_constant_value uval
;
1196 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1202 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1204 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1205 union gl_constant_value uval
[2];
1207 memcpy(uval
, &val
, sizeof(uval
));
1208 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1209 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1214 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1216 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1217 union gl_constant_value uval
;
1219 assert(native_integers
);
1222 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1228 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1230 if (native_integers
)
1231 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1232 st_src_reg_for_int(val
);
1234 return st_src_reg_for_float(val
);
1238 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1240 return type
->count_attribute_slots(is_vs_input
);
1244 type_size(const struct glsl_type
*type
)
1246 return type
->count_attribute_slots(false);
1250 * If the given GLSL type is an array or matrix or a structure containing
1251 * an array/matrix member, return true. Else return false.
1253 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1254 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1255 * we have an array that might be indexed with a variable, we need to use
1256 * the later storage type.
1259 type_has_array_or_matrix(const glsl_type
*type
)
1261 if (type
->is_array() || type
->is_matrix())
1264 if (type
->is_record()) {
1265 for (unsigned i
= 0; i
< type
->length
; i
++) {
1266 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1277 * In the initial pass of codegen, we assign temporary numbers to
1278 * intermediate results. (not SSA -- variable assignments will reuse
1282 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1286 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1291 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1292 if (next_array
>= max_num_arrays
) {
1293 max_num_arrays
+= 32;
1294 array_sizes
= (unsigned*)
1295 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1298 src
.file
= PROGRAM_ARRAY
;
1300 src
.array_id
= next_array
+ 1;
1301 array_sizes
[next_array
] = type_size(type
);
1305 src
.file
= PROGRAM_TEMPORARY
;
1306 src
.index
= next_temp
;
1307 next_temp
+= type_size(type
);
1310 if (type
->is_array() || type
->is_record()) {
1311 src
.swizzle
= SWIZZLE_NOOP
;
1313 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1320 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1322 struct hash_entry
*entry
;
1324 entry
= _mesa_hash_table_search(this->variables
, var
);
1328 return (variable_storage
*)entry
->data
;
1332 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1334 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1335 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1336 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1339 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1341 const ir_state_slot
*const slots
= ir
->get_state_slots();
1342 assert(slots
!= NULL
);
1344 /* Check if this statevar's setup in the STATE file exactly
1345 * matches how we'll want to reference it as a
1346 * struct/array/whatever. If not, then we need to move it into
1347 * temporary storage and hope that it'll get copy-propagated
1350 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1351 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1356 variable_storage
*storage
;
1358 if (i
== ir
->get_num_state_slots()) {
1359 /* We'll set the index later. */
1360 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1362 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1366 /* The variable_storage constructor allocates slots based on the size
1367 * of the type. However, this had better match the number of state
1368 * elements that we're going to copy into the new temporary.
1370 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1372 dst
= st_dst_reg(get_temp(ir
->type
));
1374 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1377 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1381 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1382 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1383 (gl_state_index
*)slots
[i
].tokens
);
1385 if (storage
->file
== PROGRAM_STATE_VAR
) {
1386 if (storage
->index
== -1) {
1387 storage
->index
= index
;
1389 assert(index
== storage
->index
+ (int)i
);
1392 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1393 * the data being moved since MOV does not care about the type of
1394 * data it is moving, and we don't want to declare registers with
1395 * array or struct types.
1397 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1398 src
.swizzle
= slots
[i
].swizzle
;
1399 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1400 /* even a float takes up a whole vec4 reg in a struct/array. */
1405 if (storage
->file
== PROGRAM_TEMPORARY
&&
1406 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1407 fail_link(this->shader_program
,
1408 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1409 ir
->name
, dst
.index
- storage
->index
,
1410 type_size(ir
->type
));
1416 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1418 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1420 visit_exec_list(&ir
->body_instructions
, this);
1422 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1426 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1429 case ir_loop_jump::jump_break
:
1430 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1432 case ir_loop_jump::jump_continue
:
1433 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1440 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1447 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1449 /* Ignore function bodies other than main() -- we shouldn't see calls to
1450 * them since they should all be inlined before we get to glsl_to_tgsi.
1452 if (strcmp(ir
->name
, "main") == 0) {
1453 const ir_function_signature
*sig
;
1456 sig
= ir
->matching_signature(NULL
, &empty
, false);
1460 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1467 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1469 int nonmul_operand
= 1 - mul_operand
;
1471 st_dst_reg result_dst
;
1473 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1474 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1477 expr
->operands
[0]->accept(this);
1479 expr
->operands
[1]->accept(this);
1481 ir
->operands
[nonmul_operand
]->accept(this);
1484 this->result
= get_temp(ir
->type
);
1485 result_dst
= st_dst_reg(this->result
);
1486 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1487 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1493 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1495 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1496 * implemented using multiplication, and logical-or is implemented using
1497 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1498 * As result, the logical expression (a & !b) can be rewritten as:
1502 * - (a * 1) - (a * b)
1506 * This final expression can be implemented as a single MAD(a, -b, a)
1510 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1512 const int other_operand
= 1 - try_operand
;
1515 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1516 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1519 ir
->operands
[other_operand
]->accept(this);
1521 expr
->operands
[0]->accept(this);
1524 b
.negate
= ~b
.negate
;
1526 this->result
= get_temp(ir
->type
);
1527 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1533 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1534 st_src_reg
*reg
, int *num_reladdr
)
1536 if (!reg
->reladdr
&& !reg
->reladdr2
)
1539 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1540 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1542 if (*num_reladdr
!= 1) {
1543 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1545 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1553 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1555 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1557 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1559 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1560 if (try_emit_mad(ir
, 1))
1562 if (try_emit_mad(ir
, 0))
1566 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1568 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1569 if (try_emit_mad_for_and_not(ir
, 1))
1571 if (try_emit_mad_for_and_not(ir
, 0))
1575 if (ir
->operation
== ir_quadop_vector
)
1576 assert(!"ir_quadop_vector should have been lowered");
1578 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1579 this->result
.file
= PROGRAM_UNDEFINED
;
1580 ir
->operands
[operand
]->accept(this);
1581 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1582 printf("Failed to get tree for expression operand:\n");
1583 ir
->operands
[operand
]->print();
1587 op
[operand
] = this->result
;
1589 /* Matrix expression operands should have been broken down to vector
1590 * operations already.
1592 assert(!ir
->operands
[operand
]->type
->is_matrix());
1595 visit_expression(ir
, op
);
1598 /* The non-recursive part of the expression visitor lives in a separate
1599 * function and should be prevented from being inlined, to avoid a stack
1600 * explosion when deeply nested expressions are visited.
1603 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1605 st_src_reg result_src
;
1606 st_dst_reg result_dst
;
1608 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1609 if (ir
->operands
[1]) {
1610 vector_elements
= MAX2(vector_elements
,
1611 ir
->operands
[1]->type
->vector_elements
);
1614 this->result
.file
= PROGRAM_UNDEFINED
;
1616 /* Storage for our result. Ideally for an assignment we'd be using
1617 * the actual storage for the result here, instead.
1619 result_src
= get_temp(ir
->type
);
1620 /* convenience for the emit functions below. */
1621 result_dst
= st_dst_reg(result_src
);
1622 /* Limit writes to the channels that will be used by result_src later.
1623 * This does limit this temp's use as a temporary for multi-instruction
1626 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1628 switch (ir
->operation
) {
1629 case ir_unop_logic_not
:
1630 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1631 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1633 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1634 * older GPUs implement SEQ using multiple instructions (i915 uses two
1635 * SGE instructions and a MUL instruction). Since our logic values are
1636 * 0.0 and 1.0, 1-x also implements !x.
1638 op
[0].negate
= ~op
[0].negate
;
1639 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1643 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1644 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1645 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1646 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1647 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1648 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1650 op
[0].negate
= ~op
[0].negate
;
1654 case ir_unop_subroutine_to_int
:
1655 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1658 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1659 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1660 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1661 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1662 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1663 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1665 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1668 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1671 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1675 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1678 assert(!"not reached: should be handled by exp_to_exp2");
1681 assert(!"not reached: should be handled by log_to_log2");
1684 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1687 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1690 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1692 case ir_unop_saturate
: {
1693 glsl_to_tgsi_instruction
*inst
;
1694 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1695 inst
->saturate
= true;
1700 case ir_unop_dFdx_coarse
:
1701 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1703 case ir_unop_dFdx_fine
:
1704 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1707 case ir_unop_dFdy_coarse
:
1708 case ir_unop_dFdy_fine
:
1710 /* The X component contains 1 or -1 depending on whether the framebuffer
1711 * is a FBO or the window system buffer, respectively.
1712 * It is then multiplied with the source operand of DDY.
1714 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1715 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1717 unsigned transform_y_index
=
1718 _mesa_add_state_reference(this->prog
->Parameters
,
1721 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1723 glsl_type::vec4_type
);
1724 transform_y
.swizzle
= SWIZZLE_XXXX
;
1726 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1728 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1729 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1730 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1734 case ir_unop_frexp_sig
:
1735 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1738 case ir_unop_frexp_exp
:
1739 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1742 case ir_unop_noise
: {
1743 /* At some point, a motivated person could add a better
1744 * implementation of noise. Currently not even the nvidia
1745 * binary drivers do anything more than this. In any case, the
1746 * place to do this is in the GL state tracker, not the poor
1749 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1754 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1757 op
[1].negate
= ~op
[1].negate
;
1758 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1762 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1765 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1768 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1769 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1771 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1775 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1777 case ir_binop_greater
:
1778 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1780 case ir_binop_lequal
:
1781 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1783 case ir_binop_gequal
:
1784 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1786 case ir_binop_equal
:
1787 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1789 case ir_binop_nequal
:
1790 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1792 case ir_binop_all_equal
:
1793 /* "==" operator producing a scalar boolean. */
1794 if (ir
->operands
[0]->type
->is_vector() ||
1795 ir
->operands
[1]->type
->is_vector()) {
1796 st_src_reg temp
= get_temp(native_integers
?
1797 glsl_type::uvec4_type
:
1798 glsl_type::vec4_type
);
1800 if (native_integers
) {
1801 st_dst_reg temp_dst
= st_dst_reg(temp
);
1802 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1804 if (ir
->operands
[0]->type
->is_boolean() &&
1805 ir
->operands
[1]->as_constant() &&
1806 ir
->operands
[1]->as_constant()->is_one()) {
1807 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1809 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1812 /* Emit 1-3 AND operations to combine the SEQ results. */
1813 switch (ir
->operands
[0]->type
->vector_elements
) {
1817 temp_dst
.writemask
= WRITEMASK_Y
;
1818 temp1
.swizzle
= SWIZZLE_YYYY
;
1819 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1820 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1823 temp_dst
.writemask
= WRITEMASK_X
;
1824 temp1
.swizzle
= SWIZZLE_XXXX
;
1825 temp2
.swizzle
= SWIZZLE_YYYY
;
1826 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1827 temp_dst
.writemask
= WRITEMASK_Y
;
1828 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1829 temp2
.swizzle
= SWIZZLE_WWWW
;
1830 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1833 temp1
.swizzle
= SWIZZLE_XXXX
;
1834 temp2
.swizzle
= SWIZZLE_YYYY
;
1835 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1837 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1839 /* After the dot-product, the value will be an integer on the
1840 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1842 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1844 /* Negating the result of the dot-product gives values on the range
1845 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1846 * This is achieved using SGE.
1848 st_src_reg sge_src
= result_src
;
1849 sge_src
.negate
= ~sge_src
.negate
;
1850 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1853 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1856 case ir_binop_any_nequal
:
1857 /* "!=" operator producing a scalar boolean. */
1858 if (ir
->operands
[0]->type
->is_vector() ||
1859 ir
->operands
[1]->type
->is_vector()) {
1860 st_src_reg temp
= get_temp(native_integers
?
1861 glsl_type::uvec4_type
:
1862 glsl_type::vec4_type
);
1863 if (ir
->operands
[0]->type
->is_boolean() &&
1864 ir
->operands
[1]->as_constant() &&
1865 ir
->operands
[1]->as_constant()->is_zero()) {
1866 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1868 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1871 if (native_integers
) {
1872 st_dst_reg temp_dst
= st_dst_reg(temp
);
1873 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1875 /* Emit 1-3 OR operations to combine the SNE results. */
1876 switch (ir
->operands
[0]->type
->vector_elements
) {
1880 temp_dst
.writemask
= WRITEMASK_Y
;
1881 temp1
.swizzle
= SWIZZLE_YYYY
;
1882 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1883 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1886 temp_dst
.writemask
= WRITEMASK_X
;
1887 temp1
.swizzle
= SWIZZLE_XXXX
;
1888 temp2
.swizzle
= SWIZZLE_YYYY
;
1889 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1890 temp_dst
.writemask
= WRITEMASK_Y
;
1891 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1892 temp2
.swizzle
= SWIZZLE_WWWW
;
1893 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1896 temp1
.swizzle
= SWIZZLE_XXXX
;
1897 temp2
.swizzle
= SWIZZLE_YYYY
;
1898 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1900 /* After the dot-product, the value will be an integer on the
1901 * range [0,4]. Zero stays zero, and positive values become 1.0.
1903 glsl_to_tgsi_instruction
*const dp
=
1904 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1905 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1906 /* The clamping to [0,1] can be done for free in the fragment
1907 * shader with a saturate.
1909 dp
->saturate
= true;
1911 /* Negating the result of the dot-product gives values on the range
1912 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1913 * achieved using SLT.
1915 st_src_reg slt_src
= result_src
;
1916 slt_src
.negate
= ~slt_src
.negate
;
1917 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1921 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1925 case ir_binop_logic_xor
:
1926 if (native_integers
)
1927 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1929 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1932 case ir_binop_logic_or
: {
1933 if (native_integers
) {
1934 /* If integers are used as booleans, we can use an actual "or"
1937 assert(native_integers
);
1938 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1940 /* After the addition, the value will be an integer on the
1941 * range [0,2]. Zero stays zero, and positive values become 1.0.
1943 glsl_to_tgsi_instruction
*add
=
1944 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1945 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1946 /* The clamping to [0,1] can be done for free in the fragment
1947 * shader with a saturate if floats are being used as boolean values.
1949 add
->saturate
= true;
1951 /* Negating the result of the addition gives values on the range
1952 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1953 * is achieved using SLT.
1955 st_src_reg slt_src
= result_src
;
1956 slt_src
.negate
= ~slt_src
.negate
;
1957 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1963 case ir_binop_logic_and
:
1964 /* If native integers are disabled, the bool args are stored as float 0.0
1965 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1966 * actual AND opcode.
1968 if (native_integers
)
1969 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1971 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1975 assert(ir
->operands
[0]->type
->is_vector());
1976 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1977 emit_dp(ir
, result_dst
, op
[0], op
[1],
1978 ir
->operands
[0]->type
->vector_elements
);
1983 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1985 /* This is the only instruction sequence that makes the game "Risen"
1986 * render correctly. ABS is not required for the game, but since GLSL
1987 * declares negative values as "undefined", allowing us to do whatever
1988 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1991 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1992 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1996 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1999 if (native_integers
) {
2000 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
2003 /* fallthrough to next case otherwise */
2005 if (native_integers
) {
2006 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
2009 /* fallthrough to next case otherwise */
2012 case ir_unop_i642u64
:
2013 case ir_unop_u642i64
:
2014 /* Converting between signed and unsigned integers is a no-op. */
2016 result_src
.type
= result_dst
.type
;
2019 if (native_integers
) {
2020 /* Booleans are stored as integers using ~0 for true and 0 for false.
2021 * GLSL requires that int(bool) return 1 for true and 0 for false.
2022 * This conversion is done with AND, but it could be done with NEG.
2024 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
2026 /* Booleans and integers are both stored as floats when native
2027 * integers are disabled.
2033 if (native_integers
)
2034 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2036 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2039 if (native_integers
)
2040 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2042 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2044 case ir_unop_bitcast_f2i
:
2045 case ir_unop_bitcast_f2u
:
2046 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2047 if (op
[0].negate
|| op
[0].abs
)
2048 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2051 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2054 case ir_unop_bitcast_i2f
:
2055 case ir_unop_bitcast_u2f
:
2057 result_src
.type
= GLSL_TYPE_FLOAT
;
2060 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2063 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2066 if (native_integers
)
2067 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2069 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2071 case ir_unop_bitcast_u642d
:
2072 case ir_unop_bitcast_i642d
:
2074 result_src
.type
= GLSL_TYPE_DOUBLE
;
2076 case ir_unop_bitcast_d2i64
:
2078 result_src
.type
= GLSL_TYPE_INT64
;
2080 case ir_unop_bitcast_d2u64
:
2082 result_src
.type
= GLSL_TYPE_UINT64
;
2085 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2088 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2091 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2093 case ir_unop_round_even
:
2094 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2097 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2101 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2104 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2107 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2110 case ir_unop_bit_not
:
2111 if (native_integers
) {
2112 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2116 if (native_integers
) {
2117 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2120 case ir_binop_lshift
:
2121 case ir_binop_rshift
:
2122 if (native_integers
) {
2123 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
2127 if (glsl_base_type_is_64bit(op
[0].type
)) {
2128 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
2131 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
2132 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
2137 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
2140 case ir_binop_bit_and
:
2141 if (native_integers
) {
2142 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2145 case ir_binop_bit_xor
:
2146 if (native_integers
) {
2147 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2150 case ir_binop_bit_or
:
2151 if (native_integers
) {
2152 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2156 assert(!"GLSL 1.30 features unsupported");
2159 case ir_binop_ubo_load
: {
2160 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2161 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2162 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2163 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2164 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2167 cbuf
.type
= ir
->type
->base_type
;
2168 cbuf
.file
= PROGRAM_CONSTANT
;
2170 cbuf
.reladdr
= NULL
;
2174 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2176 if (const_offset_ir
) {
2177 /* Constant index into constant buffer */
2178 cbuf
.reladdr
= NULL
;
2179 cbuf
.index
= const_offset
/ 16;
2182 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2183 st_src_reg offset
= op
[1];
2185 /* The OpenGL spec is written in such a way that accesses with
2186 * non-constant offset are almost always vec4-aligned. The only
2187 * exception to this are members of structs in arrays of structs:
2188 * each struct in an array of structs is at least vec4-aligned,
2189 * but single-element and [ui]vec2 members of the struct may be at
2190 * an offset that is not a multiple of 16 bytes.
2192 * Here, we extract that offset, relying on previous passes to always
2193 * generate offset expressions of the form (+ expr constant_offset).
2195 * Note that the std430 layout, which allows more cases of alignment
2196 * less than vec4 in arrays, is not supported for uniform blocks, so
2197 * we do not have to deal with it here.
2199 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2200 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2201 if (const_offset_ir
) {
2202 const_offset
= const_offset_ir
->value
.u
[0];
2203 cbuf
.index
= const_offset
/ 16;
2204 offset_expr
->operands
[0]->accept(this);
2205 offset
= this->result
;
2209 /* Relative/variable index into constant buffer */
2210 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2211 st_src_reg_for_int(4));
2212 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2213 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2216 if (const_uniform_block
) {
2217 /* Constant constant buffer */
2218 cbuf
.reladdr2
= NULL
;
2219 cbuf
.index2D
= const_block
;
2220 cbuf
.has_index2
= true;
2223 /* Relative/variable constant buffer */
2224 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2226 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2227 cbuf
.has_index2
= true;
2230 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2231 if (glsl_base_type_is_64bit(cbuf
.type
))
2232 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2233 const_offset
% 16 / 8,
2234 const_offset
% 16 / 8,
2235 const_offset
% 16 / 8);
2237 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2238 const_offset
% 16 / 4,
2239 const_offset
% 16 / 4,
2240 const_offset
% 16 / 4);
2242 if (ir
->type
->is_boolean()) {
2243 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2245 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2250 /* note: we have to reorder the three args here */
2251 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2254 if (this->ctx
->Const
.NativeIntegers
)
2255 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2257 op
[0].negate
= ~op
[0].negate
;
2258 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2261 case ir_triop_bitfield_extract
:
2262 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2264 case ir_quadop_bitfield_insert
:
2265 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2267 case ir_unop_bitfield_reverse
:
2268 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2270 case ir_unop_bit_count
:
2271 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2273 case ir_unop_find_msb
:
2274 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2276 case ir_unop_find_lsb
:
2277 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2279 case ir_binop_imul_high
:
2280 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2283 /* In theory, MAD is incorrect here. */
2285 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2287 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2289 case ir_unop_interpolate_at_centroid
:
2290 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2292 case ir_binop_interpolate_at_offset
: {
2293 /* The y coordinate needs to be flipped for the default fb */
2294 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2295 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2297 unsigned transform_y_index
=
2298 _mesa_add_state_reference(this->prog
->Parameters
,
2301 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2303 glsl_type::vec4_type
);
2304 transform_y
.swizzle
= SWIZZLE_XXXX
;
2306 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2307 st_dst_reg temp_dst
= st_dst_reg(temp
);
2309 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2310 temp_dst
.writemask
= WRITEMASK_Y
;
2311 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2312 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2315 case ir_binop_interpolate_at_sample
:
2316 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2320 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2323 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2326 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2329 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2332 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2335 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2337 case ir_unop_unpack_double_2x32
:
2338 case ir_unop_pack_double_2x32
:
2339 case ir_unop_unpack_int_2x32
:
2340 case ir_unop_pack_int_2x32
:
2341 case ir_unop_unpack_uint_2x32
:
2342 case ir_unop_pack_uint_2x32
:
2343 case ir_unop_unpack_sampler_2x32
:
2344 case ir_unop_pack_sampler_2x32
:
2345 case ir_unop_unpack_image_2x32
:
2346 case ir_unop_pack_image_2x32
:
2347 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2350 case ir_binop_ldexp
:
2351 if (ir
->operands
[0]->type
->is_double()) {
2352 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2354 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2358 case ir_unop_pack_half_2x16
:
2359 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2361 case ir_unop_unpack_half_2x16
:
2362 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2365 case ir_unop_get_buffer_size
: {
2366 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2369 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2370 (const_offset
? const_offset
->value
.u
[0] : 0),
2372 if (!const_offset
) {
2373 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2374 *buffer
.reladdr
= op
[0];
2375 emit_arl(ir
, sampler_reladdr
, op
[0]);
2377 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2383 case ir_unop_b2i64
: {
2384 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2385 st_dst_reg temp_dst
= st_dst_reg(temp
);
2386 unsigned orig_swz
= op
[0].swizzle
;
2388 * To convert unsigned to 64-bit:
2389 * zero Y channel, copy X channel.
2391 temp_dst
.writemask
= WRITEMASK_Y
;
2392 if (vector_elements
> 1)
2393 temp_dst
.writemask
|= WRITEMASK_W
;
2394 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2395 temp_dst
.writemask
= WRITEMASK_X
;
2396 if (vector_elements
> 1)
2397 temp_dst
.writemask
|= WRITEMASK_Z
;
2398 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2399 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2400 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2401 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2403 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2405 result_src
.type
= GLSL_TYPE_UINT64
;
2406 if (vector_elements
> 2) {
2407 /* Subtle: We rely on the fact that get_temp here returns the next
2408 * TGSI temporary register directly after the temp register used for
2409 * the first two components, so that the result gets picked up
2412 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2413 st_dst_reg temp_dst
= st_dst_reg(temp
);
2414 temp_dst
.writemask
= WRITEMASK_Y
;
2415 if (vector_elements
> 3)
2416 temp_dst
.writemask
|= WRITEMASK_W
;
2417 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2419 temp_dst
.writemask
= WRITEMASK_X
;
2420 if (vector_elements
> 3)
2421 temp_dst
.writemask
|= WRITEMASK_Z
;
2422 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2423 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2424 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2425 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2427 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2434 case ir_unop_i642u
: {
2435 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2436 st_dst_reg temp_dst
= st_dst_reg(temp
);
2437 unsigned orig_swz
= op
[0].swizzle
;
2438 unsigned orig_idx
= op
[0].index
;
2440 temp_dst
.writemask
= WRITEMASK_X
;
2442 for (el
= 0; el
< vector_elements
; el
++) {
2443 unsigned swz
= GET_SWZ(orig_swz
, el
);
2445 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2447 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2449 op
[0].index
= orig_idx
+ 1;
2450 op
[0].type
= GLSL_TYPE_UINT
;
2451 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2452 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2455 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2456 result_src
.type
= GLSL_TYPE_UINT
;
2458 result_src
.type
= GLSL_TYPE_INT
;
2462 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2465 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2468 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2471 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2474 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2477 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2480 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2483 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2486 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2489 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2492 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2494 /* these might be needed */
2495 case ir_unop_pack_snorm_2x16
:
2496 case ir_unop_pack_unorm_2x16
:
2497 case ir_unop_pack_snorm_4x8
:
2498 case ir_unop_pack_unorm_4x8
:
2500 case ir_unop_unpack_snorm_2x16
:
2501 case ir_unop_unpack_unorm_2x16
:
2502 case ir_unop_unpack_snorm_4x8
:
2503 case ir_unop_unpack_unorm_4x8
:
2505 case ir_quadop_vector
:
2506 case ir_binop_vector_extract
:
2507 case ir_triop_vector_insert
:
2508 case ir_binop_carry
:
2509 case ir_binop_borrow
:
2510 case ir_unop_ssbo_unsized_array_length
:
2511 /* This operation is not supported, or should have already been handled.
2513 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2517 this->result
= result_src
;
2522 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2528 /* Note that this is only swizzles in expressions, not those on the left
2529 * hand side of an assignment, which do write masking. See ir_assignment
2533 ir
->val
->accept(this);
2535 assert(src
.file
!= PROGRAM_UNDEFINED
);
2536 assert(ir
->type
->vector_elements
> 0);
2538 for (i
= 0; i
< 4; i
++) {
2539 if (i
< ir
->type
->vector_elements
) {
2542 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2545 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2548 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2551 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2555 /* If the type is smaller than a vec4, replicate the last
2558 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2562 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2567 /* Test if the variable is an array. Note that geometry and
2568 * tessellation shader inputs are outputs are always arrays (except
2569 * for patch inputs), so only the array element type is considered.
2572 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2574 const glsl_type
*type
= var
->type
;
2576 *remove_array
= false;
2578 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2579 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2582 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2583 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2584 stage
== MESA_SHADER_TESS_CTRL
) &&
2586 if (!var
->type
->is_array())
2587 return false; /* a system value probably */
2589 type
= var
->type
->fields
.array
;
2590 *remove_array
= true;
2593 return type
->is_array() || type
->is_matrix();
2597 st_translate_interp_loc(ir_variable
*var
)
2599 if (var
->data
.centroid
)
2600 return TGSI_INTERPOLATE_LOC_CENTROID
;
2601 else if (var
->data
.sample
)
2602 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2604 return TGSI_INTERPOLATE_LOC_CENTER
;
2608 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2610 variable_storage
*entry
= find_variable_storage(ir
->var
);
2611 ir_variable
*var
= ir
->var
;
2615 switch (var
->data
.mode
) {
2616 case ir_var_uniform
:
2617 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2618 var
->data
.param_index
);
2619 _mesa_hash_table_insert(this->variables
, var
, entry
);
2621 case ir_var_shader_in
: {
2622 /* The linker assigns locations for varyings and attributes,
2623 * including deprecated builtins (like gl_Color), user-assign
2624 * generic attributes (glBindVertexLocation), and
2625 * user-defined varyings.
2627 assert(var
->data
.location
!= -1);
2629 const glsl_type
*type_without_array
= var
->type
->without_array();
2630 struct inout_decl
*decl
= &inputs
[num_inputs
];
2631 unsigned component
= var
->data
.location_frac
;
2632 unsigned num_components
;
2635 if (type_without_array
->is_64bit())
2636 component
= component
/ 2;
2637 if (type_without_array
->vector_elements
)
2638 num_components
= type_without_array
->vector_elements
;
2642 decl
->mesa_index
= var
->data
.location
;
2643 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2644 decl
->interp_loc
= st_translate_interp_loc(var
);
2645 decl
->base_type
= type_without_array
->base_type
;
2646 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2648 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2649 decl
->array_id
= num_input_arrays
+ 1;
2656 decl
->size
= type_size(var
->type
->fields
.array
);
2658 decl
->size
= type_size(var
->type
);
2660 entry
= new(mem_ctx
) variable_storage(var
,
2664 entry
->component
= component
;
2666 _mesa_hash_table_insert(this->variables
, var
, entry
);
2670 case ir_var_shader_out
: {
2671 assert(var
->data
.location
!= -1);
2673 const glsl_type
*type_without_array
= var
->type
->without_array();
2674 struct inout_decl
*decl
= &outputs
[num_outputs
];
2675 unsigned component
= var
->data
.location_frac
;
2676 unsigned num_components
;
2679 if (type_without_array
->is_64bit())
2680 component
= component
/ 2;
2681 if (type_without_array
->vector_elements
)
2682 num_components
= type_without_array
->vector_elements
;
2686 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2687 decl
->base_type
= type_without_array
->base_type
;
2688 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2689 if (var
->data
.stream
& (1u << 31)) {
2690 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2692 assert(var
->data
.stream
< 4);
2693 decl
->gs_out_streams
= 0;
2694 for (unsigned i
= 0; i
< num_components
; ++i
)
2695 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2698 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2699 decl
->array_id
= num_output_arrays
+ 1;
2700 num_output_arrays
++;
2706 decl
->size
= type_size(var
->type
->fields
.array
);
2708 decl
->size
= type_size(var
->type
);
2710 if (var
->data
.fb_fetch_output
) {
2711 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2712 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2713 var
->type
, component
, decl
->array_id
);
2714 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2715 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2718 entry
= new(mem_ctx
) variable_storage(var
,
2723 entry
->component
= component
;
2725 _mesa_hash_table_insert(this->variables
, var
, entry
);
2729 case ir_var_system_value
:
2730 entry
= new(mem_ctx
) variable_storage(var
,
2731 PROGRAM_SYSTEM_VALUE
,
2732 var
->data
.location
);
2735 case ir_var_temporary
:
2736 st_src_reg src
= get_temp(var
->type
);
2738 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2740 _mesa_hash_table_insert(this->variables
, var
, entry
);
2746 printf("Failed to make storage for %s\n", var
->name
);
2751 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2752 entry
->component
, entry
->array_id
);
2753 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2754 this->result
.is_double_vertex_input
= true;
2755 if (!native_integers
)
2756 this->result
.type
= GLSL_TYPE_FLOAT
;
2760 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2761 GLbitfield64
* usage_mask
,
2762 GLbitfield64 double_usage_mask
,
2763 GLbitfield
* patch_usage_mask
)
2768 /* Fix array declarations by removing unused array elements at both ends
2769 * of the arrays. For example, mat4[3] where only mat[1] is used.
2771 for (i
= 0; i
< count
; i
++) {
2772 struct inout_decl
*decl
= &decls
[i
];
2773 if (!decl
->array_id
)
2776 /* Shrink the beginning. */
2777 for (j
= 0; j
< (int)decl
->size
; j
++) {
2778 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2779 if (*patch_usage_mask
&
2780 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2784 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2786 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2795 /* Shrink the end. */
2796 for (j
= decl
->size
-1; j
>= 0; j
--) {
2797 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2798 if (*patch_usage_mask
&
2799 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2803 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2805 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2812 /* When not all entries of an array are accessed, we mark them as used
2813 * here anyway, to ensure that the input/output mapping logic doesn't get
2816 * TODO This happens when an array isn't used via indirect access, which
2817 * some game ports do (at least eON-based). There is an optimization
2818 * opportunity here by replacing the array declaration with non-array
2819 * declarations of those slots that are actually used.
2821 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2822 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2823 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2825 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2831 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2835 int element_size
= type_size(ir
->type
);
2838 index
= ir
->array_index
->constant_expression_value();
2840 ir
->array
->accept(this);
2843 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2844 switch (this->prog
->Target
) {
2845 case GL_TESS_CONTROL_PROGRAM_NV
:
2846 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2847 !ir
->variable_referenced()->data
.patch
;
2849 case GL_TESS_EVALUATION_PROGRAM_NV
:
2850 is_2D
= src
.file
== PROGRAM_INPUT
&&
2851 !ir
->variable_referenced()->data
.patch
;
2853 case GL_GEOMETRY_PROGRAM_NV
:
2854 is_2D
= src
.file
== PROGRAM_INPUT
;
2864 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2865 src
.file
== PROGRAM_INPUT
)
2866 element_size
= attrib_type_size(ir
->type
, true);
2868 src
.index2D
= index
->value
.i
[0];
2869 src
.has_index2
= true;
2871 src
.index
+= index
->value
.i
[0] * element_size
;
2873 /* Variable index array dereference. It eats the "vec4" of the
2874 * base of the array and an index that offsets the TGSI register
2877 ir
->array_index
->accept(this);
2879 st_src_reg index_reg
;
2881 if (element_size
== 1) {
2882 index_reg
= this->result
;
2884 index_reg
= get_temp(native_integers
?
2885 glsl_type::int_type
: glsl_type::float_type
);
2887 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2888 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2891 /* If there was already a relative address register involved, add the
2892 * new and the old together to get the new offset.
2894 if (!is_2D
&& src
.reladdr
!= NULL
) {
2895 st_src_reg accum_reg
= get_temp(native_integers
?
2896 glsl_type::int_type
: glsl_type::float_type
);
2898 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2899 index_reg
, *src
.reladdr
);
2901 index_reg
= accum_reg
;
2905 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2906 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2908 src
.has_index2
= true;
2910 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2911 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2915 /* Change the register type to the element type of the array. */
2916 src
.type
= ir
->type
->base_type
;
2922 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2925 const glsl_type
*struct_type
= ir
->record
->type
;
2928 ir
->record
->accept(this);
2930 for (i
= 0; i
< struct_type
->length
; i
++) {
2931 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2933 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2936 /* If the type is smaller than a vec4, replicate the last channel out. */
2937 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2938 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2940 this->result
.swizzle
= SWIZZLE_NOOP
;
2942 this->result
.index
+= offset
;
2943 this->result
.type
= ir
->type
->base_type
;
2947 * We want to be careful in assignment setup to hit the actual storage
2948 * instead of potentially using a temporary like we might with the
2949 * ir_dereference handler.
2952 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2954 /* The LHS must be a dereference. If the LHS is a variable indexed array
2955 * access of a vector, it must be separated into a series conditional moves
2956 * before reaching this point (see ir_vec_index_to_cond_assign).
2958 assert(ir
->as_dereference());
2959 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2961 assert(!deref_array
->array
->type
->is_vector());
2964 /* Use the rvalue deref handler for the most part. We write swizzles using
2965 * the writemask, but we do extract the base component for enhanced layouts
2966 * from the source swizzle.
2969 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2970 return st_dst_reg(v
->result
);
2974 * Process the condition of a conditional assignment
2976 * Examines the condition of a conditional assignment to generate the optimal
2977 * first operand of a \c CMP instruction. If the condition is a relational
2978 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2979 * used as the source for the \c CMP instruction. Otherwise the comparison
2980 * is processed to a boolean result, and the boolean result is used as the
2981 * operand to the CMP instruction.
2984 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2986 ir_rvalue
*src_ir
= ir
;
2988 bool switch_order
= false;
2990 ir_expression
*const expr
= ir
->as_expression();
2992 if (native_integers
) {
2993 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2994 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2995 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2996 type
== GLSL_TYPE_BOOL
) {
2997 if (expr
->operation
== ir_binop_equal
) {
2998 if (expr
->operands
[0]->is_zero()) {
2999 src_ir
= expr
->operands
[1];
3000 switch_order
= true;
3002 else if (expr
->operands
[1]->is_zero()) {
3003 src_ir
= expr
->operands
[0];
3004 switch_order
= true;
3007 else if (expr
->operation
== ir_binop_nequal
) {
3008 if (expr
->operands
[0]->is_zero()) {
3009 src_ir
= expr
->operands
[1];
3011 else if (expr
->operands
[1]->is_zero()) {
3012 src_ir
= expr
->operands
[0];
3018 src_ir
->accept(this);
3019 return switch_order
;
3022 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
3023 bool zero_on_left
= false;
3025 if (expr
->operands
[0]->is_zero()) {
3026 src_ir
= expr
->operands
[1];
3027 zero_on_left
= true;
3028 } else if (expr
->operands
[1]->is_zero()) {
3029 src_ir
= expr
->operands
[0];
3030 zero_on_left
= false;
3034 * (a < 0) T F F ( a < 0) T F F
3035 * (0 < a) F F T (-a < 0) F F T
3036 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3037 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3038 * (a > 0) F F T (-a < 0) F F T
3039 * (0 > a) T F F ( a < 0) T F F
3040 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3041 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3043 * Note that exchanging the order of 0 and 'a' in the comparison simply
3044 * means that the value of 'a' should be negated.
3047 switch (expr
->operation
) {
3049 switch_order
= false;
3050 negate
= zero_on_left
;
3053 case ir_binop_greater
:
3054 switch_order
= false;
3055 negate
= !zero_on_left
;
3058 case ir_binop_lequal
:
3059 switch_order
= true;
3060 negate
= !zero_on_left
;
3063 case ir_binop_gequal
:
3064 switch_order
= true;
3065 negate
= zero_on_left
;
3069 /* This isn't the right kind of comparison afterall, so make sure
3070 * the whole condition is visited.
3078 src_ir
->accept(this);
3080 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3081 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3082 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3083 * computing the condition.
3086 this->result
.negate
= ~this->result
.negate
;
3088 return switch_order
;
3092 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3093 st_dst_reg
*l
, st_src_reg
*r
,
3094 st_src_reg
*cond
, bool cond_swap
)
3096 if (type
->is_record()) {
3097 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3098 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3104 if (type
->is_array()) {
3105 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3106 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3111 if (type
->is_matrix()) {
3112 const struct glsl_type
*vec_type
;
3114 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3115 type
->vector_elements
, 1);
3117 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3118 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3123 assert(type
->is_scalar() || type
->is_vector());
3125 l
->type
= type
->base_type
;
3126 r
->type
= type
->base_type
;
3128 st_src_reg l_src
= st_src_reg(*l
);
3129 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3131 if (native_integers
) {
3132 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3133 cond_swap
? l_src
: *r
,
3134 cond_swap
? *r
: l_src
);
3136 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3137 cond_swap
? l_src
: *r
,
3138 cond_swap
? *r
: l_src
);
3141 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3145 if (type
->is_dual_slot()) {
3147 if (r
->is_double_vertex_input
== false)
3153 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3159 /* all generated instructions need to be flaged as precise */
3160 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3161 ir
->rhs
->accept(this);
3164 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3168 int first_enabled_chan
= 0;
3170 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3172 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3173 variable
->data
.mode
== ir_var_shader_out
&&
3174 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3175 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3176 assert(ir
->lhs
->type
->is_scalar());
3177 assert(ir
->write_mask
== WRITEMASK_X
);
3179 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3180 l
.writemask
= WRITEMASK_Z
;
3182 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3183 l
.writemask
= WRITEMASK_Y
;
3185 } else if (ir
->write_mask
== 0) {
3186 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3188 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3191 l
.writemask
= u_bit_consecutive(0, num_elements
);
3193 /* The type is a struct or an array of (array of) structs. */
3194 l
.writemask
= WRITEMASK_XYZW
;
3197 l
.writemask
= ir
->write_mask
;
3200 for (int i
= 0; i
< 4; i
++) {
3201 if (l
.writemask
& (1 << i
)) {
3202 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3207 l
.writemask
= l
.writemask
<< dst_component
;
3209 /* Swizzle a small RHS vector into the channels being written.
3211 * glsl ir treats write_mask as dictating how many channels are
3212 * present on the RHS while TGSI treats write_mask as just
3213 * showing which channels of the vec4 RHS get written.
3215 for (int i
= 0; i
< 4; i
++) {
3216 if (l
.writemask
& (1 << i
))
3217 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3219 swizzles
[i
] = first_enabled_chan
;
3221 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3222 swizzles
[2], swizzles
[3]);
3225 assert(l
.file
!= PROGRAM_UNDEFINED
);
3226 assert(r
.file
!= PROGRAM_UNDEFINED
);
3228 if (ir
->condition
) {
3229 const bool switch_order
= this->process_move_condition(ir
->condition
);
3230 st_src_reg condition
= this->result
;
3232 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3233 } else if (ir
->rhs
->as_expression() &&
3234 this->instructions
.get_tail() &&
3235 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3236 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3237 type_size(ir
->lhs
->type
) == 1 &&
3238 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3239 /* To avoid emitting an extra MOV when assigning an expression to a
3240 * variable, emit the last instruction of the expression again, but
3241 * replace the destination register with the target of the assignment.
3242 * Dead code elimination will remove the original instruction.
3244 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3245 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3246 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3247 new_inst
->saturate
= inst
->saturate
;
3248 inst
->dead_mask
= inst
->dst
[0].writemask
;
3250 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3257 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3260 GLdouble stack_vals
[4] = { 0 };
3261 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3262 GLenum gl_type
= GL_NONE
;
3264 static int in_array
= 0;
3265 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3267 /* Unfortunately, 4 floats is all we can get into
3268 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3269 * aggregate constant and move each constant value into it. If we
3270 * get lucky, copy propagation will eliminate the extra moves.
3272 if (ir
->type
->is_record()) {
3273 st_src_reg temp_base
= get_temp(ir
->type
);
3274 st_dst_reg temp
= st_dst_reg(temp_base
);
3276 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3277 int size
= type_size(field_value
->type
);
3281 field_value
->accept(this);
3284 for (i
= 0; i
< (unsigned int)size
; i
++) {
3285 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3291 this->result
= temp_base
;
3295 if (ir
->type
->is_array()) {
3296 st_src_reg temp_base
= get_temp(ir
->type
);
3297 st_dst_reg temp
= st_dst_reg(temp_base
);
3298 int size
= type_size(ir
->type
->fields
.array
);
3303 for (i
= 0; i
< ir
->type
->length
; i
++) {
3304 ir
->array_elements
[i
]->accept(this);
3306 for (int j
= 0; j
< size
; j
++) {
3307 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3313 this->result
= temp_base
;
3318 if (ir
->type
->is_matrix()) {
3319 st_src_reg mat
= get_temp(ir
->type
);
3320 st_dst_reg mat_column
= st_dst_reg(mat
);
3322 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3323 switch (ir
->type
->base_type
) {
3324 case GLSL_TYPE_FLOAT
:
3325 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3327 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3328 src
.index
= add_constant(file
,
3330 ir
->type
->vector_elements
,
3333 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3335 case GLSL_TYPE_DOUBLE
:
3336 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3337 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3338 src
.index
= add_constant(file
,
3340 ir
->type
->vector_elements
,
3343 if (ir
->type
->vector_elements
>= 2) {
3344 mat_column
.writemask
= WRITEMASK_XY
;
3345 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3346 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3348 mat_column
.writemask
= WRITEMASK_X
;
3349 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3350 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3353 if (ir
->type
->vector_elements
> 2) {
3354 if (ir
->type
->vector_elements
== 4) {
3355 mat_column
.writemask
= WRITEMASK_ZW
;
3356 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3357 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3359 mat_column
.writemask
= WRITEMASK_Z
;
3360 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3361 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3362 mat_column
.writemask
= WRITEMASK_XYZW
;
3363 src
.swizzle
= SWIZZLE_XYZW
;
3369 unreachable("Illegal matrix constant type.\n");
3378 switch (ir
->type
->base_type
) {
3379 case GLSL_TYPE_FLOAT
:
3381 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3382 values
[i
].f
= ir
->value
.f
[i
];
3385 case GLSL_TYPE_DOUBLE
:
3386 gl_type
= GL_DOUBLE
;
3387 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3388 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3391 case GLSL_TYPE_INT64
:
3392 gl_type
= GL_INT64_ARB
;
3393 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3394 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3397 case GLSL_TYPE_UINT64
:
3398 gl_type
= GL_UNSIGNED_INT64_ARB
;
3399 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3400 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3403 case GLSL_TYPE_UINT
:
3404 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3405 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3406 if (native_integers
)
3407 values
[i
].u
= ir
->value
.u
[i
];
3409 values
[i
].f
= ir
->value
.u
[i
];
3413 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3414 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3415 if (native_integers
)
3416 values
[i
].i
= ir
->value
.i
[i
];
3418 values
[i
].f
= ir
->value
.i
[i
];
3421 case GLSL_TYPE_BOOL
:
3422 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3423 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3424 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3428 assert(!"Non-float/uint/int/bool constant");
3431 this->result
= st_src_reg(file
, -1, ir
->type
);
3432 this->result
.index
= add_constant(file
,
3434 ir
->type
->vector_elements
,
3436 &this->result
.swizzle
);
3440 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3442 exec_node
*param
= ir
->actual_parameters
.get_head();
3443 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3444 ir_variable
*location
= deref
->variable_referenced();
3447 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3449 /* Calculate the surface offset */
3451 unsigned array_size
= 0, base
= 0;
3454 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3456 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3457 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3458 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3459 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3460 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3462 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3465 ir
->return_deref
->accept(this);
3466 st_dst_reg
dst(this->result
);
3467 dst
.writemask
= WRITEMASK_X
;
3469 glsl_to_tgsi_instruction
*inst
;
3471 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3472 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3473 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3474 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3475 st_src_reg_for_int(1));
3476 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3477 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3478 st_src_reg_for_int(-1));
3479 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3481 param
= param
->get_next();
3482 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3485 st_src_reg data
= this->result
, data2
= undef_src
;
3487 switch (ir
->callee
->intrinsic_id
) {
3488 case ir_intrinsic_atomic_counter_add
:
3489 opcode
= TGSI_OPCODE_ATOMUADD
;
3491 case ir_intrinsic_atomic_counter_min
:
3492 opcode
= TGSI_OPCODE_ATOMIMIN
;
3494 case ir_intrinsic_atomic_counter_max
:
3495 opcode
= TGSI_OPCODE_ATOMIMAX
;
3497 case ir_intrinsic_atomic_counter_and
:
3498 opcode
= TGSI_OPCODE_ATOMAND
;
3500 case ir_intrinsic_atomic_counter_or
:
3501 opcode
= TGSI_OPCODE_ATOMOR
;
3503 case ir_intrinsic_atomic_counter_xor
:
3504 opcode
= TGSI_OPCODE_ATOMXOR
;
3506 case ir_intrinsic_atomic_counter_exchange
:
3507 opcode
= TGSI_OPCODE_ATOMXCHG
;
3509 case ir_intrinsic_atomic_counter_comp_swap
: {
3510 opcode
= TGSI_OPCODE_ATOMCAS
;
3511 param
= param
->get_next();
3512 val
= ((ir_instruction
*)param
)->as_rvalue();
3514 data2
= this->result
;
3518 assert(!"Unexpected intrinsic");
3522 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3525 inst
->resource
= buffer
;
3529 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3531 exec_node
*param
= ir
->actual_parameters
.get_head();
3533 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3535 param
= param
->get_next();
3536 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3538 ir_constant
*const_block
= block
->as_constant();
3542 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3543 (const_block
? const_block
->value
.u
[0] : 0),
3547 block
->accept(this);
3548 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3549 *buffer
.reladdr
= this->result
;
3550 emit_arl(ir
, sampler_reladdr
, this->result
);
3553 /* Calculate the surface offset */
3554 offset
->accept(this);
3555 st_src_reg off
= this->result
;
3557 st_dst_reg dst
= undef_dst
;
3558 if (ir
->return_deref
) {
3559 ir
->return_deref
->accept(this);
3560 dst
= st_dst_reg(this->result
);
3561 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3564 glsl_to_tgsi_instruction
*inst
;
3566 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3567 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3568 if (dst
.type
== GLSL_TYPE_BOOL
)
3569 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3570 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3571 param
= param
->get_next();
3572 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3575 param
= param
->get_next();
3576 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3578 dst
.writemask
= write_mask
->value
.u
[0];
3580 dst
.type
= this->result
.type
;
3581 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3583 param
= param
->get_next();
3584 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3587 st_src_reg data
= this->result
, data2
= undef_src
;
3589 switch (ir
->callee
->intrinsic_id
) {
3590 case ir_intrinsic_ssbo_atomic_add
:
3591 opcode
= TGSI_OPCODE_ATOMUADD
;
3593 case ir_intrinsic_ssbo_atomic_min
:
3594 opcode
= TGSI_OPCODE_ATOMIMIN
;
3596 case ir_intrinsic_ssbo_atomic_max
:
3597 opcode
= TGSI_OPCODE_ATOMIMAX
;
3599 case ir_intrinsic_ssbo_atomic_and
:
3600 opcode
= TGSI_OPCODE_ATOMAND
;
3602 case ir_intrinsic_ssbo_atomic_or
:
3603 opcode
= TGSI_OPCODE_ATOMOR
;
3605 case ir_intrinsic_ssbo_atomic_xor
:
3606 opcode
= TGSI_OPCODE_ATOMXOR
;
3608 case ir_intrinsic_ssbo_atomic_exchange
:
3609 opcode
= TGSI_OPCODE_ATOMXCHG
;
3611 case ir_intrinsic_ssbo_atomic_comp_swap
:
3612 opcode
= TGSI_OPCODE_ATOMCAS
;
3613 param
= param
->get_next();
3614 val
= ((ir_instruction
*)param
)->as_rvalue();
3616 data2
= this->result
;
3619 assert(!"Unexpected intrinsic");
3623 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3626 param
= param
->get_next();
3627 ir_constant
*access
= NULL
;
3628 if (!param
->is_tail_sentinel()) {
3629 access
= ((ir_instruction
*)param
)->as_constant();
3633 /* The emit_asm() might have actually split the op into pieces, e.g. for
3634 * double stores. We have to go back and fix up all the generated ops.
3636 unsigned op
= inst
->op
;
3638 inst
->resource
= buffer
;
3640 inst
->buffer_access
= access
->value
.u
[0];
3642 if (inst
== this->instructions
.get_head_raw())
3644 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3646 if (inst
->op
== TGSI_OPCODE_UADD
) {
3647 if (inst
== this->instructions
.get_head_raw())
3649 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3651 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3655 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3657 switch (ir
->callee
->intrinsic_id
) {
3658 case ir_intrinsic_memory_barrier
:
3659 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3660 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3661 TGSI_MEMBAR_ATOMIC_BUFFER
|
3662 TGSI_MEMBAR_SHADER_IMAGE
|
3663 TGSI_MEMBAR_SHARED
));
3665 case ir_intrinsic_memory_barrier_atomic_counter
:
3666 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3667 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3669 case ir_intrinsic_memory_barrier_buffer
:
3670 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3671 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3673 case ir_intrinsic_memory_barrier_image
:
3674 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3675 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3677 case ir_intrinsic_memory_barrier_shared
:
3678 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3679 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3681 case ir_intrinsic_group_memory_barrier
:
3682 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3683 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3684 TGSI_MEMBAR_ATOMIC_BUFFER
|
3685 TGSI_MEMBAR_SHADER_IMAGE
|
3686 TGSI_MEMBAR_SHARED
|
3687 TGSI_MEMBAR_THREAD_GROUP
));
3690 assert(!"Unexpected memory barrier intrinsic");
3695 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3697 exec_node
*param
= ir
->actual_parameters
.get_head();
3699 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3701 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3703 /* Calculate the surface offset */
3704 offset
->accept(this);
3705 st_src_reg off
= this->result
;
3707 st_dst_reg dst
= undef_dst
;
3708 if (ir
->return_deref
) {
3709 ir
->return_deref
->accept(this);
3710 dst
= st_dst_reg(this->result
);
3711 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3714 glsl_to_tgsi_instruction
*inst
;
3716 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3717 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3718 inst
->resource
= buffer
;
3719 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3720 param
= param
->get_next();
3721 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3724 param
= param
->get_next();
3725 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3727 dst
.writemask
= write_mask
->value
.u
[0];
3729 dst
.type
= this->result
.type
;
3730 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3731 inst
->resource
= buffer
;
3733 param
= param
->get_next();
3734 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3737 st_src_reg data
= this->result
, data2
= undef_src
;
3739 switch (ir
->callee
->intrinsic_id
) {
3740 case ir_intrinsic_shared_atomic_add
:
3741 opcode
= TGSI_OPCODE_ATOMUADD
;
3743 case ir_intrinsic_shared_atomic_min
:
3744 opcode
= TGSI_OPCODE_ATOMIMIN
;
3746 case ir_intrinsic_shared_atomic_max
:
3747 opcode
= TGSI_OPCODE_ATOMIMAX
;
3749 case ir_intrinsic_shared_atomic_and
:
3750 opcode
= TGSI_OPCODE_ATOMAND
;
3752 case ir_intrinsic_shared_atomic_or
:
3753 opcode
= TGSI_OPCODE_ATOMOR
;
3755 case ir_intrinsic_shared_atomic_xor
:
3756 opcode
= TGSI_OPCODE_ATOMXOR
;
3758 case ir_intrinsic_shared_atomic_exchange
:
3759 opcode
= TGSI_OPCODE_ATOMXCHG
;
3761 case ir_intrinsic_shared_atomic_comp_swap
:
3762 opcode
= TGSI_OPCODE_ATOMCAS
;
3763 param
= param
->get_next();
3764 val
= ((ir_instruction
*)param
)->as_rvalue();
3766 data2
= this->result
;
3769 assert(!"Unexpected intrinsic");
3773 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3774 inst
->resource
= buffer
;
3779 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3780 bool *memory_coherent
, bool *memory_volatile
,
3781 bool *memory_restrict
, unsigned *image_format
)
3784 switch (ir
->ir_type
) {
3785 case ir_type_dereference_record
: {
3786 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3787 const glsl_type
*struct_type
= deref_record
->record
->type
;
3789 for (unsigned i
= 0; i
< struct_type
->length
; i
++) {
3790 if (!strcmp(struct_type
->fields
.structure
[i
].name
,
3791 deref_record
->field
)) {
3792 *type
= struct_type
->fields
.structure
[i
].type
->without_array();
3794 struct_type
->fields
.structure
[i
].memory_coherent
;
3796 struct_type
->fields
.structure
[i
].memory_volatile
;
3798 struct_type
->fields
.structure
[i
].memory_restrict
;
3800 struct_type
->fields
.structure
[i
].image_format
;
3807 case ir_type_dereference_array
: {
3808 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3809 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3810 memory_coherent
, memory_volatile
, memory_restrict
,
3815 case ir_type_dereference_variable
: {
3816 ir_variable
*var
= ir
->variable_referenced();
3818 *type
= var
->type
->without_array();
3819 *memory_coherent
= var
->data
.memory_coherent
;
3820 *memory_volatile
= var
->data
.memory_volatile
;
3821 *memory_restrict
= var
->data
.memory_restrict
;
3822 *image_format
= var
->data
.image_format
;
3832 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3834 exec_node
*param
= ir
->actual_parameters
.get_head();
3836 ir_dereference
*img
= (ir_dereference
*)param
;
3837 const ir_variable
*imgvar
= img
->variable_referenced();
3838 unsigned sampler_array_size
= 1, sampler_base
= 0;
3839 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3840 unsigned image_format
= 0;
3841 const glsl_type
*type
= NULL
;
3843 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3844 &memory_restrict
, &image_format
);
3847 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3849 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3850 &index
, &reladdr
, !imgvar
->contains_bindless());
3852 image
.index
= index
;
3853 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3854 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3855 *image
.reladdr
= reladdr
;
3856 emit_arl(ir
, sampler_reladdr
, reladdr
);
3859 st_dst_reg dst
= undef_dst
;
3860 if (ir
->return_deref
) {
3861 ir
->return_deref
->accept(this);
3862 dst
= st_dst_reg(this->result
);
3863 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3866 glsl_to_tgsi_instruction
*inst
;
3868 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3869 dst
.writemask
= WRITEMASK_XYZ
;
3870 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3871 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3872 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3873 st_dst_reg dstres
= st_dst_reg(res
);
3874 dstres
.writemask
= WRITEMASK_W
;
3875 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3876 res
.swizzle
= SWIZZLE_WWWW
;
3877 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3879 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3881 st_dst_reg coord_dst
;
3882 coord
= get_temp(glsl_type::ivec4_type
);
3883 coord_dst
= st_dst_reg(coord
);
3884 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3885 param
= param
->get_next();
3886 ((ir_dereference
*)param
)->accept(this);
3887 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3888 coord
.swizzle
= SWIZZLE_XXXX
;
3889 switch (type
->coordinate_components()) {
3890 case 4: assert(!"unexpected coord count");
3892 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3894 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3897 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3898 param
= param
->get_next();
3899 ((ir_dereference
*)param
)->accept(this);
3900 st_src_reg sample
= this->result
;
3901 sample
.swizzle
= SWIZZLE_XXXX
;
3902 coord_dst
.writemask
= WRITEMASK_W
;
3903 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3904 coord
.swizzle
|= SWIZZLE_W
<< 9;
3907 param
= param
->get_next();
3908 if (!param
->is_tail_sentinel()) {
3909 ((ir_dereference
*)param
)->accept(this);
3910 arg1
= this->result
;
3911 param
= param
->get_next();
3914 if (!param
->is_tail_sentinel()) {
3915 ((ir_dereference
*)param
)->accept(this);
3916 arg2
= this->result
;
3917 param
= param
->get_next();
3920 assert(param
->is_tail_sentinel());
3923 switch (ir
->callee
->intrinsic_id
) {
3924 case ir_intrinsic_image_load
:
3925 opcode
= TGSI_OPCODE_LOAD
;
3927 case ir_intrinsic_image_store
:
3928 opcode
= TGSI_OPCODE_STORE
;
3930 case ir_intrinsic_image_atomic_add
:
3931 opcode
= TGSI_OPCODE_ATOMUADD
;
3933 case ir_intrinsic_image_atomic_min
:
3934 opcode
= TGSI_OPCODE_ATOMIMIN
;
3936 case ir_intrinsic_image_atomic_max
:
3937 opcode
= TGSI_OPCODE_ATOMIMAX
;
3939 case ir_intrinsic_image_atomic_and
:
3940 opcode
= TGSI_OPCODE_ATOMAND
;
3942 case ir_intrinsic_image_atomic_or
:
3943 opcode
= TGSI_OPCODE_ATOMOR
;
3945 case ir_intrinsic_image_atomic_xor
:
3946 opcode
= TGSI_OPCODE_ATOMXOR
;
3948 case ir_intrinsic_image_atomic_exchange
:
3949 opcode
= TGSI_OPCODE_ATOMXCHG
;
3951 case ir_intrinsic_image_atomic_comp_swap
:
3952 opcode
= TGSI_OPCODE_ATOMCAS
;
3955 assert(!"Unexpected intrinsic");
3959 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3960 if (opcode
== TGSI_OPCODE_STORE
)
3961 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3964 if (imgvar
->contains_bindless()) {
3966 inst
->resource
= this->result
;
3967 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3968 SWIZZLE_X
, SWIZZLE_Y
);
3970 inst
->resource
= image
;
3971 inst
->sampler_array_size
= sampler_array_size
;
3972 inst
->sampler_base
= sampler_base
;
3975 inst
->tex_target
= type
->sampler_index();
3976 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3977 _mesa_get_shader_image_format(image_format
));
3979 if (memory_coherent
)
3980 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3981 if (memory_restrict
)
3982 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3983 if (memory_volatile
)
3984 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3988 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3990 ir
->return_deref
->accept(this);
3991 st_dst_reg dst
= st_dst_reg(this->result
);
3993 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3995 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3996 unsigned num_src
= 0;
3997 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3998 assert(num_src
< ARRAY_SIZE(src
));
4000 this->result
.file
= PROGRAM_UNDEFINED
;
4001 param
->accept(this);
4002 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4004 src
[num_src
] = this->result
;
4008 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
4012 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
4014 ir_function_signature
*sig
= ir
->callee
;
4016 /* Filter out intrinsics */
4017 switch (sig
->intrinsic_id
) {
4018 case ir_intrinsic_atomic_counter_read
:
4019 case ir_intrinsic_atomic_counter_increment
:
4020 case ir_intrinsic_atomic_counter_predecrement
:
4021 case ir_intrinsic_atomic_counter_add
:
4022 case ir_intrinsic_atomic_counter_min
:
4023 case ir_intrinsic_atomic_counter_max
:
4024 case ir_intrinsic_atomic_counter_and
:
4025 case ir_intrinsic_atomic_counter_or
:
4026 case ir_intrinsic_atomic_counter_xor
:
4027 case ir_intrinsic_atomic_counter_exchange
:
4028 case ir_intrinsic_atomic_counter_comp_swap
:
4029 visit_atomic_counter_intrinsic(ir
);
4032 case ir_intrinsic_ssbo_load
:
4033 case ir_intrinsic_ssbo_store
:
4034 case ir_intrinsic_ssbo_atomic_add
:
4035 case ir_intrinsic_ssbo_atomic_min
:
4036 case ir_intrinsic_ssbo_atomic_max
:
4037 case ir_intrinsic_ssbo_atomic_and
:
4038 case ir_intrinsic_ssbo_atomic_or
:
4039 case ir_intrinsic_ssbo_atomic_xor
:
4040 case ir_intrinsic_ssbo_atomic_exchange
:
4041 case ir_intrinsic_ssbo_atomic_comp_swap
:
4042 visit_ssbo_intrinsic(ir
);
4045 case ir_intrinsic_memory_barrier
:
4046 case ir_intrinsic_memory_barrier_atomic_counter
:
4047 case ir_intrinsic_memory_barrier_buffer
:
4048 case ir_intrinsic_memory_barrier_image
:
4049 case ir_intrinsic_memory_barrier_shared
:
4050 case ir_intrinsic_group_memory_barrier
:
4051 visit_membar_intrinsic(ir
);
4054 case ir_intrinsic_shared_load
:
4055 case ir_intrinsic_shared_store
:
4056 case ir_intrinsic_shared_atomic_add
:
4057 case ir_intrinsic_shared_atomic_min
:
4058 case ir_intrinsic_shared_atomic_max
:
4059 case ir_intrinsic_shared_atomic_and
:
4060 case ir_intrinsic_shared_atomic_or
:
4061 case ir_intrinsic_shared_atomic_xor
:
4062 case ir_intrinsic_shared_atomic_exchange
:
4063 case ir_intrinsic_shared_atomic_comp_swap
:
4064 visit_shared_intrinsic(ir
);
4067 case ir_intrinsic_image_load
:
4068 case ir_intrinsic_image_store
:
4069 case ir_intrinsic_image_atomic_add
:
4070 case ir_intrinsic_image_atomic_min
:
4071 case ir_intrinsic_image_atomic_max
:
4072 case ir_intrinsic_image_atomic_and
:
4073 case ir_intrinsic_image_atomic_or
:
4074 case ir_intrinsic_image_atomic_xor
:
4075 case ir_intrinsic_image_atomic_exchange
:
4076 case ir_intrinsic_image_atomic_comp_swap
:
4077 case ir_intrinsic_image_size
:
4078 case ir_intrinsic_image_samples
:
4079 visit_image_intrinsic(ir
);
4082 case ir_intrinsic_shader_clock
:
4083 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4086 case ir_intrinsic_vote_all
:
4087 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4089 case ir_intrinsic_vote_any
:
4090 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4092 case ir_intrinsic_vote_eq
:
4093 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4095 case ir_intrinsic_ballot
:
4096 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4098 case ir_intrinsic_read_first_invocation
:
4099 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4101 case ir_intrinsic_read_invocation
:
4102 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4105 case ir_intrinsic_invalid
:
4106 case ir_intrinsic_generic_load
:
4107 case ir_intrinsic_generic_store
:
4108 case ir_intrinsic_generic_atomic_add
:
4109 case ir_intrinsic_generic_atomic_and
:
4110 case ir_intrinsic_generic_atomic_or
:
4111 case ir_intrinsic_generic_atomic_xor
:
4112 case ir_intrinsic_generic_atomic_min
:
4113 case ir_intrinsic_generic_atomic_max
:
4114 case ir_intrinsic_generic_atomic_exchange
:
4115 case ir_intrinsic_generic_atomic_comp_swap
:
4116 unreachable("Invalid intrinsic");
4121 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4122 unsigned *array_elements
,
4124 st_src_reg
*indirect
,
4127 switch (tail
->ir_type
) {
4128 case ir_type_dereference_record
: {
4129 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4130 const glsl_type
*struct_type
= deref_record
->record
->type
;
4131 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
4133 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4135 assert(field_index
>= 0);
4136 *location
+= struct_type
->record_location_offset(field_index
);
4140 case ir_type_dereference_array
: {
4141 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4142 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
4145 st_src_reg temp_reg
;
4146 st_dst_reg temp_dst
;
4148 temp_reg
= get_temp(glsl_type::uint_type
);
4149 temp_dst
= st_dst_reg(temp_reg
);
4150 temp_dst
.writemask
= 1;
4152 deref_arr
->array_index
->accept(this);
4153 if (*array_elements
!= 1)
4154 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4156 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4158 if (indirect
->file
== PROGRAM_UNDEFINED
)
4159 *indirect
= temp_reg
;
4161 temp_dst
= st_dst_reg(*indirect
);
4162 temp_dst
.writemask
= 1;
4163 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4166 *index
+= array_index
->value
.u
[0] * *array_elements
;
4168 *array_elements
*= deref_arr
->array
->type
->length
;
4170 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4179 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4180 unsigned *array_size
,
4183 st_src_reg
*reladdr
,
4186 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4187 unsigned location
= 0;
4188 ir_variable
*var
= ir
->variable_referenced();
4190 memset(reladdr
, 0, sizeof(*reladdr
));
4191 reladdr
->file
= PROGRAM_UNDEFINED
;
4197 location
= var
->data
.location
;
4198 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4201 * If we end up with no indirect then adjust the base to the index,
4202 * and set the array size to 1.
4204 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4210 assert(location
!= 0xffffffff);
4211 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4212 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4217 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4219 if (offset
.reladdr
|| offset
.reladdr2
) {
4220 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4221 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4222 tmp_dst
.writemask
= WRITEMASK_XY
;
4223 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4231 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4233 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4234 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4235 st_src_reg levels_src
, reladdr
;
4236 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4237 glsl_to_tgsi_instruction
*inst
= NULL
;
4238 unsigned opcode
= TGSI_OPCODE_NOP
;
4239 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4240 unsigned sampler_array_size
= 1, sampler_base
= 0;
4241 bool is_cube_array
= false, is_cube_shadow
= false;
4242 ir_variable
*var
= ir
->sampler
->variable_referenced();
4245 /* if we are a cube array sampler or a cube shadow */
4246 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4247 is_cube_array
= sampler_type
->sampler_array
;
4248 is_cube_shadow
= sampler_type
->sampler_shadow
;
4251 if (ir
->coordinate
) {
4252 ir
->coordinate
->accept(this);
4254 /* Put our coords in a temp. We'll need to modify them for shadow,
4255 * projection, or LOD, so the only case we'd use it as-is is if
4256 * we're doing plain old texturing. The optimization passes on
4257 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4259 coord
= get_temp(glsl_type::vec4_type
);
4260 coord_dst
= st_dst_reg(coord
);
4261 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4262 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4265 if (ir
->projector
) {
4266 ir
->projector
->accept(this);
4267 projector
= this->result
;
4270 /* Storage for our result. Ideally for an assignment we'd be using
4271 * the actual storage for the result here, instead.
4273 result_src
= get_temp(ir
->type
);
4274 result_dst
= st_dst_reg(result_src
);
4275 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4279 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4281 ir
->offset
->accept(this);
4282 offset
[0] = this->result
;
4286 if (is_cube_array
|| is_cube_shadow
) {
4287 opcode
= TGSI_OPCODE_TXB2
;
4290 opcode
= TGSI_OPCODE_TXB
;
4292 ir
->lod_info
.bias
->accept(this);
4293 lod_info
= this->result
;
4295 ir
->offset
->accept(this);
4296 offset
[0] = this->result
;
4300 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4301 opcode
= TGSI_OPCODE_TEX_LZ
;
4303 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4304 ir
->lod_info
.lod
->accept(this);
4305 lod_info
= this->result
;
4308 ir
->offset
->accept(this);
4309 offset
[0] = this->result
;
4313 opcode
= TGSI_OPCODE_TXD
;
4314 ir
->lod_info
.grad
.dPdx
->accept(this);
4316 ir
->lod_info
.grad
.dPdy
->accept(this);
4319 ir
->offset
->accept(this);
4320 offset
[0] = this->result
;
4324 opcode
= TGSI_OPCODE_TXQ
;
4325 ir
->lod_info
.lod
->accept(this);
4326 lod_info
= this->result
;
4328 case ir_query_levels
:
4329 opcode
= TGSI_OPCODE_TXQ
;
4330 lod_info
= undef_src
;
4331 levels_src
= get_temp(ir
->type
);
4334 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4335 opcode
= TGSI_OPCODE_TXF_LZ
;
4337 opcode
= TGSI_OPCODE_TXF
;
4338 ir
->lod_info
.lod
->accept(this);
4339 lod_info
= this->result
;
4342 ir
->offset
->accept(this);
4343 offset
[0] = this->result
;
4347 opcode
= TGSI_OPCODE_TXF
;
4348 ir
->lod_info
.sample_index
->accept(this);
4349 sample_index
= this->result
;
4352 opcode
= TGSI_OPCODE_TG4
;
4353 ir
->lod_info
.component
->accept(this);
4354 component
= this->result
;
4356 ir
->offset
->accept(this);
4357 if (ir
->offset
->type
->is_array()) {
4358 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4359 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4360 offset
[i
] = this->result
;
4361 offset
[i
].index
+= i
* type_size(elt_type
);
4362 offset
[i
].type
= elt_type
->base_type
;
4363 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4364 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4367 offset
[0] = canonicalize_gather_offset(this->result
);
4372 opcode
= TGSI_OPCODE_LODQ
;
4374 case ir_texture_samples
:
4375 opcode
= TGSI_OPCODE_TXQS
;
4377 case ir_samples_identical
:
4378 unreachable("Unexpected ir_samples_identical opcode");
4381 if (ir
->projector
) {
4382 if (opcode
== TGSI_OPCODE_TEX
) {
4383 /* Slot the projector in as the last component of the coord. */
4384 coord_dst
.writemask
= WRITEMASK_W
;
4385 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4386 coord_dst
.writemask
= WRITEMASK_XYZW
;
4387 opcode
= TGSI_OPCODE_TXP
;
4389 st_src_reg coord_w
= coord
;
4390 coord_w
.swizzle
= SWIZZLE_WWWW
;
4392 /* For the other TEX opcodes there's no projective version
4393 * since the last slot is taken up by LOD info. Do the
4394 * projective divide now.
4396 coord_dst
.writemask
= WRITEMASK_W
;
4397 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4399 /* In the case where we have to project the coordinates "by hand,"
4400 * the shadow comparator value must also be projected.
4402 st_src_reg tmp_src
= coord
;
4403 if (ir
->shadow_comparator
) {
4404 /* Slot the shadow value in as the second to last component of the
4407 ir
->shadow_comparator
->accept(this);
4409 tmp_src
= get_temp(glsl_type::vec4_type
);
4410 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4412 /* Projective division not allowed for array samplers. */
4413 assert(!sampler_type
->sampler_array
);
4415 tmp_dst
.writemask
= WRITEMASK_Z
;
4416 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4418 tmp_dst
.writemask
= WRITEMASK_XY
;
4419 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4422 coord_dst
.writemask
= WRITEMASK_XYZ
;
4423 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4425 coord_dst
.writemask
= WRITEMASK_XYZW
;
4426 coord
.swizzle
= SWIZZLE_XYZW
;
4430 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4431 * comparator was put in the correct place (and projected) by the code,
4432 * above, that handles by-hand projection.
4434 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4435 /* Slot the shadow value in as the second to last component of the
4438 ir
->shadow_comparator
->accept(this);
4440 if (is_cube_array
) {
4441 cube_sc
= get_temp(glsl_type::float_type
);
4442 cube_sc_dst
= st_dst_reg(cube_sc
);
4443 cube_sc_dst
.writemask
= WRITEMASK_X
;
4444 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4445 cube_sc_dst
.writemask
= WRITEMASK_X
;
4448 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4449 sampler_type
->sampler_array
) ||
4450 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4451 coord_dst
.writemask
= WRITEMASK_W
;
4453 coord_dst
.writemask
= WRITEMASK_Z
;
4455 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4456 coord_dst
.writemask
= WRITEMASK_XYZW
;
4460 if (ir
->op
== ir_txf_ms
) {
4461 coord_dst
.writemask
= WRITEMASK_W
;
4462 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4463 coord_dst
.writemask
= WRITEMASK_XYZW
;
4464 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4465 opcode
== TGSI_OPCODE_TXF
) {
4466 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4467 coord_dst
.writemask
= WRITEMASK_W
;
4468 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4469 coord_dst
.writemask
= WRITEMASK_XYZW
;
4472 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4475 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4476 &index
, &reladdr
, !var
->contains_bindless());
4478 sampler
.index
= index
;
4479 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4480 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4481 *sampler
.reladdr
= reladdr
;
4482 emit_arl(ir
, sampler_reladdr
, reladdr
);
4485 if (opcode
== TGSI_OPCODE_TXD
)
4486 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4487 else if (opcode
== TGSI_OPCODE_TXQ
) {
4488 if (ir
->op
== ir_query_levels
) {
4489 /* the level is stored in W */
4490 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4491 result_dst
.writemask
= WRITEMASK_X
;
4492 levels_src
.swizzle
= SWIZZLE_WWWW
;
4493 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4495 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4496 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4497 inst
= emit_asm(ir
, opcode
, result_dst
);
4498 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4499 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4500 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4501 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4502 } else if (opcode
== TGSI_OPCODE_TG4
) {
4503 if (is_cube_array
&& ir
->shadow_comparator
) {
4504 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4506 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4509 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4511 if (ir
->shadow_comparator
)
4512 inst
->tex_shadow
= GL_TRUE
;
4514 if (var
->contains_bindless()) {
4515 ir
->sampler
->accept(this);
4516 inst
->resource
= this->result
;
4517 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4518 SWIZZLE_X
, SWIZZLE_Y
);
4520 inst
->resource
= sampler
;
4521 inst
->sampler_array_size
= sampler_array_size
;
4522 inst
->sampler_base
= sampler_base
;
4526 if (!inst
->tex_offsets
)
4527 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4529 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4530 inst
->tex_offsets
[i
] = offset
[i
];
4531 inst
->tex_offset_num_offset
= i
;
4534 inst
->tex_target
= sampler_type
->sampler_index();
4535 inst
->tex_type
= ir
->type
->base_type
;
4537 this->result
= result_src
;
4541 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4543 assert(!ir
->get_value());
4545 emit_asm(ir
, TGSI_OPCODE_RET
);
4549 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4551 if (ir
->condition
) {
4552 ir
->condition
->accept(this);
4553 st_src_reg condition
= this->result
;
4555 /* Convert the bool condition to a float so we can negate. */
4556 if (native_integers
) {
4557 st_src_reg temp
= get_temp(ir
->condition
->type
);
4558 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4559 condition
, st_src_reg_for_float(1.0));
4563 condition
.negate
= ~condition
.negate
;
4564 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4566 /* unconditional kil */
4567 emit_asm(ir
, TGSI_OPCODE_KILL
);
4572 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4575 glsl_to_tgsi_instruction
*if_inst
;
4577 ir
->condition
->accept(this);
4578 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4580 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4582 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4584 this->instructions
.push_tail(if_inst
);
4586 visit_exec_list(&ir
->then_instructions
, this);
4588 if (!ir
->else_instructions
.is_empty()) {
4589 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4590 visit_exec_list(&ir
->else_instructions
, this);
4593 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4598 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4600 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4602 ir
->stream
->accept(this);
4603 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4607 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4609 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4611 ir
->stream
->accept(this);
4612 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4616 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4618 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4619 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4621 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4624 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4626 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4628 result
.file
= PROGRAM_UNDEFINED
;
4635 num_input_arrays
= 0;
4636 num_output_arrays
= 0;
4638 num_address_regs
= 0;
4641 indirect_addr_consts
= false;
4642 wpos_transform_const
= -1;
4644 native_integers
= false;
4645 mem_ctx
= ralloc_context(NULL
);
4648 shader_program
= NULL
;
4653 use_shared_memory
= false;
4654 has_tex_txf_lz
= false;
4658 static void var_destroy(struct hash_entry
*entry
)
4660 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4665 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4667 _mesa_hash_table_destroy(variables
, var_destroy
);
4669 ralloc_free(mem_ctx
);
4672 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4679 * Count resources used by the given gpu program (number of texture
4683 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4685 v
->samplers_used
= 0;
4688 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4689 if (inst
->info
->is_tex
) {
4690 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4691 unsigned idx
= inst
->sampler_base
+ i
;
4692 v
->samplers_used
|= 1u << idx
;
4694 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4695 v
->sampler_types
[idx
] = inst
->tex_type
;
4696 v
->sampler_targets
[idx
] =
4697 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4699 if (inst
->tex_shadow
) {
4700 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4705 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4706 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4708 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4709 is_resource_instruction(inst
->op
) ||
4710 inst
->op
== TGSI_OPCODE_STORE
)) {
4711 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4712 v
->use_shared_memory
= true;
4713 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4714 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4715 unsigned idx
= inst
->sampler_base
+ i
;
4716 v
->images_used
|= 1 << idx
;
4717 v
->image_targets
[idx
] =
4718 st_translate_texture_target(inst
->tex_target
, false);
4719 v
->image_formats
[idx
] = inst
->image_format
;
4724 prog
->SamplersUsed
= v
->samplers_used
;
4726 if (v
->shader_program
!= NULL
)
4727 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4731 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4732 * are read from the given src in this instruction
4735 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4737 int read_mask
= 0, comp
;
4739 /* Now, given the src swizzle and the written channels, find which
4740 * components are actually read
4742 for (comp
= 0; comp
< 4; ++comp
) {
4743 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4745 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4746 read_mask
|= 1 << coord
;
4753 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4754 * instruction is the first instruction to write to register T0. There are
4755 * several lowering passes done in GLSL IR (e.g. branches and
4756 * relative addressing) that create a large number of conditional assignments
4757 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4759 * Here is why this conversion is safe:
4760 * CMP T0, T1 T2 T0 can be expanded to:
4766 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4767 * as the original program. If (T1 < 0.0) evaluates to false, executing
4768 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4769 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4770 * because any instruction that was going to read from T0 after this was going
4771 * to read a garbage value anyway.
4774 glsl_to_tgsi_visitor::simplify_cmp(void)
4776 int tempWritesSize
= 0;
4777 unsigned *tempWrites
= NULL
;
4778 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4780 memset(outputWrites
, 0, sizeof(outputWrites
));
4782 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4783 unsigned prevWriteMask
= 0;
4785 /* Give up if we encounter relative addressing or flow control. */
4786 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4787 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4788 inst
->info
->is_branch
||
4789 inst
->op
== TGSI_OPCODE_CONT
||
4790 inst
->op
== TGSI_OPCODE_END
||
4791 inst
->op
== TGSI_OPCODE_RET
) {
4795 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4796 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4797 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4798 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4799 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4800 if (inst
->dst
[0].index
>= tempWritesSize
) {
4801 const int inc
= 4096;
4803 tempWrites
= (unsigned*)
4805 (tempWritesSize
+ inc
) * sizeof(unsigned));
4809 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4810 tempWritesSize
+= inc
;
4813 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4814 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4818 /* For a CMP to be considered a conditional write, the destination
4819 * register and source register two must be the same. */
4820 if (inst
->op
== TGSI_OPCODE_CMP
4821 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4822 && inst
->src
[2].file
== inst
->dst
[0].file
4823 && inst
->src
[2].index
== inst
->dst
[0].index
4824 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4826 inst
->op
= TGSI_OPCODE_MOV
;
4827 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4828 inst
->src
[0] = inst
->src
[1];
4835 /* Replaces all references to a temporary register index with another index. */
4837 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4839 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4841 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4842 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4843 int old_idx
= inst
->src
[j
].index
;
4844 if (renames
[old_idx
].valid
)
4845 inst
->src
[j
].index
= renames
[old_idx
].new_reg
;
4849 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4850 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4851 int old_idx
= inst
->tex_offsets
[j
].index
;
4852 if (renames
[old_idx
].valid
)
4853 inst
->tex_offsets
[j
].index
= renames
[old_idx
].new_reg
;
4857 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
4858 int old_idx
= inst
->resource
.index
;
4859 if (renames
[old_idx
].valid
)
4860 inst
->resource
.index
= renames
[old_idx
].new_reg
;
4863 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4864 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4865 int old_idx
= inst
->dst
[j
].index
;
4866 if (renames
[old_idx
].valid
)
4867 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;}
4873 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4875 int depth
= 0; /* loop depth */
4876 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4879 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4880 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4881 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4882 if (first_writes
[inst
->dst
[j
].index
] == -1)
4883 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4887 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4890 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4900 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4902 int depth
= 0; /* loop depth */
4903 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4906 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4907 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4908 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4909 if (first_reads
[inst
->src
[j
].index
] == -1)
4910 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4913 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4914 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4915 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4916 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4919 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4922 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4932 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4934 int depth
= 0; /* loop depth */
4935 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4938 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4939 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4940 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4941 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4943 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4944 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4945 if (first_writes
[inst
->dst
[j
].index
] == -1)
4946 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4947 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4950 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4951 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4952 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4954 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4957 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4960 for (k
= 0; k
< this->next_temp
; k
++) {
4961 if (last_reads
[k
] == -2) {
4973 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4975 int depth
= 0; /* loop depth */
4979 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4980 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4981 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4982 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4985 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4987 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4989 for (k
= 0; k
< this->next_temp
; k
++) {
4990 if (last_writes
[k
] == -2) {
5001 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5002 * channels for copy propagation and updates following instructions to
5003 * use the original versions.
5005 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5006 * will occur. As an example, a TXP production before this pass:
5008 * 0: MOV TEMP[1], INPUT[4].xyyy;
5009 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5010 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5014 * 0: MOV TEMP[1], INPUT[4].xyyy;
5015 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5016 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5018 * which allows for dead code elimination on TEMP[1]'s writes.
5021 glsl_to_tgsi_visitor::copy_propagate(void)
5023 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5024 glsl_to_tgsi_instruction
*,
5025 this->next_temp
* 4);
5026 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5029 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5030 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5031 || inst
->dst
[0].index
< this->next_temp
);
5033 /* First, do any copy propagation possible into the src regs. */
5034 for (int r
= 0; r
< 3; r
++) {
5035 glsl_to_tgsi_instruction
*first
= NULL
;
5037 int acp_base
= inst
->src
[r
].index
* 4;
5039 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5040 inst
->src
[r
].reladdr
||
5041 inst
->src
[r
].reladdr2
)
5044 /* See if we can find entries in the ACP consisting of MOVs
5045 * from the same src register for all the swizzled channels
5046 * of this src register reference.
5048 for (int i
= 0; i
< 4; i
++) {
5049 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5050 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5057 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5062 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5063 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5064 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5065 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5073 /* We've now validated that we can copy-propagate to
5074 * replace this src register reference. Do it.
5076 inst
->src
[r
].file
= first
->src
[0].file
;
5077 inst
->src
[r
].index
= first
->src
[0].index
;
5078 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5079 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5080 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5081 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5084 for (int i
= 0; i
< 4; i
++) {
5085 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5086 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5087 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5089 inst
->src
[r
].swizzle
= swizzle
;
5094 case TGSI_OPCODE_BGNLOOP
:
5095 case TGSI_OPCODE_ENDLOOP
:
5096 /* End of a basic block, clear the ACP entirely. */
5097 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5100 case TGSI_OPCODE_IF
:
5101 case TGSI_OPCODE_UIF
:
5105 case TGSI_OPCODE_ENDIF
:
5106 case TGSI_OPCODE_ELSE
:
5107 /* Clear all channels written inside the block from the ACP, but
5108 * leaving those that were not touched.
5110 for (int r
= 0; r
< this->next_temp
; r
++) {
5111 for (int c
= 0; c
< 4; c
++) {
5112 if (!acp
[4 * r
+ c
])
5115 if (acp_level
[4 * r
+ c
] >= level
)
5116 acp
[4 * r
+ c
] = NULL
;
5119 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5124 /* Continuing the block, clear any written channels from
5127 for (int d
= 0; d
< 2; d
++) {
5128 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5129 /* Any temporary might be written, so no copy propagation
5130 * across this instruction.
5132 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5133 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5134 inst
->dst
[d
].reladdr
) {
5135 /* Any output might be written, so no copy propagation
5136 * from outputs across this instruction.
5138 for (int r
= 0; r
< this->next_temp
; r
++) {
5139 for (int c
= 0; c
< 4; c
++) {
5140 if (!acp
[4 * r
+ c
])
5143 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5144 acp
[4 * r
+ c
] = NULL
;
5147 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5148 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5149 /* Clear where it's used as dst. */
5150 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5151 for (int c
= 0; c
< 4; c
++) {
5152 if (inst
->dst
[d
].writemask
& (1 << c
))
5153 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5157 /* Clear where it's used as src. */
5158 for (int r
= 0; r
< this->next_temp
; r
++) {
5159 for (int c
= 0; c
< 4; c
++) {
5160 if (!acp
[4 * r
+ c
])
5163 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5165 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5166 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5167 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5168 acp
[4 * r
+ c
] = NULL
;
5177 /* If this is a copy, add it to the ACP. */
5178 if (inst
->op
== TGSI_OPCODE_MOV
&&
5179 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5180 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5181 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5182 !inst
->dst
[0].reladdr
&&
5183 !inst
->dst
[0].reladdr2
&&
5185 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5186 !inst
->src
[0].reladdr
&&
5187 !inst
->src
[0].reladdr2
&&
5188 !inst
->src
[0].negate
&&
5189 !inst
->src
[0].abs
) {
5190 for (int i
= 0; i
< 4; i
++) {
5191 if (inst
->dst
[0].writemask
& (1 << i
)) {
5192 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5193 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5199 ralloc_free(acp_level
);
5204 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5207 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5208 * will occur. As an example, a TXP production after copy propagation but
5211 * 0: MOV TEMP[1], INPUT[4].xyyy;
5212 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5213 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5215 * and after this pass:
5217 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5220 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5222 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5223 glsl_to_tgsi_instruction
*,
5224 this->next_temp
* 4);
5225 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5229 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5230 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5231 || inst
->dst
[0].index
< this->next_temp
);
5234 case TGSI_OPCODE_BGNLOOP
:
5235 case TGSI_OPCODE_ENDLOOP
:
5236 case TGSI_OPCODE_CONT
:
5237 case TGSI_OPCODE_BRK
:
5238 /* End of a basic block, clear the write array entirely.
5240 * This keeps us from killing dead code when the writes are
5241 * on either side of a loop, even when the register isn't touched
5242 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5243 * dead code of this type, so it shouldn't make a difference as long as
5244 * the dead code elimination pass in the GLSL compiler does its job.
5246 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5249 case TGSI_OPCODE_ENDIF
:
5250 case TGSI_OPCODE_ELSE
:
5251 /* Promote the recorded level of all channels written inside the
5252 * preceding if or else block to the level above the if/else block.
5254 for (int r
= 0; r
< this->next_temp
; r
++) {
5255 for (int c
= 0; c
< 4; c
++) {
5256 if (!writes
[4 * r
+ c
])
5259 if (write_level
[4 * r
+ c
] == level
)
5260 write_level
[4 * r
+ c
] = level
-1;
5263 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5267 case TGSI_OPCODE_IF
:
5268 case TGSI_OPCODE_UIF
:
5270 /* fallthrough to default case to mark the condition as read */
5272 /* Continuing the block, clear any channels from the write array that
5273 * are read by this instruction.
5275 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5276 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5277 /* Any temporary might be read, so no dead code elimination
5278 * across this instruction.
5280 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5281 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5282 /* Clear where it's used as src. */
5283 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5284 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5285 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5286 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5288 for (int c
= 0; c
< 4; c
++) {
5289 if (src_chans
& (1 << c
))
5290 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5294 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5295 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5296 /* Any temporary might be read, so no dead code elimination
5297 * across this instruction.
5299 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5300 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5301 /* Clear where it's used as src. */
5302 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5303 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5304 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5305 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5307 for (int c
= 0; c
< 4; c
++) {
5308 if (src_chans
& (1 << c
))
5309 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5314 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5317 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5318 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5319 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5320 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5322 for (int c
= 0; c
< 4; c
++) {
5323 if (src_chans
& (1 << c
))
5324 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5331 /* If this instruction writes to a temporary, add it to the write array.
5332 * If there is already an instruction in the write array for one or more
5333 * of the channels, flag that channel write as dead.
5335 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5336 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5337 !inst
->dst
[i
].reladdr
) {
5338 for (int c
= 0; c
< 4; c
++) {
5339 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5340 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5341 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5344 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5346 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5347 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5354 /* Anything still in the write array at this point is dead code. */
5355 for (int r
= 0; r
< this->next_temp
; r
++) {
5356 for (int c
= 0; c
< 4; c
++) {
5357 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5359 inst
->dead_mask
|= (1 << c
);
5363 /* Now actually remove the instructions that are completely dead and update
5364 * the writemask of other instructions with dead channels.
5366 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5367 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5369 /* No amount of dead masks should remove memory stores */
5370 if (inst
->info
->is_store
)
5373 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5378 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5379 if (inst
->dead_mask
== WRITEMASK_XY
||
5380 inst
->dead_mask
== WRITEMASK_ZW
)
5381 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5383 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5387 ralloc_free(write_level
);
5388 ralloc_free(writes
);
5393 /* merge DFRACEXP instructions into one. */
5395 glsl_to_tgsi_visitor::merge_two_dsts(void)
5397 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5398 glsl_to_tgsi_instruction
*inst2
;
5400 if (num_inst_dst_regs(inst
) != 2)
5403 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5404 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5407 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5410 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5411 inst
->src
[0].index
== inst2
->src
[0].index
&&
5412 inst
->src
[0].type
== inst2
->src
[0].type
&&
5413 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5415 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5421 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5423 inst
->dst
[0] = inst2
->dst
[0];
5424 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5425 inst
->dst
[1] = inst2
->dst
[1];
5436 /* Merges temporary registers together where possible to reduce the number of
5437 * registers needed to run a program.
5439 * Produces optimal code only after copy propagation and dead code elimination
5442 glsl_to_tgsi_visitor::merge_registers(void)
5444 int *last_reads
= ralloc_array(mem_ctx
, int, this->next_temp
);
5445 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5446 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5449 /* Read the indices of the last read and first write to each temp register
5450 * into an array so that we don't have to traverse the instruction list as
5452 for (i
= 0; i
< this->next_temp
; i
++) {
5454 first_writes
[i
] = -1;
5456 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5458 /* Start looking for registers with non-overlapping usages that can be
5459 * merged together. */
5460 for (i
= 0; i
< this->next_temp
; i
++) {
5461 /* Don't touch unused registers. */
5462 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5464 for (j
= 0; j
< this->next_temp
; j
++) {
5465 /* Don't touch unused registers. */
5466 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5468 /* We can merge the two registers if the first write to j is after or
5469 * in the same instruction as the last read from i. Note that the
5470 * register at index i will always be used earlier or at the same time
5471 * as the register at index j. */
5472 if (first_writes
[i
] <= first_writes
[j
] &&
5473 last_reads
[i
] <= first_writes
[j
]) {
5474 renames
[j
].new_reg
= i
;
5475 renames
[j
].valid
= true;
5477 /* Update the first_writes and last_reads arrays with the new
5478 * values for the merged register index, and mark the newly unused
5479 * register index as such. */
5480 assert(last_reads
[j
] >= last_reads
[i
]);
5481 last_reads
[i
] = last_reads
[j
];
5482 first_writes
[j
] = -1;
5488 rename_temp_registers(renames
);
5489 ralloc_free(renames
);
5490 ralloc_free(last_reads
);
5491 ralloc_free(first_writes
);
5494 /* Reassign indices to temporary registers by reusing unused indices created
5495 * by optimization passes. */
5497 glsl_to_tgsi_visitor::renumber_registers(void)
5501 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5502 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5504 for (i
= 0; i
< this->next_temp
; i
++) {
5505 first_writes
[i
] = -1;
5507 get_first_temp_write(first_writes
);
5509 for (i
= 0; i
< this->next_temp
; i
++) {
5510 if (first_writes
[i
] < 0) continue;
5511 if (i
!= new_index
) {
5512 renames
[i
].new_reg
= new_index
;
5513 renames
[i
].valid
= true;
5518 rename_temp_registers(renames
);
5519 this->next_temp
= new_index
;
5520 ralloc_free(renames
);
5521 ralloc_free(first_writes
);
5524 /* ------------------------- TGSI conversion stuff -------------------------- */
5527 * Intermediate state used during shader translation.
5529 struct st_translate
{
5530 struct ureg_program
*ureg
;
5532 unsigned temps_size
;
5533 struct ureg_dst
*temps
;
5535 struct ureg_dst
*arrays
;
5536 unsigned num_temp_arrays
;
5537 struct ureg_src
*constants
;
5539 struct ureg_src
*immediates
;
5541 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5542 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5543 struct ureg_dst address
[3];
5544 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5545 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5546 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5547 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5548 struct ureg_src shared_memory
;
5549 unsigned *array_sizes
;
5550 struct inout_decl
*input_decls
;
5551 unsigned num_input_decls
;
5552 struct inout_decl
*output_decls
;
5553 unsigned num_output_decls
;
5555 const ubyte
*inputMapping
;
5556 const ubyte
*outputMapping
;
5558 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5561 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5563 _mesa_sysval_to_semantic(unsigned sysval
)
5567 case SYSTEM_VALUE_VERTEX_ID
:
5568 return TGSI_SEMANTIC_VERTEXID
;
5569 case SYSTEM_VALUE_INSTANCE_ID
:
5570 return TGSI_SEMANTIC_INSTANCEID
;
5571 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5572 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5573 case SYSTEM_VALUE_BASE_VERTEX
:
5574 return TGSI_SEMANTIC_BASEVERTEX
;
5575 case SYSTEM_VALUE_BASE_INSTANCE
:
5576 return TGSI_SEMANTIC_BASEINSTANCE
;
5577 case SYSTEM_VALUE_DRAW_ID
:
5578 return TGSI_SEMANTIC_DRAWID
;
5580 /* Geometry shader */
5581 case SYSTEM_VALUE_INVOCATION_ID
:
5582 return TGSI_SEMANTIC_INVOCATIONID
;
5584 /* Fragment shader */
5585 case SYSTEM_VALUE_FRAG_COORD
:
5586 return TGSI_SEMANTIC_POSITION
;
5587 case SYSTEM_VALUE_FRONT_FACE
:
5588 return TGSI_SEMANTIC_FACE
;
5589 case SYSTEM_VALUE_SAMPLE_ID
:
5590 return TGSI_SEMANTIC_SAMPLEID
;
5591 case SYSTEM_VALUE_SAMPLE_POS
:
5592 return TGSI_SEMANTIC_SAMPLEPOS
;
5593 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5594 return TGSI_SEMANTIC_SAMPLEMASK
;
5595 case SYSTEM_VALUE_HELPER_INVOCATION
:
5596 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5598 /* Tessellation shader */
5599 case SYSTEM_VALUE_TESS_COORD
:
5600 return TGSI_SEMANTIC_TESSCOORD
;
5601 case SYSTEM_VALUE_VERTICES_IN
:
5602 return TGSI_SEMANTIC_VERTICESIN
;
5603 case SYSTEM_VALUE_PRIMITIVE_ID
:
5604 return TGSI_SEMANTIC_PRIMID
;
5605 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5606 return TGSI_SEMANTIC_TESSOUTER
;
5607 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5608 return TGSI_SEMANTIC_TESSINNER
;
5610 /* Compute shader */
5611 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5612 return TGSI_SEMANTIC_THREAD_ID
;
5613 case SYSTEM_VALUE_WORK_GROUP_ID
:
5614 return TGSI_SEMANTIC_BLOCK_ID
;
5615 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5616 return TGSI_SEMANTIC_GRID_SIZE
;
5617 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5618 return TGSI_SEMANTIC_BLOCK_SIZE
;
5620 /* ARB_shader_ballot */
5621 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5622 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5623 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5624 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5625 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5626 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5627 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5628 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5629 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5630 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5631 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5632 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5633 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5634 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5637 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5638 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5639 case SYSTEM_VALUE_VERTEX_CNT
:
5641 assert(!"Unexpected SYSTEM_VALUE_ enum");
5642 return TGSI_SEMANTIC_COUNT
;
5647 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5649 static struct ureg_src
5650 emit_immediate(struct st_translate
*t
,
5651 gl_constant_value values
[4],
5654 struct ureg_program
*ureg
= t
->ureg
;
5659 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5661 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5663 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5664 case GL_UNSIGNED_INT64_ARB
:
5665 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5667 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5668 case GL_UNSIGNED_INT
:
5670 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5672 assert(!"should not get here - type must be float, int, uint, or bool");
5673 return ureg_src_undef();
5678 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5680 static struct ureg_dst
5681 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5687 case PROGRAM_UNDEFINED
:
5688 return ureg_dst_undef();
5690 case PROGRAM_TEMPORARY
:
5691 /* Allocate space for temporaries on demand. */
5692 if (index
>= t
->temps_size
) {
5693 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5695 t
->temps
= (struct ureg_dst
*)
5697 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5699 return ureg_dst_undef();
5701 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5702 t
->temps_size
+= inc
;
5705 if (ureg_dst_is_undef(t
->temps
[index
]))
5706 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5708 return t
->temps
[index
];
5711 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5712 array
= array_id
- 1;
5714 if (ureg_dst_is_undef(t
->arrays
[array
]))
5715 t
->arrays
[array
] = ureg_DECL_array_temporary(
5716 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5718 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5720 case PROGRAM_OUTPUT
:
5722 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5723 assert(index
< 2 * FRAG_RESULT_MAX
);
5724 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5725 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5726 assert(index
< VARYING_SLOT_TESS_MAX
);
5728 assert(index
< VARYING_SLOT_MAX
);
5730 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5731 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5732 return t
->outputs
[t
->outputMapping
[index
]];
5735 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5736 unsigned mesa_index
= decl
->mesa_index
;
5737 int slot
= t
->outputMapping
[mesa_index
];
5739 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5741 struct ureg_dst dst
= t
->outputs
[slot
];
5742 dst
.ArrayID
= array_id
;
5743 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5746 case PROGRAM_ADDRESS
:
5747 return t
->address
[index
];
5750 assert(!"unknown dst register file");
5751 return ureg_dst_undef();
5756 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5758 static struct ureg_src
5759 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5761 int index
= reg
->index
;
5762 int double_reg2
= reg
->double_reg2
? 1 : 0;
5765 case PROGRAM_UNDEFINED
:
5766 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5768 case PROGRAM_TEMPORARY
:
5770 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5772 case PROGRAM_OUTPUT
: {
5773 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5774 assert(dst
.WriteMask
!= 0);
5775 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5776 return ureg_swizzle(ureg_src(dst
),
5780 MIN2(shift
+ 3, 3));
5783 case PROGRAM_UNIFORM
:
5784 assert(reg
->index
>= 0);
5785 return reg
->index
< t
->num_constants
?
5786 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5787 case PROGRAM_STATE_VAR
:
5788 case PROGRAM_CONSTANT
: /* ie, immediate */
5789 if (reg
->has_index2
)
5790 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5792 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5793 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5795 case PROGRAM_IMMEDIATE
:
5796 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5797 return t
->immediates
[reg
->index
];
5800 /* GLSL inputs are 64-bit containers, so we have to
5801 * map back to the original index and add the offset after
5803 index
-= double_reg2
;
5804 if (!reg
->array_id
) {
5805 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5806 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5807 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5810 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5811 unsigned mesa_index
= decl
->mesa_index
;
5812 int slot
= t
->inputMapping
[mesa_index
];
5814 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5816 struct ureg_src src
= t
->inputs
[slot
];
5817 src
.ArrayID
= reg
->array_id
;
5818 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5821 case PROGRAM_ADDRESS
:
5822 return ureg_src(t
->address
[reg
->index
]);
5824 case PROGRAM_SYSTEM_VALUE
:
5825 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5826 return t
->systemValues
[reg
->index
];
5829 assert(!"unknown src register file");
5830 return ureg_src_undef();
5835 * Create a TGSI ureg_dst register from an st_dst_reg.
5837 static struct ureg_dst
5838 translate_dst(struct st_translate
*t
,
5839 const st_dst_reg
*dst_reg
,
5842 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5845 if (dst
.File
== TGSI_FILE_NULL
)
5848 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5851 dst
= ureg_saturate(dst
);
5853 if (dst_reg
->reladdr
!= NULL
) {
5854 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5855 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5858 if (dst_reg
->has_index2
) {
5859 if (dst_reg
->reladdr2
)
5860 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5863 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5870 * Create a TGSI ureg_src register from an st_src_reg.
5872 static struct ureg_src
5873 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5875 struct ureg_src src
= src_register(t
, src_reg
);
5877 if (src_reg
->has_index2
) {
5878 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5879 * and UBO constant buffers (buffer, position).
5881 if (src_reg
->reladdr2
)
5882 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5885 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5888 src
= ureg_swizzle(src
,
5889 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5890 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5891 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5892 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5895 src
= ureg_abs(src
);
5897 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5898 src
= ureg_negate(src
);
5900 if (src_reg
->reladdr
!= NULL
) {
5901 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5902 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5908 static struct tgsi_texture_offset
5909 translate_tex_offset(struct st_translate
*t
,
5910 const st_src_reg
*in_offset
)
5912 struct tgsi_texture_offset offset
;
5913 struct ureg_src src
= translate_src(t
, in_offset
);
5915 offset
.File
= src
.File
;
5916 offset
.Index
= src
.Index
;
5917 offset
.SwizzleX
= src
.SwizzleX
;
5918 offset
.SwizzleY
= src
.SwizzleY
;
5919 offset
.SwizzleZ
= src
.SwizzleZ
;
5922 assert(!src
.Indirect
);
5923 assert(!src
.DimIndirect
);
5924 assert(!src
.Dimension
);
5925 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5926 assert(!src
.Negate
);
5932 compile_tgsi_instruction(struct st_translate
*t
,
5933 const glsl_to_tgsi_instruction
*inst
)
5935 struct ureg_program
*ureg
= t
->ureg
;
5937 struct ureg_dst dst
[2];
5938 struct ureg_src src
[4];
5939 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5943 unsigned tex_target
= 0;
5945 num_dst
= num_inst_dst_regs(inst
);
5946 num_src
= num_inst_src_regs(inst
);
5948 for (i
= 0; i
< num_dst
; i
++)
5949 dst
[i
] = translate_dst(t
,
5953 for (i
= 0; i
< num_src
; i
++)
5954 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5957 case TGSI_OPCODE_BGNLOOP
:
5958 case TGSI_OPCODE_ELSE
:
5959 case TGSI_OPCODE_ENDLOOP
:
5960 case TGSI_OPCODE_IF
:
5961 case TGSI_OPCODE_UIF
:
5962 assert(num_dst
== 0);
5963 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5966 case TGSI_OPCODE_TEX
:
5967 case TGSI_OPCODE_TEX_LZ
:
5968 case TGSI_OPCODE_TXB
:
5969 case TGSI_OPCODE_TXD
:
5970 case TGSI_OPCODE_TXL
:
5971 case TGSI_OPCODE_TXP
:
5972 case TGSI_OPCODE_TXQ
:
5973 case TGSI_OPCODE_TXQS
:
5974 case TGSI_OPCODE_TXF
:
5975 case TGSI_OPCODE_TXF_LZ
:
5976 case TGSI_OPCODE_TEX2
:
5977 case TGSI_OPCODE_TXB2
:
5978 case TGSI_OPCODE_TXL2
:
5979 case TGSI_OPCODE_TG4
:
5980 case TGSI_OPCODE_LODQ
:
5981 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5982 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5984 /* Bindless samplers. */
5985 src
[num_src
] = translate_src(t
, &inst
->resource
);
5987 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5988 if (inst
->resource
.reladdr
)
5990 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5992 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5993 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5995 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6001 st_translate_texture_type(inst
->tex_type
),
6002 texoffsets
, inst
->tex_offset_num_offset
,
6006 case TGSI_OPCODE_RESQ
:
6007 case TGSI_OPCODE_LOAD
:
6008 case TGSI_OPCODE_ATOMUADD
:
6009 case TGSI_OPCODE_ATOMXCHG
:
6010 case TGSI_OPCODE_ATOMCAS
:
6011 case TGSI_OPCODE_ATOMAND
:
6012 case TGSI_OPCODE_ATOMOR
:
6013 case TGSI_OPCODE_ATOMXOR
:
6014 case TGSI_OPCODE_ATOMUMIN
:
6015 case TGSI_OPCODE_ATOMUMAX
:
6016 case TGSI_OPCODE_ATOMIMIN
:
6017 case TGSI_OPCODE_ATOMIMAX
:
6018 for (i
= num_src
- 1; i
>= 0; i
--)
6019 src
[i
+ 1] = src
[i
];
6021 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6022 src
[0] = t
->shared_memory
;
6023 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6024 src
[0] = t
->buffers
[inst
->resource
.index
];
6026 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6027 src
[0] = t
->images
[inst
->resource
.index
];
6029 /* Bindless images. */
6030 src
[0] = translate_src(t
, &inst
->resource
);
6032 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6034 if (inst
->resource
.reladdr
)
6035 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
6036 assert(src
[0].File
!= TGSI_FILE_NULL
);
6037 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6038 inst
->buffer_access
,
6039 tex_target
, inst
->image_format
);
6042 case TGSI_OPCODE_STORE
:
6043 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6044 dst
[0] = ureg_dst(t
->shared_memory
);
6045 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6046 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6048 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6049 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6051 /* Bindless images. */
6052 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6054 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6056 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6057 if (inst
->resource
.reladdr
)
6058 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
6059 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6060 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6061 inst
->buffer_access
,
6062 tex_target
, inst
->image_format
);
6065 case TGSI_OPCODE_SCS
:
6066 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
6067 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
, inst
->precise
);
6074 src
, num_src
, inst
->precise
);
6080 * Emit the TGSI instructions for inverting and adjusting WPOS.
6081 * This code is unavoidable because it also depends on whether
6082 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6085 emit_wpos_adjustment(struct gl_context
*ctx
,
6086 struct st_translate
*t
,
6087 int wpos_transform_const
,
6089 GLfloat adjX
, GLfloat adjY
[2])
6091 struct ureg_program
*ureg
= t
->ureg
;
6093 assert(wpos_transform_const
>= 0);
6095 /* Fragment program uses fragment position input.
6096 * Need to replace instances of INPUT[WPOS] with temp T
6097 * where T = INPUT[WPOS] is inverted by Y.
6099 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6100 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
6101 struct ureg_src
*wpos
=
6102 ctx
->Const
.GLSLFragCoordIsSysVal
?
6103 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6104 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6105 struct ureg_src wpos_input
= *wpos
;
6107 /* First, apply the coordinate shift: */
6108 if (adjX
|| adjY
[0] || adjY
[1]) {
6109 if (adjY
[0] != adjY
[1]) {
6110 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6111 * depending on whether inversion is actually going to be applied
6112 * or not, which is determined by testing against the inversion
6113 * state variable used below, which will be either +1 or -1.
6115 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6117 ureg_CMP(ureg
, adj_temp
,
6118 ureg_scalar(wpostrans
, invert
? 2 : 0),
6119 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6120 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6121 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6123 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6124 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6126 wpos_input
= ureg_src(wpos_temp
);
6128 /* MOV wpos_temp, input[wpos]
6130 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
6133 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6134 * inversion/identity, or the other way around if we're drawing to an FBO.
6137 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6140 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6142 ureg_scalar(wpostrans
, 0),
6143 ureg_scalar(wpostrans
, 1));
6145 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6148 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6150 ureg_scalar(wpostrans
, 2),
6151 ureg_scalar(wpostrans
, 3));
6154 /* Use wpos_temp as position input from here on:
6156 *wpos
= ureg_src(wpos_temp
);
6161 * Emit fragment position/ooordinate code.
6164 emit_wpos(struct st_context
*st
,
6165 struct st_translate
*t
,
6166 const struct gl_program
*program
,
6167 struct ureg_program
*ureg
,
6168 int wpos_transform_const
)
6170 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6171 GLfloat adjX
= 0.0f
;
6172 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6173 boolean invert
= FALSE
;
6175 /* Query the pixel center conventions supported by the pipe driver and set
6176 * adjX, adjY to help out if it cannot handle the requested one internally.
6178 * The bias of the y-coordinate depends on whether y-inversion takes place
6179 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6180 * drawing to an FBO (causes additional inversion), and whether the pipe
6181 * driver origin and the requested origin differ (the latter condition is
6182 * stored in the 'invert' variable).
6184 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6186 * center shift only:
6191 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6192 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6193 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6194 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6196 * inversion and center shift:
6197 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6198 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6199 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6200 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6202 if (program
->OriginUpperLeft
) {
6203 /* Fragment shader wants origin in upper-left */
6204 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6205 /* the driver supports upper-left origin */
6207 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6208 /* the driver supports lower-left origin, need to invert Y */
6209 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6210 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6217 /* Fragment shader wants origin in lower-left */
6218 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6219 /* the driver supports lower-left origin */
6220 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6221 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6222 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6223 /* the driver supports upper-left origin, need to invert Y */
6229 if (program
->PixelCenterInteger
) {
6230 /* Fragment shader wants pixel center integer */
6231 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6232 /* the driver supports pixel center integer */
6234 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6235 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6237 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6238 /* the driver supports pixel center half integer, need to bias X,Y */
6247 /* Fragment shader wants pixel center half integer */
6248 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6249 /* the driver supports pixel center half integer */
6251 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6252 /* the driver supports pixel center integer, need to bias X,Y */
6253 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6254 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6255 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6261 /* we invert after adjustment so that we avoid the MOV to temporary,
6262 * and reuse the adjustment ADD instead */
6263 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6267 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6268 * TGSI uses +1 for front, -1 for back.
6269 * This function converts the TGSI value to the GL value. Simply clamping/
6270 * saturating the value to [0,1] does the job.
6273 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6275 struct ureg_program
*ureg
= t
->ureg
;
6276 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6277 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6279 if (ctx
->Const
.NativeIntegers
) {
6280 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6283 /* MOV_SAT face_temp, input[face] */
6284 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6287 /* Use face_temp as face input from here on: */
6288 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6292 emit_compute_block_size(const struct gl_program
*prog
,
6293 struct ureg_program
*ureg
) {
6294 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6295 prog
->info
.cs
.local_size
[0]);
6296 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6297 prog
->info
.cs
.local_size
[1]);
6298 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6299 prog
->info
.cs
.local_size
[2]);
6302 struct sort_inout_decls
{
6303 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6304 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6307 const ubyte
*mapping
;
6310 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6312 * This is for the benefit of older drivers which are broken when the
6313 * declarations aren't sorted in this way.
6316 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6318 const ubyte mapping
[])
6320 sort_inout_decls sorter
;
6321 sorter
.mapping
= mapping
;
6322 std::sort(decls
, decls
+ count
, sorter
);
6326 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6328 switch (glsl_qual
) {
6329 case INTERP_MODE_NONE
:
6330 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6331 return TGSI_INTERPOLATE_COLOR
;
6332 return TGSI_INTERPOLATE_PERSPECTIVE
;
6333 case INTERP_MODE_SMOOTH
:
6334 return TGSI_INTERPOLATE_PERSPECTIVE
;
6335 case INTERP_MODE_FLAT
:
6336 return TGSI_INTERPOLATE_CONSTANT
;
6337 case INTERP_MODE_NOPERSPECTIVE
:
6338 return TGSI_INTERPOLATE_LINEAR
;
6340 assert(0 && "unexpected interp mode in st_translate_interp()");
6341 return TGSI_INTERPOLATE_PERSPECTIVE
;
6346 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6347 * \param program the program to translate
6348 * \param numInputs number of input registers used
6349 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6351 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6352 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6354 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6355 * \param numOutputs number of output registers used
6356 * \param outputMapping maps Mesa fragment program outputs to TGSI
6358 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6359 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6362 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6364 extern "C" enum pipe_error
6365 st_translate_program(
6366 struct gl_context
*ctx
,
6368 struct ureg_program
*ureg
,
6369 glsl_to_tgsi_visitor
*program
,
6370 const struct gl_program
*proginfo
,
6372 const ubyte inputMapping
[],
6373 const ubyte inputSlotToAttr
[],
6374 const ubyte inputSemanticName
[],
6375 const ubyte inputSemanticIndex
[],
6376 const ubyte interpMode
[],
6378 const ubyte outputMapping
[],
6379 const ubyte outputSemanticName
[],
6380 const ubyte outputSemanticIndex
[])
6382 struct st_translate
*t
;
6384 struct gl_program_constants
*frag_const
=
6385 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6386 enum pipe_error ret
= PIPE_OK
;
6388 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6389 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6391 t
= CALLOC_STRUCT(st_translate
);
6393 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6397 t
->procType
= procType
;
6398 t
->inputMapping
= inputMapping
;
6399 t
->outputMapping
= outputMapping
;
6401 t
->num_temp_arrays
= program
->next_array
;
6402 if (t
->num_temp_arrays
)
6403 t
->arrays
= (struct ureg_dst
*)
6404 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6407 * Declare input attributes.
6410 case PIPE_SHADER_FRAGMENT
:
6411 case PIPE_SHADER_GEOMETRY
:
6412 case PIPE_SHADER_TESS_EVAL
:
6413 case PIPE_SHADER_TESS_CTRL
:
6414 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6416 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6417 struct inout_decl
*decl
= &program
->inputs
[i
];
6418 unsigned slot
= inputMapping
[decl
->mesa_index
];
6419 struct ureg_src src
;
6420 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6422 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6423 if (tgsi_usage_mask
== 1)
6424 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6425 else if (tgsi_usage_mask
== 2)
6426 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6428 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6431 unsigned interp_mode
= 0;
6432 unsigned interp_location
= 0;
6433 if (procType
== PIPE_SHADER_FRAGMENT
) {
6435 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6437 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6439 interp_location
= decl
->interp_loc
;
6442 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6443 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6444 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6445 decl
->array_id
, decl
->size
);
6447 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6448 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6449 /* The ArrayID is set up in dst_register */
6450 t
->inputs
[slot
+ j
] = src
;
6451 t
->inputs
[slot
+ j
].ArrayID
= 0;
6452 t
->inputs
[slot
+ j
].Index
+= j
;
6457 case PIPE_SHADER_VERTEX
:
6458 for (i
= 0; i
< numInputs
; i
++) {
6459 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6462 case PIPE_SHADER_COMPUTE
:
6469 * Declare output attributes.
6472 case PIPE_SHADER_FRAGMENT
:
6473 case PIPE_SHADER_COMPUTE
:
6475 case PIPE_SHADER_GEOMETRY
:
6476 case PIPE_SHADER_TESS_EVAL
:
6477 case PIPE_SHADER_TESS_CTRL
:
6478 case PIPE_SHADER_VERTEX
:
6479 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6481 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6482 struct inout_decl
*decl
= &program
->outputs
[i
];
6483 unsigned slot
= outputMapping
[decl
->mesa_index
];
6484 struct ureg_dst dst
;
6485 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6487 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6488 if (tgsi_usage_mask
== 1)
6489 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6490 else if (tgsi_usage_mask
== 2)
6491 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6493 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6496 dst
= ureg_DECL_output_layout(ureg
,
6497 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6498 decl
->gs_out_streams
,
6499 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6501 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6502 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6503 /* The ArrayID is set up in dst_register */
6504 t
->outputs
[slot
+ j
] = dst
;
6505 t
->outputs
[slot
+ j
].ArrayID
= 0;
6506 t
->outputs
[slot
+ j
].Index
+= j
;
6515 if (procType
== PIPE_SHADER_FRAGMENT
) {
6516 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6517 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6518 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6520 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6521 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6524 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6525 /* Must do this after setting up t->inputs. */
6526 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6527 program
->wpos_transform_const
);
6530 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6531 emit_face_var(ctx
, t
);
6533 for (i
= 0; i
< numOutputs
; i
++) {
6534 switch (outputSemanticName
[i
]) {
6535 case TGSI_SEMANTIC_POSITION
:
6536 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6537 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6538 outputSemanticIndex
[i
]);
6539 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6541 case TGSI_SEMANTIC_STENCIL
:
6542 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6543 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6544 outputSemanticIndex
[i
]);
6545 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6547 case TGSI_SEMANTIC_COLOR
:
6548 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6549 TGSI_SEMANTIC_COLOR
,
6550 outputSemanticIndex
[i
]);
6552 case TGSI_SEMANTIC_SAMPLEMASK
:
6553 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6554 TGSI_SEMANTIC_SAMPLEMASK
,
6555 outputSemanticIndex
[i
]);
6556 /* TODO: If we ever support more than 32 samples, this will have
6557 * to become an array.
6559 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6562 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6563 ret
= PIPE_ERROR_BAD_INPUT
;
6568 else if (procType
== PIPE_SHADER_VERTEX
) {
6569 for (i
= 0; i
< numOutputs
; i
++) {
6570 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6571 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6573 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6574 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6575 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6580 if (procType
== PIPE_SHADER_COMPUTE
) {
6581 emit_compute_block_size(proginfo
, ureg
);
6584 /* Declare address register.
6586 if (program
->num_address_regs
> 0) {
6587 assert(program
->num_address_regs
<= 3);
6588 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6589 t
->address
[i
] = ureg_DECL_address(ureg
);
6592 /* Declare misc input registers
6595 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6597 for (i
= 0; sysInputs
; i
++) {
6598 if (sysInputs
& (1 << i
)) {
6599 unsigned semName
= _mesa_sysval_to_semantic(i
);
6601 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6603 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6604 semName
== TGSI_SEMANTIC_VERTEXID
) {
6605 /* From Gallium perspective, these system values are always
6606 * integer, and require native integer support. However, if
6607 * native integer is supported on the vertex stage but not the
6608 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6609 * assumes these system values are floats. To resolve the
6610 * inconsistency, we insert a U2F.
6612 struct st_context
*st
= st_context(ctx
);
6613 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6614 assert(procType
== PIPE_SHADER_VERTEX
);
6615 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6617 if (!ctx
->Const
.NativeIntegers
) {
6618 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6619 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6620 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6624 if (procType
== PIPE_SHADER_FRAGMENT
&&
6625 semName
== TGSI_SEMANTIC_POSITION
)
6626 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6627 program
->wpos_transform_const
);
6629 sysInputs
&= ~(1 << i
);
6634 t
->array_sizes
= program
->array_sizes
;
6635 t
->input_decls
= program
->inputs
;
6636 t
->num_input_decls
= program
->num_inputs
;
6637 t
->output_decls
= program
->outputs
;
6638 t
->num_output_decls
= program
->num_outputs
;
6640 /* Emit constants and uniforms. TGSI uses a single index space for these,
6641 * so we put all the translated regs in t->constants.
6643 if (proginfo
->Parameters
) {
6644 t
->constants
= (struct ureg_src
*)
6645 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6646 if (t
->constants
== NULL
) {
6647 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6650 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6652 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6653 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6654 case PROGRAM_STATE_VAR
:
6655 case PROGRAM_UNIFORM
:
6656 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6659 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6660 * addressing of the const buffer.
6661 * FIXME: Be smarter and recognize param arrays:
6662 * indirect addressing is only valid within the referenced
6665 case PROGRAM_CONSTANT
:
6666 if (program
->indirect_addr_consts
)
6667 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6669 t
->constants
[i
] = emit_immediate(t
,
6670 proginfo
->Parameters
->ParameterValues
[i
],
6671 proginfo
->Parameters
->Parameters
[i
].DataType
,
6680 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6681 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6682 unsigned num_const_vecs
= (size
+ 15) / 16;
6683 unsigned first
, last
;
6684 assert(num_const_vecs
> 0);
6686 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6687 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6690 /* Emit immediate values.
6692 t
->immediates
= (struct ureg_src
*)
6693 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6694 if (t
->immediates
== NULL
) {
6695 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6698 t
->num_immediates
= program
->num_immediates
;
6701 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6702 assert(i
< program
->num_immediates
);
6703 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6705 assert(i
== program
->num_immediates
);
6707 /* texture samplers */
6708 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6709 if (program
->samplers_used
& (1u << i
)) {
6710 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6712 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6714 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6715 type
, type
, type
, type
);
6719 /* Declare atomic and shader storage buffers. */
6721 struct gl_program
*prog
= program
->prog
;
6723 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6724 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6725 assert(index
< frag_const
->MaxAtomicBuffers
);
6726 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6729 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6730 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6731 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6732 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6736 if (program
->use_shared_memory
)
6737 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6739 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6740 if (program
->images_used
& (1 << i
)) {
6741 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6742 program
->image_targets
[i
],
6743 program
->image_formats
[i
],
6748 /* Emit each instruction in turn:
6750 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6751 compile_tgsi_instruction(t
, inst
);
6753 /* Set the next shader stage hint for VS and TES. */
6755 case PIPE_SHADER_VERTEX
:
6756 case PIPE_SHADER_TESS_EVAL
:
6757 if (program
->shader_program
->SeparateShader
)
6760 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6761 if (program
->shader_program
->_LinkedShaders
[i
]) {
6762 ureg_set_next_shader_processor(
6763 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6775 t
->num_constants
= 0;
6776 free(t
->immediates
);
6777 t
->num_immediates
= 0;
6783 /* ----------------------------- End TGSI code ------------------------------ */
6787 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6788 * generating Mesa IR.
6790 static struct gl_program
*
6791 get_mesa_program_tgsi(struct gl_context
*ctx
,
6792 struct gl_shader_program
*shader_program
,
6793 struct gl_linked_shader
*shader
)
6795 glsl_to_tgsi_visitor
* v
;
6796 struct gl_program
*prog
;
6797 struct gl_shader_compiler_options
*options
=
6798 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6799 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6800 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6801 unsigned skip_merge_registers
;
6803 validate_ir_tree(shader
->ir
);
6805 prog
= shader
->Program
;
6807 prog
->Parameters
= _mesa_new_parameter_list();
6808 v
= new glsl_to_tgsi_visitor();
6811 v
->shader_program
= shader_program
;
6813 v
->options
= options
;
6814 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6815 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6817 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6818 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6819 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6820 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6821 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6822 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6824 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6825 _mesa_key_pointer_equal
);
6826 skip_merge_registers
=
6827 pscreen
->get_shader_param(pscreen
, ptarget
,
6828 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6830 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6833 /* Remove reads from output registers. */
6834 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6835 lower_output_reads(shader
->Stage
, shader
->ir
);
6837 /* Emit intermediate IR for main(). */
6838 visit_exec_list(shader
->ir
, v
);
6841 /* Print out some information (for debugging purposes) used by the
6842 * optimization passes. */
6845 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6846 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6847 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6848 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6850 for (i
= 0; i
< v
->next_temp
; i
++) {
6851 first_writes
[i
] = -1;
6852 first_reads
[i
] = -1;
6853 last_writes
[i
] = -1;
6856 v
->get_first_temp_read(first_reads
);
6857 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6858 v
->get_last_temp_write(last_writes
);
6859 for (i
= 0; i
< v
->next_temp
; i
++)
6860 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6864 ralloc_free(first_writes
);
6865 ralloc_free(first_reads
);
6866 ralloc_free(last_writes
);
6867 ralloc_free(last_reads
);
6871 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6874 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6875 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6876 v
->copy_propagate();
6878 while (v
->eliminate_dead_code());
6880 v
->merge_two_dsts();
6881 if (!skip_merge_registers
)
6882 v
->merge_registers();
6883 v
->renumber_registers();
6885 /* Write the END instruction. */
6886 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6888 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6890 _mesa_log("GLSL IR for linked %s program %d:\n",
6891 _mesa_shader_stage_to_string(shader
->Stage
),
6892 shader_program
->Name
);
6893 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6897 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6898 _mesa_copy_linked_program_data(shader_program
, shader
);
6899 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6900 &prog
->info
.inputs_read
,
6901 prog
->info
.double_inputs_read
,
6902 &prog
->info
.patch_inputs_read
);
6903 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6904 &prog
->info
.outputs_written
, 0ULL,
6905 &prog
->info
.patch_outputs_written
);
6906 count_resources(v
, prog
);
6908 /* The GLSL IR won't be needed anymore. */
6909 ralloc_free(shader
->ir
);
6912 /* This must be done before the uniform storage is associated. */
6913 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6914 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6915 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6916 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6917 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6920 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6921 wposTransformState
);
6924 /* Avoid reallocation of the program parameter list, because the uniform
6925 * storage is only associated with the original parameter list.
6926 * This should be enough for Bitmap and DrawPixels constants.
6928 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6930 /* This has to be done last. Any operation the can cause
6931 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6932 * program constant) has to happen before creating this linkage.
6934 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6935 if (!shader_program
->data
->LinkStatus
) {
6936 free_glsl_to_tgsi_visitor(v
);
6937 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6941 struct st_vertex_program
*stvp
;
6942 struct st_fragment_program
*stfp
;
6943 struct st_common_program
*stp
;
6944 struct st_compute_program
*stcp
;
6946 switch (shader
->Stage
) {
6947 case MESA_SHADER_VERTEX
:
6948 stvp
= (struct st_vertex_program
*)prog
;
6949 stvp
->glsl_to_tgsi
= v
;
6951 case MESA_SHADER_FRAGMENT
:
6952 stfp
= (struct st_fragment_program
*)prog
;
6953 stfp
->glsl_to_tgsi
= v
;
6955 case MESA_SHADER_TESS_CTRL
:
6956 case MESA_SHADER_TESS_EVAL
:
6957 case MESA_SHADER_GEOMETRY
:
6958 stp
= st_common_program(prog
);
6959 stp
->glsl_to_tgsi
= v
;
6961 case MESA_SHADER_COMPUTE
:
6962 stcp
= (struct st_compute_program
*)prog
;
6963 stcp
->glsl_to_tgsi
= v
;
6966 assert(!"should not be reached");
6973 /* See if there are unsupported control flow statements. */
6974 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6976 const struct gl_shader_compiler_options
*options
;
6978 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6984 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6986 /* Other functions are skipped (same as glsl_to_tgsi). */
6987 if (strcmp(ir
->name
, "main") == 0)
6988 return visit_continue
;
6990 return visit_continue_with_parent
;
6993 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6995 if (!ir
->callee
->is_intrinsic()) {
6996 unsupported
= true; /* it's a function call */
6999 return visit_continue
;
7002 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7004 if (options
->EmitNoMainReturn
) {
7008 return visit_continue
;
7015 has_unsupported_control_flow(exec_list
*ir
,
7016 const struct gl_shader_compiler_options
*options
)
7018 ir_control_flow_info_visitor
visitor(options
);
7019 visit_list_elements(&visitor
, ir
);
7020 return visitor
.unsupported
;
7027 * Called via ctx->Driver.LinkShader()
7028 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7029 * with code lowering and other optimizations.
7032 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7034 /* Return early if we are loading the shader from on-disk cache */
7035 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
7039 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7040 assert(prog
->data
->LinkStatus
);
7042 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7043 if (prog
->_LinkedShaders
[i
] == NULL
)
7046 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7047 exec_list
*ir
= shader
->ir
;
7048 gl_shader_stage stage
= shader
->Stage
;
7049 const struct gl_shader_compiler_options
*options
=
7050 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7051 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
7052 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7053 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7054 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7055 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7056 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7057 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7059 /* If there are forms of indirect addressing that the driver
7060 * cannot handle, perform the lowering pass.
7062 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7063 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7064 lower_variable_index_to_cond_assign(stage
, ir
,
7065 options
->EmitNoIndirectInput
,
7066 options
->EmitNoIndirectOutput
,
7067 options
->EmitNoIndirectTemp
,
7068 options
->EmitNoIndirectUniform
);
7071 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7072 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7074 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7075 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7076 LOWER_UNPACK_SNORM_2x16
|
7077 LOWER_PACK_UNORM_2x16
|
7078 LOWER_UNPACK_UNORM_2x16
|
7079 LOWER_PACK_SNORM_4x8
|
7080 LOWER_UNPACK_SNORM_4x8
|
7081 LOWER_UNPACK_UNORM_4x8
|
7082 LOWER_PACK_UNORM_4x8
;
7084 if (ctx
->Extensions
.ARB_gpu_shader5
)
7085 lower_inst
|= LOWER_PACK_USE_BFI
|
7087 if (!ctx
->st
->has_half_float_packing
)
7088 lower_inst
|= LOWER_PACK_HALF_2x16
|
7089 LOWER_UNPACK_HALF_2x16
;
7091 lower_packing_builtins(ir
, lower_inst
);
7094 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7095 lower_offset_arrays(ir
);
7096 do_mat_op_to_vec(ir
);
7098 if (stage
== MESA_SHADER_FRAGMENT
)
7099 lower_blend_equation_advanced(shader
);
7101 lower_instructions(ir
,
7107 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7110 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7111 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7112 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7113 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7114 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7115 /* Assume that if ARB_gpu_shader5 is not supported
7116 * then all of the extended integer functions need
7117 * lowering. It may be necessary to add some caps
7118 * for individual instructions.
7120 (!ctx
->Extensions
.ARB_gpu_shader5
7121 ? BIT_COUNT_TO_MATH
|
7125 FIND_LSB_TO_FLOAT_CAST
|
7126 FIND_MSB_TO_FLOAT_CAST
|
7130 do_vec_index_to_cond_assign(ir
);
7131 lower_vector_insert(ir
, true);
7132 lower_quadop_vector(ir
, false);
7134 if (options
->MaxIfDepth
== 0) {
7138 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7139 /* Do it once and repeat only if there's unsupported control flow. */
7141 do_common_optimization(ir
, true, true, options
,
7142 ctx
->Const
.NativeIntegers
);
7143 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7144 options
->MaxIfDepth
, if_threshold
);
7145 } while (has_unsupported_control_flow(ir
, options
));
7147 /* Repeat it until it stops making changes. */
7150 progress
= do_common_optimization(ir
, true, true, options
,
7151 ctx
->Const
.NativeIntegers
);
7152 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7153 options
->MaxIfDepth
, if_threshold
);
7157 validate_ir_tree(ir
);
7160 build_program_resource_list(ctx
, prog
);
7162 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7163 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7167 enum pipe_shader_type ptarget
=
7168 st_shader_stage_to_ptarget(shader
->Stage
);
7169 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7170 pscreen
->get_shader_param(pscreen
, ptarget
,
7171 PIPE_SHADER_CAP_PREFERRED_IR
);
7173 struct gl_program
*linked_prog
= NULL
;
7174 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
7175 /* TODO only for GLSL VS/FS/CS for now: */
7176 switch (shader
->Stage
) {
7177 case MESA_SHADER_VERTEX
:
7178 case MESA_SHADER_FRAGMENT
:
7179 case MESA_SHADER_COMPUTE
:
7180 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
7185 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
7189 st_set_prog_affected_state_flags(linked_prog
);
7190 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7191 _mesa_shader_stage_to_program(i
),
7193 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7203 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7204 const ubyte outputMapping
[],
7205 struct pipe_stream_output_info
*so
)
7207 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7210 struct gl_transform_feedback_info
*info
=
7211 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7212 st_translate_stream_output_info2(info
, outputMapping
, so
);
7216 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7217 const ubyte outputMapping
[],
7218 struct pipe_stream_output_info
*so
)
7222 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7223 so
->output
[i
].register_index
=
7224 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7225 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7226 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7227 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7228 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7229 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7232 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7233 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7235 so
->num_outputs
= info
->NumOutputs
;