2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
129 static struct inout_decl
*
130 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
132 assert(array_id
!= 0);
134 for (unsigned i
= 0; i
< count
; i
++) {
135 struct inout_decl
*decl
= &decls
[i
];
137 if (array_id
== decl
->array_id
) {
145 static enum glsl_base_type
146 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
149 return GLSL_TYPE_ERROR
;
150 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
152 return decl
->base_type
;
153 return GLSL_TYPE_ERROR
;
156 struct hwatomic_decl
{
163 struct glsl_to_tgsi_visitor
: public ir_visitor
{
165 glsl_to_tgsi_visitor();
166 ~glsl_to_tgsi_visitor();
168 struct gl_context
*ctx
;
169 struct gl_program
*prog
;
170 struct gl_shader_program
*shader_program
;
171 struct gl_linked_shader
*shader
;
172 struct gl_shader_compiler_options
*options
;
176 unsigned *array_sizes
;
177 unsigned max_num_arrays
;
180 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
182 unsigned num_input_arrays
;
183 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
184 unsigned num_outputs
;
185 unsigned num_output_arrays
;
187 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
188 unsigned num_atomics
;
189 unsigned num_atomic_arrays
;
190 int num_address_regs
;
191 uint32_t samplers_used
;
192 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
193 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
195 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
196 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
197 bool indirect_addr_consts
;
198 int wpos_transform_const
;
200 bool native_integers
;
203 bool use_shared_memory
;
208 variable_storage
*find_variable_storage(ir_variable
*var
);
210 int add_constant(gl_register_file file
, gl_constant_value values
[8],
211 int size
, GLenum datatype
, uint16_t *swizzle_out
);
213 st_src_reg
get_temp(const glsl_type
*type
);
214 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
216 st_src_reg
st_src_reg_for_double(double val
);
217 st_src_reg
st_src_reg_for_float(float val
);
218 st_src_reg
st_src_reg_for_int(int val
);
219 st_src_reg
st_src_reg_for_int64(int64_t val
);
220 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
223 * \name Visit methods
225 * As typical for the visitor pattern, there must be one \c visit method for
226 * each concrete subclass of \c ir_instruction. Virtual base classes within
227 * the hierarchy should not have \c visit methods.
230 virtual void visit(ir_variable
*);
231 virtual void visit(ir_loop
*);
232 virtual void visit(ir_loop_jump
*);
233 virtual void visit(ir_function_signature
*);
234 virtual void visit(ir_function
*);
235 virtual void visit(ir_expression
*);
236 virtual void visit(ir_swizzle
*);
237 virtual void visit(ir_dereference_variable
*);
238 virtual void visit(ir_dereference_array
*);
239 virtual void visit(ir_dereference_record
*);
240 virtual void visit(ir_assignment
*);
241 virtual void visit(ir_constant
*);
242 virtual void visit(ir_call
*);
243 virtual void visit(ir_return
*);
244 virtual void visit(ir_discard
*);
245 virtual void visit(ir_texture
*);
246 virtual void visit(ir_if
*);
247 virtual void visit(ir_emit_vertex
*);
248 virtual void visit(ir_end_primitive
*);
249 virtual void visit(ir_barrier
*);
252 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
254 void visit_atomic_counter_intrinsic(ir_call
*);
255 void visit_ssbo_intrinsic(ir_call
*);
256 void visit_membar_intrinsic(ir_call
*);
257 void visit_shared_intrinsic(ir_call
*);
258 void visit_image_intrinsic(ir_call
*);
259 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
263 /** List of variable_storage */
264 struct hash_table
*variables
;
266 /** List of immediate_storage */
267 exec_list immediates
;
268 unsigned num_immediates
;
270 /** List of glsl_to_tgsi_instruction */
271 exec_list instructions
;
273 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
274 st_dst_reg dst
= undef_dst
,
275 st_src_reg src0
= undef_src
,
276 st_src_reg src1
= undef_src
,
277 st_src_reg src2
= undef_src
,
278 st_src_reg src3
= undef_src
);
280 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
281 st_dst_reg dst
, st_dst_reg dst1
,
282 st_src_reg src0
= undef_src
,
283 st_src_reg src1
= undef_src
,
284 st_src_reg src2
= undef_src
,
285 st_src_reg src3
= undef_src
);
287 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
289 st_src_reg src0
, st_src_reg src1
);
292 * Emit the correct dot-product instruction for the type of arguments
294 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
300 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
301 st_dst_reg dst
, st_src_reg src0
);
303 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
304 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
306 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
308 void get_deref_offsets(ir_dereference
*ir
,
309 unsigned *array_size
,
314 void calc_deref_offsets(ir_dereference
*tail
,
315 unsigned *array_elements
,
317 st_src_reg
*indirect
,
319 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
320 bool handle_bound_deref(ir_dereference
*ir
);
322 bool try_emit_mad(ir_expression
*ir
,
324 bool try_emit_mad_for_and_not(ir_expression
*ir
,
327 void emit_swz(ir_expression
*ir
);
329 bool process_move_condition(ir_rvalue
*ir
);
331 void simplify_cmp(void);
333 void rename_temp_registers(struct rename_reg_pair
*renames
);
334 void get_first_temp_read(int *first_reads
);
335 void get_first_temp_write(int *first_writes
);
336 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
337 void get_last_temp_write(int *last_writes
);
339 void copy_propagate(void);
340 int eliminate_dead_code(void);
342 void merge_two_dsts(void);
343 void merge_registers(void);
344 void renumber_registers(void);
346 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
347 st_dst_reg
*l
, st_src_reg
*r
,
348 st_src_reg
*cond
, bool cond_swap
);
353 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
355 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
357 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
361 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
365 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
369 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
372 prog
->data
->LinkStatus
= LINKING_FAILURE
;
376 swizzle_for_size(int size
)
378 static const int size_swizzles
[4] = {
379 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
380 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
381 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
382 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
385 assert((size
>= 1) && (size
<= 4));
386 return size_swizzles
[size
- 1];
390 glsl_to_tgsi_instruction
*
391 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
392 st_dst_reg dst
, st_dst_reg dst1
,
393 st_src_reg src0
, st_src_reg src1
,
394 st_src_reg src2
, st_src_reg src3
)
396 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
397 int num_reladdr
= 0, i
, j
;
398 bool dst_is_64bit
[2];
400 op
= get_opcode(op
, dst
, src0
, src1
);
402 /* If we have to do relative addressing, we want to load the ARL
403 * reg directly for one of the regs, and preload the other reladdr
404 * sources into temps.
406 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
407 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
408 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
409 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
410 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
411 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
413 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
414 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
415 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
416 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
418 if (dst
.reladdr
|| dst
.reladdr2
) {
420 emit_arl(ir
, address_reg
, *dst
.reladdr
);
422 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
426 assert(num_reladdr
== 0);
428 /* inst->op has only 8 bits. */
429 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
432 inst
->precise
= this->precise
;
433 inst
->info
= tgsi_get_opcode_info(op
);
440 inst
->is_64bit_expanded
= false;
443 inst
->tex_offsets
= NULL
;
444 inst
->tex_offset_num_offset
= 0;
446 inst
->tex_shadow
= 0;
447 /* default to float, for paths where this is not initialized
448 * (since 0==UINT which is likely wrong):
450 inst
->tex_type
= GLSL_TYPE_FLOAT
;
452 /* Update indirect addressing status used by TGSI */
453 if (dst
.reladdr
|| dst
.reladdr2
) {
455 case PROGRAM_STATE_VAR
:
456 case PROGRAM_CONSTANT
:
457 case PROGRAM_UNIFORM
:
458 this->indirect_addr_consts
= true;
460 case PROGRAM_IMMEDIATE
:
461 assert(!"immediates should not have indirect addressing");
468 for (i
= 0; i
< 4; i
++) {
469 if (inst
->src
[i
].reladdr
) {
470 switch (inst
->src
[i
].file
) {
471 case PROGRAM_STATE_VAR
:
472 case PROGRAM_CONSTANT
:
473 case PROGRAM_UNIFORM
:
474 this->indirect_addr_consts
= true;
476 case PROGRAM_IMMEDIATE
:
477 assert(!"immediates should not have indirect addressing");
487 * This section contains the double processing.
488 * GLSL just represents doubles as single channel values,
489 * however most HW and TGSI represent doubles as pairs of register channels.
491 * so we have to fixup destination writemask/index and src swizzle/indexes.
492 * dest writemasks need to translate from single channel write mask
493 * to a dual-channel writemask, but also need to modify the index,
494 * if we are touching the Z,W fields in the pre-translated writemask.
496 * src channels have similiar index modifications along with swizzle
497 * changes to we pick the XY, ZW pairs from the correct index.
499 * GLSL [0].x -> TGSI [0].xy
500 * GLSL [0].y -> TGSI [0].zw
501 * GLSL [0].z -> TGSI [1].xy
502 * GLSL [0].w -> TGSI [1].zw
504 for (j
= 0; j
< 2; j
++) {
505 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
506 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
507 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
508 enum glsl_base_type type
= find_array_type(this->outputs
,
510 inst
->dst
[j
].array_id
);
511 if (glsl_base_type_is_64bit(type
))
512 dst_is_64bit
[j
] = true;
516 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
517 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
518 glsl_to_tgsi_instruction
*dinst
= NULL
;
519 int initial_src_swz
[4], initial_src_idx
[4];
520 int initial_dst_idx
[2], initial_dst_writemask
[2];
521 /* select the writemask for dst0 or dst1 */
522 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
523 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
525 /* copy out the writemask, index and swizzles for all src/dsts. */
526 for (j
= 0; j
< 2; j
++) {
527 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
528 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
531 for (j
= 0; j
< 4; j
++) {
532 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
533 initial_src_idx
[j
] = inst
->src
[j
].index
;
537 * scan all the components in the dst writemask
538 * generate an instruction for each of them if required.
543 int i
= u_bit_scan(&writemask
);
545 /* before emitting the instruction, see if we have to adjust
546 * load / store address */
547 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
548 inst
->op
== TGSI_OPCODE_STORE
) &&
549 addr
.file
== PROGRAM_UNDEFINED
) {
550 /* We have to advance the buffer address by 16 */
551 addr
= get_temp(glsl_type::uint_type
);
552 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
553 inst
->src
[0], st_src_reg_for_int(16));
556 /* first time use previous instruction */
560 /* create a new instructions for subsequent attempts */
561 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
566 this->instructions
.push_tail(dinst
);
567 dinst
->is_64bit_expanded
= true;
569 /* modify the destination if we are splitting */
570 for (j
= 0; j
< 2; j
++) {
571 if (dst_is_64bit
[j
]) {
572 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
573 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
575 if (dinst
->op
== TGSI_OPCODE_LOAD
||
576 dinst
->op
== TGSI_OPCODE_STORE
)
577 dinst
->src
[0] = addr
;
578 if (dinst
->op
!= TGSI_OPCODE_STORE
)
579 dinst
->dst
[j
].index
++;
582 /* if we aren't writing to a double, just get the bit of the
583 * initial writemask for this channel
585 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
589 /* modify the src registers */
590 for (j
= 0; j
< 4; j
++) {
591 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
593 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
594 dinst
->src
[j
].index
= initial_src_idx
[j
];
596 dinst
->src
[j
].double_reg2
= true;
597 dinst
->src
[j
].index
++;
601 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
602 SWIZZLE_Z
, SWIZZLE_W
);
604 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
605 SWIZZLE_X
, SWIZZLE_Y
);
608 /* some opcodes are special case in what they use as sources
609 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
612 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
613 op
== TGSI_OPCODE_I2D
||
614 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
615 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
616 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
617 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
624 this->instructions
.push_tail(inst
);
631 glsl_to_tgsi_instruction
*
632 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
634 st_src_reg src0
, st_src_reg src1
,
635 st_src_reg src2
, st_src_reg src3
)
637 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
641 * Determines whether to use an integer, unsigned integer, or float opcode
642 * based on the operands and input opcode, then emits the result.
645 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
647 st_src_reg src0
, st_src_reg src1
)
649 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
651 if (op
== TGSI_OPCODE_MOV
)
654 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
655 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
656 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
657 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
659 if (is_resource_instruction(op
))
661 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
662 type
= GLSL_TYPE_INT64
;
663 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
664 type
= GLSL_TYPE_UINT64
;
665 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
666 type
= GLSL_TYPE_DOUBLE
;
667 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
668 type
= GLSL_TYPE_FLOAT
;
669 else if (native_integers
)
670 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
672 #define case7(c, f, i, u, d, i64, ui64) \
673 case TGSI_OPCODE_##c: \
674 if (type == GLSL_TYPE_UINT64) \
675 op = TGSI_OPCODE_##ui64; \
676 else if (type == GLSL_TYPE_INT64) \
677 op = TGSI_OPCODE_##i64; \
678 else if (type == GLSL_TYPE_DOUBLE) \
679 op = TGSI_OPCODE_##d; \
680 else if (type == GLSL_TYPE_INT) \
681 op = TGSI_OPCODE_##i; \
682 else if (type == GLSL_TYPE_UINT) \
683 op = TGSI_OPCODE_##u; \
685 op = TGSI_OPCODE_##f; \
688 #define casecomp(c, f, i, u, d, i64, ui64) \
689 case TGSI_OPCODE_##c: \
690 if (type == GLSL_TYPE_INT64) \
691 op = TGSI_OPCODE_##i64; \
692 else if (type == GLSL_TYPE_UINT64) \
693 op = TGSI_OPCODE_##ui64; \
694 else if (type == GLSL_TYPE_DOUBLE) \
695 op = TGSI_OPCODE_##d; \
696 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
697 op = TGSI_OPCODE_##i; \
698 else if (type == GLSL_TYPE_UINT) \
699 op = TGSI_OPCODE_##u; \
700 else if (native_integers) \
701 op = TGSI_OPCODE_##f; \
703 op = TGSI_OPCODE_##c; \
707 /* Some instructions are initially selected without considering the type.
708 * This fixes the type:
710 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
712 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
713 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
714 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
715 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
716 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
717 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
718 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
719 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
720 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
721 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
722 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
723 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
724 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
725 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
726 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
727 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
729 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
730 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
731 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
732 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
733 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
734 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
735 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
736 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
738 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
739 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
740 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
741 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
747 assert(op
!= TGSI_OPCODE_LAST
);
751 glsl_to_tgsi_instruction
*
752 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
753 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
756 static const enum tgsi_opcode dot_opcodes
[] = {
757 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
760 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
764 * Emits TGSI scalar opcodes to produce unique answers across channels.
766 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
767 * channel determines the result across all channels. So to do a vec4
768 * of this operation, we want to emit a scalar per source channel used
769 * to produce dest channels.
772 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
774 st_src_reg orig_src0
, st_src_reg orig_src1
)
777 int done_mask
= ~dst
.writemask
;
779 /* TGSI RCP is a scalar operation splatting results to all channels,
780 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
783 for (i
= 0; i
< 4; i
++) {
784 GLuint this_mask
= (1 << i
);
785 st_src_reg src0
= orig_src0
;
786 st_src_reg src1
= orig_src1
;
788 if (done_mask
& this_mask
)
791 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
792 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
793 for (j
= i
+ 1; j
< 4; j
++) {
794 /* If there is another enabled component in the destination that is
795 * derived from the same inputs, generate its value on this pass as
798 if (!(done_mask
& (1 << j
)) &&
799 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
800 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
801 this_mask
|= (1 << j
);
804 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
805 src0_swiz
, src0_swiz
);
806 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
807 src1_swiz
, src1_swiz
);
809 dst
.writemask
= this_mask
;
810 emit_asm(ir
, op
, dst
, src0
, src1
);
811 done_mask
|= this_mask
;
816 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
817 st_dst_reg dst
, st_src_reg src0
)
819 st_src_reg undef
= undef_src
;
821 undef
.swizzle
= SWIZZLE_XXXX
;
823 emit_scalar(ir
, op
, dst
, src0
, undef
);
827 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
828 st_dst_reg dst
, st_src_reg src0
)
830 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
832 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
833 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
836 op
= TGSI_OPCODE_UARL
;
839 assert(dst
.file
== PROGRAM_ADDRESS
);
840 if (dst
.index
>= this->num_address_regs
)
841 this->num_address_regs
= dst
.index
+ 1;
843 emit_asm(NULL
, op
, dst
, src0
);
847 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
848 gl_constant_value values
[8], int size
,
850 uint16_t *swizzle_out
)
852 if (file
== PROGRAM_CONSTANT
) {
853 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
854 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
855 values
, size
, datatype
,
858 *swizzle_out
= swizzle
;
862 assert(file
== PROGRAM_IMMEDIATE
);
865 immediate_storage
*entry
;
866 int size32
= size
* ((datatype
== GL_DOUBLE
||
867 datatype
== GL_INT64_ARB
||
868 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
871 /* Search immediate storage to see if we already have an identical
872 * immediate that we can use instead of adding a duplicate entry.
874 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
875 immediate_storage
*tmp
= entry
;
877 for (i
= 0; i
* 4 < size32
; i
++) {
878 int slot_size
= MIN2(size32
- (i
* 4), 4);
879 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
881 if (memcmp(tmp
->values
, &values
[i
* 4],
882 slot_size
* sizeof(gl_constant_value
)))
885 /* Everything matches, keep going until the full size is matched */
886 tmp
= (immediate_storage
*)tmp
->next
;
889 /* The full value matched */
896 for (i
= 0; i
* 4 < size32
; i
++) {
897 int slot_size
= MIN2(size32
- (i
* 4), 4);
898 /* Add this immediate to the list. */
899 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
900 slot_size
, datatype
);
901 this->immediates
.push_tail(entry
);
902 this->num_immediates
++;
908 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
910 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
911 union gl_constant_value uval
;
914 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
920 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
922 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
923 union gl_constant_value uval
[2];
925 memcpy(uval
, &val
, sizeof(uval
));
926 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
927 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
932 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
934 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
935 union gl_constant_value uval
;
937 assert(native_integers
);
940 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
946 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
948 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
949 union gl_constant_value uval
[2];
951 memcpy(uval
, &val
, sizeof(uval
));
952 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
953 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
959 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
962 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
963 st_src_reg_for_int(val
);
965 return st_src_reg_for_float(val
);
969 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
971 return type
->count_attribute_slots(is_vs_input
);
975 type_size(const struct glsl_type
*type
)
977 return type
->count_attribute_slots(false);
981 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
982 exec_list
*instructions
, ir_constant
*access
)
985 * emit_asm() might have actually split the op into pieces, e.g. for
986 * double stores. We have to go back and fix up all the generated ops.
988 enum tgsi_opcode op
= inst
->op
;
990 inst
->resource
= *buf
;
992 inst
->buffer_access
= access
->value
.u
[0];
994 if (inst
== instructions
->get_head_raw())
996 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
998 if (inst
->op
== TGSI_OPCODE_UADD
) {
999 if (inst
== instructions
->get_head_raw())
1001 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1003 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1007 * If the given GLSL type is an array or matrix or a structure containing
1008 * an array/matrix member, return true. Else return false.
1010 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1011 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1012 * we have an array that might be indexed with a variable, we need to use
1013 * the later storage type.
1016 type_has_array_or_matrix(const glsl_type
*type
)
1018 if (type
->is_array() || type
->is_matrix())
1021 if (type
->is_record()) {
1022 for (unsigned i
= 0; i
< type
->length
; i
++) {
1023 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1034 * In the initial pass of codegen, we assign temporary numbers to
1035 * intermediate results. (not SSA -- variable assignments will reuse
1039 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1043 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1048 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1049 if (next_array
>= max_num_arrays
) {
1050 max_num_arrays
+= 32;
1051 array_sizes
= (unsigned*)
1052 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1055 src
.file
= PROGRAM_ARRAY
;
1057 src
.array_id
= next_array
+ 1;
1058 array_sizes
[next_array
] = type_size(type
);
1062 src
.file
= PROGRAM_TEMPORARY
;
1063 src
.index
= next_temp
;
1064 next_temp
+= type_size(type
);
1067 if (type
->is_array() || type
->is_record()) {
1068 src
.swizzle
= SWIZZLE_NOOP
;
1070 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1077 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1079 struct hash_entry
*entry
;
1081 entry
= _mesa_hash_table_search(this->variables
, var
);
1085 return (variable_storage
*)entry
->data
;
1089 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1091 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1092 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1093 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1096 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1098 const ir_state_slot
*const slots
= ir
->get_state_slots();
1099 assert(slots
!= NULL
);
1101 /* Check if this statevar's setup in the STATE file exactly
1102 * matches how we'll want to reference it as a
1103 * struct/array/whatever. If not, then we need to move it into
1104 * temporary storage and hope that it'll get copy-propagated
1107 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1108 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1113 variable_storage
*storage
;
1115 if (i
== ir
->get_num_state_slots()) {
1116 /* We'll set the index later. */
1117 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1119 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1123 /* The variable_storage constructor allocates slots based on the size
1124 * of the type. However, this had better match the number of state
1125 * elements that we're going to copy into the new temporary.
1127 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1129 dst
= st_dst_reg(get_temp(ir
->type
));
1131 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1134 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1138 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1139 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1142 if (storage
->file
== PROGRAM_STATE_VAR
) {
1143 if (storage
->index
== -1) {
1144 storage
->index
= index
;
1146 assert(index
== storage
->index
+ (int)i
);
1149 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1150 * the data being moved since MOV does not care about the type of
1151 * data it is moving, and we don't want to declare registers with
1152 * array or struct types.
1154 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1155 src
.swizzle
= slots
[i
].swizzle
;
1156 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1157 /* even a float takes up a whole vec4 reg in a struct/array. */
1162 if (storage
->file
== PROGRAM_TEMPORARY
&&
1163 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1164 fail_link(this->shader_program
,
1165 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1166 ir
->name
, dst
.index
- storage
->index
,
1167 type_size(ir
->type
));
1173 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1175 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1177 visit_exec_list(&ir
->body_instructions
, this);
1179 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1183 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1186 case ir_loop_jump::jump_break
:
1187 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1189 case ir_loop_jump::jump_continue
:
1190 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1197 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1204 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1206 /* Ignore function bodies other than main() -- we shouldn't see calls to
1207 * them since they should all be inlined before we get to glsl_to_tgsi.
1209 if (strcmp(ir
->name
, "main") == 0) {
1210 const ir_function_signature
*sig
;
1213 sig
= ir
->matching_signature(NULL
, &empty
, false);
1217 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1224 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1226 int nonmul_operand
= 1 - mul_operand
;
1228 st_dst_reg result_dst
;
1230 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1231 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1234 expr
->operands
[0]->accept(this);
1236 expr
->operands
[1]->accept(this);
1238 ir
->operands
[nonmul_operand
]->accept(this);
1241 this->result
= get_temp(ir
->type
);
1242 result_dst
= st_dst_reg(this->result
);
1243 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1244 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1250 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1252 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1253 * implemented using multiplication, and logical-or is implemented using
1254 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1255 * As result, the logical expression (a & !b) can be rewritten as:
1259 * - (a * 1) - (a * b)
1263 * This final expression can be implemented as a single MAD(a, -b, a)
1267 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1270 const int other_operand
= 1 - try_operand
;
1273 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1274 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1277 ir
->operands
[other_operand
]->accept(this);
1279 expr
->operands
[0]->accept(this);
1282 b
.negate
= ~b
.negate
;
1284 this->result
= get_temp(ir
->type
);
1285 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1291 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1292 st_src_reg
*reg
, int *num_reladdr
)
1294 if (!reg
->reladdr
&& !reg
->reladdr2
)
1298 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1300 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1302 if (*num_reladdr
!= 1) {
1303 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1305 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1313 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1315 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1317 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1319 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1320 if (try_emit_mad(ir
, 1))
1322 if (try_emit_mad(ir
, 0))
1326 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1328 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1329 if (try_emit_mad_for_and_not(ir
, 1))
1331 if (try_emit_mad_for_and_not(ir
, 0))
1335 if (ir
->operation
== ir_quadop_vector
)
1336 assert(!"ir_quadop_vector should have been lowered");
1338 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1339 this->result
.file
= PROGRAM_UNDEFINED
;
1340 ir
->operands
[operand
]->accept(this);
1341 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1342 printf("Failed to get tree for expression operand:\n");
1343 ir
->operands
[operand
]->print();
1347 op
[operand
] = this->result
;
1349 /* Matrix expression operands should have been broken down to vector
1350 * operations already.
1352 assert(!ir
->operands
[operand
]->type
->is_matrix());
1355 visit_expression(ir
, op
);
1358 /* The non-recursive part of the expression visitor lives in a separate
1359 * function and should be prevented from being inlined, to avoid a stack
1360 * explosion when deeply nested expressions are visited.
1363 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1365 st_src_reg result_src
;
1366 st_dst_reg result_dst
;
1368 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1369 if (ir
->operands
[1] &&
1370 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1371 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1372 st_src_reg
*swz_op
= NULL
;
1373 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1374 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1376 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1377 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1381 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1382 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1383 swizzle_x
, swizzle_x
);
1385 vector_elements
= MAX2(vector_elements
,
1386 ir
->operands
[1]->type
->vector_elements
);
1388 if (ir
->operands
[2] &&
1389 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1390 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1391 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1392 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1393 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1394 swizzle_x
, swizzle_x
);
1397 this->result
.file
= PROGRAM_UNDEFINED
;
1399 /* Storage for our result. Ideally for an assignment we'd be using
1400 * the actual storage for the result here, instead.
1402 result_src
= get_temp(ir
->type
);
1403 /* convenience for the emit functions below. */
1404 result_dst
= st_dst_reg(result_src
);
1405 /* Limit writes to the channels that will be used by result_src later.
1406 * This does limit this temp's use as a temporary for multi-instruction
1409 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1411 switch (ir
->operation
) {
1412 case ir_unop_logic_not
:
1413 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1414 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1416 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1417 * older GPUs implement SEQ using multiple instructions (i915 uses two
1418 * SGE instructions and a MUL instruction). Since our logic values are
1419 * 0.0 and 1.0, 1-x also implements !x.
1421 op
[0].negate
= ~op
[0].negate
;
1422 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1423 st_src_reg_for_float(1.0));
1427 if (result_dst
.type
== GLSL_TYPE_INT64
||
1428 result_dst
.type
== GLSL_TYPE_UINT64
)
1429 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1430 else if (result_dst
.type
== GLSL_TYPE_INT
||
1431 result_dst
.type
== GLSL_TYPE_UINT
)
1432 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1433 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1434 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1436 op
[0].negate
= ~op
[0].negate
;
1440 case ir_unop_subroutine_to_int
:
1441 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1444 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1445 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1446 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1447 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1448 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1449 result_dst
.type
== GLSL_TYPE_UINT64
)
1450 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1452 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1455 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1458 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1462 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1465 assert(!"not reached: should be handled by exp_to_exp2");
1468 assert(!"not reached: should be handled by log_to_log2");
1471 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1474 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1477 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1479 case ir_unop_saturate
: {
1480 glsl_to_tgsi_instruction
*inst
;
1481 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1482 inst
->saturate
= true;
1487 case ir_unop_dFdx_coarse
:
1488 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1490 case ir_unop_dFdx_fine
:
1491 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1494 case ir_unop_dFdy_coarse
:
1495 case ir_unop_dFdy_fine
:
1497 /* The X component contains 1 or -1 depending on whether the framebuffer
1498 * is a FBO or the window system buffer, respectively.
1499 * It is then multiplied with the source operand of DDY.
1501 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1502 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1504 unsigned transform_y_index
=
1505 _mesa_add_state_reference(this->prog
->Parameters
,
1508 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1510 glsl_type::vec4_type
);
1511 transform_y
.swizzle
= SWIZZLE_XXXX
;
1513 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1515 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1516 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1517 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1521 case ir_unop_frexp_sig
:
1522 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1525 case ir_unop_frexp_exp
:
1526 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1529 case ir_unop_noise
: {
1530 /* At some point, a motivated person could add a better
1531 * implementation of noise. Currently not even the nvidia
1532 * binary drivers do anything more than this. In any case, the
1533 * place to do this is in the GL state tracker, not the poor
1536 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1541 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1544 op
[1].negate
= ~op
[1].negate
;
1545 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1549 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1552 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1555 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1556 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1558 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1562 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1564 case ir_binop_gequal
:
1565 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1567 case ir_binop_equal
:
1568 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1570 case ir_binop_nequal
:
1571 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1573 case ir_binop_all_equal
:
1574 /* "==" operator producing a scalar boolean. */
1575 if (ir
->operands
[0]->type
->is_vector() ||
1576 ir
->operands
[1]->type
->is_vector()) {
1577 st_src_reg temp
= get_temp(native_integers
?
1578 glsl_type::uvec4_type
:
1579 glsl_type::vec4_type
);
1581 if (native_integers
) {
1582 st_dst_reg temp_dst
= st_dst_reg(temp
);
1583 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1585 if (ir
->operands
[0]->type
->is_boolean() &&
1586 ir
->operands
[1]->as_constant() &&
1587 ir
->operands
[1]->as_constant()->is_one()) {
1588 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1590 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1593 /* Emit 1-3 AND operations to combine the SEQ results. */
1594 switch (ir
->operands
[0]->type
->vector_elements
) {
1598 temp_dst
.writemask
= WRITEMASK_Y
;
1599 temp1
.swizzle
= SWIZZLE_YYYY
;
1600 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1601 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1604 temp_dst
.writemask
= WRITEMASK_X
;
1605 temp1
.swizzle
= SWIZZLE_XXXX
;
1606 temp2
.swizzle
= SWIZZLE_YYYY
;
1607 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1608 temp_dst
.writemask
= WRITEMASK_Y
;
1609 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1610 temp2
.swizzle
= SWIZZLE_WWWW
;
1611 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1614 temp1
.swizzle
= SWIZZLE_XXXX
;
1615 temp2
.swizzle
= SWIZZLE_YYYY
;
1616 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1618 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1620 /* After the dot-product, the value will be an integer on the
1621 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1623 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1625 /* Negating the result of the dot-product gives values on the range
1626 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1627 * This is achieved using SGE.
1629 st_src_reg sge_src
= result_src
;
1630 sge_src
.negate
= ~sge_src
.negate
;
1631 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1632 st_src_reg_for_float(0.0));
1635 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1638 case ir_binop_any_nequal
:
1639 /* "!=" operator producing a scalar boolean. */
1640 if (ir
->operands
[0]->type
->is_vector() ||
1641 ir
->operands
[1]->type
->is_vector()) {
1642 st_src_reg temp
= get_temp(native_integers
?
1643 glsl_type::uvec4_type
:
1644 glsl_type::vec4_type
);
1645 if (ir
->operands
[0]->type
->is_boolean() &&
1646 ir
->operands
[1]->as_constant() &&
1647 ir
->operands
[1]->as_constant()->is_zero()) {
1648 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1650 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1653 if (native_integers
) {
1654 st_dst_reg temp_dst
= st_dst_reg(temp
);
1655 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1657 /* Emit 1-3 OR operations to combine the SNE results. */
1658 switch (ir
->operands
[0]->type
->vector_elements
) {
1662 temp_dst
.writemask
= WRITEMASK_Y
;
1663 temp1
.swizzle
= SWIZZLE_YYYY
;
1664 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1665 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1668 temp_dst
.writemask
= WRITEMASK_X
;
1669 temp1
.swizzle
= SWIZZLE_XXXX
;
1670 temp2
.swizzle
= SWIZZLE_YYYY
;
1671 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1672 temp_dst
.writemask
= WRITEMASK_Y
;
1673 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1674 temp2
.swizzle
= SWIZZLE_WWWW
;
1675 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1678 temp1
.swizzle
= SWIZZLE_XXXX
;
1679 temp2
.swizzle
= SWIZZLE_YYYY
;
1680 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1682 /* After the dot-product, the value will be an integer on the
1683 * range [0,4]. Zero stays zero, and positive values become 1.0.
1685 glsl_to_tgsi_instruction
*const dp
=
1686 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1687 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1688 /* The clamping to [0,1] can be done for free in the fragment
1689 * shader with a saturate.
1691 dp
->saturate
= true;
1693 /* Negating the result of the dot-product gives values on the
1694 * range [-4, 0]. Zero stays zero, and negative values become
1695 * 1.0. This achieved using SLT.
1697 st_src_reg slt_src
= result_src
;
1698 slt_src
.negate
= ~slt_src
.negate
;
1699 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1700 st_src_reg_for_float(0.0));
1704 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1708 case ir_binop_logic_xor
:
1709 if (native_integers
)
1710 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1712 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1715 case ir_binop_logic_or
: {
1716 if (native_integers
) {
1717 /* If integers are used as booleans, we can use an actual "or"
1720 assert(native_integers
);
1721 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1723 /* After the addition, the value will be an integer on the
1724 * range [0,2]. Zero stays zero, and positive values become 1.0.
1726 glsl_to_tgsi_instruction
*add
=
1727 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1728 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1729 /* The clamping to [0,1] can be done for free in the fragment
1730 * shader with a saturate if floats are being used as boolean
1733 add
->saturate
= true;
1735 /* Negating the result of the addition gives values on the range
1736 * [-2, 0]. Zero stays zero, and negative values become 1.0
1737 * This is achieved using SLT.
1739 st_src_reg slt_src
= result_src
;
1740 slt_src
.negate
= ~slt_src
.negate
;
1741 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1742 st_src_reg_for_float(0.0));
1748 case ir_binop_logic_and
:
1749 /* If native integers are disabled, the bool args are stored as float 0.0
1750 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1751 * actual AND opcode.
1753 if (native_integers
)
1754 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1756 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1760 assert(ir
->operands
[0]->type
->is_vector());
1761 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1762 emit_dp(ir
, result_dst
, op
[0], op
[1],
1763 ir
->operands
[0]->type
->vector_elements
);
1768 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1770 /* This is the only instruction sequence that makes the game "Risen"
1771 * render correctly. ABS is not required for the game, but since GLSL
1772 * declares negative values as "undefined", allowing us to do whatever
1773 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1776 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1777 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1781 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1784 if (native_integers
) {
1785 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1788 /* fallthrough to next case otherwise */
1790 if (native_integers
) {
1791 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1792 st_src_reg_for_float(1.0));
1795 /* fallthrough to next case otherwise */
1798 case ir_unop_i642u64
:
1799 case ir_unop_u642i64
:
1800 /* Converting between signed and unsigned integers is a no-op. */
1802 result_src
.type
= result_dst
.type
;
1805 if (native_integers
) {
1806 /* Booleans are stored as integers using ~0 for true and 0 for false.
1807 * GLSL requires that int(bool) return 1 for true and 0 for false.
1808 * This conversion is done with AND, but it could be done with NEG.
1810 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1811 st_src_reg_for_int(1));
1813 /* Booleans and integers are both stored as floats when native
1814 * integers are disabled.
1820 if (native_integers
)
1821 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1823 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1826 if (native_integers
)
1827 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1829 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1831 case ir_unop_bitcast_f2i
:
1832 case ir_unop_bitcast_f2u
:
1833 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1834 if (op
[0].negate
|| op
[0].abs
)
1835 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1838 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1841 case ir_unop_bitcast_i2f
:
1842 case ir_unop_bitcast_u2f
:
1844 result_src
.type
= GLSL_TYPE_FLOAT
;
1847 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1848 st_src_reg_for_float(0.0));
1851 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1852 st_src_reg_for_double(0.0));
1855 if (native_integers
)
1856 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1857 st_src_reg_for_int(0));
1859 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1860 st_src_reg_for_float(0.0));
1862 case ir_unop_bitcast_u642d
:
1863 case ir_unop_bitcast_i642d
:
1865 result_src
.type
= GLSL_TYPE_DOUBLE
;
1867 case ir_unop_bitcast_d2i64
:
1869 result_src
.type
= GLSL_TYPE_INT64
;
1871 case ir_unop_bitcast_d2u64
:
1873 result_src
.type
= GLSL_TYPE_UINT64
;
1876 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1879 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1882 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1884 case ir_unop_round_even
:
1885 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1888 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1892 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1895 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1898 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1901 case ir_unop_bit_not
:
1902 if (native_integers
) {
1903 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1907 if (native_integers
) {
1908 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1911 case ir_binop_lshift
:
1912 case ir_binop_rshift
:
1913 if (native_integers
) {
1914 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1915 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1918 if (glsl_base_type_is_64bit(op
[0].type
)) {
1919 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1922 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1923 ->type
->components()));
1924 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1929 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1932 case ir_binop_bit_and
:
1933 if (native_integers
) {
1934 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1937 case ir_binop_bit_xor
:
1938 if (native_integers
) {
1939 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1942 case ir_binop_bit_or
:
1943 if (native_integers
) {
1944 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1948 assert(!"GLSL 1.30 features unsupported");
1951 case ir_binop_ubo_load
: {
1952 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1953 ir_rvalue
*block
= ir
->operands
[0];
1954 ir_rvalue
*offset
= ir
->operands
[1];
1955 ir_constant
*const_block
= block
->as_constant();
1957 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1958 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1959 ir
->type
->base_type
);
1961 cbuf
.has_index2
= true;
1964 block
->accept(this);
1965 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1966 *cbuf
.reladdr
= this->result
;
1967 emit_arl(ir
, sampler_reladdr
, this->result
);
1970 /* Calculate the surface offset */
1971 offset
->accept(this);
1972 st_src_reg off
= this->result
;
1974 glsl_to_tgsi_instruction
*inst
=
1975 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1977 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1978 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1979 st_src_reg_for_int(0));
1981 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1984 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1985 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1986 unsigned const_offset
= const_offset_ir
?
1987 const_offset_ir
->value
.u
[0] : 0;
1988 unsigned const_block
= const_uniform_block
?
1989 const_uniform_block
->value
.u
[0] + 1 : 1;
1990 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1993 cbuf
.type
= ir
->type
->base_type
;
1994 cbuf
.file
= PROGRAM_CONSTANT
;
1996 cbuf
.reladdr
= NULL
;
1999 cbuf
.index2D
= const_block
;
2001 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2003 if (const_offset_ir
) {
2004 /* Constant index into constant buffer */
2005 cbuf
.reladdr
= NULL
;
2006 cbuf
.index
= const_offset
/ 16;
2008 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2009 st_src_reg offset
= op
[1];
2011 /* The OpenGL spec is written in such a way that accesses with
2012 * non-constant offset are almost always vec4-aligned. The only
2013 * exception to this are members of structs in arrays of structs:
2014 * each struct in an array of structs is at least vec4-aligned,
2015 * but single-element and [ui]vec2 members of the struct may be at
2016 * an offset that is not a multiple of 16 bytes.
2018 * Here, we extract that offset, relying on previous passes to
2019 * always generate offset expressions of the form
2020 * (+ expr constant_offset).
2022 * Note that the std430 layout, which allows more cases of
2023 * alignment less than vec4 in arrays, is not supported for
2024 * uniform blocks, so we do not have to deal with it here.
2026 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2027 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2028 if (const_offset_ir
) {
2029 const_offset
= const_offset_ir
->value
.u
[0];
2030 cbuf
.index
= const_offset
/ 16;
2031 offset_expr
->operands
[0]->accept(this);
2032 offset
= this->result
;
2036 /* Relative/variable index into constant buffer */
2037 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2038 st_src_reg_for_int(4));
2039 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2040 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2043 if (const_uniform_block
) {
2044 /* Constant constant buffer */
2045 cbuf
.reladdr2
= NULL
;
2047 /* Relative/variable constant buffer */
2048 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2049 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2051 cbuf
.has_index2
= true;
2053 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2054 if (glsl_base_type_is_64bit(cbuf
.type
))
2055 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2056 const_offset
% 16 / 8,
2057 const_offset
% 16 / 8,
2058 const_offset
% 16 / 8);
2060 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2061 const_offset
% 16 / 4,
2062 const_offset
% 16 / 4,
2063 const_offset
% 16 / 4);
2065 if (ir
->type
->is_boolean()) {
2066 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2067 st_src_reg_for_int(0));
2069 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2075 /* note: we have to reorder the three args here */
2076 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2079 if (this->ctx
->Const
.NativeIntegers
)
2080 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2082 op
[0].negate
= ~op
[0].negate
;
2083 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2086 case ir_triop_bitfield_extract
:
2087 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2089 case ir_quadop_bitfield_insert
:
2090 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2092 case ir_unop_bitfield_reverse
:
2093 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2095 case ir_unop_bit_count
:
2096 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2098 case ir_unop_find_msb
:
2099 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2101 case ir_unop_find_lsb
:
2102 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2104 case ir_binop_imul_high
:
2105 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2108 /* In theory, MAD is incorrect here. */
2110 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2112 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2114 case ir_unop_interpolate_at_centroid
:
2115 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2117 case ir_binop_interpolate_at_offset
: {
2118 /* The y coordinate needs to be flipped for the default fb */
2119 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2120 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2122 unsigned transform_y_index
=
2123 _mesa_add_state_reference(this->prog
->Parameters
,
2126 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2128 glsl_type::vec4_type
);
2129 transform_y
.swizzle
= SWIZZLE_XXXX
;
2131 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2132 st_dst_reg temp_dst
= st_dst_reg(temp
);
2134 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2135 temp_dst
.writemask
= WRITEMASK_Y
;
2136 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2137 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2140 case ir_binop_interpolate_at_sample
:
2141 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2145 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2148 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2151 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2154 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2157 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2160 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2162 case ir_unop_unpack_double_2x32
:
2163 case ir_unop_pack_double_2x32
:
2164 case ir_unop_unpack_int_2x32
:
2165 case ir_unop_pack_int_2x32
:
2166 case ir_unop_unpack_uint_2x32
:
2167 case ir_unop_pack_uint_2x32
:
2168 case ir_unop_unpack_sampler_2x32
:
2169 case ir_unop_pack_sampler_2x32
:
2170 case ir_unop_unpack_image_2x32
:
2171 case ir_unop_pack_image_2x32
:
2172 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2175 case ir_binop_ldexp
:
2176 if (ir
->operands
[0]->type
->is_double()) {
2177 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2178 } else if (ir
->operands
[0]->type
->is_float()) {
2179 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2181 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2185 case ir_unop_pack_half_2x16
:
2186 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2188 case ir_unop_unpack_half_2x16
:
2189 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2192 case ir_unop_get_buffer_size
: {
2193 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2194 int buf_base
= ctx
->st
->has_hw_atomics
2195 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
2198 buf_base
+ (const_offset
? const_offset
->value
.u
[0] : 0),
2200 if (!const_offset
) {
2201 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2202 *buffer
.reladdr
= op
[0];
2203 emit_arl(ir
, sampler_reladdr
, op
[0]);
2205 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2211 case ir_unop_b2i64
: {
2212 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2213 st_dst_reg temp_dst
= st_dst_reg(temp
);
2214 unsigned orig_swz
= op
[0].swizzle
;
2216 * To convert unsigned to 64-bit:
2217 * zero Y channel, copy X channel.
2219 temp_dst
.writemask
= WRITEMASK_Y
;
2220 if (vector_elements
> 1)
2221 temp_dst
.writemask
|= WRITEMASK_W
;
2222 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2223 temp_dst
.writemask
= WRITEMASK_X
;
2224 if (vector_elements
> 1)
2225 temp_dst
.writemask
|= WRITEMASK_Z
;
2226 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2227 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2228 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2229 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2231 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2233 result_src
.type
= GLSL_TYPE_UINT64
;
2234 if (vector_elements
> 2) {
2235 /* Subtle: We rely on the fact that get_temp here returns the next
2236 * TGSI temporary register directly after the temp register used for
2237 * the first two components, so that the result gets picked up
2240 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2241 st_dst_reg temp_dst
= st_dst_reg(temp
);
2242 temp_dst
.writemask
= WRITEMASK_Y
;
2243 if (vector_elements
> 3)
2244 temp_dst
.writemask
|= WRITEMASK_W
;
2245 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2247 temp_dst
.writemask
= WRITEMASK_X
;
2248 if (vector_elements
> 3)
2249 temp_dst
.writemask
|= WRITEMASK_Z
;
2250 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2251 GET_SWZ(orig_swz
, 2),
2252 GET_SWZ(orig_swz
, 3),
2253 GET_SWZ(orig_swz
, 3));
2254 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2255 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2257 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2258 st_src_reg_for_int(1));
2265 case ir_unop_i642u
: {
2266 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2267 st_dst_reg temp_dst
= st_dst_reg(temp
);
2268 unsigned orig_swz
= op
[0].swizzle
;
2269 unsigned orig_idx
= op
[0].index
;
2271 temp_dst
.writemask
= WRITEMASK_X
;
2273 for (el
= 0; el
< vector_elements
; el
++) {
2274 unsigned swz
= GET_SWZ(orig_swz
, el
);
2276 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2277 SWIZZLE_Z
, SWIZZLE_Z
);
2279 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2280 SWIZZLE_X
, SWIZZLE_X
);
2282 op
[0].index
= orig_idx
+ 1;
2283 op
[0].type
= GLSL_TYPE_UINT
;
2284 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2285 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2288 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2289 result_src
.type
= GLSL_TYPE_UINT
;
2291 result_src
.type
= GLSL_TYPE_INT
;
2295 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2296 st_src_reg_for_int64(0));
2299 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2302 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2305 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2308 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2311 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2314 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2317 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2320 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2323 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2326 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2328 /* these might be needed */
2329 case ir_unop_pack_snorm_2x16
:
2330 case ir_unop_pack_unorm_2x16
:
2331 case ir_unop_pack_snorm_4x8
:
2332 case ir_unop_pack_unorm_4x8
:
2334 case ir_unop_unpack_snorm_2x16
:
2335 case ir_unop_unpack_unorm_2x16
:
2336 case ir_unop_unpack_snorm_4x8
:
2337 case ir_unop_unpack_unorm_4x8
:
2339 case ir_quadop_vector
:
2340 case ir_binop_vector_extract
:
2341 case ir_triop_vector_insert
:
2342 case ir_binop_carry
:
2343 case ir_binop_borrow
:
2344 case ir_unop_ssbo_unsized_array_length
:
2345 /* This operation is not supported, or should have already been handled.
2347 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2351 this->result
= result_src
;
2356 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2362 /* Note that this is only swizzles in expressions, not those on the left
2363 * hand side of an assignment, which do write masking. See ir_assignment
2367 ir
->val
->accept(this);
2369 assert(src
.file
!= PROGRAM_UNDEFINED
);
2370 assert(ir
->type
->vector_elements
> 0);
2372 for (i
= 0; i
< 4; i
++) {
2373 if (i
< ir
->type
->vector_elements
) {
2376 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2379 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2382 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2385 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2389 /* If the type is smaller than a vec4, replicate the last
2392 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2396 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2401 /* Test if the variable is an array. Note that geometry and
2402 * tessellation shader inputs are outputs are always arrays (except
2403 * for patch inputs), so only the array element type is considered.
2406 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2408 const glsl_type
*type
= var
->type
;
2410 *remove_array
= false;
2412 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2413 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2416 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2417 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2418 stage
== MESA_SHADER_TESS_CTRL
) &&
2420 if (!var
->type
->is_array())
2421 return false; /* a system value probably */
2423 type
= var
->type
->fields
.array
;
2424 *remove_array
= true;
2427 return type
->is_array() || type
->is_matrix();
2431 st_translate_interp_loc(ir_variable
*var
)
2433 if (var
->data
.centroid
)
2434 return TGSI_INTERPOLATE_LOC_CENTROID
;
2435 else if (var
->data
.sample
)
2436 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2438 return TGSI_INTERPOLATE_LOC_CENTER
;
2442 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2444 variable_storage
*entry
;
2445 ir_variable
*var
= ir
->var
;
2448 if (handle_bound_deref(ir
->as_dereference()))
2451 entry
= find_variable_storage(ir
->var
);
2454 switch (var
->data
.mode
) {
2455 case ir_var_uniform
:
2456 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2457 var
->data
.param_index
);
2458 _mesa_hash_table_insert(this->variables
, var
, entry
);
2460 case ir_var_shader_in
: {
2461 /* The linker assigns locations for varyings and attributes,
2462 * including deprecated builtins (like gl_Color), user-assign
2463 * generic attributes (glBindVertexLocation), and
2464 * user-defined varyings.
2466 assert(var
->data
.location
!= -1);
2468 const glsl_type
*type_without_array
= var
->type
->without_array();
2469 struct inout_decl
*decl
= &inputs
[num_inputs
];
2470 unsigned component
= var
->data
.location_frac
;
2471 unsigned num_components
;
2474 if (type_without_array
->is_64bit())
2475 component
= component
/ 2;
2476 if (type_without_array
->vector_elements
)
2477 num_components
= type_without_array
->vector_elements
;
2481 decl
->mesa_index
= var
->data
.location
;
2482 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2483 decl
->interp_loc
= st_translate_interp_loc(var
);
2484 decl
->base_type
= type_without_array
->base_type
;
2485 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2487 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2488 decl
->array_id
= num_input_arrays
+ 1;
2495 decl
->size
= type_size(var
->type
->fields
.array
);
2497 decl
->size
= type_size(var
->type
);
2499 entry
= new(mem_ctx
) variable_storage(var
,
2503 entry
->component
= component
;
2505 _mesa_hash_table_insert(this->variables
, var
, entry
);
2509 case ir_var_shader_out
: {
2510 assert(var
->data
.location
!= -1);
2512 const glsl_type
*type_without_array
= var
->type
->without_array();
2513 struct inout_decl
*decl
= &outputs
[num_outputs
];
2514 unsigned component
= var
->data
.location_frac
;
2515 unsigned num_components
;
2518 decl
->invariant
= var
->data
.invariant
;
2520 if (type_without_array
->is_64bit())
2521 component
= component
/ 2;
2522 if (type_without_array
->vector_elements
)
2523 num_components
= type_without_array
->vector_elements
;
2527 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2528 decl
->base_type
= type_without_array
->base_type
;
2529 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2530 if (var
->data
.stream
& (1u << 31)) {
2531 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2533 assert(var
->data
.stream
< 4);
2534 decl
->gs_out_streams
= 0;
2535 for (unsigned i
= 0; i
< num_components
; ++i
)
2536 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2539 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2540 decl
->array_id
= num_output_arrays
+ 1;
2541 num_output_arrays
++;
2547 decl
->size
= type_size(var
->type
->fields
.array
);
2549 decl
->size
= type_size(var
->type
);
2551 if (var
->data
.fb_fetch_output
) {
2552 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2553 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2554 var
->type
, component
, decl
->array_id
);
2555 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2556 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2559 entry
= new(mem_ctx
) variable_storage(var
,
2564 entry
->component
= component
;
2566 _mesa_hash_table_insert(this->variables
, var
, entry
);
2570 case ir_var_system_value
:
2571 entry
= new(mem_ctx
) variable_storage(var
,
2572 PROGRAM_SYSTEM_VALUE
,
2573 var
->data
.location
);
2576 case ir_var_temporary
:
2577 st_src_reg src
= get_temp(var
->type
);
2579 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2581 _mesa_hash_table_insert(this->variables
, var
, entry
);
2587 printf("Failed to make storage for %s\n", var
->name
);
2592 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2593 entry
->component
, entry
->array_id
);
2594 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2595 var
->data
.mode
== ir_var_shader_in
&&
2596 var
->type
->without_array()->is_double())
2597 this->result
.is_double_vertex_input
= true;
2598 if (!native_integers
)
2599 this->result
.type
= GLSL_TYPE_FLOAT
;
2603 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2604 GLbitfield64
* usage_mask
,
2605 GLbitfield64 double_usage_mask
,
2606 GLbitfield
* patch_usage_mask
)
2611 /* Fix array declarations by removing unused array elements at both ends
2612 * of the arrays. For example, mat4[3] where only mat[1] is used.
2614 for (i
= 0; i
< count
; i
++) {
2615 struct inout_decl
*decl
= &decls
[i
];
2616 if (!decl
->array_id
)
2619 /* Shrink the beginning. */
2620 for (j
= 0; j
< (int)decl
->size
; j
++) {
2621 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2622 if (*patch_usage_mask
&
2623 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2627 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2629 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2638 /* Shrink the end. */
2639 for (j
= decl
->size
-1; j
>= 0; j
--) {
2640 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2641 if (*patch_usage_mask
&
2642 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2646 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2648 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2655 /* When not all entries of an array are accessed, we mark them as used
2656 * here anyway, to ensure that the input/output mapping logic doesn't get
2659 * TODO This happens when an array isn't used via indirect access, which
2660 * some game ports do (at least eON-based). There is an optimization
2661 * opportunity here by replacing the array declaration with non-array
2662 * declarations of those slots that are actually used.
2664 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2665 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2666 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2668 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2674 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2679 ir_variable
*var
= ir
->variable_referenced();
2681 if (handle_bound_deref(ir
->as_dereference()))
2684 /* We only need the logic provided by st_glsl_storage_type_size()
2685 * for arrays of structs. Indirect sampler and image indexing is handled
2688 int element_size
= ir
->type
->without_array()->is_record() ?
2689 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2690 type_size(ir
->type
);
2692 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2694 ir
->array
->accept(this);
2697 if (!src
.has_index2
) {
2698 switch (this->prog
->Target
) {
2699 case GL_TESS_CONTROL_PROGRAM_NV
:
2700 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2701 !ir
->variable_referenced()->data
.patch
;
2703 case GL_TESS_EVALUATION_PROGRAM_NV
:
2704 is_2D
= src
.file
== PROGRAM_INPUT
&&
2705 !ir
->variable_referenced()->data
.patch
;
2707 case GL_GEOMETRY_PROGRAM_NV
:
2708 is_2D
= src
.file
== PROGRAM_INPUT
;
2718 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2719 src
.file
== PROGRAM_INPUT
)
2720 element_size
= attrib_type_size(ir
->type
, true);
2722 src
.index2D
= index
->value
.i
[0];
2723 src
.has_index2
= true;
2725 src
.index
+= index
->value
.i
[0] * element_size
;
2727 /* Variable index array dereference. It eats the "vec4" of the
2728 * base of the array and an index that offsets the TGSI register
2731 ir
->array_index
->accept(this);
2733 st_src_reg index_reg
;
2735 if (element_size
== 1) {
2736 index_reg
= this->result
;
2738 index_reg
= get_temp(native_integers
?
2739 glsl_type::int_type
: glsl_type::float_type
);
2741 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2742 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2745 /* If there was already a relative address register involved, add the
2746 * new and the old together to get the new offset.
2748 if (!is_2D
&& src
.reladdr
!= NULL
) {
2749 st_src_reg accum_reg
= get_temp(native_integers
?
2750 glsl_type::int_type
: glsl_type::float_type
);
2752 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2753 index_reg
, *src
.reladdr
);
2755 index_reg
= accum_reg
;
2759 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2760 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2762 src
.has_index2
= true;
2764 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2765 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2769 /* Change the register type to the element type of the array. */
2770 src
.type
= ir
->type
->base_type
;
2776 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2779 const glsl_type
*struct_type
= ir
->record
->type
;
2780 ir_variable
*var
= ir
->record
->variable_referenced();
2783 if (handle_bound_deref(ir
->as_dereference()))
2786 ir
->record
->accept(this);
2788 assert(ir
->field_idx
>= 0);
2790 for (i
= 0; i
< struct_type
->length
; i
++) {
2791 if (i
== (unsigned) ir
->field_idx
)
2793 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2794 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2797 /* If the type is smaller than a vec4, replicate the last channel out. */
2798 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2799 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2801 this->result
.swizzle
= SWIZZLE_NOOP
;
2803 this->result
.index
+= offset
;
2804 this->result
.type
= ir
->type
->base_type
;
2808 * We want to be careful in assignment setup to hit the actual storage
2809 * instead of potentially using a temporary like we might with the
2810 * ir_dereference handler.
2813 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2815 /* The LHS must be a dereference. If the LHS is a variable indexed array
2816 * access of a vector, it must be separated into a series conditional moves
2817 * before reaching this point (see ir_vec_index_to_cond_assign).
2819 assert(ir
->as_dereference());
2820 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2822 assert(!deref_array
->array
->type
->is_vector());
2825 /* Use the rvalue deref handler for the most part. We write swizzles using
2826 * the writemask, but we do extract the base component for enhanced layouts
2827 * from the source swizzle.
2830 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2831 return st_dst_reg(v
->result
);
2835 * Process the condition of a conditional assignment
2837 * Examines the condition of a conditional assignment to generate the optimal
2838 * first operand of a \c CMP instruction. If the condition is a relational
2839 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2840 * used as the source for the \c CMP instruction. Otherwise the comparison
2841 * is processed to a boolean result, and the boolean result is used as the
2842 * operand to the CMP instruction.
2845 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2847 ir_rvalue
*src_ir
= ir
;
2849 bool switch_order
= false;
2851 ir_expression
*const expr
= ir
->as_expression();
2853 if (native_integers
) {
2854 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2855 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2856 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2857 type
== GLSL_TYPE_BOOL
) {
2858 if (expr
->operation
== ir_binop_equal
) {
2859 if (expr
->operands
[0]->is_zero()) {
2860 src_ir
= expr
->operands
[1];
2861 switch_order
= true;
2863 else if (expr
->operands
[1]->is_zero()) {
2864 src_ir
= expr
->operands
[0];
2865 switch_order
= true;
2868 else if (expr
->operation
== ir_binop_nequal
) {
2869 if (expr
->operands
[0]->is_zero()) {
2870 src_ir
= expr
->operands
[1];
2872 else if (expr
->operands
[1]->is_zero()) {
2873 src_ir
= expr
->operands
[0];
2879 src_ir
->accept(this);
2880 return switch_order
;
2883 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2884 bool zero_on_left
= false;
2886 if (expr
->operands
[0]->is_zero()) {
2887 src_ir
= expr
->operands
[1];
2888 zero_on_left
= true;
2889 } else if (expr
->operands
[1]->is_zero()) {
2890 src_ir
= expr
->operands
[0];
2891 zero_on_left
= false;
2895 * (a < 0) T F F ( a < 0) T F F
2896 * (0 < a) F F T (-a < 0) F F T
2897 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2898 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2900 * Note that exchanging the order of 0 and 'a' in the comparison simply
2901 * means that the value of 'a' should be negated.
2904 switch (expr
->operation
) {
2906 switch_order
= false;
2907 negate
= zero_on_left
;
2910 case ir_binop_gequal
:
2911 switch_order
= true;
2912 negate
= zero_on_left
;
2916 /* This isn't the right kind of comparison afterall, so make sure
2917 * the whole condition is visited.
2925 src_ir
->accept(this);
2927 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2928 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2929 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2930 * computing the condition.
2933 this->result
.negate
= ~this->result
.negate
;
2935 return switch_order
;
2939 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2940 st_dst_reg
*l
, st_src_reg
*r
,
2941 st_src_reg
*cond
, bool cond_swap
)
2943 if (type
->is_record()) {
2944 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2945 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2951 if (type
->is_array()) {
2952 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2953 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2958 if (type
->is_matrix()) {
2959 const struct glsl_type
*vec_type
;
2961 vec_type
= glsl_type::get_instance(type
->is_double()
2962 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2963 type
->vector_elements
, 1);
2965 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2966 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2971 assert(type
->is_scalar() || type
->is_vector());
2973 l
->type
= type
->base_type
;
2974 r
->type
= type
->base_type
;
2976 st_src_reg l_src
= st_src_reg(*l
);
2978 if (l_src
.file
== PROGRAM_OUTPUT
&&
2979 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
2980 (l_src
.index
== FRAG_RESULT_DEPTH
||
2981 l_src
.index
== FRAG_RESULT_STENCIL
)) {
2982 /* This is a special case because the source swizzles will be shifted
2983 * later to account for the difference between GLSL (where they're
2984 * plain floats) and TGSI (where they're Z and Y components). */
2985 l_src
.swizzle
= SWIZZLE_XXXX
;
2988 if (native_integers
) {
2989 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2990 cond_swap
? l_src
: *r
,
2991 cond_swap
? *r
: l_src
);
2993 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2994 cond_swap
? l_src
: *r
,
2995 cond_swap
? *r
: l_src
);
2998 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3002 if (type
->is_dual_slot()) {
3004 if (r
->is_double_vertex_input
== false)
3010 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3016 /* all generated instructions need to be flaged as precise */
3017 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3018 ir
->rhs
->accept(this);
3021 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3025 int first_enabled_chan
= 0;
3027 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3029 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3030 variable
->data
.mode
== ir_var_shader_out
&&
3031 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3032 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3033 assert(ir
->lhs
->type
->is_scalar());
3034 assert(ir
->write_mask
== WRITEMASK_X
);
3036 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3037 l
.writemask
= WRITEMASK_Z
;
3039 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3040 l
.writemask
= WRITEMASK_Y
;
3042 } else if (ir
->write_mask
== 0) {
3043 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3045 unsigned num_elements
=
3046 ir
->lhs
->type
->without_array()->vector_elements
;
3049 l
.writemask
= u_bit_consecutive(0, num_elements
);
3051 /* The type is a struct or an array of (array of) structs. */
3052 l
.writemask
= WRITEMASK_XYZW
;
3055 l
.writemask
= ir
->write_mask
;
3058 for (int i
= 0; i
< 4; i
++) {
3059 if (l
.writemask
& (1 << i
)) {
3060 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3065 l
.writemask
= l
.writemask
<< dst_component
;
3067 /* Swizzle a small RHS vector into the channels being written.
3069 * glsl ir treats write_mask as dictating how many channels are
3070 * present on the RHS while TGSI treats write_mask as just
3071 * showing which channels of the vec4 RHS get written.
3073 for (int i
= 0; i
< 4; i
++) {
3074 if (l
.writemask
& (1 << i
))
3075 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3077 swizzles
[i
] = first_enabled_chan
;
3079 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3080 swizzles
[2], swizzles
[3]);
3083 assert(l
.file
!= PROGRAM_UNDEFINED
);
3084 assert(r
.file
!= PROGRAM_UNDEFINED
);
3086 if (ir
->condition
) {
3087 const bool switch_order
= this->process_move_condition(ir
->condition
);
3088 st_src_reg condition
= this->result
;
3090 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3091 } else if (ir
->rhs
->as_expression() &&
3092 this->instructions
.get_tail() &&
3093 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3094 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3095 type_size(ir
->lhs
->type
) == 1 &&
3096 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3097 /* To avoid emitting an extra MOV when assigning an expression to a
3098 * variable, emit the last instruction of the expression again, but
3099 * replace the destination register with the target of the assignment.
3100 * Dead code elimination will remove the original instruction.
3102 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3103 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3104 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3105 new_inst
->saturate
= inst
->saturate
;
3106 new_inst
->resource
= inst
->resource
;
3107 inst
->dead_mask
= inst
->dst
[0].writemask
;
3109 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3116 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3119 GLdouble stack_vals
[4] = { 0 };
3120 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3121 GLenum gl_type
= GL_NONE
;
3122 unsigned int i
, elements
;
3123 static int in_array
= 0;
3124 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3126 /* Unfortunately, 4 floats is all we can get into
3127 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3128 * aggregate constant and move each constant value into it. If we
3129 * get lucky, copy propagation will eliminate the extra moves.
3131 if (ir
->type
->is_record()) {
3132 st_src_reg temp_base
= get_temp(ir
->type
);
3133 st_dst_reg temp
= st_dst_reg(temp_base
);
3135 for (i
= 0; i
< ir
->type
->length
; i
++) {
3136 ir_constant
*const field_value
= ir
->get_record_field(i
);
3137 int size
= type_size(field_value
->type
);
3141 field_value
->accept(this);
3144 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3145 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3151 this->result
= temp_base
;
3155 if (ir
->type
->is_array()) {
3156 st_src_reg temp_base
= get_temp(ir
->type
);
3157 st_dst_reg temp
= st_dst_reg(temp_base
);
3158 int size
= type_size(ir
->type
->fields
.array
);
3163 for (i
= 0; i
< ir
->type
->length
; i
++) {
3164 ir
->const_elements
[i
]->accept(this);
3166 for (int j
= 0; j
< size
; j
++) {
3167 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3173 this->result
= temp_base
;
3178 if (ir
->type
->is_matrix()) {
3179 st_src_reg mat
= get_temp(ir
->type
);
3180 st_dst_reg mat_column
= st_dst_reg(mat
);
3182 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3183 switch (ir
->type
->base_type
) {
3184 case GLSL_TYPE_FLOAT
:
3185 values
= (gl_constant_value
*)
3186 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3188 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3189 src
.index
= add_constant(file
,
3191 ir
->type
->vector_elements
,
3194 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3196 case GLSL_TYPE_DOUBLE
:
3197 values
= (gl_constant_value
*)
3198 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3199 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3200 src
.index
= add_constant(file
,
3202 ir
->type
->vector_elements
,
3205 if (ir
->type
->vector_elements
>= 2) {
3206 mat_column
.writemask
= WRITEMASK_XY
;
3207 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3208 SWIZZLE_X
, SWIZZLE_Y
);
3209 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3211 mat_column
.writemask
= WRITEMASK_X
;
3212 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3213 SWIZZLE_X
, SWIZZLE_X
);
3214 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3217 if (ir
->type
->vector_elements
> 2) {
3218 if (ir
->type
->vector_elements
== 4) {
3219 mat_column
.writemask
= WRITEMASK_ZW
;
3220 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3221 SWIZZLE_X
, SWIZZLE_Y
);
3222 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3224 mat_column
.writemask
= WRITEMASK_Z
;
3225 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3226 SWIZZLE_Y
, SWIZZLE_Y
);
3227 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3228 mat_column
.writemask
= WRITEMASK_XYZW
;
3229 src
.swizzle
= SWIZZLE_XYZW
;
3235 unreachable("Illegal matrix constant type.\n");
3244 elements
= ir
->type
->vector_elements
;
3245 switch (ir
->type
->base_type
) {
3246 case GLSL_TYPE_FLOAT
:
3248 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3249 values
[i
].f
= ir
->value
.f
[i
];
3252 case GLSL_TYPE_DOUBLE
:
3253 gl_type
= GL_DOUBLE
;
3254 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3255 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3258 case GLSL_TYPE_INT64
:
3259 gl_type
= GL_INT64_ARB
;
3260 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3261 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3264 case GLSL_TYPE_UINT64
:
3265 gl_type
= GL_UNSIGNED_INT64_ARB
;
3266 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3267 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3270 case GLSL_TYPE_UINT
:
3271 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3272 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3273 if (native_integers
)
3274 values
[i
].u
= ir
->value
.u
[i
];
3276 values
[i
].f
= ir
->value
.u
[i
];
3280 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3281 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3282 if (native_integers
)
3283 values
[i
].i
= ir
->value
.i
[i
];
3285 values
[i
].f
= ir
->value
.i
[i
];
3288 case GLSL_TYPE_BOOL
:
3289 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3290 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3291 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3294 case GLSL_TYPE_SAMPLER
:
3295 case GLSL_TYPE_IMAGE
:
3296 gl_type
= GL_UNSIGNED_INT
;
3298 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3299 values
[1].u
= ir
->value
.u64
[0] >> 32;
3302 assert(!"Non-float/uint/int/bool/sampler/image constant");
3305 this->result
= st_src_reg(file
, -1, ir
->type
);
3306 this->result
.index
= add_constant(file
,
3310 &this->result
.swizzle
);
3314 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3316 exec_node
*param
= ir
->actual_parameters
.get_head();
3317 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3318 ir_variable
*location
= deref
->variable_referenced();
3319 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3320 /* Calculate the surface offset */
3322 unsigned array_size
= 0, base
= 0;
3324 st_src_reg resource
;
3326 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3328 if (has_hw_atomics
) {
3329 variable_storage
*entry
= find_variable_storage(location
);
3330 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3331 location
->data
.binding
);
3334 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3336 _mesa_hash_table_insert(this->variables
, location
, entry
);
3338 atomic_info
[num_atomics
].location
= location
->data
.location
;
3339 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3340 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3341 if (atomic_info
[num_atomics
].size
== 0)
3342 atomic_info
[num_atomics
].size
= 1;
3343 atomic_info
[num_atomics
].array_id
= 0;
3347 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3348 if (atomic_info
[entry
->index
].array_id
== 0) {
3349 num_atomic_arrays
++;
3350 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3352 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3355 buffer
.index
= index
;
3356 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3357 buffer
.has_index2
= true;
3359 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3360 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3361 *buffer
.reladdr
= offset
;
3362 emit_arl(ir
, sampler_reladdr
, offset
);
3364 offset
= st_src_reg_for_int(0);
3368 st_src_reg
buffer(PROGRAM_BUFFER
, location
->data
.binding
,
3369 GLSL_TYPE_ATOMIC_UINT
);
3371 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3372 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3373 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3374 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3375 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3377 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3382 ir
->return_deref
->accept(this);
3383 st_dst_reg
dst(this->result
);
3384 dst
.writemask
= WRITEMASK_X
;
3386 glsl_to_tgsi_instruction
*inst
;
3388 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3389 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3390 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3391 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3392 st_src_reg_for_int(1));
3393 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3394 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3395 st_src_reg_for_int(-1));
3396 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3398 param
= param
->get_next();
3399 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3402 st_src_reg data
= this->result
, data2
= undef_src
;
3403 enum tgsi_opcode opcode
;
3404 switch (ir
->callee
->intrinsic_id
) {
3405 case ir_intrinsic_atomic_counter_add
:
3406 opcode
= TGSI_OPCODE_ATOMUADD
;
3408 case ir_intrinsic_atomic_counter_min
:
3409 opcode
= TGSI_OPCODE_ATOMIMIN
;
3411 case ir_intrinsic_atomic_counter_max
:
3412 opcode
= TGSI_OPCODE_ATOMIMAX
;
3414 case ir_intrinsic_atomic_counter_and
:
3415 opcode
= TGSI_OPCODE_ATOMAND
;
3417 case ir_intrinsic_atomic_counter_or
:
3418 opcode
= TGSI_OPCODE_ATOMOR
;
3420 case ir_intrinsic_atomic_counter_xor
:
3421 opcode
= TGSI_OPCODE_ATOMXOR
;
3423 case ir_intrinsic_atomic_counter_exchange
:
3424 opcode
= TGSI_OPCODE_ATOMXCHG
;
3426 case ir_intrinsic_atomic_counter_comp_swap
: {
3427 opcode
= TGSI_OPCODE_ATOMCAS
;
3428 param
= param
->get_next();
3429 val
= ((ir_instruction
*)param
)->as_rvalue();
3431 data2
= this->result
;
3435 assert(!"Unexpected intrinsic");
3439 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3442 inst
->resource
= resource
;
3446 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3448 exec_node
*param
= ir
->actual_parameters
.get_head();
3450 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3452 param
= param
->get_next();
3453 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3455 ir_constant
*const_block
= block
->as_constant();
3456 int buf_base
= st_context(ctx
)->has_hw_atomics
3457 ? 0 : ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
;
3460 buf_base
+ (const_block
? const_block
->value
.u
[0] : 0),
3464 block
->accept(this);
3465 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3466 *buffer
.reladdr
= this->result
;
3467 emit_arl(ir
, sampler_reladdr
, this->result
);
3470 /* Calculate the surface offset */
3471 offset
->accept(this);
3472 st_src_reg off
= this->result
;
3474 st_dst_reg dst
= undef_dst
;
3475 if (ir
->return_deref
) {
3476 ir
->return_deref
->accept(this);
3477 dst
= st_dst_reg(this->result
);
3478 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3481 glsl_to_tgsi_instruction
*inst
;
3483 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3484 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3485 if (dst
.type
== GLSL_TYPE_BOOL
)
3486 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3487 st_src_reg_for_int(0));
3488 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3489 param
= param
->get_next();
3490 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3493 param
= param
->get_next();
3494 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3496 dst
.writemask
= write_mask
->value
.u
[0];
3498 dst
.type
= this->result
.type
;
3499 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3501 param
= param
->get_next();
3502 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3505 st_src_reg data
= this->result
, data2
= undef_src
;
3506 enum tgsi_opcode opcode
;
3507 switch (ir
->callee
->intrinsic_id
) {
3508 case ir_intrinsic_ssbo_atomic_add
:
3509 opcode
= TGSI_OPCODE_ATOMUADD
;
3511 case ir_intrinsic_ssbo_atomic_min
:
3512 opcode
= TGSI_OPCODE_ATOMIMIN
;
3514 case ir_intrinsic_ssbo_atomic_max
:
3515 opcode
= TGSI_OPCODE_ATOMIMAX
;
3517 case ir_intrinsic_ssbo_atomic_and
:
3518 opcode
= TGSI_OPCODE_ATOMAND
;
3520 case ir_intrinsic_ssbo_atomic_or
:
3521 opcode
= TGSI_OPCODE_ATOMOR
;
3523 case ir_intrinsic_ssbo_atomic_xor
:
3524 opcode
= TGSI_OPCODE_ATOMXOR
;
3526 case ir_intrinsic_ssbo_atomic_exchange
:
3527 opcode
= TGSI_OPCODE_ATOMXCHG
;
3529 case ir_intrinsic_ssbo_atomic_comp_swap
:
3530 opcode
= TGSI_OPCODE_ATOMCAS
;
3531 param
= param
->get_next();
3532 val
= ((ir_instruction
*)param
)->as_rvalue();
3534 data2
= this->result
;
3537 assert(!"Unexpected intrinsic");
3541 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3544 param
= param
->get_next();
3545 ir_constant
*access
= NULL
;
3546 if (!param
->is_tail_sentinel()) {
3547 access
= ((ir_instruction
*)param
)->as_constant();
3551 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3555 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3557 switch (ir
->callee
->intrinsic_id
) {
3558 case ir_intrinsic_memory_barrier
:
3559 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3560 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3561 TGSI_MEMBAR_ATOMIC_BUFFER
|
3562 TGSI_MEMBAR_SHADER_IMAGE
|
3563 TGSI_MEMBAR_SHARED
));
3565 case ir_intrinsic_memory_barrier_atomic_counter
:
3566 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3567 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3569 case ir_intrinsic_memory_barrier_buffer
:
3570 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3571 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3573 case ir_intrinsic_memory_barrier_image
:
3574 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3575 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3577 case ir_intrinsic_memory_barrier_shared
:
3578 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3579 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3581 case ir_intrinsic_group_memory_barrier
:
3582 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3583 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3584 TGSI_MEMBAR_ATOMIC_BUFFER
|
3585 TGSI_MEMBAR_SHADER_IMAGE
|
3586 TGSI_MEMBAR_SHARED
|
3587 TGSI_MEMBAR_THREAD_GROUP
));
3590 assert(!"Unexpected memory barrier intrinsic");
3595 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3597 exec_node
*param
= ir
->actual_parameters
.get_head();
3599 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3601 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3603 /* Calculate the surface offset */
3604 offset
->accept(this);
3605 st_src_reg off
= this->result
;
3607 st_dst_reg dst
= undef_dst
;
3608 if (ir
->return_deref
) {
3609 ir
->return_deref
->accept(this);
3610 dst
= st_dst_reg(this->result
);
3611 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3614 glsl_to_tgsi_instruction
*inst
;
3616 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3617 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3618 inst
->resource
= buffer
;
3619 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3620 param
= param
->get_next();
3621 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3624 param
= param
->get_next();
3625 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3627 dst
.writemask
= write_mask
->value
.u
[0];
3629 dst
.type
= this->result
.type
;
3630 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3631 inst
->resource
= buffer
;
3633 param
= param
->get_next();
3634 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3637 st_src_reg data
= this->result
, data2
= undef_src
;
3638 enum tgsi_opcode opcode
;
3639 switch (ir
->callee
->intrinsic_id
) {
3640 case ir_intrinsic_shared_atomic_add
:
3641 opcode
= TGSI_OPCODE_ATOMUADD
;
3643 case ir_intrinsic_shared_atomic_min
:
3644 opcode
= TGSI_OPCODE_ATOMIMIN
;
3646 case ir_intrinsic_shared_atomic_max
:
3647 opcode
= TGSI_OPCODE_ATOMIMAX
;
3649 case ir_intrinsic_shared_atomic_and
:
3650 opcode
= TGSI_OPCODE_ATOMAND
;
3652 case ir_intrinsic_shared_atomic_or
:
3653 opcode
= TGSI_OPCODE_ATOMOR
;
3655 case ir_intrinsic_shared_atomic_xor
:
3656 opcode
= TGSI_OPCODE_ATOMXOR
;
3658 case ir_intrinsic_shared_atomic_exchange
:
3659 opcode
= TGSI_OPCODE_ATOMXCHG
;
3661 case ir_intrinsic_shared_atomic_comp_swap
:
3662 opcode
= TGSI_OPCODE_ATOMCAS
;
3663 param
= param
->get_next();
3664 val
= ((ir_instruction
*)param
)->as_rvalue();
3666 data2
= this->result
;
3669 assert(!"Unexpected intrinsic");
3673 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3674 inst
->resource
= buffer
;
3679 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3680 bool *memory_coherent
, bool *memory_volatile
,
3681 bool *memory_restrict
, unsigned *image_format
)
3684 switch (ir
->ir_type
) {
3685 case ir_type_dereference_record
: {
3686 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3687 const glsl_type
*struct_type
= deref_record
->record
->type
;
3688 int fild_idx
= deref_record
->field_idx
;
3690 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3692 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3694 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3696 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3698 struct_type
->fields
.structure
[fild_idx
].image_format
;
3702 case ir_type_dereference_array
: {
3703 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3704 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3705 memory_coherent
, memory_volatile
, memory_restrict
,
3710 case ir_type_dereference_variable
: {
3711 ir_variable
*var
= ir
->variable_referenced();
3713 *type
= var
->type
->without_array();
3714 *memory_coherent
= var
->data
.memory_coherent
;
3715 *memory_volatile
= var
->data
.memory_volatile
;
3716 *memory_restrict
= var
->data
.memory_restrict
;
3717 *image_format
= var
->data
.image_format
;
3727 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3729 exec_node
*param
= ir
->actual_parameters
.get_head();
3731 ir_dereference
*img
= (ir_dereference
*)param
;
3732 const ir_variable
*imgvar
= img
->variable_referenced();
3733 unsigned sampler_array_size
= 1, sampler_base
= 0;
3734 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3735 unsigned image_format
= 0;
3736 const glsl_type
*type
= NULL
;
3738 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3739 &memory_restrict
, &image_format
);
3742 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3744 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3745 &index
, &reladdr
, !imgvar
->contains_bindless());
3747 image
.index
= index
;
3748 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3749 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3750 *image
.reladdr
= reladdr
;
3751 emit_arl(ir
, sampler_reladdr
, reladdr
);
3754 st_dst_reg dst
= undef_dst
;
3755 if (ir
->return_deref
) {
3756 ir
->return_deref
->accept(this);
3757 dst
= st_dst_reg(this->result
);
3758 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3761 glsl_to_tgsi_instruction
*inst
;
3763 st_src_reg bindless
;
3764 if (imgvar
->contains_bindless()) {
3766 bindless
= this->result
;
3769 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3770 dst
.writemask
= WRITEMASK_XYZ
;
3771 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3772 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3773 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3774 st_dst_reg dstres
= st_dst_reg(res
);
3775 dstres
.writemask
= WRITEMASK_W
;
3776 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3777 res
.swizzle
= SWIZZLE_WWWW
;
3778 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3780 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3782 st_dst_reg coord_dst
;
3783 coord
= get_temp(glsl_type::ivec4_type
);
3784 coord_dst
= st_dst_reg(coord
);
3785 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3786 param
= param
->get_next();
3787 ((ir_dereference
*)param
)->accept(this);
3788 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3789 coord
.swizzle
= SWIZZLE_XXXX
;
3790 switch (type
->coordinate_components()) {
3791 case 4: assert(!"unexpected coord count");
3793 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3795 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3798 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3799 param
= param
->get_next();
3800 ((ir_dereference
*)param
)->accept(this);
3801 st_src_reg sample
= this->result
;
3802 sample
.swizzle
= SWIZZLE_XXXX
;
3803 coord_dst
.writemask
= WRITEMASK_W
;
3804 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3805 coord
.swizzle
|= SWIZZLE_W
<< 9;
3808 param
= param
->get_next();
3809 if (!param
->is_tail_sentinel()) {
3810 ((ir_dereference
*)param
)->accept(this);
3811 arg1
= this->result
;
3812 param
= param
->get_next();
3815 if (!param
->is_tail_sentinel()) {
3816 ((ir_dereference
*)param
)->accept(this);
3817 arg2
= this->result
;
3818 param
= param
->get_next();
3821 assert(param
->is_tail_sentinel());
3823 enum tgsi_opcode opcode
;
3824 switch (ir
->callee
->intrinsic_id
) {
3825 case ir_intrinsic_image_load
:
3826 opcode
= TGSI_OPCODE_LOAD
;
3828 case ir_intrinsic_image_store
:
3829 opcode
= TGSI_OPCODE_STORE
;
3831 case ir_intrinsic_image_atomic_add
:
3832 opcode
= TGSI_OPCODE_ATOMUADD
;
3834 case ir_intrinsic_image_atomic_min
:
3835 opcode
= TGSI_OPCODE_ATOMIMIN
;
3837 case ir_intrinsic_image_atomic_max
:
3838 opcode
= TGSI_OPCODE_ATOMIMAX
;
3840 case ir_intrinsic_image_atomic_and
:
3841 opcode
= TGSI_OPCODE_ATOMAND
;
3843 case ir_intrinsic_image_atomic_or
:
3844 opcode
= TGSI_OPCODE_ATOMOR
;
3846 case ir_intrinsic_image_atomic_xor
:
3847 opcode
= TGSI_OPCODE_ATOMXOR
;
3849 case ir_intrinsic_image_atomic_exchange
:
3850 opcode
= TGSI_OPCODE_ATOMXCHG
;
3852 case ir_intrinsic_image_atomic_comp_swap
:
3853 opcode
= TGSI_OPCODE_ATOMCAS
;
3856 assert(!"Unexpected intrinsic");
3860 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3861 if (opcode
== TGSI_OPCODE_STORE
)
3862 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3865 if (imgvar
->contains_bindless()) {
3866 inst
->resource
= bindless
;
3867 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3868 SWIZZLE_X
, SWIZZLE_Y
);
3870 inst
->resource
= image
;
3871 inst
->sampler_array_size
= sampler_array_size
;
3872 inst
->sampler_base
= sampler_base
;
3875 inst
->tex_target
= type
->sampler_index();
3876 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3877 _mesa_get_shader_image_format(image_format
));
3879 if (memory_coherent
)
3880 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3881 if (memory_restrict
)
3882 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3883 if (memory_volatile
)
3884 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3888 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
3890 ir
->return_deref
->accept(this);
3891 st_dst_reg dst
= st_dst_reg(this->result
);
3893 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3895 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3896 unsigned num_src
= 0;
3897 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3898 assert(num_src
< ARRAY_SIZE(src
));
3900 this->result
.file
= PROGRAM_UNDEFINED
;
3901 param
->accept(this);
3902 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3904 src
[num_src
] = this->result
;
3908 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3912 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3914 ir_function_signature
*sig
= ir
->callee
;
3916 /* Filter out intrinsics */
3917 switch (sig
->intrinsic_id
) {
3918 case ir_intrinsic_atomic_counter_read
:
3919 case ir_intrinsic_atomic_counter_increment
:
3920 case ir_intrinsic_atomic_counter_predecrement
:
3921 case ir_intrinsic_atomic_counter_add
:
3922 case ir_intrinsic_atomic_counter_min
:
3923 case ir_intrinsic_atomic_counter_max
:
3924 case ir_intrinsic_atomic_counter_and
:
3925 case ir_intrinsic_atomic_counter_or
:
3926 case ir_intrinsic_atomic_counter_xor
:
3927 case ir_intrinsic_atomic_counter_exchange
:
3928 case ir_intrinsic_atomic_counter_comp_swap
:
3929 visit_atomic_counter_intrinsic(ir
);
3932 case ir_intrinsic_ssbo_load
:
3933 case ir_intrinsic_ssbo_store
:
3934 case ir_intrinsic_ssbo_atomic_add
:
3935 case ir_intrinsic_ssbo_atomic_min
:
3936 case ir_intrinsic_ssbo_atomic_max
:
3937 case ir_intrinsic_ssbo_atomic_and
:
3938 case ir_intrinsic_ssbo_atomic_or
:
3939 case ir_intrinsic_ssbo_atomic_xor
:
3940 case ir_intrinsic_ssbo_atomic_exchange
:
3941 case ir_intrinsic_ssbo_atomic_comp_swap
:
3942 visit_ssbo_intrinsic(ir
);
3945 case ir_intrinsic_memory_barrier
:
3946 case ir_intrinsic_memory_barrier_atomic_counter
:
3947 case ir_intrinsic_memory_barrier_buffer
:
3948 case ir_intrinsic_memory_barrier_image
:
3949 case ir_intrinsic_memory_barrier_shared
:
3950 case ir_intrinsic_group_memory_barrier
:
3951 visit_membar_intrinsic(ir
);
3954 case ir_intrinsic_shared_load
:
3955 case ir_intrinsic_shared_store
:
3956 case ir_intrinsic_shared_atomic_add
:
3957 case ir_intrinsic_shared_atomic_min
:
3958 case ir_intrinsic_shared_atomic_max
:
3959 case ir_intrinsic_shared_atomic_and
:
3960 case ir_intrinsic_shared_atomic_or
:
3961 case ir_intrinsic_shared_atomic_xor
:
3962 case ir_intrinsic_shared_atomic_exchange
:
3963 case ir_intrinsic_shared_atomic_comp_swap
:
3964 visit_shared_intrinsic(ir
);
3967 case ir_intrinsic_image_load
:
3968 case ir_intrinsic_image_store
:
3969 case ir_intrinsic_image_atomic_add
:
3970 case ir_intrinsic_image_atomic_min
:
3971 case ir_intrinsic_image_atomic_max
:
3972 case ir_intrinsic_image_atomic_and
:
3973 case ir_intrinsic_image_atomic_or
:
3974 case ir_intrinsic_image_atomic_xor
:
3975 case ir_intrinsic_image_atomic_exchange
:
3976 case ir_intrinsic_image_atomic_comp_swap
:
3977 case ir_intrinsic_image_size
:
3978 case ir_intrinsic_image_samples
:
3979 visit_image_intrinsic(ir
);
3982 case ir_intrinsic_shader_clock
:
3983 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3986 case ir_intrinsic_vote_all
:
3987 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3989 case ir_intrinsic_vote_any
:
3990 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3992 case ir_intrinsic_vote_eq
:
3993 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3995 case ir_intrinsic_ballot
:
3996 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3998 case ir_intrinsic_read_first_invocation
:
3999 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4001 case ir_intrinsic_read_invocation
:
4002 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4005 case ir_intrinsic_invalid
:
4006 case ir_intrinsic_generic_load
:
4007 case ir_intrinsic_generic_store
:
4008 case ir_intrinsic_generic_atomic_add
:
4009 case ir_intrinsic_generic_atomic_and
:
4010 case ir_intrinsic_generic_atomic_or
:
4011 case ir_intrinsic_generic_atomic_xor
:
4012 case ir_intrinsic_generic_atomic_min
:
4013 case ir_intrinsic_generic_atomic_max
:
4014 case ir_intrinsic_generic_atomic_exchange
:
4015 case ir_intrinsic_generic_atomic_comp_swap
:
4016 case ir_intrinsic_begin_invocation_interlock
:
4017 case ir_intrinsic_end_invocation_interlock
:
4018 unreachable("Invalid intrinsic");
4023 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4024 unsigned *array_elements
,
4026 st_src_reg
*indirect
,
4029 switch (tail
->ir_type
) {
4030 case ir_type_dereference_record
: {
4031 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4032 const glsl_type
*struct_type
= deref_record
->record
->type
;
4033 int field_index
= deref_record
->field_idx
;
4035 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4037 assert(field_index
>= 0);
4038 *location
+= struct_type
->record_location_offset(field_index
);
4042 case ir_type_dereference_array
: {
4043 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4045 void *mem_ctx
= ralloc_parent(deref_arr
);
4046 ir_constant
*array_index
=
4047 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4050 st_src_reg temp_reg
;
4051 st_dst_reg temp_dst
;
4053 temp_reg
= get_temp(glsl_type::uint_type
);
4054 temp_dst
= st_dst_reg(temp_reg
);
4055 temp_dst
.writemask
= 1;
4057 deref_arr
->array_index
->accept(this);
4058 if (*array_elements
!= 1)
4059 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4061 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4063 if (indirect
->file
== PROGRAM_UNDEFINED
)
4064 *indirect
= temp_reg
;
4066 temp_dst
= st_dst_reg(*indirect
);
4067 temp_dst
.writemask
= 1;
4068 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4071 *index
+= array_index
->value
.u
[0] * *array_elements
;
4073 *array_elements
*= deref_arr
->array
->type
->length
;
4075 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4084 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4085 unsigned *array_size
,
4088 st_src_reg
*reladdr
,
4091 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4092 unsigned location
= 0;
4093 ir_variable
*var
= ir
->variable_referenced();
4095 memset(reladdr
, 0, sizeof(*reladdr
));
4096 reladdr
->file
= PROGRAM_UNDEFINED
;
4102 location
= var
->data
.location
;
4103 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4106 * If we end up with no indirect then adjust the base to the index,
4107 * and set the array size to 1.
4109 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4115 assert(location
!= 0xffffffff);
4116 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4117 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4122 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4124 if (offset
.reladdr
|| offset
.reladdr2
||
4125 offset
.has_index2
||
4126 offset
.file
== PROGRAM_UNIFORM
||
4127 offset
.file
== PROGRAM_CONSTANT
||
4128 offset
.file
== PROGRAM_STATE_VAR
) {
4129 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4130 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4131 tmp_dst
.writemask
= WRITEMASK_XY
;
4132 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4140 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4142 ir_variable
*var
= ir
->variable_referenced();
4144 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4145 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4148 /* Convert from bound sampler/image to bindless handle. */
4149 bool is_image
= ir
->type
->is_image();
4150 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4152 unsigned array_size
= 1, base
= 0;
4154 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4156 resource
.index
= index
;
4157 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4158 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4159 *resource
.reladdr
= reladdr
;
4160 emit_arl(ir
, sampler_reladdr
, reladdr
);
4163 this->result
= get_temp(glsl_type::uvec2_type
);
4164 st_dst_reg
dst(this->result
);
4165 dst
.writemask
= WRITEMASK_XY
;
4167 glsl_to_tgsi_instruction
*inst
= emit_asm(
4168 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4170 inst
->tex_target
= ir
->type
->sampler_index();
4171 inst
->resource
= resource
;
4172 inst
->sampler_array_size
= array_size
;
4173 inst
->sampler_base
= base
;
4179 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4181 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4182 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4183 st_src_reg levels_src
, reladdr
;
4184 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4185 glsl_to_tgsi_instruction
*inst
= NULL
;
4186 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4187 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4188 unsigned sampler_array_size
= 1, sampler_base
= 0;
4189 bool is_cube_array
= false, is_cube_shadow
= false;
4190 ir_variable
*var
= ir
->sampler
->variable_referenced();
4193 /* if we are a cube array sampler or a cube shadow */
4194 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4195 is_cube_array
= sampler_type
->sampler_array
;
4196 is_cube_shadow
= sampler_type
->sampler_shadow
;
4199 if (ir
->coordinate
) {
4200 ir
->coordinate
->accept(this);
4202 /* Put our coords in a temp. We'll need to modify them for shadow,
4203 * projection, or LOD, so the only case we'd use it as-is is if
4204 * we're doing plain old texturing. The optimization passes on
4205 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4207 coord
= get_temp(glsl_type::vec4_type
);
4208 coord_dst
= st_dst_reg(coord
);
4209 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4210 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4213 if (ir
->projector
) {
4214 ir
->projector
->accept(this);
4215 projector
= this->result
;
4218 /* Storage for our result. Ideally for an assignment we'd be using
4219 * the actual storage for the result here, instead.
4221 result_src
= get_temp(ir
->type
);
4222 result_dst
= st_dst_reg(result_src
);
4223 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4227 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4229 ir
->offset
->accept(this);
4230 offset
[0] = this->result
;
4234 if (is_cube_array
|| is_cube_shadow
) {
4235 opcode
= TGSI_OPCODE_TXB2
;
4238 opcode
= TGSI_OPCODE_TXB
;
4240 ir
->lod_info
.bias
->accept(this);
4241 lod_info
= this->result
;
4243 ir
->offset
->accept(this);
4244 offset
[0] = this->result
;
4248 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4249 opcode
= TGSI_OPCODE_TEX_LZ
;
4251 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4252 ir
->lod_info
.lod
->accept(this);
4253 lod_info
= this->result
;
4256 ir
->offset
->accept(this);
4257 offset
[0] = this->result
;
4261 opcode
= TGSI_OPCODE_TXD
;
4262 ir
->lod_info
.grad
.dPdx
->accept(this);
4264 ir
->lod_info
.grad
.dPdy
->accept(this);
4267 ir
->offset
->accept(this);
4268 offset
[0] = this->result
;
4272 opcode
= TGSI_OPCODE_TXQ
;
4273 ir
->lod_info
.lod
->accept(this);
4274 lod_info
= this->result
;
4276 case ir_query_levels
:
4277 opcode
= TGSI_OPCODE_TXQ
;
4278 lod_info
= undef_src
;
4279 levels_src
= get_temp(ir
->type
);
4282 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4283 opcode
= TGSI_OPCODE_TXF_LZ
;
4285 opcode
= TGSI_OPCODE_TXF
;
4286 ir
->lod_info
.lod
->accept(this);
4287 lod_info
= this->result
;
4290 ir
->offset
->accept(this);
4291 offset
[0] = this->result
;
4295 opcode
= TGSI_OPCODE_TXF
;
4296 ir
->lod_info
.sample_index
->accept(this);
4297 sample_index
= this->result
;
4300 opcode
= TGSI_OPCODE_TG4
;
4301 ir
->lod_info
.component
->accept(this);
4302 component
= this->result
;
4304 ir
->offset
->accept(this);
4305 if (ir
->offset
->type
->is_array()) {
4306 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4307 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4308 offset
[i
] = this->result
;
4309 offset
[i
].index
+= i
* type_size(elt_type
);
4310 offset
[i
].type
= elt_type
->base_type
;
4311 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4312 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4315 offset
[0] = canonicalize_gather_offset(this->result
);
4320 opcode
= TGSI_OPCODE_LODQ
;
4322 case ir_texture_samples
:
4323 opcode
= TGSI_OPCODE_TXQS
;
4325 case ir_samples_identical
:
4326 unreachable("Unexpected ir_samples_identical opcode");
4329 if (ir
->projector
) {
4330 if (opcode
== TGSI_OPCODE_TEX
) {
4331 /* Slot the projector in as the last component of the coord. */
4332 coord_dst
.writemask
= WRITEMASK_W
;
4333 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4334 coord_dst
.writemask
= WRITEMASK_XYZW
;
4335 opcode
= TGSI_OPCODE_TXP
;
4337 st_src_reg coord_w
= coord
;
4338 coord_w
.swizzle
= SWIZZLE_WWWW
;
4340 /* For the other TEX opcodes there's no projective version
4341 * since the last slot is taken up by LOD info. Do the
4342 * projective divide now.
4344 coord_dst
.writemask
= WRITEMASK_W
;
4345 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4347 /* In the case where we have to project the coordinates "by hand,"
4348 * the shadow comparator value must also be projected.
4350 st_src_reg tmp_src
= coord
;
4351 if (ir
->shadow_comparator
) {
4352 /* Slot the shadow value in as the second to last component of the
4355 ir
->shadow_comparator
->accept(this);
4357 tmp_src
= get_temp(glsl_type::vec4_type
);
4358 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4360 /* Projective division not allowed for array samplers. */
4361 assert(!sampler_type
->sampler_array
);
4363 tmp_dst
.writemask
= WRITEMASK_Z
;
4364 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4366 tmp_dst
.writemask
= WRITEMASK_XY
;
4367 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4370 coord_dst
.writemask
= WRITEMASK_XYZ
;
4371 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4373 coord_dst
.writemask
= WRITEMASK_XYZW
;
4374 coord
.swizzle
= SWIZZLE_XYZW
;
4378 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4379 * shadow comparator was put in the correct place (and projected) by the
4380 * code, above, that handles by-hand projection.
4382 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4383 /* Slot the shadow value in as the second to last component of the
4386 ir
->shadow_comparator
->accept(this);
4388 if (is_cube_array
) {
4389 cube_sc
= get_temp(glsl_type::float_type
);
4390 cube_sc_dst
= st_dst_reg(cube_sc
);
4391 cube_sc_dst
.writemask
= WRITEMASK_X
;
4392 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4393 cube_sc_dst
.writemask
= WRITEMASK_X
;
4396 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4397 sampler_type
->sampler_array
) ||
4398 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4399 coord_dst
.writemask
= WRITEMASK_W
;
4401 coord_dst
.writemask
= WRITEMASK_Z
;
4403 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4404 coord_dst
.writemask
= WRITEMASK_XYZW
;
4408 if (ir
->op
== ir_txf_ms
) {
4409 coord_dst
.writemask
= WRITEMASK_W
;
4410 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4411 coord_dst
.writemask
= WRITEMASK_XYZW
;
4412 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4413 opcode
== TGSI_OPCODE_TXF
) {
4414 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4415 coord_dst
.writemask
= WRITEMASK_W
;
4416 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4417 coord_dst
.writemask
= WRITEMASK_XYZW
;
4420 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4423 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4424 &index
, &reladdr
, !var
->contains_bindless());
4426 sampler
.index
= index
;
4427 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4428 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4429 *sampler
.reladdr
= reladdr
;
4430 emit_arl(ir
, sampler_reladdr
, reladdr
);
4433 st_src_reg bindless
;
4434 if (var
->contains_bindless()) {
4435 ir
->sampler
->accept(this);
4436 bindless
= this->result
;
4439 if (opcode
== TGSI_OPCODE_TXD
)
4440 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4441 else if (opcode
== TGSI_OPCODE_TXQ
) {
4442 if (ir
->op
== ir_query_levels
) {
4443 /* the level is stored in W */
4444 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4445 result_dst
.writemask
= WRITEMASK_X
;
4446 levels_src
.swizzle
= SWIZZLE_WWWW
;
4447 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4449 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4450 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4451 inst
= emit_asm(ir
, opcode
, result_dst
);
4452 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4453 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4454 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4455 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4456 } else if (opcode
== TGSI_OPCODE_TG4
) {
4457 if (is_cube_array
&& ir
->shadow_comparator
) {
4458 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4460 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4463 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4465 if (ir
->shadow_comparator
)
4466 inst
->tex_shadow
= GL_TRUE
;
4468 if (var
->contains_bindless()) {
4469 inst
->resource
= bindless
;
4470 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4471 SWIZZLE_X
, SWIZZLE_Y
);
4473 inst
->resource
= sampler
;
4474 inst
->sampler_array_size
= sampler_array_size
;
4475 inst
->sampler_base
= sampler_base
;
4479 if (!inst
->tex_offsets
)
4480 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4481 MAX_GLSL_TEXTURE_OFFSET
);
4483 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4484 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4485 inst
->tex_offsets
[i
] = offset
[i
];
4486 inst
->tex_offset_num_offset
= i
;
4489 inst
->tex_target
= sampler_type
->sampler_index();
4490 inst
->tex_type
= ir
->type
->base_type
;
4492 this->result
= result_src
;
4496 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4498 assert(!ir
->get_value());
4500 emit_asm(ir
, TGSI_OPCODE_RET
);
4504 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4506 if (ir
->condition
) {
4507 ir
->condition
->accept(this);
4508 st_src_reg condition
= this->result
;
4510 /* Convert the bool condition to a float so we can negate. */
4511 if (native_integers
) {
4512 st_src_reg temp
= get_temp(ir
->condition
->type
);
4513 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4514 condition
, st_src_reg_for_float(1.0));
4518 condition
.negate
= ~condition
.negate
;
4519 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4521 /* unconditional kil */
4522 emit_asm(ir
, TGSI_OPCODE_KILL
);
4527 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4529 enum tgsi_opcode if_opcode
;
4530 glsl_to_tgsi_instruction
*if_inst
;
4532 ir
->condition
->accept(this);
4533 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4535 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4537 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4539 this->instructions
.push_tail(if_inst
);
4541 visit_exec_list(&ir
->then_instructions
, this);
4543 if (!ir
->else_instructions
.is_empty()) {
4544 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4545 visit_exec_list(&ir
->else_instructions
, this);
4548 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4553 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4555 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4557 ir
->stream
->accept(this);
4558 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4562 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4564 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4566 ir
->stream
->accept(this);
4567 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4571 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4573 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4574 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4576 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4579 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4581 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4583 result
.file
= PROGRAM_UNDEFINED
;
4590 num_input_arrays
= 0;
4591 num_output_arrays
= 0;
4593 num_atomic_arrays
= 0;
4595 num_address_regs
= 0;
4598 indirect_addr_consts
= false;
4599 wpos_transform_const
= -1;
4600 native_integers
= false;
4601 mem_ctx
= ralloc_context(NULL
);
4605 shader_program
= NULL
;
4610 use_shared_memory
= false;
4611 has_tex_txf_lz
= false;
4615 static void var_destroy(struct hash_entry
*entry
)
4617 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4622 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4624 _mesa_hash_table_destroy(variables
, var_destroy
);
4626 ralloc_free(mem_ctx
);
4629 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4636 * Count resources used by the given gpu program (number of texture
4640 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4642 v
->samplers_used
= 0;
4644 prog
->info
.textures_used_by_txf
= 0;
4646 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4647 if (inst
->info
->is_tex
) {
4648 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4649 unsigned idx
= inst
->sampler_base
+ i
;
4650 v
->samplers_used
|= 1u << idx
;
4652 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4653 v
->sampler_types
[idx
] = inst
->tex_type
;
4654 v
->sampler_targets
[idx
] =
4655 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4657 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4658 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4663 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4664 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4666 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4667 is_resource_instruction(inst
->op
) ||
4668 inst
->op
== TGSI_OPCODE_STORE
)) {
4669 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4670 v
->use_shared_memory
= true;
4671 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4672 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4673 unsigned idx
= inst
->sampler_base
+ i
;
4674 v
->images_used
|= 1 << idx
;
4675 v
->image_targets
[idx
] =
4676 st_translate_texture_target(inst
->tex_target
, false);
4677 v
->image_formats
[idx
] = inst
->image_format
;
4682 prog
->SamplersUsed
= v
->samplers_used
;
4684 if (v
->shader_program
!= NULL
)
4685 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4689 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4690 * are read from the given src in this instruction
4693 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4695 int read_mask
= 0, comp
;
4697 /* Now, given the src swizzle and the written channels, find which
4698 * components are actually read
4700 for (comp
= 0; comp
< 4; ++comp
) {
4701 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4703 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4704 read_mask
|= 1 << coord
;
4711 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4712 * instruction is the first instruction to write to register T0. There are
4713 * several lowering passes done in GLSL IR (e.g. branches and
4714 * relative addressing) that create a large number of conditional assignments
4715 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4717 * Here is why this conversion is safe:
4718 * CMP T0, T1 T2 T0 can be expanded to:
4724 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4725 * as the original program. If (T1 < 0.0) evaluates to false, executing
4726 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4727 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4728 * because any instruction that was going to read from T0 after this was going
4729 * to read a garbage value anyway.
4732 glsl_to_tgsi_visitor::simplify_cmp(void)
4734 int tempWritesSize
= 0;
4735 unsigned *tempWrites
= NULL
;
4736 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4738 memset(outputWrites
, 0, sizeof(outputWrites
));
4740 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4741 unsigned prevWriteMask
= 0;
4743 /* Give up if we encounter relative addressing or flow control. */
4744 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4745 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4746 inst
->info
->is_branch
||
4747 inst
->op
== TGSI_OPCODE_CONT
||
4748 inst
->op
== TGSI_OPCODE_END
||
4749 inst
->op
== TGSI_OPCODE_RET
) {
4753 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4754 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4755 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4756 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4757 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4758 if (inst
->dst
[0].index
>= tempWritesSize
) {
4759 const int inc
= 4096;
4761 tempWrites
= (unsigned*)
4763 (tempWritesSize
+ inc
) * sizeof(unsigned));
4767 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4768 tempWritesSize
+= inc
;
4771 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4772 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4776 /* For a CMP to be considered a conditional write, the destination
4777 * register and source register two must be the same. */
4778 if (inst
->op
== TGSI_OPCODE_CMP
4779 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4780 && inst
->src
[2].file
== inst
->dst
[0].file
4781 && inst
->src
[2].index
== inst
->dst
[0].index
4782 && inst
->dst
[0].writemask
==
4783 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4785 inst
->op
= TGSI_OPCODE_MOV
;
4786 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4787 inst
->src
[0] = inst
->src
[1];
4795 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4797 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4798 int old_idx
= src
->index
;
4799 if (renames
[old_idx
].valid
)
4800 src
->index
= renames
[old_idx
].new_reg
;
4804 /* Replaces all references to a temporary register index with another index. */
4806 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4808 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4810 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4811 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4812 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4813 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4816 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4817 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4818 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4819 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4822 rename_temp_handle_src(renames
, &inst
->resource
);
4823 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4824 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4826 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4827 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4828 int old_idx
= inst
->dst
[j
].index
;
4829 if (renames
[old_idx
].valid
)
4830 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4832 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4833 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4839 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4841 int depth
= 0; /* loop depth */
4842 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4845 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4846 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4847 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4848 if (first_writes
[inst
->dst
[j
].index
] == -1)
4849 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4853 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4856 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4866 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4868 int depth
= 0; /* loop depth */
4869 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4872 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4873 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4874 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4875 if (first_reads
[inst
->src
[j
].index
] == -1)
4876 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4879 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4880 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4881 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4882 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4885 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4888 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4898 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4900 int depth
= 0; /* loop depth */
4901 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4904 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4905 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4906 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4907 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4909 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4910 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4911 if (first_writes
[inst
->dst
[j
].index
] == -1)
4912 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4913 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4916 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4917 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4918 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4920 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4923 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4926 for (k
= 0; k
< this->next_temp
; k
++) {
4927 if (last_reads
[k
] == -2) {
4939 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4941 int depth
= 0; /* loop depth */
4945 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4946 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4947 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4948 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4951 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4953 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4955 for (k
= 0; k
< this->next_temp
; k
++) {
4956 if (last_writes
[k
] == -2) {
4967 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4968 * channels for copy propagation and updates following instructions to
4969 * use the original versions.
4971 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4972 * will occur. As an example, a TXP production before this pass:
4974 * 0: MOV TEMP[1], INPUT[4].xyyy;
4975 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4976 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4980 * 0: MOV TEMP[1], INPUT[4].xyyy;
4981 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4982 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4984 * which allows for dead code elimination on TEMP[1]'s writes.
4987 glsl_to_tgsi_visitor::copy_propagate(void)
4989 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4990 glsl_to_tgsi_instruction
*,
4991 this->next_temp
* 4);
4992 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4995 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4996 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4997 || inst
->dst
[0].index
< this->next_temp
);
4999 /* First, do any copy propagation possible into the src regs. */
5000 for (int r
= 0; r
< 3; r
++) {
5001 glsl_to_tgsi_instruction
*first
= NULL
;
5003 int acp_base
= inst
->src
[r
].index
* 4;
5005 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5006 inst
->src
[r
].reladdr
||
5007 inst
->src
[r
].reladdr2
)
5010 /* See if we can find entries in the ACP consisting of MOVs
5011 * from the same src register for all the swizzled channels
5012 * of this src register reference.
5014 for (int i
= 0; i
< 4; i
++) {
5015 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5016 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5023 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5028 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5029 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5030 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5031 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5039 /* We've now validated that we can copy-propagate to
5040 * replace this src register reference. Do it.
5042 inst
->src
[r
].file
= first
->src
[0].file
;
5043 inst
->src
[r
].index
= first
->src
[0].index
;
5044 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5045 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5046 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5047 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5050 for (int i
= 0; i
< 4; i
++) {
5051 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5052 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5053 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5055 inst
->src
[r
].swizzle
= swizzle
;
5060 case TGSI_OPCODE_BGNLOOP
:
5061 case TGSI_OPCODE_ENDLOOP
:
5062 /* End of a basic block, clear the ACP entirely. */
5063 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5066 case TGSI_OPCODE_IF
:
5067 case TGSI_OPCODE_UIF
:
5071 case TGSI_OPCODE_ENDIF
:
5072 case TGSI_OPCODE_ELSE
:
5073 /* Clear all channels written inside the block from the ACP, but
5074 * leaving those that were not touched.
5076 for (int r
= 0; r
< this->next_temp
; r
++) {
5077 for (int c
= 0; c
< 4; c
++) {
5078 if (!acp
[4 * r
+ c
])
5081 if (acp_level
[4 * r
+ c
] >= level
)
5082 acp
[4 * r
+ c
] = NULL
;
5085 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5090 /* Continuing the block, clear any written channels from
5093 for (int d
= 0; d
< 2; d
++) {
5094 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5095 /* Any temporary might be written, so no copy propagation
5096 * across this instruction.
5098 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5099 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5100 inst
->dst
[d
].reladdr
) {
5101 /* Any output might be written, so no copy propagation
5102 * from outputs across this instruction.
5104 for (int r
= 0; r
< this->next_temp
; r
++) {
5105 for (int c
= 0; c
< 4; c
++) {
5106 if (!acp
[4 * r
+ c
])
5109 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5110 acp
[4 * r
+ c
] = NULL
;
5113 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5114 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5115 /* Clear where it's used as dst. */
5116 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5117 for (int c
= 0; c
< 4; c
++) {
5118 if (inst
->dst
[d
].writemask
& (1 << c
))
5119 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5123 /* Clear where it's used as src. */
5124 for (int r
= 0; r
< this->next_temp
; r
++) {
5125 for (int c
= 0; c
< 4; c
++) {
5126 if (!acp
[4 * r
+ c
])
5129 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5131 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5132 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5133 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5134 acp
[4 * r
+ c
] = NULL
;
5143 /* If this is a copy, add it to the ACP. */
5144 if (inst
->op
== TGSI_OPCODE_MOV
&&
5145 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5146 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5147 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5148 !inst
->dst
[0].reladdr
&&
5149 !inst
->dst
[0].reladdr2
&&
5151 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5152 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5153 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5154 !inst
->src
[0].reladdr
&&
5155 !inst
->src
[0].reladdr2
&&
5156 !inst
->src
[0].negate
&&
5157 !inst
->src
[0].abs
) {
5158 for (int i
= 0; i
< 4; i
++) {
5159 if (inst
->dst
[0].writemask
& (1 << i
)) {
5160 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5161 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5167 ralloc_free(acp_level
);
5172 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5174 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5175 /* Clear where it's used as src. */
5176 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5177 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5182 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5185 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5186 * will occur. As an example, a TXP production after copy propagation but
5189 * 0: MOV TEMP[1], INPUT[4].xyyy;
5190 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5191 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5193 * and after this pass:
5195 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5198 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5200 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5201 glsl_to_tgsi_instruction
*,
5202 this->next_temp
* 4);
5203 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5207 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5208 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5209 || inst
->dst
[0].index
< this->next_temp
);
5212 case TGSI_OPCODE_BGNLOOP
:
5213 case TGSI_OPCODE_ENDLOOP
:
5214 case TGSI_OPCODE_CONT
:
5215 case TGSI_OPCODE_BRK
:
5216 /* End of a basic block, clear the write array entirely.
5218 * This keeps us from killing dead code when the writes are
5219 * on either side of a loop, even when the register isn't touched
5220 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5221 * dead code of this type, so it shouldn't make a difference as long as
5222 * the dead code elimination pass in the GLSL compiler does its job.
5224 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5227 case TGSI_OPCODE_ENDIF
:
5228 case TGSI_OPCODE_ELSE
:
5229 /* Promote the recorded level of all channels written inside the
5230 * preceding if or else block to the level above the if/else block.
5232 for (int r
= 0; r
< this->next_temp
; r
++) {
5233 for (int c
= 0; c
< 4; c
++) {
5234 if (!writes
[4 * r
+ c
])
5237 if (write_level
[4 * r
+ c
] == level
)
5238 write_level
[4 * r
+ c
] = level
-1;
5241 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5245 case TGSI_OPCODE_IF
:
5246 case TGSI_OPCODE_UIF
:
5248 /* fallthrough to default case to mark the condition as read */
5250 /* Continuing the block, clear any channels from the write array that
5251 * are read by this instruction.
5253 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5254 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5255 /* Any temporary might be read, so no dead code elimination
5256 * across this instruction.
5258 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5259 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5260 /* Clear where it's used as src. */
5261 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5262 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5263 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5264 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5266 for (int c
= 0; c
< 4; c
++) {
5267 if (src_chans
& (1 << c
))
5268 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5271 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5272 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5274 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5275 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5276 /* Any temporary might be read, so no dead code elimination
5277 * across this instruction.
5279 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5280 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5281 /* Clear where it's used as src. */
5282 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5283 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5284 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5285 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5287 for (int c
= 0; c
< 4; c
++) {
5288 if (src_chans
& (1 << c
))
5289 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5292 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5293 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5296 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5299 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5300 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5301 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5302 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5304 for (int c
= 0; c
< 4; c
++) {
5305 if (src_chans
& (1 << c
))
5306 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5309 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5310 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5312 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5313 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5314 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5319 /* If this instruction writes to a temporary, add it to the write array.
5320 * If there is already an instruction in the write array for one or more
5321 * of the channels, flag that channel write as dead.
5323 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5324 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5325 !inst
->dst
[i
].reladdr
) {
5326 for (int c
= 0; c
< 4; c
++) {
5327 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5328 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5329 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5332 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5334 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5335 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5342 /* Anything still in the write array at this point is dead code. */
5343 for (int r
= 0; r
< this->next_temp
; r
++) {
5344 for (int c
= 0; c
< 4; c
++) {
5345 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5347 inst
->dead_mask
|= (1 << c
);
5351 /* Now actually remove the instructions that are completely dead and update
5352 * the writemask of other instructions with dead channels.
5354 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5355 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5357 /* No amount of dead masks should remove memory stores */
5358 if (inst
->info
->is_store
)
5361 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5366 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5367 if (inst
->dead_mask
== WRITEMASK_XY
||
5368 inst
->dead_mask
== WRITEMASK_ZW
)
5369 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5371 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5375 ralloc_free(write_level
);
5376 ralloc_free(writes
);
5381 /* merge DFRACEXP instructions into one. */
5383 glsl_to_tgsi_visitor::merge_two_dsts(void)
5385 /* We never delete inst, but we may delete its successor. */
5386 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5387 glsl_to_tgsi_instruction
*inst2
;
5390 if (num_inst_dst_regs(inst
) != 2)
5393 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5394 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5397 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5398 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5400 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5405 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5406 while (!inst2
->is_tail_sentinel()) {
5407 if (inst
->op
== inst2
->op
&&
5408 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5409 inst
->src
[0].file
== inst2
->src
[0].file
&&
5410 inst
->src
[0].index
== inst2
->src
[0].index
&&
5411 inst
->src
[0].type
== inst2
->src
[0].type
&&
5412 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5414 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5417 if (inst2
->is_tail_sentinel()) {
5418 /* Undefined destinations are not allowed, substitute with an unused
5419 * temporary register.
5421 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5422 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5423 inst
->dst
[defined
^ 1].writemask
= 0;
5427 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5433 /* Merges temporary registers together where possible to reduce the number of
5434 * registers needed to run a program.
5436 * Produces optimal code only after copy propagation and dead code elimination
5439 glsl_to_tgsi_visitor::merge_registers(void)
5441 struct lifetime
*lifetimes
=
5442 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5444 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5445 this->next_temp
, lifetimes
)) {
5446 struct rename_reg_pair
*renames
=
5447 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5448 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5449 rename_temp_registers(renames
);
5450 ralloc_free(renames
);
5453 ralloc_free(lifetimes
);
5456 /* Reassign indices to temporary registers by reusing unused indices created
5457 * by optimization passes. */
5459 glsl_to_tgsi_visitor::renumber_registers(void)
5463 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5464 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5466 for (i
= 0; i
< this->next_temp
; i
++) {
5467 first_writes
[i
] = -1;
5469 get_first_temp_write(first_writes
);
5471 for (i
= 0; i
< this->next_temp
; i
++) {
5472 if (first_writes
[i
] < 0) continue;
5473 if (i
!= new_index
) {
5474 renames
[i
].new_reg
= new_index
;
5475 renames
[i
].valid
= true;
5480 rename_temp_registers(renames
);
5481 this->next_temp
= new_index
;
5482 ralloc_free(renames
);
5483 ralloc_free(first_writes
);
5486 /* ------------------------- TGSI conversion stuff -------------------------- */
5489 * Intermediate state used during shader translation.
5491 struct st_translate
{
5492 struct ureg_program
*ureg
;
5494 unsigned temps_size
;
5495 struct ureg_dst
*temps
;
5497 struct ureg_dst
*arrays
;
5498 unsigned num_temp_arrays
;
5499 struct ureg_src
*constants
;
5501 struct ureg_src
*immediates
;
5503 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5504 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5505 struct ureg_dst address
[3];
5506 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5507 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5508 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5509 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5510 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5511 struct ureg_src shared_memory
;
5512 unsigned *array_sizes
;
5513 struct inout_decl
*input_decls
;
5514 unsigned num_input_decls
;
5515 struct inout_decl
*output_decls
;
5516 unsigned num_output_decls
;
5518 const ubyte
*inputMapping
;
5519 const ubyte
*outputMapping
;
5521 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5525 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5527 _mesa_sysval_to_semantic(unsigned sysval
)
5531 case SYSTEM_VALUE_VERTEX_ID
:
5532 return TGSI_SEMANTIC_VERTEXID
;
5533 case SYSTEM_VALUE_INSTANCE_ID
:
5534 return TGSI_SEMANTIC_INSTANCEID
;
5535 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5536 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5537 case SYSTEM_VALUE_BASE_VERTEX
:
5538 return TGSI_SEMANTIC_BASEVERTEX
;
5539 case SYSTEM_VALUE_BASE_INSTANCE
:
5540 return TGSI_SEMANTIC_BASEINSTANCE
;
5541 case SYSTEM_VALUE_DRAW_ID
:
5542 return TGSI_SEMANTIC_DRAWID
;
5544 /* Geometry shader */
5545 case SYSTEM_VALUE_INVOCATION_ID
:
5546 return TGSI_SEMANTIC_INVOCATIONID
;
5548 /* Fragment shader */
5549 case SYSTEM_VALUE_FRAG_COORD
:
5550 return TGSI_SEMANTIC_POSITION
;
5551 case SYSTEM_VALUE_FRONT_FACE
:
5552 return TGSI_SEMANTIC_FACE
;
5553 case SYSTEM_VALUE_SAMPLE_ID
:
5554 return TGSI_SEMANTIC_SAMPLEID
;
5555 case SYSTEM_VALUE_SAMPLE_POS
:
5556 return TGSI_SEMANTIC_SAMPLEPOS
;
5557 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5558 return TGSI_SEMANTIC_SAMPLEMASK
;
5559 case SYSTEM_VALUE_HELPER_INVOCATION
:
5560 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5562 /* Tessellation shader */
5563 case SYSTEM_VALUE_TESS_COORD
:
5564 return TGSI_SEMANTIC_TESSCOORD
;
5565 case SYSTEM_VALUE_VERTICES_IN
:
5566 return TGSI_SEMANTIC_VERTICESIN
;
5567 case SYSTEM_VALUE_PRIMITIVE_ID
:
5568 return TGSI_SEMANTIC_PRIMID
;
5569 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5570 return TGSI_SEMANTIC_TESSOUTER
;
5571 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5572 return TGSI_SEMANTIC_TESSINNER
;
5574 /* Compute shader */
5575 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5576 return TGSI_SEMANTIC_THREAD_ID
;
5577 case SYSTEM_VALUE_WORK_GROUP_ID
:
5578 return TGSI_SEMANTIC_BLOCK_ID
;
5579 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5580 return TGSI_SEMANTIC_GRID_SIZE
;
5581 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5582 return TGSI_SEMANTIC_BLOCK_SIZE
;
5584 /* ARB_shader_ballot */
5585 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5586 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5587 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5588 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5589 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5590 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5591 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5592 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5593 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5594 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5595 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5596 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5597 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5598 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5601 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5602 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5603 case SYSTEM_VALUE_VERTEX_CNT
:
5605 assert(!"Unexpected SYSTEM_VALUE_ enum");
5606 return TGSI_SEMANTIC_COUNT
;
5611 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5613 static struct ureg_src
5614 emit_immediate(struct st_translate
*t
,
5615 gl_constant_value values
[4],
5616 GLenum type
, int size
)
5618 struct ureg_program
*ureg
= t
->ureg
;
5622 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5624 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5626 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5627 case GL_UNSIGNED_INT64_ARB
:
5628 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5630 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5631 case GL_UNSIGNED_INT
:
5633 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5635 assert(!"should not get here - type must be float, int, uint, or bool");
5636 return ureg_src_undef();
5641 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5643 static struct ureg_dst
5644 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5650 case PROGRAM_UNDEFINED
:
5651 return ureg_dst_undef();
5653 case PROGRAM_TEMPORARY
:
5654 /* Allocate space for temporaries on demand. */
5655 if (index
>= t
->temps_size
) {
5656 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5658 t
->temps
= (struct ureg_dst
*)
5660 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5662 return ureg_dst_undef();
5664 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5665 t
->temps_size
+= inc
;
5668 if (ureg_dst_is_undef(t
->temps
[index
]))
5669 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5671 return t
->temps
[index
];
5674 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5675 array
= array_id
- 1;
5677 if (ureg_dst_is_undef(t
->arrays
[array
]))
5678 t
->arrays
[array
] = ureg_DECL_array_temporary(
5679 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5681 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5683 case PROGRAM_OUTPUT
:
5685 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5686 assert(index
< 2 * FRAG_RESULT_MAX
);
5687 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5688 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5689 assert(index
< VARYING_SLOT_TESS_MAX
);
5691 assert(index
< VARYING_SLOT_MAX
);
5693 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5694 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5695 return t
->outputs
[t
->outputMapping
[index
]];
5698 struct inout_decl
*decl
=
5699 find_inout_array(t
->output_decls
,
5700 t
->num_output_decls
, array_id
);
5701 unsigned mesa_index
= decl
->mesa_index
;
5702 int slot
= t
->outputMapping
[mesa_index
];
5704 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5706 struct ureg_dst dst
= t
->outputs
[slot
];
5707 dst
.ArrayID
= array_id
;
5708 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5711 case PROGRAM_ADDRESS
:
5712 return t
->address
[index
];
5715 assert(!"unknown dst register file");
5716 return ureg_dst_undef();
5720 static struct ureg_src
5721 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5723 static struct ureg_src
5724 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5725 unsigned addr_index
)
5727 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5728 return ureg_src(t
->address
[addr_index
]);
5730 return translate_src(t
, reladdr
);
5734 * Create a TGSI ureg_dst register from an st_dst_reg.
5736 static struct ureg_dst
5737 translate_dst(struct st_translate
*t
,
5738 const st_dst_reg
*dst_reg
,
5741 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5744 if (dst
.File
== TGSI_FILE_NULL
)
5747 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5750 dst
= ureg_saturate(dst
);
5752 if (dst_reg
->reladdr
!= NULL
) {
5753 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5754 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5757 if (dst_reg
->has_index2
) {
5758 if (dst_reg
->reladdr2
)
5759 dst
= ureg_dst_dimension_indirect(dst
,
5760 translate_addr(t
, dst_reg
->reladdr2
, 1),
5763 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5770 * Create a TGSI ureg_src register from an st_src_reg.
5772 static struct ureg_src
5773 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5775 struct ureg_src src
;
5776 int index
= src_reg
->index
;
5777 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5779 switch (src_reg
->file
) {
5780 case PROGRAM_UNDEFINED
:
5781 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5784 case PROGRAM_TEMPORARY
:
5786 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
5787 src_reg
->array_id
));
5790 case PROGRAM_OUTPUT
: {
5791 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
5793 assert(dst
.WriteMask
!= 0);
5794 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5795 src
= ureg_swizzle(ureg_src(dst
),
5799 MIN2(shift
+ 3, 3));
5803 case PROGRAM_UNIFORM
:
5804 assert(src_reg
->index
>= 0);
5805 src
= src_reg
->index
< t
->num_constants
?
5806 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5808 case PROGRAM_STATE_VAR
:
5809 case PROGRAM_CONSTANT
: /* ie, immediate */
5810 if (src_reg
->has_index2
)
5811 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5813 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5814 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5817 case PROGRAM_IMMEDIATE
:
5818 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5819 src
= t
->immediates
[src_reg
->index
];
5823 /* GLSL inputs are 64-bit containers, so we have to
5824 * map back to the original index and add the offset after
5826 index
-= double_reg2
;
5827 if (!src_reg
->array_id
) {
5828 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5829 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5830 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5833 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
5836 unsigned mesa_index
= decl
->mesa_index
;
5837 int slot
= t
->inputMapping
[mesa_index
];
5839 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5841 src
= t
->inputs
[slot
];
5842 src
.ArrayID
= src_reg
->array_id
;
5843 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5847 case PROGRAM_ADDRESS
:
5848 src
= ureg_src(t
->address
[src_reg
->index
]);
5851 case PROGRAM_SYSTEM_VALUE
:
5852 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5853 src
= t
->systemValues
[src_reg
->index
];
5856 case PROGRAM_HW_ATOMIC
:
5857 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
5862 assert(!"unknown src register file");
5863 return ureg_src_undef();
5866 if (src_reg
->has_index2
) {
5867 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5868 * and UBO constant buffers (buffer, position).
5870 if (src_reg
->reladdr2
)
5871 src
= ureg_src_dimension_indirect(src
,
5872 translate_addr(t
, src_reg
->reladdr2
, 1),
5875 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5878 src
= ureg_swizzle(src
,
5879 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5880 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5881 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5882 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5885 src
= ureg_abs(src
);
5887 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5888 src
= ureg_negate(src
);
5890 if (src_reg
->reladdr
!= NULL
) {
5891 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5892 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5898 static struct tgsi_texture_offset
5899 translate_tex_offset(struct st_translate
*t
,
5900 const st_src_reg
*in_offset
)
5902 struct tgsi_texture_offset offset
;
5903 struct ureg_src src
= translate_src(t
, in_offset
);
5905 offset
.File
= src
.File
;
5906 offset
.Index
= src
.Index
;
5907 offset
.SwizzleX
= src
.SwizzleX
;
5908 offset
.SwizzleY
= src
.SwizzleY
;
5909 offset
.SwizzleZ
= src
.SwizzleZ
;
5912 assert(!src
.Indirect
);
5913 assert(!src
.DimIndirect
);
5914 assert(!src
.Dimension
);
5915 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5916 assert(!src
.Negate
);
5922 compile_tgsi_instruction(struct st_translate
*t
,
5923 const glsl_to_tgsi_instruction
*inst
)
5925 struct ureg_program
*ureg
= t
->ureg
;
5927 struct ureg_dst dst
[2];
5928 struct ureg_src src
[4];
5929 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5933 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
5935 num_dst
= num_inst_dst_regs(inst
);
5936 num_src
= num_inst_src_regs(inst
);
5938 for (i
= 0; i
< num_dst
; i
++)
5939 dst
[i
] = translate_dst(t
,
5943 for (i
= 0; i
< num_src
; i
++)
5944 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5947 case TGSI_OPCODE_BGNLOOP
:
5948 case TGSI_OPCODE_ELSE
:
5949 case TGSI_OPCODE_ENDLOOP
:
5950 case TGSI_OPCODE_IF
:
5951 case TGSI_OPCODE_UIF
:
5952 assert(num_dst
== 0);
5953 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5956 case TGSI_OPCODE_TEX
:
5957 case TGSI_OPCODE_TEX_LZ
:
5958 case TGSI_OPCODE_TXB
:
5959 case TGSI_OPCODE_TXD
:
5960 case TGSI_OPCODE_TXL
:
5961 case TGSI_OPCODE_TXP
:
5962 case TGSI_OPCODE_TXQ
:
5963 case TGSI_OPCODE_TXQS
:
5964 case TGSI_OPCODE_TXF
:
5965 case TGSI_OPCODE_TXF_LZ
:
5966 case TGSI_OPCODE_TEX2
:
5967 case TGSI_OPCODE_TXB2
:
5968 case TGSI_OPCODE_TXL2
:
5969 case TGSI_OPCODE_TG4
:
5970 case TGSI_OPCODE_LODQ
:
5971 case TGSI_OPCODE_SAMP2HND
:
5972 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5973 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5975 /* Bindless samplers. */
5976 src
[num_src
] = translate_src(t
, &inst
->resource
);
5978 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5979 if (inst
->resource
.reladdr
)
5981 ureg_src_indirect(src
[num_src
],
5982 translate_addr(t
, inst
->resource
.reladdr
, 2));
5984 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5985 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5987 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5993 st_translate_texture_type(inst
->tex_type
),
5994 texoffsets
, inst
->tex_offset_num_offset
,
5998 case TGSI_OPCODE_RESQ
:
5999 case TGSI_OPCODE_LOAD
:
6000 case TGSI_OPCODE_ATOMUADD
:
6001 case TGSI_OPCODE_ATOMXCHG
:
6002 case TGSI_OPCODE_ATOMCAS
:
6003 case TGSI_OPCODE_ATOMAND
:
6004 case TGSI_OPCODE_ATOMOR
:
6005 case TGSI_OPCODE_ATOMXOR
:
6006 case TGSI_OPCODE_ATOMUMIN
:
6007 case TGSI_OPCODE_ATOMUMAX
:
6008 case TGSI_OPCODE_ATOMIMIN
:
6009 case TGSI_OPCODE_ATOMIMAX
:
6010 case TGSI_OPCODE_IMG2HND
:
6011 for (i
= num_src
- 1; i
>= 0; i
--)
6012 src
[i
+ 1] = src
[i
];
6014 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6015 src
[0] = t
->shared_memory
;
6016 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6017 src
[0] = t
->buffers
[inst
->resource
.index
];
6018 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6019 src
[0] = translate_src(t
, &inst
->resource
);
6020 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6021 assert(inst
->resource
.has_index2
);
6022 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6024 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6025 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6026 src
[0] = t
->images
[inst
->resource
.index
];
6028 /* Bindless images. */
6029 src
[0] = translate_src(t
, &inst
->resource
);
6031 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6033 if (inst
->resource
.reladdr
)
6034 src
[0] = ureg_src_indirect(src
[0],
6035 translate_addr(t
, inst
->resource
.reladdr
, 2));
6036 assert(src
[0].File
!= TGSI_FILE_NULL
);
6037 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6038 inst
->buffer_access
,
6039 tex_target
, inst
->image_format
);
6042 case TGSI_OPCODE_STORE
:
6043 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6044 dst
[0] = ureg_dst(t
->shared_memory
);
6045 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6046 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6048 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6049 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6051 /* Bindless images. */
6052 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6054 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6056 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6057 if (inst
->resource
.reladdr
)
6058 dst
[0] = ureg_dst_indirect(dst
[0],
6059 translate_addr(t
, inst
->resource
.reladdr
, 2));
6060 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6061 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6062 inst
->buffer_access
,
6063 tex_target
, inst
->image_format
);
6070 src
, num_src
, inst
->precise
);
6076 * Emit the TGSI instructions for inverting and adjusting WPOS.
6077 * This code is unavoidable because it also depends on whether
6078 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6081 emit_wpos_adjustment(struct gl_context
*ctx
,
6082 struct st_translate
*t
,
6083 int wpos_transform_const
,
6085 GLfloat adjX
, GLfloat adjY
[2])
6087 struct ureg_program
*ureg
= t
->ureg
;
6089 assert(wpos_transform_const
>= 0);
6091 /* Fragment program uses fragment position input.
6092 * Need to replace instances of INPUT[WPOS] with temp T
6093 * where T = INPUT[WPOS] is inverted by Y.
6095 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6096 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6097 struct ureg_src
*wpos
=
6098 ctx
->Const
.GLSLFragCoordIsSysVal
?
6099 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6100 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6101 struct ureg_src wpos_input
= *wpos
;
6103 /* First, apply the coordinate shift: */
6104 if (adjX
|| adjY
[0] || adjY
[1]) {
6105 if (adjY
[0] != adjY
[1]) {
6106 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6107 * depending on whether inversion is actually going to be applied
6108 * or not, which is determined by testing against the inversion
6109 * state variable used below, which will be either +1 or -1.
6111 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6113 ureg_CMP(ureg
, adj_temp
,
6114 ureg_scalar(wpostrans
, invert
? 2 : 0),
6115 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6116 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6117 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6119 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6120 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6122 wpos_input
= ureg_src(wpos_temp
);
6124 /* MOV wpos_temp, input[wpos]
6126 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6129 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6130 * inversion/identity, or the other way around if we're drawing to an FBO.
6133 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6136 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6138 ureg_scalar(wpostrans
, 0),
6139 ureg_scalar(wpostrans
, 1));
6141 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6144 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6146 ureg_scalar(wpostrans
, 2),
6147 ureg_scalar(wpostrans
, 3));
6150 /* Use wpos_temp as position input from here on:
6152 *wpos
= ureg_src(wpos_temp
);
6157 * Emit fragment position/ooordinate code.
6160 emit_wpos(struct st_context
*st
,
6161 struct st_translate
*t
,
6162 const struct gl_program
*program
,
6163 struct ureg_program
*ureg
,
6164 int wpos_transform_const
)
6166 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6167 GLfloat adjX
= 0.0f
;
6168 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6169 boolean invert
= FALSE
;
6171 /* Query the pixel center conventions supported by the pipe driver and set
6172 * adjX, adjY to help out if it cannot handle the requested one internally.
6174 * The bias of the y-coordinate depends on whether y-inversion takes place
6175 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6176 * drawing to an FBO (causes additional inversion), and whether the pipe
6177 * driver origin and the requested origin differ (the latter condition is
6178 * stored in the 'invert' variable).
6180 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6182 * center shift only:
6187 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6188 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6189 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6190 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6192 * inversion and center shift:
6193 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6194 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6195 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6196 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6198 if (program
->OriginUpperLeft
) {
6199 /* Fragment shader wants origin in upper-left */
6200 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6201 /* the driver supports upper-left origin */
6203 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6204 /* the driver supports lower-left origin, need to invert Y */
6205 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6206 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6213 /* Fragment shader wants origin in lower-left */
6214 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6215 /* the driver supports lower-left origin */
6216 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6217 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6218 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6219 /* the driver supports upper-left origin, need to invert Y */
6225 if (program
->PixelCenterInteger
) {
6226 /* Fragment shader wants pixel center integer */
6227 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6228 /* the driver supports pixel center integer */
6230 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6231 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6233 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6234 /* the driver supports pixel center half integer, need to bias X,Y */
6243 /* Fragment shader wants pixel center half integer */
6244 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6245 /* the driver supports pixel center half integer */
6247 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6248 /* the driver supports pixel center integer, need to bias X,Y */
6249 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6250 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6251 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6257 /* we invert after adjustment so that we avoid the MOV to temporary,
6258 * and reuse the adjustment ADD instead */
6259 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6263 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6264 * TGSI uses +1 for front, -1 for back.
6265 * This function converts the TGSI value to the GL value. Simply clamping/
6266 * saturating the value to [0,1] does the job.
6269 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6271 struct ureg_program
*ureg
= t
->ureg
;
6272 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6273 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6275 if (ctx
->Const
.NativeIntegers
) {
6276 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6279 /* MOV_SAT face_temp, input[face] */
6280 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6283 /* Use face_temp as face input from here on: */
6284 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6288 emit_compute_block_size(const struct gl_program
*prog
,
6289 struct ureg_program
*ureg
) {
6290 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6291 prog
->info
.cs
.local_size
[0]);
6292 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6293 prog
->info
.cs
.local_size
[1]);
6294 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6295 prog
->info
.cs
.local_size
[2]);
6298 struct sort_inout_decls
{
6299 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6300 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6303 const ubyte
*mapping
;
6306 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6308 * This is for the benefit of older drivers which are broken when the
6309 * declarations aren't sorted in this way.
6312 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6314 const ubyte mapping
[])
6316 sort_inout_decls sorter
;
6317 sorter
.mapping
= mapping
;
6318 std::sort(decls
, decls
+ count
, sorter
);
6321 static enum tgsi_interpolate_mode
6322 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6324 switch (glsl_qual
) {
6325 case INTERP_MODE_NONE
:
6326 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6327 return TGSI_INTERPOLATE_COLOR
;
6328 return TGSI_INTERPOLATE_PERSPECTIVE
;
6329 case INTERP_MODE_SMOOTH
:
6330 return TGSI_INTERPOLATE_PERSPECTIVE
;
6331 case INTERP_MODE_FLAT
:
6332 return TGSI_INTERPOLATE_CONSTANT
;
6333 case INTERP_MODE_NOPERSPECTIVE
:
6334 return TGSI_INTERPOLATE_LINEAR
;
6336 assert(0 && "unexpected interp mode in st_translate_interp()");
6337 return TGSI_INTERPOLATE_PERSPECTIVE
;
6342 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6343 * \param program the program to translate
6344 * \param numInputs number of input registers used
6345 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6347 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6348 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6350 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6351 * \param numOutputs number of output registers used
6352 * \param outputMapping maps Mesa fragment program outputs to TGSI
6354 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6355 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6358 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6360 extern "C" enum pipe_error
6361 st_translate_program(
6362 struct gl_context
*ctx
,
6363 enum pipe_shader_type procType
,
6364 struct ureg_program
*ureg
,
6365 glsl_to_tgsi_visitor
*program
,
6366 const struct gl_program
*proginfo
,
6368 const ubyte inputMapping
[],
6369 const ubyte inputSlotToAttr
[],
6370 const ubyte inputSemanticName
[],
6371 const ubyte inputSemanticIndex
[],
6372 const ubyte interpMode
[],
6374 const ubyte outputMapping
[],
6375 const ubyte outputSemanticName
[],
6376 const ubyte outputSemanticIndex
[])
6378 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6379 struct st_translate
*t
;
6381 struct gl_program_constants
*frag_const
=
6382 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6383 enum pipe_error ret
= PIPE_OK
;
6385 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6386 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6388 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6389 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6390 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6391 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6392 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6393 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6394 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6395 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6396 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6397 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6399 t
= CALLOC_STRUCT(st_translate
);
6401 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6405 t
->procType
= procType
;
6406 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6407 t
->inputMapping
= inputMapping
;
6408 t
->outputMapping
= outputMapping
;
6410 t
->num_temp_arrays
= program
->next_array
;
6411 if (t
->num_temp_arrays
)
6412 t
->arrays
= (struct ureg_dst
*)
6413 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6416 * Declare input attributes.
6419 case PIPE_SHADER_FRAGMENT
:
6420 case PIPE_SHADER_GEOMETRY
:
6421 case PIPE_SHADER_TESS_EVAL
:
6422 case PIPE_SHADER_TESS_CTRL
:
6423 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6425 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6426 struct inout_decl
*decl
= &program
->inputs
[i
];
6427 unsigned slot
= inputMapping
[decl
->mesa_index
];
6428 struct ureg_src src
;
6429 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6431 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6432 if (tgsi_usage_mask
== 1)
6433 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6434 else if (tgsi_usage_mask
== 2)
6435 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6437 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6440 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6441 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6442 if (procType
== PIPE_SHADER_FRAGMENT
) {
6444 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6445 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6446 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6448 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6451 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6452 (enum tgsi_semantic
) inputSemanticName
[slot
],
6453 inputSemanticIndex
[slot
],
6454 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6455 decl
->array_id
, decl
->size
);
6457 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6458 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6459 /* The ArrayID is set up in dst_register */
6460 t
->inputs
[slot
+ j
] = src
;
6461 t
->inputs
[slot
+ j
].ArrayID
= 0;
6462 t
->inputs
[slot
+ j
].Index
+= j
;
6467 case PIPE_SHADER_VERTEX
:
6468 for (i
= 0; i
< numInputs
; i
++) {
6469 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6472 case PIPE_SHADER_COMPUTE
:
6479 * Declare output attributes.
6482 case PIPE_SHADER_FRAGMENT
:
6483 case PIPE_SHADER_COMPUTE
:
6485 case PIPE_SHADER_GEOMETRY
:
6486 case PIPE_SHADER_TESS_EVAL
:
6487 case PIPE_SHADER_TESS_CTRL
:
6488 case PIPE_SHADER_VERTEX
:
6489 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6491 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6492 struct inout_decl
*decl
= &program
->outputs
[i
];
6493 unsigned slot
= outputMapping
[decl
->mesa_index
];
6494 struct ureg_dst dst
;
6495 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6497 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6498 if (tgsi_usage_mask
== 1)
6499 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6500 else if (tgsi_usage_mask
== 2)
6501 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6503 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6506 dst
= ureg_DECL_output_layout(ureg
,
6507 (enum tgsi_semantic
) outputSemanticName
[slot
],
6508 outputSemanticIndex
[slot
],
6509 decl
->gs_out_streams
,
6510 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6511 dst
.Invariant
= decl
->invariant
;
6512 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6513 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6514 /* The ArrayID is set up in dst_register */
6515 t
->outputs
[slot
+ j
] = dst
;
6516 t
->outputs
[slot
+ j
].ArrayID
= 0;
6517 t
->outputs
[slot
+ j
].Index
+= j
;
6518 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6527 if (procType
== PIPE_SHADER_FRAGMENT
) {
6528 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6529 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6530 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6532 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6533 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6536 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6537 /* Must do this after setting up t->inputs. */
6538 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6539 program
->wpos_transform_const
);
6542 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6543 emit_face_var(ctx
, t
);
6545 for (i
= 0; i
< numOutputs
; i
++) {
6546 switch (outputSemanticName
[i
]) {
6547 case TGSI_SEMANTIC_POSITION
:
6548 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6549 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6550 outputSemanticIndex
[i
]);
6551 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6553 case TGSI_SEMANTIC_STENCIL
:
6554 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6555 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6556 outputSemanticIndex
[i
]);
6557 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6559 case TGSI_SEMANTIC_COLOR
:
6560 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6561 TGSI_SEMANTIC_COLOR
,
6562 outputSemanticIndex
[i
]);
6564 case TGSI_SEMANTIC_SAMPLEMASK
:
6565 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6566 TGSI_SEMANTIC_SAMPLEMASK
,
6567 outputSemanticIndex
[i
]);
6568 /* TODO: If we ever support more than 32 samples, this will have
6569 * to become an array.
6571 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6574 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6575 ret
= PIPE_ERROR_BAD_INPUT
;
6580 else if (procType
== PIPE_SHADER_VERTEX
) {
6581 for (i
= 0; i
< numOutputs
; i
++) {
6582 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6583 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6585 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6586 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6587 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6592 if (procType
== PIPE_SHADER_COMPUTE
) {
6593 emit_compute_block_size(proginfo
, ureg
);
6596 /* Declare address register.
6598 if (program
->num_address_regs
> 0) {
6599 assert(program
->num_address_regs
<= 3);
6600 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6601 t
->address
[i
] = ureg_DECL_address(ureg
);
6604 /* Declare misc input registers
6607 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6609 for (i
= 0; sysInputs
; i
++) {
6610 if (sysInputs
& (1ull << i
)) {
6611 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6613 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6615 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6616 semName
== TGSI_SEMANTIC_VERTEXID
) {
6617 /* From Gallium perspective, these system values are always
6618 * integer, and require native integer support. However, if
6619 * native integer is supported on the vertex stage but not the
6620 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6621 * assumes these system values are floats. To resolve the
6622 * inconsistency, we insert a U2F.
6624 struct st_context
*st
= st_context(ctx
);
6625 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6626 assert(procType
== PIPE_SHADER_VERTEX
);
6627 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6629 if (!ctx
->Const
.NativeIntegers
) {
6630 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6631 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6632 t
->systemValues
[i
]);
6633 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6637 if (procType
== PIPE_SHADER_FRAGMENT
&&
6638 semName
== TGSI_SEMANTIC_POSITION
)
6639 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6640 program
->wpos_transform_const
);
6642 sysInputs
&= ~(1ull << i
);
6647 t
->array_sizes
= program
->array_sizes
;
6648 t
->input_decls
= program
->inputs
;
6649 t
->num_input_decls
= program
->num_inputs
;
6650 t
->output_decls
= program
->outputs
;
6651 t
->num_output_decls
= program
->num_outputs
;
6653 /* Emit constants and uniforms. TGSI uses a single index space for these,
6654 * so we put all the translated regs in t->constants.
6656 if (proginfo
->Parameters
) {
6657 t
->constants
= (struct ureg_src
*)
6658 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6659 if (t
->constants
== NULL
) {
6660 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6663 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6665 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6666 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6668 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6669 case PROGRAM_STATE_VAR
:
6670 case PROGRAM_UNIFORM
:
6671 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6674 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6675 * addressing of the const buffer.
6676 * FIXME: Be smarter and recognize param arrays:
6677 * indirect addressing is only valid within the referenced
6680 case PROGRAM_CONSTANT
:
6681 if (program
->indirect_addr_consts
)
6682 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6684 t
->constants
[i
] = emit_immediate(t
,
6685 proginfo
->Parameters
->ParameterValues
+ pvo
,
6686 proginfo
->Parameters
->Parameters
[i
].DataType
,
6695 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6696 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6697 unsigned num_const_vecs
= (size
+ 15) / 16;
6698 unsigned first
, last
;
6699 assert(num_const_vecs
> 0);
6701 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6702 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6705 /* Emit immediate values.
6707 t
->immediates
= (struct ureg_src
*)
6708 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6709 if (t
->immediates
== NULL
) {
6710 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6713 t
->num_immediates
= program
->num_immediates
;
6716 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6717 assert(i
< program
->num_immediates
);
6718 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6720 assert(i
== program
->num_immediates
);
6722 /* texture samplers */
6723 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6724 if (program
->samplers_used
& (1u << i
)) {
6725 enum tgsi_return_type type
=
6726 st_translate_texture_type(program
->sampler_types
[i
]);
6728 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6730 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
6731 type
, type
, type
, type
);
6735 /* Declare atomic and shader storage buffers. */
6737 struct gl_program
*prog
= program
->prog
;
6739 if (!st_context(ctx
)->has_hw_atomics
) {
6740 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6741 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6742 assert(index
< frag_const
->MaxAtomicBuffers
);
6743 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6746 for (i
= 0; i
< program
->num_atomics
; i
++) {
6747 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
6748 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
6749 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
6750 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
6755 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6756 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6758 if (!st_context(ctx
)->has_hw_atomics
)
6759 index
+= frag_const
->MaxAtomicBuffers
;
6761 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6765 if (program
->use_shared_memory
)
6766 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6768 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6769 if (program
->images_used
& (1 << i
)) {
6770 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6771 program
->image_targets
[i
],
6772 program
->image_formats
[i
],
6777 /* Emit each instruction in turn:
6779 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6780 compile_tgsi_instruction(t
, inst
);
6782 /* Set the next shader stage hint for VS and TES. */
6784 case PIPE_SHADER_VERTEX
:
6785 case PIPE_SHADER_TESS_EVAL
:
6786 if (program
->shader_program
->SeparateShader
)
6789 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6790 if (program
->shader_program
->_LinkedShaders
[i
]) {
6791 ureg_set_next_shader_processor(
6792 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6798 ; /* nothing - silence compiler warning */
6806 t
->num_constants
= 0;
6807 free(t
->immediates
);
6808 t
->num_immediates
= 0;
6814 /* ----------------------------- End TGSI code ------------------------------ */
6818 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6819 * generating Mesa IR.
6821 static struct gl_program
*
6822 get_mesa_program_tgsi(struct gl_context
*ctx
,
6823 struct gl_shader_program
*shader_program
,
6824 struct gl_linked_shader
*shader
)
6826 glsl_to_tgsi_visitor
* v
;
6827 struct gl_program
*prog
;
6828 struct gl_shader_compiler_options
*options
=
6829 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6830 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6831 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6832 unsigned skip_merge_registers
;
6834 validate_ir_tree(shader
->ir
);
6836 prog
= shader
->Program
;
6838 prog
->Parameters
= _mesa_new_parameter_list();
6839 v
= new glsl_to_tgsi_visitor();
6842 v
->shader_program
= shader_program
;
6844 v
->options
= options
;
6845 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6847 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6848 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6849 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6850 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6851 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6852 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6853 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6855 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6856 _mesa_key_pointer_equal
);
6857 skip_merge_registers
=
6858 pscreen
->get_shader_param(pscreen
, ptarget
,
6859 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6861 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6864 /* Remove reads from output registers. */
6865 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6866 lower_output_reads(shader
->Stage
, shader
->ir
);
6868 /* Emit intermediate IR for main(). */
6869 visit_exec_list(shader
->ir
, v
);
6872 /* Print out some information (for debugging purposes) used by the
6873 * optimization passes. */
6876 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6877 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6878 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6879 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6881 for (i
= 0; i
< v
->next_temp
; i
++) {
6882 first_writes
[i
] = -1;
6883 first_reads
[i
] = -1;
6884 last_writes
[i
] = -1;
6887 v
->get_first_temp_read(first_reads
);
6888 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6889 v
->get_last_temp_write(last_writes
);
6890 for (i
= 0; i
< v
->next_temp
; i
++)
6891 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6895 ralloc_free(first_writes
);
6896 ralloc_free(first_reads
);
6897 ralloc_free(last_writes
);
6898 ralloc_free(last_reads
);
6902 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6904 v
->copy_propagate();
6906 while (v
->eliminate_dead_code());
6908 v
->merge_two_dsts();
6909 if (!skip_merge_registers
)
6910 v
->merge_registers();
6911 v
->renumber_registers();
6913 /* Write the END instruction. */
6914 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6916 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6918 _mesa_log("GLSL IR for linked %s program %d:\n",
6919 _mesa_shader_stage_to_string(shader
->Stage
),
6920 shader_program
->Name
);
6921 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6925 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6926 _mesa_copy_linked_program_data(shader_program
, shader
);
6927 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6928 &prog
->info
.inputs_read
,
6929 prog
->info
.vs
.double_inputs_read
,
6930 &prog
->info
.patch_inputs_read
);
6931 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6932 &prog
->info
.outputs_written
, 0ULL,
6933 &prog
->info
.patch_outputs_written
);
6934 count_resources(v
, prog
);
6936 /* The GLSL IR won't be needed anymore. */
6937 ralloc_free(shader
->ir
);
6940 /* This must be done before the uniform storage is associated. */
6941 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6942 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6943 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
))) {
6944 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
6945 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6948 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6949 wposTransformState
);
6952 /* Avoid reallocation of the program parameter list, because the uniform
6953 * storage is only associated with the original parameter list.
6954 * This should be enough for Bitmap and DrawPixels constants.
6956 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6958 /* This has to be done last. Any operation the can cause
6959 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6960 * program constant) has to happen before creating this linkage.
6962 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6963 if (!shader_program
->data
->LinkStatus
) {
6964 free_glsl_to_tgsi_visitor(v
);
6965 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6969 struct st_vertex_program
*stvp
;
6970 struct st_fragment_program
*stfp
;
6971 struct st_common_program
*stp
;
6972 struct st_compute_program
*stcp
;
6974 switch (shader
->Stage
) {
6975 case MESA_SHADER_VERTEX
:
6976 stvp
= (struct st_vertex_program
*)prog
;
6977 stvp
->glsl_to_tgsi
= v
;
6979 case MESA_SHADER_FRAGMENT
:
6980 stfp
= (struct st_fragment_program
*)prog
;
6981 stfp
->glsl_to_tgsi
= v
;
6983 case MESA_SHADER_TESS_CTRL
:
6984 case MESA_SHADER_TESS_EVAL
:
6985 case MESA_SHADER_GEOMETRY
:
6986 stp
= st_common_program(prog
);
6987 stp
->glsl_to_tgsi
= v
;
6989 case MESA_SHADER_COMPUTE
:
6990 stcp
= (struct st_compute_program
*)prog
;
6991 stcp
->glsl_to_tgsi
= v
;
6994 assert(!"should not be reached");
7001 /* See if there are unsupported control flow statements. */
7002 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7004 const struct gl_shader_compiler_options
*options
;
7006 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7012 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7014 /* Other functions are skipped (same as glsl_to_tgsi). */
7015 if (strcmp(ir
->name
, "main") == 0)
7016 return visit_continue
;
7018 return visit_continue_with_parent
;
7021 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7023 if (!ir
->callee
->is_intrinsic()) {
7024 unsupported
= true; /* it's a function call */
7027 return visit_continue
;
7030 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7032 if (options
->EmitNoMainReturn
) {
7036 return visit_continue
;
7043 has_unsupported_control_flow(exec_list
*ir
,
7044 const struct gl_shader_compiler_options
*options
)
7046 ir_control_flow_info_visitor
visitor(options
);
7047 visit_list_elements(&visitor
, ir
);
7048 return visitor
.unsupported
;
7055 * Called via ctx->Driver.LinkShader()
7056 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7057 * with code lowering and other optimizations.
7060 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7062 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7064 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7065 pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
,
7066 PIPE_SHADER_CAP_PREFERRED_IR
);
7067 bool use_nir
= preferred_ir
== PIPE_SHADER_IR_NIR
;
7069 /* Return early if we are loading the shader from on-disk cache */
7070 if (st_load_ir_from_disk_cache(ctx
, prog
, use_nir
)) {
7074 assert(prog
->data
->LinkStatus
);
7076 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7077 if (prog
->_LinkedShaders
[i
] == NULL
)
7080 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7081 exec_list
*ir
= shader
->ir
;
7082 gl_shader_stage stage
= shader
->Stage
;
7083 const struct gl_shader_compiler_options
*options
=
7084 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7085 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7086 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7087 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7088 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7089 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7090 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7091 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
7092 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7093 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7095 /* If there are forms of indirect addressing that the driver
7096 * cannot handle, perform the lowering pass.
7098 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7099 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7100 lower_variable_index_to_cond_assign(stage
, ir
,
7101 options
->EmitNoIndirectInput
,
7102 options
->EmitNoIndirectOutput
,
7103 options
->EmitNoIndirectTemp
,
7104 options
->EmitNoIndirectUniform
);
7107 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7108 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7110 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7111 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7112 LOWER_UNPACK_SNORM_2x16
|
7113 LOWER_PACK_UNORM_2x16
|
7114 LOWER_UNPACK_UNORM_2x16
|
7115 LOWER_PACK_SNORM_4x8
|
7116 LOWER_UNPACK_SNORM_4x8
|
7117 LOWER_UNPACK_UNORM_4x8
|
7118 LOWER_PACK_UNORM_4x8
;
7120 if (ctx
->Extensions
.ARB_gpu_shader5
)
7121 lower_inst
|= LOWER_PACK_USE_BFI
|
7123 if (!ctx
->st
->has_half_float_packing
)
7124 lower_inst
|= LOWER_PACK_HALF_2x16
|
7125 LOWER_UNPACK_HALF_2x16
;
7127 lower_packing_builtins(ir
, lower_inst
);
7130 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7131 lower_offset_arrays(ir
);
7132 do_mat_op_to_vec(ir
);
7134 if (stage
== MESA_SHADER_FRAGMENT
)
7135 lower_blend_equation_advanced(
7136 shader
, ctx
->Extensions
.KHR_blend_equation_advanced_coherent
);
7138 lower_instructions(ir
,
7143 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
7144 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7147 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7148 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7149 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7150 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7151 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7152 /* Assume that if ARB_gpu_shader5 is not supported
7153 * then all of the extended integer functions need
7154 * lowering. It may be necessary to add some caps
7155 * for individual instructions.
7157 (!ctx
->Extensions
.ARB_gpu_shader5
7158 ? BIT_COUNT_TO_MATH
|
7162 FIND_LSB_TO_FLOAT_CAST
|
7163 FIND_MSB_TO_FLOAT_CAST
|
7167 do_vec_index_to_cond_assign(ir
);
7168 lower_vector_insert(ir
, true);
7169 lower_quadop_vector(ir
, false);
7171 if (options
->MaxIfDepth
== 0) {
7175 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7176 /* Do it once and repeat only if there's unsupported control flow. */
7178 do_common_optimization(ir
, true, true, options
,
7179 ctx
->Const
.NativeIntegers
);
7180 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7181 options
->MaxIfDepth
, if_threshold
);
7182 } while (has_unsupported_control_flow(ir
, options
));
7184 /* Repeat it until it stops making changes. */
7187 progress
= do_common_optimization(ir
, true, true, options
,
7188 ctx
->Const
.NativeIntegers
);
7189 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7190 options
->MaxIfDepth
, if_threshold
);
7194 /* Do this again to lower ir_binop_vector_extract introduced
7195 * by optimization passes.
7197 do_vec_index_to_cond_assign(ir
);
7199 validate_ir_tree(ir
);
7202 build_program_resource_list(ctx
, prog
);
7205 return st_link_nir(ctx
, prog
);
7207 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7208 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7212 struct gl_program
*linked_prog
=
7213 get_mesa_program_tgsi(ctx
, prog
, shader
);
7214 st_set_prog_affected_state_flags(linked_prog
);
7217 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7218 _mesa_shader_stage_to_program(i
),
7220 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7230 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7231 const ubyte outputMapping
[],
7232 struct pipe_stream_output_info
*so
)
7234 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7237 struct gl_transform_feedback_info
*info
=
7238 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7239 st_translate_stream_output_info2(info
, outputMapping
, so
);
7243 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7244 const ubyte outputMapping
[],
7245 struct pipe_stream_output_info
*so
)
7249 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7250 so
->output
[i
].register_index
=
7251 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7252 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7253 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7254 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7255 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7256 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7259 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7260 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7262 so
->num_outputs
= info
->NumOutputs
;