2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2011 Bryan Cain
4 * Copyright © 2017 Gert Wollny
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #ifndef ST_GLSL_TO_TGSI_PRIVATE_H
27 #define ST_GLSL_TO_TGSI_PRIVATE_H
29 #include "mesa/main/mtypes.h"
30 #include "program/prog_parameter.h"
31 #include "compiler/glsl_types.h"
32 #include "compiler/glsl/ir.h"
33 #include "tgsi/tgsi_info.h"
36 int swizzle_for_size(int size
);
40 * This struct is a corresponding struct to TGSI ureg_src.
44 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
45 int component
= 0, unsigned array_id
= 0);
47 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
);
49 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
);
52 st_src_reg(const st_src_reg
®
);
53 void operator=(const st_src_reg
®
);
55 explicit st_src_reg(st_dst_reg reg
);
59 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
62 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
63 int negate
:4; /**< NEGATE_XYZW mask from mesa */
65 enum glsl_base_type type
:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
66 unsigned has_index2
:1;
67 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
69 * Is this the second half of a double register pair?
70 * currently used for input mapping only.
72 unsigned double_reg2
:1;
73 unsigned is_double_vertex_input
:1;
75 /** Register index should be offset by the integer in this reg. */
79 bool is_legal_tgsi_address_operand() const
81 /* 2D registers can't be used as an address operand, or if the address
82 * operand itself is a result of indirect addressing.
84 return (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
) &&
85 !has_index2
&& !reladdr
&& !reladdr2
;
89 bool operator == (const st_src_reg
& lhs
, const st_src_reg
& rhs
);
91 std::ostream
& operator << (std::ostream
& os
, const st_src_reg
& reg
);
95 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
);
97 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
);
100 st_dst_reg(const st_dst_reg
®
);
101 void operator=(const st_dst_reg
®
);
103 explicit st_dst_reg(st_src_reg reg
);
105 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
107 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
108 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
109 enum glsl_base_type type
:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
110 unsigned has_index2
:1;
111 unsigned array_id
:10;
113 /** Register index should be offset by the integer in this reg. */
115 st_src_reg
*reladdr2
;
118 bool operator == (const st_dst_reg
& lhs
, const st_dst_reg
& rhs
);
120 std::ostream
& operator << (std::ostream
& os
, const st_dst_reg
& reg
);
123 class glsl_to_tgsi_instruction
: public exec_node
{
125 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
129 st_src_reg resource
; /**< sampler or buffer register */
130 st_src_reg
*tex_offsets
;
132 /** Pointer to the ir source this tree came fe02549fdrom for debugging */
135 enum tgsi_opcode op
:10; /**< TGSI opcode */
138 unsigned is_64bit_expanded
:1;
139 unsigned sampler_base
:5;
140 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
141 gl_texture_index tex_target
:5;
142 glsl_base_type tex_type
:6;
143 unsigned tex_shadow
:1;
144 enum pipe_format image_format
:10;
145 unsigned tex_offset_num_offset
:3;
146 unsigned dead_mask
:4; /**< Used in dead code elimination */
147 unsigned buffer_access
:3; /**< bitmask of TGSI_MEMORY_x bits */
148 unsigned read_only
:1;
150 const struct tgsi_opcode_info
*info
;
152 void print(std::ostream
& os
) const;
156 operator << (std::ostream
& os
, const glsl_to_tgsi_instruction
& instr
)
162 struct rename_reg_pair
{
168 is_resource_instruction(unsigned opcode
)
171 case TGSI_OPCODE_RESQ
:
172 case TGSI_OPCODE_LOAD
:
173 case TGSI_OPCODE_ATOMUADD
:
174 case TGSI_OPCODE_ATOMXCHG
:
175 case TGSI_OPCODE_ATOMCAS
:
176 case TGSI_OPCODE_ATOMAND
:
177 case TGSI_OPCODE_ATOMOR
:
178 case TGSI_OPCODE_ATOMXOR
:
179 case TGSI_OPCODE_ATOMUMIN
:
180 case TGSI_OPCODE_ATOMUMAX
:
181 case TGSI_OPCODE_ATOMIMIN
:
182 case TGSI_OPCODE_ATOMIMAX
:
183 case TGSI_OPCODE_IMG2HND
:
190 inline static unsigned
191 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
193 return op
->info
->num_dst
;
196 inline static unsigned
197 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
199 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
200 op
->info
->num_src
- 1 : op
->info
->num_src
;