src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "tgsi/tgsi_from_mesa.h"
  41 #include "st_mesa_to_tgsi.h"
  42 #include "st_context.h"
  43 #include "program/prog_instruction.h"
  44 #include "program/prog_parameter.h"
  45 #include "util/u_debug.h"
  46 #include "util/u_math.h"
  47 #include "util/u_memory.h"
  48 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  49
  50
  51 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  52                            (1 << PROGRAM_CONSTANT) |     \
  53                            (1 << PROGRAM_UNIFORM))
  54
  55 /**
  56  * Intermediate state used during shader translation.
  57  */
  58 struct st_translate {
  59    struct ureg_program *ureg;
  60
  61    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  62    struct ureg_src *constants;
  63    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  64    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  65    struct ureg_dst address[1];
  66    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  67    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  68
  69    const ubyte *inputMapping;
  70    const ubyte *outputMapping;
  71
  72    unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
  73 };
  74
  75
  76 /**
  77  * Map a Mesa dst register to a TGSI ureg_dst register.
  78  */
  79 static struct ureg_dst
  80 dst_register(struct st_translate *t, gl_register_file file, GLuint index)
  81 {
  82    switch(file) {
  83    case PROGRAM_UNDEFINED:
  84       return ureg_dst_undef();
  85
  86    case PROGRAM_TEMPORARY:
  87       if (ureg_dst_is_undef(t->temps[index]))
  88          t->temps[index] = ureg_DECL_temporary(t->ureg);
  89
  90       return t->temps[index];
  91
  92    case PROGRAM_OUTPUT:
  93       if (t->procType == PIPE_SHADER_VERTEX)
  94          assert(index < VARYING_SLOT_MAX);
  95       else if (t->procType == PIPE_SHADER_FRAGMENT)
  96          assert(index < FRAG_RESULT_MAX);
  97       else
  98          assert(index < VARYING_SLOT_MAX);
  99
 100       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 101
 102       return t->outputs[t->outputMapping[index]];
 103
 104    case PROGRAM_ADDRESS:
 105       return t->address[index];
 106
 107    default:
 108       debug_assert(0);
 109       return ureg_dst_undef();
 110    }
 111 }
 112
 113
 114 /**
 115  * Map a Mesa src register to a TGSI ureg_src register.
 116  */
 117 static struct ureg_src
 118 src_register(struct st_translate *t,
 119               gl_register_file file,
 120               GLint index)
 121 {
 122    switch(file) {
 123    case PROGRAM_UNDEFINED:
 124       return ureg_src_undef();
 125
 126    case PROGRAM_TEMPORARY:
 127       assert(index >= 0);
 128       assert(index < ARRAY_SIZE(t->temps));
 129       if (ureg_dst_is_undef(t->temps[index]))
 130          t->temps[index] = ureg_DECL_temporary(t->ureg);
 131       return ureg_src(t->temps[index]);
 132
 133    case PROGRAM_UNIFORM:
 134       assert(index >= 0);
 135       return t->constants[index];
 136    case PROGRAM_STATE_VAR:
 137    case PROGRAM_CONSTANT:       /* ie, immediate */
 138       if (index < 0)
 139          return ureg_DECL_constant(t->ureg, 0);
 140       else
 141          return t->constants[index];
 142
 143    case PROGRAM_INPUT:
 144       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 145       return t->inputs[t->inputMapping[index]];
 146
 147    case PROGRAM_OUTPUT:
 148       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 149       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 150
 151    case PROGRAM_ADDRESS:
 152       return ureg_src(t->address[index]);
 153
 154    case PROGRAM_SYSTEM_VALUE:
 155       assert(index < ARRAY_SIZE(t->systemValues));
 156       return t->systemValues[index];
 157
 158    default:
 159       debug_assert(0);
 160       return ureg_src_undef();
 161    }
 162 }
 163
 164
 165 /**
 166  * Map mesa texture target to TGSI texture target.
 167  */
 168 enum tgsi_texture_type
 169 st_translate_texture_target(gl_texture_index textarget, GLboolean shadow)
 170 {
 171    if (shadow) {
 172       switch (textarget) {
 173       case TEXTURE_1D_INDEX:
 174          return TGSI_TEXTURE_SHADOW1D;
 175       case TEXTURE_2D_INDEX:
 176          return TGSI_TEXTURE_SHADOW2D;
 177       case TEXTURE_RECT_INDEX:
 178          return TGSI_TEXTURE_SHADOWRECT;
 179       case TEXTURE_1D_ARRAY_INDEX:
 180          return TGSI_TEXTURE_SHADOW1D_ARRAY;
 181       case TEXTURE_2D_ARRAY_INDEX:
 182          return TGSI_TEXTURE_SHADOW2D_ARRAY;
 183       case TEXTURE_CUBE_INDEX:
 184          return TGSI_TEXTURE_SHADOWCUBE;
 185       case TEXTURE_CUBE_ARRAY_INDEX:
 186          return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 187       default:
 188          break;
 189       }
 190    }
 191
 192    switch (textarget) {
 193    case TEXTURE_2D_MULTISAMPLE_INDEX:
 194       return TGSI_TEXTURE_2D_MSAA;
 195    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
 196       return TGSI_TEXTURE_2D_ARRAY_MSAA;
 197    case TEXTURE_BUFFER_INDEX:
 198       return TGSI_TEXTURE_BUFFER;
 199    case TEXTURE_1D_INDEX:
 200       return TGSI_TEXTURE_1D;
 201    case TEXTURE_2D_INDEX:
 202       return TGSI_TEXTURE_2D;
 203    case TEXTURE_3D_INDEX:
 204       return TGSI_TEXTURE_3D;
 205    case TEXTURE_CUBE_INDEX:
 206       return TGSI_TEXTURE_CUBE;
 207    case TEXTURE_CUBE_ARRAY_INDEX:
 208       return TGSI_TEXTURE_CUBE_ARRAY;
 209    case TEXTURE_RECT_INDEX:
 210       return TGSI_TEXTURE_RECT;
 211    case TEXTURE_1D_ARRAY_INDEX:
 212       return TGSI_TEXTURE_1D_ARRAY;
 213    case TEXTURE_2D_ARRAY_INDEX:
 214       return TGSI_TEXTURE_2D_ARRAY;
 215    case TEXTURE_EXTERNAL_INDEX:
 216       return TGSI_TEXTURE_2D;
 217    default:
 218       debug_assert(!"unexpected texture target index");
 219       return TGSI_TEXTURE_1D;
 220    }
 221 }
 222
 223
 224 /**
 225  * Map GLSL base type to TGSI return type.
 226  */
 227 enum tgsi_return_type
 228 st_translate_texture_type(enum glsl_base_type type)
 229 {
 230    switch (type) {
 231    case GLSL_TYPE_INT:
 232       return TGSI_RETURN_TYPE_SINT;
 233    case GLSL_TYPE_UINT:
 234       return TGSI_RETURN_TYPE_UINT;
 235    case GLSL_TYPE_FLOAT:
 236       return TGSI_RETURN_TYPE_FLOAT;
 237    default:
 238       assert(!"unexpected texture type");
 239       return TGSI_RETURN_TYPE_UNKNOWN;
 240    }
 241 }
 242
 243
 244 /**
 245  * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
 246  */
 247 static unsigned
 248 translate_texture_index(GLbitfield texBit, bool shadow)
 249 {
 250    int index = ffs(texBit);
 251    assert(index > 0);
 252    assert(index - 1 < NUM_TEXTURE_TARGETS);
 253    return st_translate_texture_target(index - 1, shadow);
 254 }
 255
 256
 257 /**
 258  * Create a TGSI ureg_dst register from a Mesa dest register.
 259  */
 260 static struct ureg_dst
 261 translate_dst(struct st_translate *t,
 262               const struct prog_dst_register *DstReg,
 263               boolean saturate)
 264 {
 265    struct ureg_dst dst = dst_register(t, DstReg->File, DstReg->Index);
 266
 267    dst = ureg_writemask(dst, DstReg->WriteMask);
 268
 269    if (saturate)
 270       dst = ureg_saturate(dst);
 271
 272    if (DstReg->RelAddr)
 273       dst = ureg_dst_indirect(dst, ureg_src(t->address[0]));
 274
 275    return dst;
 276 }
 277
 278
 279 /**
 280  * Create a TGSI ureg_src register from a Mesa src register.
 281  */
 282 static struct ureg_src
 283 translate_src(struct st_translate *t,
 284               const struct prog_src_register *SrcReg)
 285 {
 286    struct ureg_src src = src_register(t, SrcReg->File, SrcReg->Index);
 287
 288    src = ureg_swizzle(src,
 289                       GET_SWZ(SrcReg->Swizzle, 0) & 0x3,
 290                       GET_SWZ(SrcReg->Swizzle, 1) & 0x3,
 291                       GET_SWZ(SrcReg->Swizzle, 2) & 0x3,
 292                       GET_SWZ(SrcReg->Swizzle, 3) & 0x3);
 293
 294    if (SrcReg->Negate == NEGATE_XYZW)
 295       src = ureg_negate(src);
 296
 297    if (SrcReg->RelAddr) {
 298       src = ureg_src_indirect(src, ureg_src(t->address[0]));
 299       if (SrcReg->File != PROGRAM_INPUT &&
 300           SrcReg->File != PROGRAM_OUTPUT) {
 301          /* If SrcReg->Index was negative, it was set to zero in
 302           * src_register().  Reassign it now.  But don't do this
 303           * for input/output regs since they get remapped while
 304           * const buffers don't.
 305           */
 306          src.Index = SrcReg->Index;
 307       }
 308    }
 309
 310    return src;
 311 }
 312
 313
 314 static struct ureg_src
 315 swizzle_4v(struct ureg_src src, const unsigned *swz)
 316 {
 317    return ureg_swizzle(src, swz[0], swz[1], swz[2], swz[3]);
 318 }
 319
 320
 321 /**
 322  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 323  *
 324  *   SWZ dst, src.x-y10
 325  *
 326  * becomes:
 327  *
 328  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 329  */
 330 static void
 331 emit_swz(struct st_translate *t,
 332          struct ureg_dst dst,
 333          const struct prog_src_register *SrcReg)
 334 {
 335    struct ureg_program *ureg = t->ureg;
 336    struct ureg_src src = src_register(t, SrcReg->File, SrcReg->Index);
 337
 338    unsigned negate_mask =  SrcReg->Negate;
 339
 340    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 341                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 342                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 343                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 344
 345    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 346                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 347                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 348                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 349
 350    unsigned negative_one_mask = one_mask & negate_mask;
 351    unsigned positive_one_mask = one_mask & ~negate_mask;
 352
 353    struct ureg_src imm;
 354    unsigned i;
 355    unsigned mul_swizzle[4] = {0,0,0,0};
 356    unsigned add_swizzle[4] = {0,0,0,0};
 357    unsigned src_swizzle[4] = {0,0,0,0};
 358    boolean need_add = FALSE;
 359    boolean need_mul = FALSE;
 360
 361    if (dst.WriteMask == 0)
 362       return;
 363
 364    /* Is this just a MOV?
 365     */
 366    if (zero_mask == 0 &&
 367        one_mask == 0 &&
 368        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW)) {
 369       ureg_MOV(ureg, dst, translate_src(t, SrcReg));
 370       return;
 371    }
 372
 373 #define IMM_ZERO    0
 374 #define IMM_ONE     1
 375 #define IMM_NEG_ONE 2
 376
 377    imm = ureg_imm3f(ureg, 0, 1, -1);
 378
 379    for (i = 0; i < 4; i++) {
 380       unsigned bit = 1 << i;
 381
 382       if (dst.WriteMask & bit) {
 383          if (positive_one_mask & bit) {
 384             mul_swizzle[i] = IMM_ZERO;
 385             add_swizzle[i] = IMM_ONE;
 386             need_add = TRUE;
 387          }
 388          else if (negative_one_mask & bit) {
 389             mul_swizzle[i] = IMM_ZERO;
 390             add_swizzle[i] = IMM_NEG_ONE;
 391             need_add = TRUE;
 392          }
 393          else if (zero_mask & bit) {
 394             mul_swizzle[i] = IMM_ZERO;
 395             add_swizzle[i] = IMM_ZERO;
 396             need_add = TRUE;
 397          }
 398          else {
 399             add_swizzle[i] = IMM_ZERO;
 400             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 401             need_mul = TRUE;
 402             if (negate_mask & bit) {
 403                mul_swizzle[i] = IMM_NEG_ONE;
 404             }
 405             else {
 406                mul_swizzle[i] = IMM_ONE;
 407             }
 408          }
 409       }
 410    }
 411
 412    if (need_mul && need_add) {
 413       ureg_MAD(ureg,
 414                dst,
 415                swizzle_4v(src, src_swizzle),
 416                swizzle_4v(imm, mul_swizzle),
 417                swizzle_4v(imm, add_swizzle));
 418    }
 419    else if (need_mul) {
 420       ureg_MUL(ureg,
 421                dst,
 422                swizzle_4v(src, src_swizzle),
 423                swizzle_4v(imm, mul_swizzle));
 424    }
 425    else if (need_add) {
 426       ureg_MOV(ureg,
 427                dst,
 428                swizzle_4v(imm, add_swizzle));
 429    }
 430    else {
 431       debug_assert(0);
 432    }
 433
 434 #undef IMM_ZERO
 435 #undef IMM_ONE
 436 #undef IMM_NEG_ONE
 437 }
 438
 439
 440 static unsigned
 441 translate_opcode(unsigned op)
 442 {
 443    switch(op) {
 444    case OPCODE_ARL:
 445       return TGSI_OPCODE_ARL;
 446    case OPCODE_ADD:
 447       return TGSI_OPCODE_ADD;
 448    case OPCODE_CMP:
 449       return TGSI_OPCODE_CMP;
 450    case OPCODE_COS:
 451       return TGSI_OPCODE_COS;
 452    case OPCODE_DP3:
 453       return TGSI_OPCODE_DP3;
 454    case OPCODE_DP4:
 455       return TGSI_OPCODE_DP4;
 456    case OPCODE_DST:
 457       return TGSI_OPCODE_DST;
 458    case OPCODE_EX2:
 459       return TGSI_OPCODE_EX2;
 460    case OPCODE_EXP:
 461       return TGSI_OPCODE_EXP;
 462    case OPCODE_FLR:
 463       return TGSI_OPCODE_FLR;
 464    case OPCODE_FRC:
 465       return TGSI_OPCODE_FRC;
 466    case OPCODE_KIL:
 467       return TGSI_OPCODE_KILL_IF;
 468    case OPCODE_LG2:
 469       return TGSI_OPCODE_LG2;
 470    case OPCODE_LOG:
 471       return TGSI_OPCODE_LOG;
 472    case OPCODE_LIT:
 473       return TGSI_OPCODE_LIT;
 474    case OPCODE_LRP:
 475       return TGSI_OPCODE_LRP;
 476    case OPCODE_MAD:
 477       return TGSI_OPCODE_MAD;
 478    case OPCODE_MAX:
 479       return TGSI_OPCODE_MAX;
 480    case OPCODE_MIN:
 481       return TGSI_OPCODE_MIN;
 482    case OPCODE_MOV:
 483       return TGSI_OPCODE_MOV;
 484    case OPCODE_MUL:
 485       return TGSI_OPCODE_MUL;
 486    case OPCODE_POW:
 487       return TGSI_OPCODE_POW;
 488    case OPCODE_RCP:
 489       return TGSI_OPCODE_RCP;
 490    case OPCODE_SGE:
 491       return TGSI_OPCODE_SGE;
 492    case OPCODE_SIN:
 493       return TGSI_OPCODE_SIN;
 494    case OPCODE_SLT:
 495       return TGSI_OPCODE_SLT;
 496    case OPCODE_TEX:
 497       return TGSI_OPCODE_TEX;
 498    case OPCODE_TXB:
 499       return TGSI_OPCODE_TXB;
 500    case OPCODE_TXP:
 501       return TGSI_OPCODE_TXP;
 502    case OPCODE_END:
 503       return TGSI_OPCODE_END;
 504    default:
 505       debug_assert(0);
 506       return TGSI_OPCODE_NOP;
 507    }
 508 }
 509
 510
 511 static void
 512 compile_instruction(struct gl_context *ctx,
 513                     struct st_translate *t,
 514                     const struct prog_instruction *inst)
 515 {
 516    struct ureg_program *ureg = t->ureg;
 517    GLuint i;
 518    struct ureg_dst dst[1] = { { 0 } };
 519    struct ureg_src src[4];
 520    unsigned num_dst;
 521    unsigned num_src;
 522
 523    num_dst = _mesa_num_inst_dst_regs(inst->Opcode);
 524    num_src = _mesa_num_inst_src_regs(inst->Opcode);
 525
 526    if (num_dst)
 527       dst[0] = translate_dst(t, &inst->DstReg, inst->Saturate);
 528
 529    for (i = 0; i < num_src; i++)
 530       src[i] = translate_src(t, &inst->SrcReg[i]);
 531
 532    switch(inst->Opcode) {
 533    case OPCODE_SWZ:
 534       emit_swz(t, dst[0], &inst->SrcReg[0]);
 535       return;
 536
 537    case OPCODE_TEX:
 538    case OPCODE_TXB:
 539    case OPCODE_TXP:
 540       src[num_src++] = t->samplers[inst->TexSrcUnit];
 541       ureg_tex_insn(ureg,
 542                     translate_opcode(inst->Opcode),
 543                     dst, num_dst,
 544                     st_translate_texture_target(inst->TexSrcTarget,
 545                                                 inst->TexShadow),
 546                     TGSI_RETURN_TYPE_FLOAT,
 547                     NULL, 0,
 548                     src, num_src);
 549       return;
 550
 551    case OPCODE_SCS:
 552       ureg_COS(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_X),
 553                ureg_scalar(src[0], TGSI_SWIZZLE_X));
 554       ureg_SIN(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_Y),
 555                ureg_scalar(src[0], TGSI_SWIZZLE_X));
 556       break;
 557
 558    case OPCODE_XPD: {
 559       struct ureg_dst tmp = ureg_DECL_temporary(ureg);
 560
 561       ureg_MUL(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_XYZ),
 562                ureg_swizzle(src[0], TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z,
 563                             TGSI_SWIZZLE_X, 0),
 564                ureg_swizzle(src[1], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
 565                             TGSI_SWIZZLE_Y, 0));
 566       ureg_MAD(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ),
 567                ureg_swizzle(src[0], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
 568                             TGSI_SWIZZLE_Y, 0),
 569                ureg_negate(ureg_swizzle(src[1], TGSI_SWIZZLE_Y,
 570                                         TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X, 0)),
 571                ureg_src(tmp));
 572       break;
 573    }
 574
 575    case OPCODE_RSQ:
 576       ureg_RSQ(ureg, dst[0], ureg_abs(src[0]));
 577       break;
 578
 579    case OPCODE_ABS:
 580       ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
 581       break;
 582
 583    case OPCODE_SUB:
 584       ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
 585       break;
 586
 587    case OPCODE_DPH: {
 588       struct ureg_dst temp = ureg_DECL_temporary(ureg);
 589
 590       /* DPH = DP4(src0, src1) where src0.w = 1. */
 591       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_XYZ), src[0]);
 592       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_W),
 593                ureg_imm1f(ureg, 1));
 594       ureg_DP4(ureg, dst[0], ureg_src(temp), src[1]);
 595       break;
 596    }
 597
 598    default:
 599       ureg_insn(ureg,
 600                  translate_opcode(inst->Opcode),
 601                  dst, num_dst,
 602                  src, num_src, 0);
 603       break;
 604    }
 605 }
 606
 607
 608 /**
 609  * Emit the TGSI instructions for inverting and adjusting WPOS.
 610  * This code is unavoidable because it also depends on whether
 611  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 612  */
 613 static void
 614 emit_wpos_adjustment(struct gl_context *ctx,
 615                      struct st_translate *t,
 616                      const struct gl_program *program,
 617                      boolean invert,
 618                      GLfloat adjX, GLfloat adjY[2])
 619 {
 620    struct ureg_program *ureg = t->ureg;
 621
 622    /* Fragment program uses fragment position input.
 623     * Need to replace instances of INPUT[WPOS] with temp T
 624     * where T = INPUT[WPOS] by y is inverted.
 625     */
 626    static const gl_state_index16 wposTransformState[STATE_LENGTH]
 627       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 628
 629    /* XXX: note we are modifying the incoming shader here!  Need to
 630     * do this before emitting the constant decls below, or this
 631     * will be missed:
 632     */
 633    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 634                                                        wposTransformState);
 635
 636    struct ureg_src wpostrans = ureg_DECL_constant(ureg, wposTransConst);
 637    struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
 638    struct ureg_src *wpos =
 639       ctx->Const.GLSLFragCoordIsSysVal ?
 640          &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
 641          &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 642    struct ureg_src wpos_input = *wpos;
 643
 644    /* First, apply the coordinate shift: */
 645    if (adjX || adjY[0] || adjY[1]) {
 646       if (adjY[0] != adjY[1]) {
 647          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 648           * depending on whether inversion is actually going to be applied
 649           * or not, which is determined by testing against the inversion
 650           * state variable used below, which will be either +1 or -1.
 651           */
 652          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 653
 654          ureg_CMP(ureg, adj_temp,
 655                   ureg_scalar(wpostrans, invert ? 2 : 0),
 656                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 657                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 658          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 659       } else {
 660          ureg_ADD(ureg, wpos_temp, wpos_input,
 661                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 662       }
 663       wpos_input = ureg_src(wpos_temp);
 664    } else {
 665       /* MOV wpos_temp, input[wpos]
 666        */
 667       ureg_MOV(ureg, wpos_temp, wpos_input);
 668    }
 669
 670    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 671     * inversion/identity, or the other way around if we're drawing to an FBO.
 672     */
 673    if (invert) {
 674       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 675        */
 676       ureg_MAD(ureg,
 677                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
 678                 wpos_input,
 679                 ureg_scalar(wpostrans, 0),
 680                 ureg_scalar(wpostrans, 1));
 681    } else {
 682       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 683        */
 684       ureg_MAD(ureg,
 685                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
 686                 wpos_input,
 687                 ureg_scalar(wpostrans, 2),
 688                 ureg_scalar(wpostrans, 3));
 689    }
 690
 691    /* Use wpos_temp as position input from here on:
 692     */
 693    *wpos = ureg_src(wpos_temp);
 694 }
 695
 696
 697 /**
 698  * Emit fragment position/coordinate code.
 699  */
 700 static void
 701 emit_wpos(struct st_context *st,
 702           struct st_translate *t,
 703           const struct gl_program *program,
 704           struct ureg_program *ureg)
 705 {
 706    struct pipe_screen *pscreen = st->pipe->screen;
 707    GLfloat adjX = 0.0f;
 708    GLfloat adjY[2] = { 0.0f, 0.0f };
 709    boolean invert = FALSE;
 710
 711    /* Query the pixel center conventions supported by the pipe driver and set
 712     * adjX, adjY to help out if it cannot handle the requested one internally.
 713     *
 714     * The bias of the y-coordinate depends on whether y-inversion takes place
 715     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 716     * drawing to an FBO (causes additional inversion), and whether the pipe
 717     * driver origin and the requested origin differ (the latter condition is
 718     * stored in the 'invert' variable).
 719     *
 720     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 721     *
 722     * center shift only:
 723     * i -> h: +0.5
 724     * h -> i: -0.5
 725     *
 726     * inversion only:
 727     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 728     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 729     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 730     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 731     *
 732     * inversion and center shift:
 733     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 734     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 735     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 736     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 737     */
 738    if (program->info.fs.origin_upper_left) {
 739       /* Fragment shader wants origin in upper-left */
 740       if (pscreen->get_param(pscreen,
 741                              PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 742          /* the driver supports upper-left origin */
 743       }
 744       else if (pscreen->get_param(pscreen,
 745                                   PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 746          /* the driver supports lower-left origin, need to invert Y */
 747          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 748                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 749          invert = TRUE;
 750       }
 751       else
 752          assert(0);
 753    }
 754    else {
 755       /* Fragment shader wants origin in lower-left */
 756       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 757          /* the driver supports lower-left origin */
 758          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 759                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 760       else if (pscreen->get_param(pscreen,
 761                                   PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 762          /* the driver supports upper-left origin, need to invert Y */
 763          invert = TRUE;
 764       else
 765          assert(0);
 766    }
 767
 768    if (program->info.fs.pixel_center_integer) {
 769       /* Fragment shader wants pixel center integer */
 770       if (pscreen->get_param(pscreen,
 771                              PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 772          /* the driver supports pixel center integer */
 773          adjY[1] = 1.0f;
 774          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 775                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 776       }
 777       else if (pscreen->get_param(pscreen,
 778                             PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 779          /* the driver supports pixel center half integer, need to bias X,Y */
 780          adjX = -0.5f;
 781          adjY[0] = -0.5f;
 782          adjY[1] = 0.5f;
 783       }
 784       else
 785          assert(0);
 786    }
 787    else {
 788       /* Fragment shader wants pixel center half integer */
 789       if (pscreen->get_param(pscreen,
 790                           PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 791          /* the driver supports pixel center half integer */
 792       }
 793       else if (pscreen->get_param(pscreen,
 794                                PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 795          /* the driver supports pixel center integer, need to bias X,Y */
 796          adjX = adjY[0] = adjY[1] = 0.5f;
 797          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 798                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 799       }
 800       else
 801          assert(0);
 802    }
 803
 804    /* we invert after adjustment so that we avoid the MOV to temporary,
 805     * and reuse the adjustment ADD instead */
 806    emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
 807 }
 808
 809
 810 /**
 811  * Translate Mesa program to TGSI format.
 812  * \param program  the program to translate
 813  * \param numInputs  number of input registers used
 814  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 815  *                      input indexes
 816  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 817  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 818  *                            each input
 819  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 820  * \param numOutputs  number of output registers used
 821  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 822  *                       generic outputs
 823  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 824  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 825  *                             each output
 826  *
 827  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 828  */
 829 enum pipe_error
 830 st_translate_mesa_program(struct gl_context *ctx,
 831                           uint procType,
 832                           struct ureg_program *ureg,
 833                           const struct gl_program *program,
 834                           GLuint numInputs,
 835                           const ubyte inputMapping[],
 836                           const ubyte inputSemanticName[],
 837                           const ubyte inputSemanticIndex[],
 838                           const ubyte interpMode[],
 839                           GLuint numOutputs,
 840                           const ubyte outputMapping[],
 841                           const ubyte outputSemanticName[],
 842                           const ubyte outputSemanticIndex[])
 843 {
 844    struct st_translate translate, *t;
 845    unsigned i;
 846    enum pipe_error ret = PIPE_OK;
 847
 848    assert(numInputs <= ARRAY_SIZE(t->inputs));
 849    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 850
 851    t = &translate;
 852    memset(t, 0, sizeof *t);
 853
 854    t->procType = procType;
 855    t->inputMapping = inputMapping;
 856    t->outputMapping = outputMapping;
 857    t->ureg = ureg;
 858
 859    /*_mesa_print_program(program);*/
 860
 861    /*
 862     * Declare input attributes.
 863     */
 864    if (procType == PIPE_SHADER_FRAGMENT) {
 865       for (i = 0; i < numInputs; i++) {
 866          t->inputs[i] = ureg_DECL_fs_input(ureg,
 867                                            inputSemanticName[i],
 868                                            inputSemanticIndex[i],
 869                                            interpMode[i]);
 870       }
 871
 872       if (program->info.inputs_read & VARYING_BIT_POS) {
 873          /* Must do this after setting up t->inputs, and before
 874           * emitting constant references, below:
 875           */
 876          emit_wpos(st_context(ctx), t, program, ureg);
 877       }
 878
 879       /*
 880        * Declare output attributes.
 881        */
 882       for (i = 0; i < numOutputs; i++) {
 883          switch (outputSemanticName[i]) {
 884          case TGSI_SEMANTIC_POSITION:
 885             t->outputs[i] = ureg_DECL_output(ureg,
 886                                              TGSI_SEMANTIC_POSITION, /* Z / Depth */
 887                                              outputSemanticIndex[i]);
 888
 889             t->outputs[i] = ureg_writemask(t->outputs[i],
 890                                            TGSI_WRITEMASK_Z);
 891             break;
 892          case TGSI_SEMANTIC_STENCIL:
 893             t->outputs[i] = ureg_DECL_output(ureg,
 894                                              TGSI_SEMANTIC_STENCIL, /* Stencil */
 895                                              outputSemanticIndex[i]);
 896             t->outputs[i] = ureg_writemask(t->outputs[i],
 897                                            TGSI_WRITEMASK_Y);
 898             break;
 899          case TGSI_SEMANTIC_COLOR:
 900             t->outputs[i] = ureg_DECL_output(ureg,
 901                                              TGSI_SEMANTIC_COLOR,
 902                                              outputSemanticIndex[i]);
 903             break;
 904          default:
 905             debug_assert(0);
 906             return 0;
 907          }
 908       }
 909    }
 910    else if (procType == PIPE_SHADER_GEOMETRY) {
 911       for (i = 0; i < numInputs; i++) {
 912          t->inputs[i] = ureg_DECL_input(ureg,
 913                                         inputSemanticName[i],
 914                                         inputSemanticIndex[i], 0, 1);
 915       }
 916
 917       for (i = 0; i < numOutputs; i++) {
 918          t->outputs[i] = ureg_DECL_output(ureg,
 919                                           outputSemanticName[i],
 920                                           outputSemanticIndex[i]);
 921       }
 922    }
 923    else {
 924       assert(procType == PIPE_SHADER_VERTEX);
 925
 926       for (i = 0; i < numInputs; i++) {
 927          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
 928       }
 929
 930       for (i = 0; i < numOutputs; i++) {
 931          t->outputs[i] = ureg_DECL_output(ureg,
 932                                           outputSemanticName[i],
 933                                           outputSemanticIndex[i]);
 934          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
 935             /* force register to contain a fog coordinate in the
 936              * form (F, 0, 0, 1).
 937              */
 938             ureg_MOV(ureg,
 939                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
 940                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
 941             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
 942          }
 943       }
 944    }
 945
 946    /* Declare address register.
 947     */
 948    if (program->arb.NumAddressRegs > 0) {
 949       debug_assert(program->arb.NumAddressRegs == 1);
 950       t->address[0] = ureg_DECL_address(ureg);
 951    }
 952
 953    /* Declare misc input registers
 954     */
 955    GLbitfield64 sysInputs = program->info.system_values_read;
 956    for (i = 0; sysInputs; i++) {
 957       if (sysInputs & (1ull << i)) {
 958          unsigned semName = tgsi_get_sysval_semantic(i);
 959
 960          t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 961
 962          if (semName == TGSI_SEMANTIC_INSTANCEID ||
 963              semName == TGSI_SEMANTIC_VERTEXID) {
 964             /* From Gallium perspective, these system values are always
 965              * integer, and require native integer support.  However, if
 966              * native integer is supported on the vertex stage but not the
 967              * pixel stage (e.g, i915g + draw), Mesa will generate IR that
 968              * assumes these system values are floats. To resolve the
 969              * inconsistency, we insert a U2F.
 970              */
 971             struct st_context *st = st_context(ctx);
 972             struct pipe_screen *pscreen = st->pipe->screen;
 973             assert(procType == PIPE_SHADER_VERTEX);
 974             assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
 975                    PIPE_SHADER_CAP_INTEGERS));
 976             (void) pscreen;  /* silence non-debug build warnings */
 977             if (!ctx->Const.NativeIntegers) {
 978                struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
 979                ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
 980                         t->systemValues[i]);
 981                t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
 982             }
 983          }
 984
 985          if (procType == PIPE_SHADER_FRAGMENT &&
 986              semName == TGSI_SEMANTIC_POSITION)
 987             emit_wpos(st_context(ctx), t, program, ureg);
 988
 989           sysInputs &= ~(1ull << i);
 990       }
 991    }
 992
 993    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
 994       /* If temps are accessed with indirect addressing, declare temporaries
 995        * in sequential order.  Else, we declare them on demand elsewhere.
 996        */
 997       for (i = 0; i < program->arb.NumTemporaries; i++) {
 998          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
 999          t->temps[i] = ureg_DECL_temporary(t->ureg);
1000       }
1001    }
1002
1003    /* Emit constants and immediates.  Mesa uses a single index space
1004     * for these, so we put all the translated regs in t->constants.
1005     */
1006    if (program->Parameters) {
1007       t->constants = calloc(program->Parameters->NumParameters,
1008                              sizeof t->constants[0]);
1009       if (t->constants == NULL) {
1010          ret = PIPE_ERROR_OUT_OF_MEMORY;
1011          goto out;
1012       }
1013
1014       for (i = 0; i < program->Parameters->NumParameters; i++) {
1015          unsigned pvo = program->Parameters->ParameterValueOffset[i];
1016
1017          switch (program->Parameters->Parameters[i].Type) {
1018          case PROGRAM_STATE_VAR:
1019          case PROGRAM_UNIFORM:
1020             t->constants[i] = ureg_DECL_constant(ureg, i);
1021             break;
1022
1023             /* Emit immediates only when there's no indirect addressing of
1024              * the const buffer.
1025              * FIXME: Be smarter and recognize param arrays:
1026              * indirect addressing is only valid within the referenced
1027              * array.
1028              */
1029          case PROGRAM_CONSTANT:
1030             if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
1031                t->constants[i] = ureg_DECL_constant( ureg, i );
1032             else
1033                t->constants[i] =
1034                   ureg_DECL_immediate(ureg,
1035                                       (const float *)
1036                                       program->Parameters->ParameterValues + pvo,
1037                                       4);
1038             break;
1039          default:
1040             break;
1041          }
1042       }
1043    }
1044
1045    /* texture samplers */
1046    for (i = 0;
1047         i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1048       if (program->SamplersUsed & (1u << i)) {
1049          unsigned target =
1050             translate_texture_index(program->TexturesUsed[i],
1051                                     !!(program->ShadowSamplers & (1 << i)));
1052          t->samplers[i] = ureg_DECL_sampler(ureg, i);
1053          ureg_DECL_sampler_view(ureg, i, target,
1054                                 TGSI_RETURN_TYPE_FLOAT,
1055                                 TGSI_RETURN_TYPE_FLOAT,
1056                                 TGSI_RETURN_TYPE_FLOAT,
1057                                 TGSI_RETURN_TYPE_FLOAT);
1058
1059       }
1060    }
1061
1062    /* Emit each instruction in turn:
1063     */
1064    for (i = 0; i < program->arb.NumInstructions; i++)
1065       compile_instruction(ctx, t, &program->arb.Instructions[i]);
1066
1067 out:
1068    free(t->constants);
1069    return ret;
1070 }