2 * Copyright (C) 2020 Collabora, Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define RETURN_PACKED(str) { \
28 memcpy(&temp, &str, sizeof(str)); \
32 /* This file contains the final passes of the compiler. Running after
33 * scheduling and RA, the IR is now finalized, so we need to emit it to actual
34 * bits on the wire (as well as fixup branches) */
37 bi_pack_header(bi_clause
*clause
, bi_clause
*next
, bool is_fragment
)
39 struct bifrost_header header
= {
40 .back_to_back
= clause
->back_to_back
,
41 .no_end_of_shader
= (next
!= NULL
),
42 .elide_writes
= is_fragment
,
43 .branch_cond
= clause
->branch_conditional
,
44 .datareg_writebarrier
= clause
->data_register_write_barrier
,
45 .datareg
= clause
->data_register
,
46 .scoreboard_deps
= next
? next
->dependencies
: 0,
47 .scoreboard_index
= clause
->scoreboard_id
,
48 .clause_type
= clause
->clause_type
,
49 .next_clause_type
= next
? next
->clause_type
: 0,
52 header
.branch_cond
|= header
.back_to_back
;
55 memcpy(&u
, &header
, sizeof(header
));
59 /* Represents the assignment of ports for a given bundle */
62 /* Register to assign to each port */
65 /* Read ports can be disabled */
68 /* Should we write FMA? what about ADD? If only a single port is
69 * enabled it is in port 2, else ADD/FMA is 2/3 respectively */
70 bool write_fma
, write_add
;
72 /* Should we read with port 3? */
75 /* Packed uniform/constant */
76 uint8_t uniform_constant
;
78 /* Whether writes are actually for the last instruction */
79 bool first_instruction
;
83 bi_print_ports(struct bi_registers
*regs
)
85 for (unsigned i
= 0; i
< 2; ++i
) {
87 printf("port %u: %u\n", i
, regs
->port
[i
]);
90 if (regs
->write_fma
|| regs
->write_add
) {
91 printf("port 2 (%s): %u\n",
92 regs
->write_add
? "ADD" : "FMA",
96 if ((regs
->write_fma
&& regs
->write_add
) || regs
->read_port3
) {
97 printf("port 3 (%s): %u\n",
98 regs
->read_port3
? "read" : "FMA",
103 /* The uniform/constant slot allows loading a contiguous 64-bit immediate or
104 * pushed uniform per bundle. Figure out which one we need in the bundle (the
105 * scheduler needs to ensure we only have one type per bundle), validate
106 * everything, and rewrite away the register/uniform indices to use 3-bit
107 * sources directly. */
110 bi_lookup_constant(bi_clause
*clause
, uint64_t cons
, bool *hi
, bool b64
)
112 uint64_t want
= (cons
>> 4);
114 for (unsigned i
= 0; i
< clause
->constant_count
; ++i
) {
115 /* Only check top 60-bits since that's what's actually embedded
116 * in the clause, the bottom 4-bits are bundle-inline */
118 uint64_t candidates
[2] = {
119 clause
->constants
[i
] >> 4,
120 clause
->constants
[i
] >> 36
123 /* For <64-bit mode, we treat lo/hi separately */
126 candidates
[0] &= (0xFFFFFFFF >> 4);
128 if (candidates
[0] == want
)
131 if (candidates
[1] == want
&& !b64
) {
137 unreachable("Invalid constant accessed");
141 bi_constant_field(unsigned idx
)
145 const unsigned values
[] = {
149 return values
[idx
] << 4;
153 bi_assign_uniform_constant_single(
154 struct bi_registers
*regs
,
156 bi_instruction
*ins
, bool assigned
, bool fast_zero
)
161 bi_foreach_src(ins
, s
) {
162 if (s
== 0 && (ins
->type
== BI_LOAD_VAR_ADDRESS
|| ins
->type
== BI_LOAD_ATTR
)) continue;
164 if (ins
->src
[s
] & BIR_INDEX_CONSTANT
) {
166 bool b64
= nir_alu_type_get_type_size(ins
->src_types
[s
]) > 32;
167 uint64_t cons
= bi_get_immediate(ins
, s
);
168 unsigned idx
= bi_lookup_constant(clause
, cons
, &hi
, b64
);
169 unsigned lo
= clause
->constants
[idx
] & 0xF;
170 unsigned f
= bi_constant_field(idx
) | lo
;
172 if (assigned
&& regs
->uniform_constant
!= f
)
173 unreachable("Mismatched uniform/const field: imm");
175 regs
->uniform_constant
= f
;
176 ins
->src
[s
] = BIR_INDEX_PASS
| (hi
? BIFROST_SRC_CONST_HI
: BIFROST_SRC_CONST_LO
);
178 } else if (ins
->src
[s
] & BIR_INDEX_ZERO
&& (ins
->type
== BI_LOAD_UNIFORM
|| ins
->type
== BI_LOAD_VAR
)) {
179 /* XXX: HACK UNTIL WE HAVE HI MATCHING DUE TO OVERFLOW XXX */
180 ins
->src
[s
] = BIR_INDEX_PASS
| BIFROST_SRC_CONST_HI
;
181 } else if (ins
->src
[s
] & BIR_INDEX_ZERO
&& !fast_zero
) {
182 /* FMAs have a fast zero port, ADD needs to use the
183 * uniform/const port's special 0 mode handled here */
186 if (assigned
&& regs
->uniform_constant
!= f
)
187 unreachable("Mismatched uniform/const field: 0");
189 regs
->uniform_constant
= f
;
190 ins
->src
[s
] = BIR_INDEX_PASS
| BIFROST_SRC_CONST_LO
;
192 } else if (s
& BIR_INDEX_UNIFORM
) {
193 unreachable("Push uniforms not implemented yet");
201 bi_assign_uniform_constant(
203 struct bi_registers
*regs
,
207 bi_assign_uniform_constant_single(regs
, clause
, bundle
.fma
, false, true);
209 bi_assign_uniform_constant_single(regs
, clause
, bundle
.add
, assigned
, false);
212 /* Assigns a port for reading, before anything is written */
215 bi_assign_port_read(struct bi_registers
*regs
, unsigned src
)
217 /* We only assign for registers */
218 if (!(src
& BIR_INDEX_REGISTER
))
221 unsigned reg
= src
& ~BIR_INDEX_REGISTER
;
223 /* Check if we already assigned the port */
224 for (unsigned i
= 0; i
<= 1; ++i
) {
225 if (regs
->port
[i
] == reg
&& regs
->enabled
[i
])
229 if (regs
->port
[3] == reg
&& regs
->read_port3
)
234 for (unsigned i
= 0; i
<= 1; ++i
) {
235 if (!regs
->enabled
[i
]) {
237 regs
->enabled
[i
] = true;
242 if (!regs
->read_port3
) {
244 regs
->read_port3
= true;
248 bi_print_ports(regs
);
249 unreachable("Failed to find a free port for src");
252 static struct bi_registers
253 bi_assign_ports(bi_bundle now
, bi_bundle prev
)
255 struct bi_registers regs
= { 0 };
257 /* We assign ports for the main register mechanism. Special ops
258 * use the data registers, which has its own mechanism entirely
259 * and thus gets skipped over here. */
261 unsigned read_dreg
= now
.add
&&
262 bi_class_props
[now
.add
->type
] & BI_DATA_REG_SRC
;
264 unsigned write_dreg
= prev
.add
&&
265 bi_class_props
[prev
.add
->type
] & BI_DATA_REG_DEST
;
267 /* First, assign reads */
270 bi_foreach_src(now
.fma
, src
)
271 bi_assign_port_read(®s
, now
.fma
->src
[src
]);
274 bi_foreach_src(now
.add
, src
) {
275 if (!(src
== 0 && read_dreg
))
276 bi_assign_port_read(®s
, now
.add
->src
[src
]);
280 /* Next, assign writes */
282 if (prev
.add
&& prev
.add
->dest
& BIR_INDEX_REGISTER
&& !write_dreg
) {
283 regs
.port
[2] = prev
.add
->dest
& ~BIR_INDEX_REGISTER
;
284 regs
.write_add
= true;
287 if (prev
.fma
&& prev
.fma
->dest
& BIR_INDEX_REGISTER
) {
288 unsigned r
= prev
.fma
->dest
& ~BIR_INDEX_REGISTER
;
290 if (regs
.write_add
) {
291 /* Scheduler constraint: cannot read 3 and write 2 */
292 assert(!regs
.read_port3
);
298 regs
.write_fma
= true;
301 /* Finally, ensure port 1 > port 0 for the 63-x trick to function */
303 if (regs
.enabled
[0] && regs
.enabled
[1] && regs
.port
[1] < regs
.port
[0]) {
304 unsigned temp
= regs
.port
[0];
305 regs
.port
[0] = regs
.port
[1];
312 /* Determines the register control field, ignoring the first? flag */
314 static enum bifrost_reg_control
315 bi_pack_register_ctrl_lo(struct bi_registers r
)
319 assert(!r
.read_port3
);
320 return BIFROST_WRITE_ADD_P2_FMA_P3
;
323 return BIFROST_WRITE_FMA_P2_READ_P3
;
325 return BIFROST_WRITE_FMA_P2
;
327 } else if (r
.write_add
) {
329 return BIFROST_WRITE_ADD_P2_READ_P3
;
331 return BIFROST_WRITE_ADD_P2
;
332 } else if (r
.read_port3
)
333 return BIFROST_READ_P3
;
335 return BIFROST_REG_NONE
;
338 /* Ditto but account for the first? flag this time */
340 static enum bifrost_reg_control
341 bi_pack_register_ctrl(struct bi_registers r
)
343 enum bifrost_reg_control ctrl
= bi_pack_register_ctrl_lo(r
);
345 if (r
.first_instruction
) {
346 if (ctrl
== BIFROST_REG_NONE
)
347 ctrl
= BIFROST_FIRST_NONE
;
348 else if (ctrl
== BIFROST_WRITE_FMA_P2_READ_P3
)
349 ctrl
= BIFROST_FIRST_WRITE_FMA_P2_READ_P3
;
351 ctrl
|= BIFROST_FIRST_NONE
;
358 bi_pack_registers(struct bi_registers regs
)
360 enum bifrost_reg_control ctrl
= bi_pack_register_ctrl(regs
);
361 struct bifrost_regs s
= { 0 };
364 if (regs
.enabled
[1]) {
365 /* Gotta save that bit!~ Required by the 63-x trick */
366 assert(regs
.port
[1] > regs
.port
[0]);
367 assert(regs
.enabled
[0]);
369 /* Do the 63-x trick, see docs/disasm */
370 if (regs
.port
[0] > 31) {
371 regs
.port
[0] = 63 - regs
.port
[0];
372 regs
.port
[1] = 63 - regs
.port
[1];
375 assert(regs
.port
[0] <= 31);
376 assert(regs
.port
[1] <= 63);
379 s
.reg1
= regs
.port
[1];
380 s
.reg0
= regs
.port
[0];
382 /* Port 1 disabled, so set to zero and use port 1 for ctrl */
386 if (regs
.enabled
[0]) {
387 /* Bit 0 upper bit of port 0 */
388 s
.reg1
|= (regs
.port
[0] >> 5);
390 /* Rest of port 0 in usual spot */
391 s
.reg0
= (regs
.port
[0] & 0b11111);
393 /* Bit 1 set if port 0 also disabled */
398 /* When port 3 isn't used, we have to set it to port 2, and vice versa,
399 * or INSTR_INVALID_ENC is raised. The reason is unknown. */
401 bool has_port2
= regs
.write_fma
|| regs
.write_add
;
402 bool has_port3
= regs
.read_port3
|| (regs
.write_fma
&& regs
.write_add
);
405 regs
.port
[3] = regs
.port
[2];
408 regs
.port
[2] = regs
.port
[3];
410 s
.reg3
= regs
.port
[3];
411 s
.reg2
= regs
.port
[2];
412 s
.uniform_const
= regs
.uniform_constant
;
414 memcpy(&packed
, &s
, sizeof(s
));
419 bi_set_data_register(bi_clause
*clause
, unsigned idx
)
421 assert(idx
& BIR_INDEX_REGISTER
);
422 unsigned reg
= idx
& ~BIR_INDEX_REGISTER
;
424 clause
->data_register
= reg
;
428 bi_read_data_register(bi_clause
*clause
, bi_instruction
*ins
)
430 bi_set_data_register(clause
, ins
->src
[0]);
434 bi_write_data_register(bi_clause
*clause
, bi_instruction
*ins
)
436 bi_set_data_register(clause
, ins
->dest
);
439 static enum bifrost_packed_src
440 bi_get_src_reg_port(struct bi_registers
*regs
, unsigned src
)
442 unsigned reg
= src
& ~BIR_INDEX_REGISTER
;
444 if (regs
->port
[0] == reg
&& regs
->enabled
[0])
445 return BIFROST_SRC_PORT0
;
446 else if (regs
->port
[1] == reg
&& regs
->enabled
[1])
447 return BIFROST_SRC_PORT1
;
448 else if (regs
->port
[3] == reg
&& regs
->read_port3
)
449 return BIFROST_SRC_PORT3
;
451 unreachable("Tried to access register with no port");
454 static enum bifrost_packed_src
455 bi_get_src(bi_instruction
*ins
, struct bi_registers
*regs
, unsigned s
, bool is_fma
)
457 unsigned src
= ins
->src
[s
];
459 if (src
& BIR_INDEX_REGISTER
)
460 return bi_get_src_reg_port(regs
, src
);
461 else if (src
& BIR_INDEX_ZERO
&& is_fma
)
462 return BIFROST_SRC_STAGE
;
463 else if (src
& BIR_INDEX_PASS
)
464 return src
& ~BIR_INDEX_PASS
;
466 unreachable("Unknown src");
469 /* Constructs a packed 2-bit swizzle for a 16-bit vec2 source. Source must be
470 * 16-bit and written components must correspond to valid swizzles (component x
474 bi_swiz16(bi_instruction
*ins
, unsigned src
)
476 assert(nir_alu_type_get_type_size(ins
->src_types
[src
]) == 16);
477 unsigned swizzle
= 0;
479 for (unsigned c
= 0; c
< 2; ++c
) {
480 if (!bi_writes_component(ins
, src
)) continue;
482 unsigned k
= ins
->swizzle
[src
][c
];
491 bi_pack_fma_fma(bi_instruction
*ins
, struct bi_registers
*regs
)
493 /* (-a)(-b) = ab, so we only need one negate bit */
494 bool negate_mul
= ins
->src_neg
[0] ^ ins
->src_neg
[1];
496 if (ins
->op
.mscale
) {
497 assert(!(ins
->src_abs
[0] && ins
->src_abs
[1]));
498 assert(!ins
->src_abs
[2] || !ins
->src_neg
[3] || !ins
->src_abs
[3]);
500 /* We can have exactly one abs, and can flip the multiplication
501 * to make it fit if we have to */
502 bool flip_ab
= ins
->src_abs
[1];
504 struct bifrost_fma_mscale pack
= {
505 .src0
= bi_get_src(ins
, regs
, flip_ab
? 1 : 0, true),
506 .src1
= bi_get_src(ins
, regs
, flip_ab
? 0 : 1, true),
507 .src2
= bi_get_src(ins
, regs
, 2, true),
508 .src3
= bi_get_src(ins
, regs
, 3, true),
511 .src0_abs
= ins
->src_abs
[0] || ins
->src_abs
[1],
512 .src1_neg
= negate_mul
,
513 .src2_neg
= ins
->src_neg
[2],
514 .op
= BIFROST_FMA_OP_MSCALE
,
518 } else if (ins
->dest_type
== nir_type_float32
) {
519 struct bifrost_fma_fma pack
= {
520 .src0
= bi_get_src(ins
, regs
, 0, true),
521 .src1
= bi_get_src(ins
, regs
, 1, true),
522 .src2
= bi_get_src(ins
, regs
, 2, true),
523 .src0_abs
= ins
->src_abs
[0],
524 .src1_abs
= ins
->src_abs
[1],
525 .src2_abs
= ins
->src_abs
[2],
526 .src0_neg
= negate_mul
,
527 .src2_neg
= ins
->src_neg
[2],
528 .outmod
= ins
->outmod
,
529 .roundmode
= ins
->roundmode
,
530 .op
= BIFROST_FMA_OP_FMA
534 } else if (ins
->dest_type
== nir_type_float16
) {
535 struct bifrost_fma_fma16 pack
= {
536 .src0
= bi_get_src(ins
, regs
, 0, true),
537 .src1
= bi_get_src(ins
, regs
, 1, true),
538 .src2
= bi_get_src(ins
, regs
, 2, true),
539 .swizzle_0
= bi_swiz16(ins
, 0),
540 .swizzle_1
= bi_swiz16(ins
, 1),
541 .swizzle_2
= bi_swiz16(ins
, 2),
542 .src0_neg
= negate_mul
,
543 .src2_neg
= ins
->src_neg
[2],
544 .outmod
= ins
->outmod
,
545 .roundmode
= ins
->roundmode
,
546 .op
= BIFROST_FMA_OP_FMA16
551 unreachable("Invalid fma dest type");
556 bi_pack_fma_addmin_f32(bi_instruction
*ins
, struct bi_registers
*regs
)
559 (ins
->type
== BI_ADD
) ? BIFROST_FMA_OP_FADD32
:
560 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_FMA_OP_FMIN32
:
561 BIFROST_FMA_OP_FMAX32
;
563 struct bifrost_fma_add pack
= {
564 .src0
= bi_get_src(ins
, regs
, 0, true),
565 .src1
= bi_get_src(ins
, regs
, 1, true),
566 .src0_abs
= ins
->src_abs
[0],
567 .src1_abs
= ins
->src_abs
[1],
568 .src0_neg
= ins
->src_neg
[0],
569 .src1_neg
= ins
->src_neg
[1],
571 .outmod
= ins
->outmod
,
572 .roundmode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
580 bi_pack_fma_addmin_f16(bi_instruction
*ins
, struct bi_registers
*regs
)
583 (ins
->type
== BI_ADD
) ? BIFROST_FMA_OP_FADD16
:
584 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_FMA_OP_FMIN16
:
585 BIFROST_FMA_OP_FMAX16
;
587 /* Absolute values are packed in a quirky way. Let k = src1 < src0. Let
588 * l be an auxiliary bit we encode. Then the hardware determines:
593 * Since add/min/max are commutative, this saves a bit by using the
594 * order of the operands as a bit (k). To pack this, first note:
596 * (l && k) implies (l || k).
598 * That is, if the second argument is abs'd, then the first argument
599 * also has abs. So there are three cases:
601 * Case 0: Neither src has absolute value. Then we have l = k = 0.
603 * Case 1: Exactly one src has absolute value. Assign that source to
604 * src0 and the other source to src1. Compute k = src1 < src0 based on
605 * that assignment. Then l = ~k.
607 * Case 2: Both sources have absolute value. Then we have l = k = 1.
608 * Note to force k = 1 requires that (src1 < src0) OR (src0 < src1).
609 * That is, this encoding is only valid if src1 and src0 are distinct.
610 * This is a scheduling restriction (XXX); if an op of this type
611 * requires both identical sources to have abs value, then we must
612 * schedule to ADD (which does not use this ordering trick).
615 unsigned abs_0
= ins
->src_abs
[0], abs_1
= ins
->src_abs
[1];
616 unsigned src_0
= bi_get_src(ins
, regs
, 0, true);
617 unsigned src_1
= bi_get_src(ins
, regs
, 1, true);
621 if (!abs_0
&& !abs_1
) {
622 /* Force k = 0 <===> NOT(src1 < src0) */
623 flip
= (src_1
< src_0
);
624 } else if (abs_0
&& !abs_1
) {
626 } else if (abs_1
&& !abs_0
) {
630 flip
= (src_0
>= src_1
);
634 struct bifrost_fma_add_minmax16 pack
= {
635 .src0
= flip
? src_1
: src_0
,
636 .src1
= flip
? src_0
: src_1
,
637 .src0_neg
= ins
->src_neg
[flip
? 1 : 0],
638 .src1_neg
= ins
->src_neg
[flip
? 0 : 1],
640 .outmod
= ins
->outmod
,
641 .mode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
649 bi_pack_fma_addmin(bi_instruction
*ins
, struct bi_registers
*regs
)
651 if (ins
->dest_type
== nir_type_float32
)
652 return bi_pack_fma_addmin_f32(ins
, regs
);
653 else if(ins
->dest_type
== nir_type_float16
)
654 return bi_pack_fma_addmin_f16(ins
, regs
);
656 unreachable("Unknown FMA/ADD type");
660 bi_pack_fma_1src(bi_instruction
*ins
, struct bi_registers
*regs
, unsigned op
)
662 struct bifrost_fma_inst pack
= {
663 .src0
= bi_get_src(ins
, regs
, 0, true),
671 bi_pack_fma_2src(bi_instruction
*ins
, struct bi_registers
*regs
, unsigned op
)
673 struct bifrost_fma_2src pack
= {
674 .src0
= bi_get_src(ins
, regs
, 0, true),
675 .src1
= bi_get_src(ins
, regs
, 1, true),
683 bi_pack_add_1src(bi_instruction
*ins
, struct bi_registers
*regs
, unsigned op
)
685 struct bifrost_add_inst pack
= {
686 .src0
= bi_get_src(ins
, regs
, 0, true),
693 static enum bifrost_csel_cond
694 bi_cond_to_csel(enum bi_cond cond
, bool *flip
, bool *invert
, nir_alu_type T
)
696 nir_alu_type B
= nir_alu_type_get_base_type(T
);
697 unsigned idx
= (B
== nir_type_float
) ? 0 :
698 ((B
== nir_type_int
) ? 1 : 2);
704 const enum bifrost_csel_cond ops
[] = {
715 const enum bifrost_csel_cond ops
[] = {
726 const enum bifrost_csel_cond ops
[] = {
729 BIFROST_IEQ_F
/* sign is irrelevant */
735 unreachable("Invalid op for csel");
740 bi_pack_fma_csel(bi_instruction
*ins
, struct bi_registers
*regs
)
742 /* TODO: Use csel3 as well */
743 bool flip
= false, invert
= false;
745 enum bifrost_csel_cond cond
=
746 bi_cond_to_csel(ins
->csel_cond
, &flip
, &invert
, ins
->src_types
[0]);
748 unsigned size
= nir_alu_type_get_type_size(ins
->dest_type
);
750 unsigned cmp_0
= (flip
? 1 : 0);
751 unsigned cmp_1
= (flip
? 0 : 1);
752 unsigned res_0
= (invert
? 3 : 2);
753 unsigned res_1
= (invert
? 2 : 3);
755 struct bifrost_csel4 pack
= {
756 .src0
= bi_get_src(ins
, regs
, cmp_0
, true),
757 .src1
= bi_get_src(ins
, regs
, cmp_1
, true),
758 .src2
= bi_get_src(ins
, regs
, res_0
, true),
759 .src3
= bi_get_src(ins
, regs
, res_1
, true),
761 .op
= (size
== 16) ? BIFROST_FMA_OP_CSEL4_V16
:
769 bi_pack_fma_frexp(bi_instruction
*ins
, struct bi_registers
*regs
)
771 unsigned op
= BIFROST_FMA_OP_FREXPE_LOG
;
772 return bi_pack_fma_1src(ins
, regs
, op
);
776 bi_pack_fma_reduce(bi_instruction
*ins
, struct bi_registers
*regs
)
778 if (ins
->op
.reduce
== BI_REDUCE_ADD_FREXPM
) {
779 return bi_pack_fma_2src(ins
, regs
, BIFROST_FMA_OP_ADD_FREXPM
);
781 unreachable("Invalid reduce op");
785 /* We have a single convert opcode in the IR but a number of opcodes that could
786 * come out. In particular we have native opcodes for:
788 * [ui]16 --> [fui]32 -- int16_to_32
789 * f16 --> f32 -- float16_to_32
790 * f32 --> f16 -- float32_to_16
791 * f32 --> [ui]32 -- float32_to_int
792 * [ui]32 --> f32 -- int_to_float32
793 * [fui]16 --> [fui]16 -- f2i_i2f16
797 bi_pack_convert(bi_instruction
*ins
, struct bi_registers
*regs
, bool FMA
)
799 nir_alu_type from_base
= nir_alu_type_get_base_type(ins
->src_types
[0]);
800 unsigned from_size
= nir_alu_type_get_type_size(ins
->src_types
[0]);
801 bool from_unsigned
= from_base
== nir_type_uint
;
803 nir_alu_type to_base
= nir_alu_type_get_base_type(ins
->dest_type
);
804 unsigned to_size
= nir_alu_type_get_type_size(ins
->dest_type
);
805 bool to_unsigned
= to_base
== nir_type_uint
;
806 bool to_float
= to_base
== nir_type_float
;
809 assert((from_base
!= to_base
) || (from_size
!= to_size
));
810 assert((MAX2(from_size
, to_size
) / MIN2(from_size
, to_size
)) <= 2);
812 /* f32 to f16 is special */
813 if (from_size
== 32 && to_size
== 16 && from_base
== nir_type_float
&& to_base
== from_base
) {
814 /* TODO: second vectorized source? */
815 struct bifrost_fma_2src pfma
= {
816 .src0
= bi_get_src(ins
, regs
, 0, true),
817 .src1
= BIFROST_SRC_STAGE
, /* 0 */
818 .op
= BIFROST_FMA_FLOAT32_TO_16
821 struct bifrost_add_2src padd
= {
822 .src0
= bi_get_src(ins
, regs
, 0, true),
823 .src1
= BIFROST_SRC_STAGE
, /* 0 */
824 .op
= BIFROST_ADD_FLOAT32_TO_16
834 /* Otherwise, figure out the mode */
837 if (from_size
== 16 && to_size
== 32) {
838 unsigned component
= ins
->swizzle
[0][0];
839 assert(component
<= 1);
841 if (from_base
== nir_type_float
)
842 op
= BIFROST_CONVERT_5(component
);
844 op
= BIFROST_CONVERT_4(from_unsigned
, component
, to_float
);
847 unsigned swizzle
= (from_size
== 16) ? bi_swiz16(ins
, 0) : 0;
848 bool is_unsigned
= from_unsigned
;
850 if (from_base
== nir_type_float
) {
851 assert(to_base
!= nir_type_float
);
852 is_unsigned
= to_unsigned
;
854 if (from_size
== 32 && to_size
== 32)
855 mode
= BIFROST_CONV_F32_TO_I32
;
856 else if (from_size
== 16 && to_size
== 16)
857 mode
= BIFROST_CONV_F16_TO_I16
;
859 unreachable("Invalid float conversion");
861 assert(to_base
== nir_type_float
);
862 assert(from_size
== to_size
);
865 mode
= BIFROST_CONV_I32_TO_F32
;
866 else if (to_size
== 16)
867 mode
= BIFROST_CONV_I16_TO_F16
;
869 unreachable("Invalid int conversion");
872 /* Fixup swizzle for 32-bit only modes */
874 if (mode
== BIFROST_CONV_I32_TO_F32
)
876 else if (mode
== BIFROST_CONV_F32_TO_I32
)
879 op
= BIFROST_CONVERT(is_unsigned
, ins
->roundmode
, swizzle
, mode
);
881 /* Unclear what the top bit is for... maybe 16-bit related */
882 bool mode2
= mode
== BIFROST_CONV_F16_TO_I16
;
883 bool mode6
= mode
== BIFROST_CONV_I16_TO_F16
;
885 if (!(mode2
|| mode6
))
890 return bi_pack_fma_1src(ins
, regs
, BIFROST_FMA_CONVERT
| op
);
892 return bi_pack_add_1src(ins
, regs
, BIFROST_ADD_CONVERT
| op
);
896 bi_pack_fma(bi_clause
*clause
, bi_bundle bundle
, struct bi_registers
*regs
)
899 return BIFROST_FMA_NOP
;
901 switch (bundle
.fma
->type
) {
903 return bi_pack_fma_addmin(bundle
.fma
, regs
);
906 return BIFROST_FMA_NOP
;
908 return bi_pack_convert(bundle
.fma
, regs
, true);
910 return bi_pack_fma_csel(bundle
.fma
, regs
);
912 return bi_pack_fma_fma(bundle
.fma
, regs
);
914 return bi_pack_fma_frexp(bundle
.fma
, regs
);
916 return BIFROST_FMA_NOP
;
918 return bi_pack_fma_addmin(bundle
.fma
, regs
);
920 return bi_pack_fma_1src(bundle
.fma
, regs
, BIFROST_FMA_OP_MOV
);
924 return BIFROST_FMA_NOP
;
926 return bi_pack_fma_reduce(bundle
.fma
, regs
);
928 unreachable("Cannot encode class as FMA");
933 bi_pack_add_ld_vary(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
935 unsigned size
= nir_alu_type_get_type_size(ins
->dest_type
);
936 assert(size
== 32 || size
== 16);
938 unsigned op
= (size
== 32) ?
939 BIFROST_ADD_OP_LD_VAR_32
:
940 BIFROST_ADD_OP_LD_VAR_16
;
942 unsigned cmask
= bi_from_bytemask(ins
->writemask
, size
/ 8);
943 unsigned channels
= util_bitcount(cmask
);
944 assert(cmask
== ((1 << channels
) - 1));
946 unsigned packed_addr
= 0;
948 if (ins
->src
[0] & BIR_INDEX_CONSTANT
) {
949 /* Direct uses address field directly */
950 packed_addr
= bi_get_immediate(ins
, 0);
951 assert(packed_addr
< 0b1000);
953 /* Indirect gets an extra source */
954 packed_addr
= bi_get_src(ins
, regs
, 0, false) | 0b11000;
957 /* The destination is thrown in the data register */
958 assert(ins
->dest
& BIR_INDEX_REGISTER
);
959 clause
->data_register
= ins
->dest
& ~BIR_INDEX_REGISTER
;
961 assert(channels
>= 1 && channels
<= 4);
963 struct bifrost_ld_var pack
= {
964 .src0
= bi_get_src(ins
, regs
, 1, false),
966 .channels
= MALI_POSITIVE(channels
),
967 .interp_mode
= ins
->load_vary
.interp_mode
,
968 .reuse
= ins
->load_vary
.reuse
,
969 .flat
= ins
->load_vary
.flat
,
977 bi_pack_add_2src(bi_instruction
*ins
, struct bi_registers
*regs
, unsigned op
)
979 struct bifrost_add_2src pack
= {
980 .src0
= bi_get_src(ins
, regs
, 0, true),
981 .src1
= bi_get_src(ins
, regs
, 1, true),
989 bi_pack_add_addmin_f32(bi_instruction
*ins
, struct bi_registers
*regs
)
992 (ins
->type
== BI_ADD
) ? BIFROST_ADD_OP_FADD32
:
993 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_ADD_OP_FMIN32
:
994 BIFROST_ADD_OP_FMAX32
;
996 struct bifrost_add_faddmin pack
= {
997 .src0
= bi_get_src(ins
, regs
, 0, true),
998 .src1
= bi_get_src(ins
, regs
, 1, true),
999 .src0_abs
= ins
->src_abs
[0],
1000 .src1_abs
= ins
->src_abs
[1],
1001 .src0_neg
= ins
->src_neg
[0],
1002 .src1_neg
= ins
->src_neg
[1],
1003 .outmod
= ins
->outmod
,
1004 .mode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
1008 RETURN_PACKED(pack
);
1012 bi_pack_add_addmin(bi_instruction
*ins
, struct bi_registers
*regs
)
1014 if (ins
->dest_type
== nir_type_float32
)
1015 return bi_pack_add_addmin_f32(ins
, regs
);
1016 else if(ins
->dest_type
== nir_type_float16
)
1017 unreachable("todo");
1018 //return bi_pack_add_addmin_f16(ins, regs);
1020 unreachable("Unknown FMA/ADD type");
1024 bi_pack_add_ld_ubo(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1026 unsigned components
= bi_load32_components(ins
);
1028 const unsigned ops
[4] = {
1029 BIFROST_ADD_OP_LD_UBO_1
,
1030 BIFROST_ADD_OP_LD_UBO_2
,
1031 BIFROST_ADD_OP_LD_UBO_3
,
1032 BIFROST_ADD_OP_LD_UBO_4
1035 bi_write_data_register(clause
, ins
);
1036 return bi_pack_add_2src(ins
, regs
, ops
[components
- 1]);
1039 static enum bifrost_ldst_type
1040 bi_pack_ldst_type(nir_alu_type T
)
1043 case nir_type_float16
: return BIFROST_LDST_F16
;
1044 case nir_type_float32
: return BIFROST_LDST_F32
;
1045 case nir_type_int32
: return BIFROST_LDST_I32
;
1046 case nir_type_uint32
: return BIFROST_LDST_U32
;
1047 default: unreachable("Invalid type loaded");
1052 bi_pack_add_ld_var_addr(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1054 struct bifrost_ld_var_addr pack
= {
1055 .src0
= bi_get_src(ins
, regs
, 1, false),
1056 .src1
= bi_get_src(ins
, regs
, 2, false),
1057 .location
= bi_get_immediate(ins
, 0),
1058 .type
= bi_pack_ldst_type(ins
->src_types
[3]),
1059 .op
= BIFROST_ADD_OP_LD_VAR_ADDR
1062 bi_write_data_register(clause
, ins
);
1063 RETURN_PACKED(pack
);
1067 bi_pack_add_ld_attr(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1069 struct bifrost_ld_attr pack
= {
1070 .src0
= bi_get_src(ins
, regs
, 1, false),
1071 .src1
= bi_get_src(ins
, regs
, 2, false),
1072 .location
= bi_get_immediate(ins
, 0),
1073 .channels
= MALI_POSITIVE(bi_load32_components(ins
)),
1074 .type
= bi_pack_ldst_type(ins
->dest_type
),
1075 .op
= BIFROST_ADD_OP_LD_ATTR
1078 bi_write_data_register(clause
, ins
);
1079 RETURN_PACKED(pack
);
1083 bi_pack_add_st_vary(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1085 assert(ins
->store_channels
>= 1 && ins
->store_channels
<= 4);
1087 struct bifrost_st_vary pack
= {
1088 .src0
= bi_get_src(ins
, regs
, 1, false),
1089 .src1
= bi_get_src(ins
, regs
, 2, false),
1090 .src2
= bi_get_src(ins
, regs
, 3, false),
1091 .channels
= MALI_POSITIVE(ins
->store_channels
),
1092 .op
= BIFROST_ADD_OP_ST_VAR
1095 bi_read_data_register(clause
, ins
);
1096 RETURN_PACKED(pack
);
1100 bi_pack_add_atest(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1103 assert(ins
->src_types
[1] == nir_type_float32
);
1105 struct bifrost_add_atest pack
= {
1106 .src0
= bi_get_src(ins
, regs
, 0, false),
1107 .src1
= bi_get_src(ins
, regs
, 1, false),
1108 .component
= 1, /* Set for fp32 */
1109 .op
= BIFROST_ADD_OP_ATEST
,
1112 /* Despite *also* writing with the usual mechanism... quirky and
1113 * perhaps unnecessary, but let's match the blob */
1114 clause
->data_register
= ins
->dest
& ~BIR_INDEX_REGISTER
;
1116 RETURN_PACKED(pack
);
1120 bi_pack_add_blend(bi_clause
*clause
, bi_instruction
*ins
, struct bi_registers
*regs
)
1122 struct bifrost_add_inst pack
= {
1123 .src0
= bi_get_src(ins
, regs
, 1, false),
1124 .op
= BIFROST_ADD_OP_BLEND
1127 /* TODO: Pack location in uniform_const */
1128 assert(ins
->blend_location
== 0);
1130 bi_read_data_register(clause
, ins
);
1131 RETURN_PACKED(pack
);
1135 bi_pack_add_special(bi_instruction
*ins
, struct bi_registers
*regs
)
1138 bool fp16
= ins
->dest_type
== nir_type_float16
;
1139 bool Y
= ins
->swizzle
[0][0];
1141 if (ins
->op
.special
== BI_SPECIAL_FRCP
) {
1143 (Y
? BIFROST_ADD_OP_FRCP_FAST_F16_Y
:
1144 BIFROST_ADD_OP_FRCP_FAST_F16_X
) :
1145 BIFROST_ADD_OP_FRCP_FAST_F32
;
1146 } else if (ins
->op
.special
== BI_SPECIAL_FRSQ
) {
1148 (Y
? BIFROST_ADD_OP_FRSQ_FAST_F16_Y
:
1149 BIFROST_ADD_OP_FRSQ_FAST_F16_X
) :
1150 BIFROST_ADD_OP_FRSQ_FAST_F32
;
1152 } else if (ins
->op
.special
== BI_SPECIAL_EXP2_LOW
) {
1154 op
= BIFROST_ADD_OP_FEXP2_FAST
;
1156 unreachable("Unknown special op");
1159 return bi_pack_add_1src(ins
, regs
, op
);
1163 bi_pack_add_table(bi_instruction
*ins
, struct bi_registers
*regs
)
1166 assert(ins
->dest_type
== nir_type_float32
);
1168 op
= BIFROST_ADD_OP_LOG2_HELP
;
1169 return bi_pack_add_1src(ins
, regs
, op
);
1173 bi_pack_add(bi_clause
*clause
, bi_bundle bundle
, struct bi_registers
*regs
)
1176 return BIFROST_ADD_NOP
;
1178 switch (bundle
.add
->type
) {
1180 return bi_pack_add_addmin(bundle
.add
, regs
);
1182 return bi_pack_add_atest(clause
, bundle
.add
, regs
);
1185 return BIFROST_ADD_NOP
;
1187 return bi_pack_add_blend(clause
, bundle
.add
, regs
);
1189 return BIFROST_ADD_NOP
;
1191 return bi_pack_convert(bundle
.add
, regs
, false);
1196 return BIFROST_ADD_NOP
;
1198 return bi_pack_add_ld_attr(clause
, bundle
.add
, regs
);
1199 case BI_LOAD_UNIFORM
:
1200 return bi_pack_add_ld_ubo(clause
, bundle
.add
, regs
);
1202 return bi_pack_add_ld_vary(clause
, bundle
.add
, regs
);
1203 case BI_LOAD_VAR_ADDRESS
:
1204 return bi_pack_add_ld_var_addr(clause
, bundle
.add
, regs
);
1206 return bi_pack_add_addmin(bundle
.add
, regs
);
1210 return BIFROST_ADD_NOP
;
1212 return bi_pack_add_st_vary(clause
, bundle
.add
, regs
);
1214 return bi_pack_add_special(bundle
.add
, regs
);
1216 return bi_pack_add_table(bundle
.add
, regs
);
1220 return BIFROST_ADD_NOP
;
1222 unreachable("Cannot encode class as ADD");
1226 struct bi_packed_bundle
{
1231 static struct bi_packed_bundle
1232 bi_pack_bundle(bi_clause
*clause
, bi_bundle bundle
, bi_bundle prev
, bool first_bundle
)
1234 struct bi_registers regs
= bi_assign_ports(bundle
, prev
);
1235 bi_assign_uniform_constant(clause
, ®s
, bundle
);
1236 regs
.first_instruction
= first_bundle
;
1238 uint64_t reg
= bi_pack_registers(regs
);
1239 uint64_t fma
= bi_pack_fma(clause
, bundle
, ®s
);
1240 uint64_t add
= bi_pack_add(clause
, bundle
, ®s
);
1242 struct bi_packed_bundle packed
= {
1243 .lo
= reg
| (fma
<< 35) | ((add
& 0b111111) << 58),
1250 /* Packs the next two constants as a dedicated constant quadword at the end of
1251 * the clause, returning the number packed. */
1254 bi_pack_constants(bi_context
*ctx
, bi_clause
*clause
,
1256 struct util_dynarray
*emission
)
1258 /* After these two, are we done? Determines tag */
1259 bool done
= clause
->constant_count
<= (index
+ 2);
1260 bool only
= clause
->constant_count
<= (index
+ 1);
1263 assert(index
== 0 && clause
->bundle_count
== 1);
1266 uint64_t hi
= clause
->constants
[index
+ 0] >> 60ull;
1268 struct bifrost_fmt_constant quad
= {
1269 .pos
= 0, /* TODO */
1270 .tag
= done
? BIFROST_FMTC_FINAL
: BIFROST_FMTC_CONSTANTS
,
1271 .imm_1
= clause
->constants
[index
+ 0] >> 4,
1272 .imm_2
= ((hi
< 8) ? (hi
<< 60ull) : 0) >> 4,
1275 /* XXX: On G71, Connor observed that the difference of the top 4 bits
1276 * of the second constant with the first must be less than 8, otherwise
1277 * we have to swap them. On G52, I'm able to reproduce a similar issue
1278 * but with a different workaround (modeled above with a single
1279 * constant, unclear how to workaround for multiple constants.) Further
1280 * investigation needed. Possibly an errata. XXX */
1282 util_dynarray_append(emission
, struct bifrost_fmt_constant
, quad
);
1288 bi_pack_clause(bi_context
*ctx
, bi_clause
*clause
, bi_clause
*next
,
1289 struct util_dynarray
*emission
)
1291 struct bi_packed_bundle ins_1
= bi_pack_bundle(clause
, clause
->bundles
[0], clause
->bundles
[0], true);
1292 assert(clause
->bundle_count
== 1);
1294 /* Used to decide if we elide writes */
1295 bool is_fragment
= ctx
->stage
== MESA_SHADER_FRAGMENT
;
1297 /* State for packing constants throughout */
1298 unsigned constant_index
= 0;
1300 struct bifrost_fmt1 quad_1
= {
1301 .tag
= clause
->constant_count
? BIFROST_FMT1_CONSTANTS
: BIFROST_FMT1_FINAL
,
1302 .header
= bi_pack_header(clause
, next
, is_fragment
),
1304 .ins_2
= ins_1
.hi
& ((1 << 11) - 1),
1305 .ins_0
= (ins_1
.hi
>> 11) & 0b111,
1308 util_dynarray_append(emission
, struct bifrost_fmt1
, quad_1
);
1310 /* Pack the remaining constants */
1312 while (constant_index
< clause
->constant_count
) {
1313 constant_index
+= bi_pack_constants(ctx
, clause
,
1314 constant_index
, emission
);
1319 bi_next_clause(bi_context
*ctx
, pan_block
*block
, bi_clause
*clause
)
1321 /* Try the next clause in this block */
1322 if (clause
->link
.next
!= &((bi_block
*) block
)->clauses
)
1323 return list_first_entry(&(clause
->link
), bi_clause
, link
);
1325 /* Try the next block, or the one after that if it's empty, etc .*/
1326 pan_block
*next_block
= pan_next_block(block
);
1328 bi_foreach_block_from(ctx
, next_block
, block
) {
1329 bi_block
*blk
= (bi_block
*) block
;
1331 if (!list_is_empty(&blk
->clauses
))
1332 return list_first_entry(&(blk
->clauses
), bi_clause
, link
);
1339 bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
)
1341 util_dynarray_init(emission
, NULL
);
1343 bi_foreach_block(ctx
, _block
) {
1344 bi_block
*block
= (bi_block
*) _block
;
1346 bi_foreach_clause_in_block(block
, clause
) {
1347 bi_clause
*next
= bi_next_clause(ctx
, _block
, clause
);
1348 bi_pack_clause(ctx
, clause
, next
, emission
);