src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest),
 106         bi_emit(ctx, ins);
 107 }
 108
 109 static void
 110 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 111 {
 112         if (!ctx->emitted_atest) {
 113                 bi_instruction ins = {
 114                         .type = BI_ATEST
 115                 };
 116
 117                 bi_emit(ctx, ins);
 118                 bi_schedule_barrier(ctx);
 119                 ctx->emitted_atest = true;
 120         }
 121
 122         bi_instruction blend = {
 123                 .type = BI_BLEND,
 124                 .blend_location = nir_intrinsic_base(instr),
 125                 .src = {
 126                         bir_src_index(&instr->src[0])
 127                 },
 128                 .src_types = {
 129                         nir_type_float32,
 130                 },
 131                 .swizzle = {
 132                         { 0, 1, 2, 3 }
 133                 }
 134         };
 135
 136         bi_emit(ctx, blend);
 137         bi_schedule_barrier(ctx);
 138 }
 139
 140 static void
 141 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 142 {
 143         bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
 144         address.dest = bi_make_temp(ctx);
 145         address.dest_type = nir_type_uint64;
 146         address.writemask = (1 << 8) - 1;
 147
 148         bi_instruction st = {
 149                 .type = BI_STORE_VAR,
 150                 .src = {
 151                         address.dest,
 152                         bir_src_index(&instr->src[0])
 153                 },
 154                 .src_types = {
 155                         nir_type_uint64,
 156                         nir_type_uint32
 157                 },
 158                 .swizzle = {
 159                         { 0 },
 160                         { 0, 1, 2, 3 }
 161                 }
 162         };
 163
 164         bi_emit(ctx, address);
 165         bi_emit(ctx, st);
 166 }
 167
 168 static void
 169 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 170 {
 171         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 172         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 173
 174         /* TODO: Indirect access, since we need to multiply by the element
 175          * size. I believe we can get this lowering automatically via
 176          * nir_lower_io (as mul instructions) with the proper options, but this
 177          * is TODO */
 178         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 179         ld.constant.u64 += ctx->sysvals.sysval_count;
 180         ld.constant.u64 *= 16;
 181
 182         bi_emit(ctx, ld);
 183 }
 184
 185 static void
 186 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 187                 unsigned nr_components, unsigned offset)
 188 {
 189         nir_dest nir_dest;
 190
 191         /* Figure out which uniform this is */
 192         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 193         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 194
 195         /* Sysvals are prefix uniforms */
 196         unsigned uniform = ((uintptr_t) val) - 1;
 197
 198         /* Emit the read itself -- this is never indirect */
 199
 200         bi_instruction load = {
 201                 .type = BI_LOAD_UNIFORM,
 202                 .writemask = (1 << (nr_components * 4)) - 1,
 203                 .src = { BIR_INDEX_CONSTANT},
 204                 .constant = { (uniform * 16) + offset },
 205                 .dest = bir_dest_index(&nir_dest),
 206                 .dest_type = nir_type_uint32, /* TODO */
 207         };
 208
 209         bi_emit(ctx, load);
 210 }
 211
 212 static void
 213 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 214 {
 215
 216         switch (instr->intrinsic) {
 217         case nir_intrinsic_load_barycentric_pixel:
 218                 /* stub */
 219                 break;
 220         case nir_intrinsic_load_interpolated_input:
 221         case nir_intrinsic_load_input:
 222                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 223                         bi_emit_ld_vary(ctx, instr);
 224                 else if (ctx->stage == MESA_SHADER_VERTEX)
 225                         bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
 226                 else {
 227                         unreachable("Unsupported shader stage");
 228                 }
 229                 break;
 230
 231         case nir_intrinsic_store_output:
 232                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 233                         bi_emit_frag_out(ctx, instr);
 234                 else if (ctx->stage == MESA_SHADER_VERTEX)
 235                         bi_emit_st_vary(ctx, instr);
 236                 else
 237                         unreachable("Unsupported shader stage");
 238                 break;
 239
 240         case nir_intrinsic_load_uniform:
 241                 bi_emit_ld_uniform(ctx, instr);
 242                 break;
 243
 244         case nir_intrinsic_load_ssbo_address:
 245                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 246                 break;
 247
 248         case nir_intrinsic_get_buffer_size:
 249                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 250                 break;
 251
 252         case nir_intrinsic_load_viewport_scale:
 253         case nir_intrinsic_load_viewport_offset:
 254         case nir_intrinsic_load_num_work_groups:
 255         case nir_intrinsic_load_sampler_lod_parameters_pan:
 256                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 257                 break;
 258
 259         default:
 260                 /* todo */
 261                 break;
 262         }
 263 }
 264
 265 static void
 266 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 267 {
 268         /* Make sure we've been lowered */
 269         assert(instr->def.num_components == 1);
 270
 271         bi_instruction move = {
 272                 .type = BI_MOV,
 273                 .dest = bir_ssa_index(&instr->def),
 274                 .dest_type = instr->def.bit_size | nir_type_uint,
 275                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 276                 .src = {
 277                         BIR_INDEX_CONSTANT
 278                 },
 279                 .constant = {
 280                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 281                 }
 282         };
 283
 284         bi_emit(ctx, move);
 285 }
 286
 287 static enum bi_class
 288 bi_class_for_nir_alu(nir_op op)
 289 {
 290         switch (op) {
 291         case nir_op_iadd:
 292         case nir_op_fadd:
 293         case nir_op_fsub:
 294                 return BI_ADD;
 295         case nir_op_isub:
 296                 return BI_ISUB;
 297
 298         case nir_op_flt:
 299         case nir_op_fge:
 300         case nir_op_feq:
 301         case nir_op_fne:
 302         case nir_op_ilt:
 303         case nir_op_ige:
 304         case nir_op_ieq:
 305         case nir_op_ine:
 306                 return BI_CMP;
 307
 308         case nir_op_bcsel:
 309                 return BI_CSEL;
 310
 311         case nir_op_i2i8:
 312         case nir_op_i2i16:
 313         case nir_op_i2i32:
 314         case nir_op_i2i64:
 315         case nir_op_u2u8:
 316         case nir_op_u2u16:
 317         case nir_op_u2u32:
 318         case nir_op_u2u64:
 319         case nir_op_f2i16:
 320         case nir_op_f2i32:
 321         case nir_op_f2i64:
 322         case nir_op_f2u16:
 323         case nir_op_f2u32:
 324         case nir_op_f2u64:
 325         case nir_op_i2f16:
 326         case nir_op_i2f32:
 327         case nir_op_i2f64:
 328         case nir_op_u2f16:
 329         case nir_op_u2f32:
 330         case nir_op_u2f64:
 331                 return BI_CONVERT;
 332
 333         case nir_op_ffma:
 334         case nir_op_fmul:
 335                 return BI_FMA;
 336
 337         case nir_op_imin:
 338         case nir_op_imax:
 339         case nir_op_umin:
 340         case nir_op_umax:
 341         case nir_op_fmin:
 342         case nir_op_fmax:
 343                 return BI_MINMAX;
 344
 345         case nir_op_fsat:
 346         case nir_op_fneg:
 347         case nir_op_fabs:
 348         case nir_op_mov:
 349                 return BI_MOV;
 350
 351         case nir_op_frcp:
 352         case nir_op_frsq:
 353         case nir_op_fsin:
 354         case nir_op_fcos:
 355                 return BI_SPECIAL;
 356
 357         default:
 358                 unreachable("Unknown ALU op");
 359         }
 360 }
 361
 362 static enum bi_cond
 363 bi_cond_for_nir(nir_op op)
 364 {
 365         switch (op) {
 366         case nir_op_flt:
 367         case nir_op_ilt:
 368                 return BI_COND_LT;
 369         case nir_op_fge:
 370         case nir_op_ige:
 371                 return BI_COND_GE;
 372         case nir_op_feq:
 373         case nir_op_ieq:
 374                 return BI_COND_EQ;
 375         case nir_op_fne:
 376         case nir_op_ine:
 377                 return BI_COND_NE;
 378         default:
 379                 unreachable("Invalid compare");
 380         }
 381 }
 382
 383 static void
 384 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 385 {
 386         /* Assume it's something we can handle normally */
 387         bi_instruction alu = {
 388                 .type = bi_class_for_nir_alu(instr->op),
 389                 .dest = bir_dest_index(&instr->dest.dest),
 390                 .dest_type = nir_op_infos[instr->op].output_type
 391                         | nir_dest_bit_size(instr->dest.dest),
 392         };
 393
 394         /* TODO: Implement lowering of special functions for older Bifrost */
 395         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 396
 397         if (instr->dest.dest.is_ssa) {
 398                 /* Construct a writemask */
 399                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 400                 unsigned comps = instr->dest.dest.ssa.num_components;
 401                 assert(comps == 1);
 402                 unsigned bits = bits_per_comp * comps;
 403                 unsigned bytes = MAX2(bits / 8, 1);
 404                 alu.writemask = (1 << bytes) - 1;
 405         } else {
 406                 unsigned comp_mask = instr->dest.write_mask;
 407
 408                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 409                                 comp_mask);
 410         }
 411
 412         /* We inline constants as we go. This tracks how many constants have
 413          * been inlined, since we're limited to 64-bits of constants per
 414          * instruction */
 415
 416         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 417         unsigned constants_left = (64 / dest_bits);
 418         unsigned constant_shift = 0;
 419
 420         /* Copy sources */
 421
 422         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 423         assert(num_inputs <= ARRAY_SIZE(alu.src));
 424
 425         for (unsigned i = 0; i < num_inputs; ++i) {
 426                 unsigned bits = nir_src_bit_size(instr->src[i].src);
 427                 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
 428                         | bits;
 429
 430                 /* Try to inline a constant */
 431                 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
 432                         alu.constant.u64 |=
 433                                 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
 434
 435                         alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
 436                         --constants_left;
 437                         constant_shift += dest_bits;
 438                         continue;
 439                 }
 440
 441                 alu.src[i] = bir_src_index(&instr->src[i].src);
 442
 443                 /* We assert scalarization above */
 444                 alu.swizzle[i][0] = instr->src[i].swizzle[0];
 445         }
 446
 447         /* Op-specific fixup */
 448         switch (instr->op) {
 449         case nir_op_fmul:
 450                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 451                 break;
 452         case nir_op_fsat:
 453                 alu.outmod = BIFROST_SAT; /* MOV */
 454                 break;
 455         case nir_op_fneg:
 456                 alu.src_neg[0] = true; /* MOV */
 457                 break;
 458         case nir_op_fabs:
 459                 alu.src_abs[0] = true; /* MOV */
 460                 break;
 461         case nir_op_fsub:
 462                 alu.src_neg[1] = true; /* ADD */
 463                 break;
 464         case nir_op_fmax:
 465         case nir_op_imax:
 466         case nir_op_umax:
 467                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 468                 break;
 469         case nir_op_frcp:
 470                 alu.op.special = BI_SPECIAL_FRCP;
 471                 break;
 472         case nir_op_frsq:
 473                 alu.op.special = BI_SPECIAL_FRSQ;
 474                 break;
 475         case nir_op_fsin:
 476                 alu.op.special = BI_SPECIAL_FSIN;
 477                 break;
 478         case nir_op_fcos:
 479                 alu.op.special = BI_SPECIAL_FCOS;
 480                 break;
 481         case nir_op_flt:
 482         case nir_op_ilt:
 483         case nir_op_fge:
 484         case nir_op_ige:
 485         case nir_op_feq:
 486         case nir_op_ieq:
 487         case nir_op_fne:
 488         case nir_op_ine:
 489                 alu.op.compare = bi_cond_for_nir(instr->op);
 490                 break;
 491         default:
 492                 break;
 493         }
 494
 495         bi_emit(ctx, alu);
 496 }
 497
 498 static void
 499 emit_instr(bi_context *ctx, struct nir_instr *instr)
 500 {
 501         switch (instr->type) {
 502         case nir_instr_type_load_const:
 503                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 504                 break;
 505
 506         case nir_instr_type_intrinsic:
 507                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 508                 break;
 509
 510         case nir_instr_type_alu:
 511                 emit_alu(ctx, nir_instr_as_alu(instr));
 512                 break;
 513
 514 #if 0
 515         case nir_instr_type_tex:
 516                 emit_tex(ctx, nir_instr_as_tex(instr));
 517                 break;
 518 #endif
 519
 520         case nir_instr_type_jump:
 521                 emit_jump(ctx, nir_instr_as_jump(instr));
 522                 break;
 523
 524         case nir_instr_type_ssa_undef:
 525                 /* Spurious */
 526                 break;
 527
 528         default:
 529                 //unreachable("Unhandled instruction type");
 530                 break;
 531         }
 532 }
 533
 534
 535
 536 static bi_block *
 537 create_empty_block(bi_context *ctx)
 538 {
 539         bi_block *blk = rzalloc(ctx, bi_block);
 540
 541         blk->base.predecessors = _mesa_set_create(blk,
 542                         _mesa_hash_pointer,
 543                         _mesa_key_pointer_equal);
 544
 545         blk->base.name = ctx->block_name_count++;
 546
 547         return blk;
 548 }
 549
 550 static void
 551 bi_schedule_barrier(bi_context *ctx)
 552 {
 553         bi_block *temp = ctx->after_block;
 554         ctx->after_block = create_empty_block(ctx);
 555         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 556         list_inithead(&ctx->after_block->base.instructions);
 557         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 558         ctx->current_block = ctx->after_block;
 559         ctx->after_block = temp;
 560 }
 561
 562 static bi_block *
 563 emit_block(bi_context *ctx, nir_block *block)
 564 {
 565         if (ctx->after_block) {
 566                 ctx->current_block = ctx->after_block;
 567                 ctx->after_block = NULL;
 568         } else {
 569                 ctx->current_block = create_empty_block(ctx);
 570         }
 571
 572         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 573         list_inithead(&ctx->current_block->base.instructions);
 574
 575         nir_foreach_instr(instr, block) {
 576                 emit_instr(ctx, instr);
 577                 ++ctx->instruction_count;
 578         }
 579
 580         return ctx->current_block;
 581 }
 582
 583 /* Emits an unconditional branch to the end of the current block, returning a
 584  * pointer so the user can fill in details */
 585
 586 static bi_instruction *
 587 bi_emit_branch(bi_context *ctx)
 588 {
 589         bi_instruction branch = {
 590                 .type = BI_BRANCH,
 591                 .branch = {
 592                         .cond = BI_COND_ALWAYS
 593                 }
 594         };
 595
 596         return bi_emit(ctx, branch);
 597 }
 598
 599 /* Sets a condition for a branch by examing the NIR condition. If we're
 600  * familiar with the condition, we unwrap it to fold it into the branch
 601  * instruction. Otherwise, we consume the condition directly. We
 602  * generally use 1-bit booleans which allows us to use small types for
 603  * the conditions.
 604  */
 605
 606 static void
 607 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 608 {
 609         /* TODO: Try to unwrap instead of always bailing */
 610         branch->src[0] = bir_src_index(cond);
 611         branch->src[1] = BIR_INDEX_ZERO;
 612         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 613         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 614 }
 615
 616 static void
 617 emit_if(bi_context *ctx, nir_if *nif)
 618 {
 619         bi_block *before_block = ctx->current_block;
 620
 621         /* Speculatively emit the branch, but we can't fill it in until later */
 622         bi_instruction *then_branch = bi_emit_branch(ctx);
 623         bi_set_branch_cond(then_branch, &nif->condition, true);
 624
 625         /* Emit the two subblocks. */
 626         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 627         bi_block *end_then_block = ctx->current_block;
 628
 629         /* Emit a jump from the end of the then block to the end of the else */
 630         bi_instruction *then_exit = bi_emit_branch(ctx);
 631
 632         /* Emit second block, and check if it's empty */
 633
 634         int count_in = ctx->instruction_count;
 635         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 636         bi_block *end_else_block = ctx->current_block;
 637         ctx->after_block = create_empty_block(ctx);
 638
 639         /* Now that we have the subblocks emitted, fix up the branches */
 640
 641         assert(then_block);
 642         assert(else_block);
 643
 644         if (ctx->instruction_count == count_in) {
 645                 /* The else block is empty, so don't emit an exit jump */
 646                 bi_remove_instruction(then_exit);
 647                 then_branch->branch.target = ctx->after_block;
 648         } else {
 649                 then_branch->branch.target = else_block;
 650                 then_exit->branch.target = ctx->after_block;
 651                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 652         }
 653
 654         /* Wire up the successors */
 655
 656         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 657
 658         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 659         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 660 }
 661
 662 static void
 663 emit_loop(bi_context *ctx, nir_loop *nloop)
 664 {
 665         /* Remember where we are */
 666         bi_block *start_block = ctx->current_block;
 667
 668         bi_block *saved_break = ctx->break_block;
 669         bi_block *saved_continue = ctx->continue_block;
 670
 671         ctx->continue_block = create_empty_block(ctx);
 672         ctx->break_block = create_empty_block(ctx);
 673         ctx->after_block = ctx->continue_block;
 674
 675         /* Emit the body itself */
 676         emit_cf_list(ctx, &nloop->body);
 677
 678         /* Branch back to loop back */
 679         bi_instruction *br_back = bi_emit_branch(ctx);
 680         br_back->branch.target = ctx->continue_block;
 681         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 682         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 683
 684         ctx->after_block = ctx->break_block;
 685
 686         /* Pop off */
 687         ctx->break_block = saved_break;
 688         ctx->continue_block = saved_continue;
 689         ++ctx->loop_count;
 690 }
 691
 692 static bi_block *
 693 emit_cf_list(bi_context *ctx, struct exec_list *list)
 694 {
 695         bi_block *start_block = NULL;
 696
 697         foreach_list_typed(nir_cf_node, node, node, list) {
 698                 switch (node->type) {
 699                 case nir_cf_node_block: {
 700                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 701
 702                         if (!start_block)
 703                                 start_block = block;
 704
 705                         break;
 706                 }
 707
 708                 case nir_cf_node_if:
 709                         emit_if(ctx, nir_cf_node_as_if(node));
 710                         break;
 711
 712                 case nir_cf_node_loop:
 713                         emit_loop(ctx, nir_cf_node_as_loop(node));
 714                         break;
 715
 716                 default:
 717                         unreachable("Unknown control flow");
 718                 }
 719         }
 720
 721         return start_block;
 722 }
 723
 724 static int
 725 glsl_type_size(const struct glsl_type *type, bool bindless)
 726 {
 727         return glsl_count_attribute_slots(type, false);
 728 }
 729
 730 static void
 731 bi_optimize_nir(nir_shader *nir)
 732 {
 733         bool progress;
 734         unsigned lower_flrp = 16 | 32 | 64;
 735
 736         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 737         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 738
 739         nir_lower_tex_options lower_tex_options = {
 740                 .lower_txs_lod = true,
 741                 .lower_txp = ~0,
 742                 .lower_tex_without_implicit_lod = true,
 743                 .lower_txd = true,
 744         };
 745
 746         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 747         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 748         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 749
 750         do {
 751                 progress = false;
 752
 753                 NIR_PASS(progress, nir, nir_lower_var_copies);
 754                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 755
 756                 NIR_PASS(progress, nir, nir_copy_prop);
 757                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 758                 NIR_PASS(progress, nir, nir_opt_dce);
 759                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 760                 NIR_PASS(progress, nir, nir_opt_cse);
 761                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 762                 NIR_PASS(progress, nir, nir_opt_algebraic);
 763                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 764
 765                 if (lower_flrp != 0) {
 766                         bool lower_flrp_progress = false;
 767                         NIR_PASS(lower_flrp_progress,
 768                                  nir,
 769                                  nir_lower_flrp,
 770                                  lower_flrp,
 771                                  false /* always_precise */,
 772                                  nir->options->lower_ffma);
 773                         if (lower_flrp_progress) {
 774                                 NIR_PASS(progress, nir,
 775                                          nir_opt_constant_folding);
 776                                 progress = true;
 777                         }
 778
 779                         /* Nothing should rematerialize any flrps, so we only
 780                          * need to do this lowering once.
 781                          */
 782                         lower_flrp = 0;
 783                 }
 784
 785                 NIR_PASS(progress, nir, nir_opt_undef);
 786                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 787                          nir_var_shader_in |
 788                          nir_var_shader_out |
 789                          nir_var_function_temp);
 790         } while (progress);
 791
 792         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 793         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 794         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 795         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 796
 797         /* Take us out of SSA */
 798         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 799         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 800
 801         /* We're a primary scalar architecture but there's enough vector that
 802          * we use a vector IR so let's not also deal with scalar hacks on top
 803          * of the vector hacks */
 804
 805         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 806         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 807         NIR_PASS(progress, nir, nir_opt_dce);
 808 }
 809
 810 void
 811 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 812 {
 813         bi_context *ctx = rzalloc(NULL, bi_context);
 814         ctx->nir = nir;
 815         ctx->stage = nir->info.stage;
 816         ctx->quirks = bifrost_get_quirks(product_id);
 817         list_inithead(&ctx->blocks);
 818
 819         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 820          * (so we don't accidentally duplicate the epilogue since mesa/st has
 821          * messed with our I/O quite a bit already) */
 822
 823         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 824
 825         if (ctx->stage == MESA_SHADER_VERTEX) {
 826                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 827                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 828         }
 829
 830         NIR_PASS_V(nir, nir_split_var_copies);
 831         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 832         NIR_PASS_V(nir, nir_lower_var_copies);
 833         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 834         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 835         NIR_PASS_V(nir, nir_lower_ssbo);
 836
 837         bi_optimize_nir(nir);
 838         nir_print_shader(nir, stdout);
 839
 840         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 841         program->sysval_count = ctx->sysvals.sysval_count;
 842         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 843
 844         nir_foreach_function(func, nir) {
 845                 if (!func->impl)
 846                         continue;
 847
 848                 ctx->impl = func->impl;
 849                 emit_cf_list(ctx, &func->impl->body);
 850                 break; /* TODO: Multi-function shaders */
 851         }
 852
 853         bool progress = false;
 854
 855         do {
 856                 progress = false;
 857
 858                 bi_foreach_block(ctx, _block) {
 859                         bi_block *block = (bi_block *) _block;
 860                         progress |= bi_opt_dead_code_eliminate(ctx, block);
 861                 }
 862         } while(progress);
 863
 864         bi_print_shader(ctx, stdout);
 865         bi_schedule(ctx);
 866
 867         ralloc_free(ctx);
 868 }