src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static void
 171 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
 174         address.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 175         address.src[2] = BIR_INDEX_REGISTER | 62;
 176         address.src[3] = 0;
 177         address.src_types[1] = nir_type_uint32;
 178         address.src_types[2] = nir_type_uint32;
 179         address.src_types[3] = nir_intrinsic_type(instr);
 180         address.dest = bi_make_temp(ctx);
 181         address.dest_type = nir_type_uint64;
 182         address.writemask = (1 << 8) - 1;
 183
 184         bi_instruction st = {
 185                 .type = BI_STORE_VAR,
 186                 .src = {
 187                         address.dest,
 188                         bir_src_index(&instr->src[0])
 189                 },
 190                 .src_types = {
 191                         nir_type_uint64,
 192                         nir_type_uint32
 193                 },
 194                 .swizzle = {
 195                         { 0 },
 196                         { 0, 1, 2, 3 }
 197                 }
 198         };
 199
 200         bi_emit(ctx, address);
 201         bi_emit(ctx, st);
 202 }
 203
 204 static void
 205 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 206 {
 207         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 208         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 209
 210         /* TODO: Indirect access, since we need to multiply by the element
 211          * size. I believe we can get this lowering automatically via
 212          * nir_lower_io (as mul instructions) with the proper options, but this
 213          * is TODO */
 214         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 215         ld.constant.u64 += ctx->sysvals.sysval_count;
 216         ld.constant.u64 *= 16;
 217
 218         bi_emit(ctx, ld);
 219 }
 220
 221 static void
 222 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 223                 unsigned nr_components, unsigned offset)
 224 {
 225         nir_dest nir_dest;
 226
 227         /* Figure out which uniform this is */
 228         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 229         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 230
 231         /* Sysvals are prefix uniforms */
 232         unsigned uniform = ((uintptr_t) val) - 1;
 233
 234         /* Emit the read itself -- this is never indirect */
 235
 236         bi_instruction load = {
 237                 .type = BI_LOAD_UNIFORM,
 238                 .writemask = (1 << (nr_components * 4)) - 1,
 239                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 240                 .constant = { (uniform * 16) + offset },
 241                 .dest = bir_dest_index(&nir_dest),
 242                 .dest_type = nir_type_uint32, /* TODO */
 243         };
 244
 245         bi_emit(ctx, load);
 246 }
 247
 248 static void
 249 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 250 {
 251
 252         switch (instr->intrinsic) {
 253         case nir_intrinsic_load_barycentric_pixel:
 254                 /* stub */
 255                 break;
 256         case nir_intrinsic_load_interpolated_input:
 257         case nir_intrinsic_load_input:
 258                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 259                         bi_emit_ld_vary(ctx, instr);
 260                 else if (ctx->stage == MESA_SHADER_VERTEX)
 261                         bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
 262                 else {
 263                         unreachable("Unsupported shader stage");
 264                 }
 265                 break;
 266
 267         case nir_intrinsic_store_output:
 268                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 269                         bi_emit_frag_out(ctx, instr);
 270                 else if (ctx->stage == MESA_SHADER_VERTEX)
 271                         bi_emit_st_vary(ctx, instr);
 272                 else
 273                         unreachable("Unsupported shader stage");
 274                 break;
 275
 276         case nir_intrinsic_load_uniform:
 277                 bi_emit_ld_uniform(ctx, instr);
 278                 break;
 279
 280         case nir_intrinsic_load_ssbo_address:
 281                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 282                 break;
 283
 284         case nir_intrinsic_get_buffer_size:
 285                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 286                 break;
 287
 288         case nir_intrinsic_load_viewport_scale:
 289         case nir_intrinsic_load_viewport_offset:
 290         case nir_intrinsic_load_num_work_groups:
 291         case nir_intrinsic_load_sampler_lod_parameters_pan:
 292                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 293                 break;
 294
 295         default:
 296                 /* todo */
 297                 break;
 298         }
 299 }
 300
 301 static void
 302 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 303 {
 304         /* Make sure we've been lowered */
 305         assert(instr->def.num_components == 1);
 306
 307         bi_instruction move = {
 308                 .type = BI_MOV,
 309                 .dest = bir_ssa_index(&instr->def),
 310                 .dest_type = instr->def.bit_size | nir_type_uint,
 311                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 312                 .src = {
 313                         BIR_INDEX_CONSTANT
 314                 },
 315                 .constant = {
 316                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 317                 }
 318         };
 319
 320         bi_emit(ctx, move);
 321 }
 322
 323 static enum bi_class
 324 bi_class_for_nir_alu(nir_op op)
 325 {
 326         switch (op) {
 327         case nir_op_iadd:
 328         case nir_op_fadd:
 329         case nir_op_fsub:
 330                 return BI_ADD;
 331         case nir_op_isub:
 332                 return BI_ISUB;
 333
 334         case nir_op_flt:
 335         case nir_op_fge:
 336         case nir_op_feq:
 337         case nir_op_fne:
 338         case nir_op_ilt:
 339         case nir_op_ige:
 340         case nir_op_ieq:
 341         case nir_op_ine:
 342                 return BI_CMP;
 343
 344         case nir_op_bcsel:
 345                 return BI_CSEL;
 346
 347         case nir_op_i2i8:
 348         case nir_op_i2i16:
 349         case nir_op_i2i32:
 350         case nir_op_i2i64:
 351         case nir_op_u2u8:
 352         case nir_op_u2u16:
 353         case nir_op_u2u32:
 354         case nir_op_u2u64:
 355         case nir_op_f2i16:
 356         case nir_op_f2i32:
 357         case nir_op_f2i64:
 358         case nir_op_f2u16:
 359         case nir_op_f2u32:
 360         case nir_op_f2u64:
 361         case nir_op_i2f16:
 362         case nir_op_i2f32:
 363         case nir_op_i2f64:
 364         case nir_op_u2f16:
 365         case nir_op_u2f32:
 366         case nir_op_u2f64:
 367                 return BI_CONVERT;
 368
 369         case nir_op_ffma:
 370         case nir_op_fmul:
 371                 return BI_FMA;
 372
 373         case nir_op_imin:
 374         case nir_op_imax:
 375         case nir_op_umin:
 376         case nir_op_umax:
 377         case nir_op_fmin:
 378         case nir_op_fmax:
 379                 return BI_MINMAX;
 380
 381         case nir_op_fsat:
 382         case nir_op_fneg:
 383         case nir_op_fabs:
 384                 return BI_FMOV;
 385         case nir_op_mov:
 386                 return BI_MOV;
 387
 388         case nir_op_frcp:
 389         case nir_op_frsq:
 390         case nir_op_fsin:
 391         case nir_op_fcos:
 392                 return BI_SPECIAL;
 393
 394         default:
 395                 unreachable("Unknown ALU op");
 396         }
 397 }
 398
 399 static enum bi_cond
 400 bi_cond_for_nir(nir_op op)
 401 {
 402         switch (op) {
 403         case nir_op_flt:
 404         case nir_op_ilt:
 405                 return BI_COND_LT;
 406         case nir_op_fge:
 407         case nir_op_ige:
 408                 return BI_COND_GE;
 409         case nir_op_feq:
 410         case nir_op_ieq:
 411                 return BI_COND_EQ;
 412         case nir_op_fne:
 413         case nir_op_ine:
 414                 return BI_COND_NE;
 415         default:
 416                 unreachable("Invalid compare");
 417         }
 418 }
 419
 420 static void
 421 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 422 {
 423         /* Assume it's something we can handle normally */
 424         bi_instruction alu = {
 425                 .type = bi_class_for_nir_alu(instr->op),
 426                 .dest = bir_dest_index(&instr->dest.dest),
 427                 .dest_type = nir_op_infos[instr->op].output_type
 428                         | nir_dest_bit_size(instr->dest.dest),
 429         };
 430
 431         /* TODO: Implement lowering of special functions for older Bifrost */
 432         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 433
 434         if (instr->dest.dest.is_ssa) {
 435                 /* Construct a writemask */
 436                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 437                 unsigned comps = instr->dest.dest.ssa.num_components;
 438                 assert(comps == 1);
 439                 unsigned bits = bits_per_comp * comps;
 440                 unsigned bytes = MAX2(bits / 8, 1);
 441                 alu.writemask = (1 << bytes) - 1;
 442         } else {
 443                 unsigned comp_mask = instr->dest.write_mask;
 444
 445                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 446                                 comp_mask);
 447         }
 448
 449         /* We inline constants as we go. This tracks how many constants have
 450          * been inlined, since we're limited to 64-bits of constants per
 451          * instruction */
 452
 453         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 454         unsigned constants_left = (64 / dest_bits);
 455         unsigned constant_shift = 0;
 456
 457         /* Copy sources */
 458
 459         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 460         assert(num_inputs <= ARRAY_SIZE(alu.src));
 461
 462         for (unsigned i = 0; i < num_inputs; ++i) {
 463                 unsigned bits = nir_src_bit_size(instr->src[i].src);
 464                 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
 465                         | bits;
 466
 467                 /* Try to inline a constant */
 468                 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
 469                         alu.constant.u64 |=
 470                                 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
 471
 472                         alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
 473                         --constants_left;
 474                         constant_shift += dest_bits;
 475                         continue;
 476                 }
 477
 478                 alu.src[i] = bir_src_index(&instr->src[i].src);
 479
 480                 /* We assert scalarization above */
 481                 alu.swizzle[i][0] = instr->src[i].swizzle[0];
 482         }
 483
 484         /* Op-specific fixup */
 485         switch (instr->op) {
 486         case nir_op_fmul:
 487                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 488                 break;
 489         case nir_op_fsat:
 490                 alu.outmod = BIFROST_SAT; /* FMOV */
 491                 break;
 492         case nir_op_fneg:
 493                 alu.src_neg[0] = true; /* FMOV */
 494                 break;
 495         case nir_op_fabs:
 496                 alu.src_abs[0] = true; /* FMOV */
 497                 break;
 498         case nir_op_fsub:
 499                 alu.src_neg[1] = true; /* FADD */
 500                 break;
 501         case nir_op_fmax:
 502         case nir_op_imax:
 503         case nir_op_umax:
 504                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 505                 break;
 506         case nir_op_frcp:
 507                 alu.op.special = BI_SPECIAL_FRCP;
 508                 break;
 509         case nir_op_frsq:
 510                 alu.op.special = BI_SPECIAL_FRSQ;
 511                 break;
 512         case nir_op_fsin:
 513                 alu.op.special = BI_SPECIAL_FSIN;
 514                 break;
 515         case nir_op_fcos:
 516                 alu.op.special = BI_SPECIAL_FCOS;
 517                 break;
 518         case nir_op_flt:
 519         case nir_op_ilt:
 520         case nir_op_fge:
 521         case nir_op_ige:
 522         case nir_op_feq:
 523         case nir_op_ieq:
 524         case nir_op_fne:
 525         case nir_op_ine:
 526                 alu.op.compare = bi_cond_for_nir(instr->op);
 527                 break;
 528         default:
 529                 break;
 530         }
 531
 532         bi_emit(ctx, alu);
 533 }
 534
 535 static void
 536 emit_instr(bi_context *ctx, struct nir_instr *instr)
 537 {
 538         switch (instr->type) {
 539         case nir_instr_type_load_const:
 540                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 541                 break;
 542
 543         case nir_instr_type_intrinsic:
 544                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 545                 break;
 546
 547         case nir_instr_type_alu:
 548                 emit_alu(ctx, nir_instr_as_alu(instr));
 549                 break;
 550
 551 #if 0
 552         case nir_instr_type_tex:
 553                 emit_tex(ctx, nir_instr_as_tex(instr));
 554                 break;
 555 #endif
 556
 557         case nir_instr_type_jump:
 558                 emit_jump(ctx, nir_instr_as_jump(instr));
 559                 break;
 560
 561         case nir_instr_type_ssa_undef:
 562                 /* Spurious */
 563                 break;
 564
 565         default:
 566                 //unreachable("Unhandled instruction type");
 567                 break;
 568         }
 569 }
 570
 571
 572
 573 static bi_block *
 574 create_empty_block(bi_context *ctx)
 575 {
 576         bi_block *blk = rzalloc(ctx, bi_block);
 577
 578         blk->base.predecessors = _mesa_set_create(blk,
 579                         _mesa_hash_pointer,
 580                         _mesa_key_pointer_equal);
 581
 582         blk->base.name = ctx->block_name_count++;
 583
 584         return blk;
 585 }
 586
 587 static void
 588 bi_schedule_barrier(bi_context *ctx)
 589 {
 590         bi_block *temp = ctx->after_block;
 591         ctx->after_block = create_empty_block(ctx);
 592         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 593         list_inithead(&ctx->after_block->base.instructions);
 594         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 595         ctx->current_block = ctx->after_block;
 596         ctx->after_block = temp;
 597 }
 598
 599 static bi_block *
 600 emit_block(bi_context *ctx, nir_block *block)
 601 {
 602         if (ctx->after_block) {
 603                 ctx->current_block = ctx->after_block;
 604                 ctx->after_block = NULL;
 605         } else {
 606                 ctx->current_block = create_empty_block(ctx);
 607         }
 608
 609         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 610         list_inithead(&ctx->current_block->base.instructions);
 611
 612         nir_foreach_instr(instr, block) {
 613                 emit_instr(ctx, instr);
 614                 ++ctx->instruction_count;
 615         }
 616
 617         return ctx->current_block;
 618 }
 619
 620 /* Emits an unconditional branch to the end of the current block, returning a
 621  * pointer so the user can fill in details */
 622
 623 static bi_instruction *
 624 bi_emit_branch(bi_context *ctx)
 625 {
 626         bi_instruction branch = {
 627                 .type = BI_BRANCH,
 628                 .branch = {
 629                         .cond = BI_COND_ALWAYS
 630                 }
 631         };
 632
 633         return bi_emit(ctx, branch);
 634 }
 635
 636 /* Sets a condition for a branch by examing the NIR condition. If we're
 637  * familiar with the condition, we unwrap it to fold it into the branch
 638  * instruction. Otherwise, we consume the condition directly. We
 639  * generally use 1-bit booleans which allows us to use small types for
 640  * the conditions.
 641  */
 642
 643 static void
 644 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 645 {
 646         /* TODO: Try to unwrap instead of always bailing */
 647         branch->src[0] = bir_src_index(cond);
 648         branch->src[1] = BIR_INDEX_ZERO;
 649         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 650         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 651 }
 652
 653 static void
 654 emit_if(bi_context *ctx, nir_if *nif)
 655 {
 656         bi_block *before_block = ctx->current_block;
 657
 658         /* Speculatively emit the branch, but we can't fill it in until later */
 659         bi_instruction *then_branch = bi_emit_branch(ctx);
 660         bi_set_branch_cond(then_branch, &nif->condition, true);
 661
 662         /* Emit the two subblocks. */
 663         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 664         bi_block *end_then_block = ctx->current_block;
 665
 666         /* Emit a jump from the end of the then block to the end of the else */
 667         bi_instruction *then_exit = bi_emit_branch(ctx);
 668
 669         /* Emit second block, and check if it's empty */
 670
 671         int count_in = ctx->instruction_count;
 672         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 673         bi_block *end_else_block = ctx->current_block;
 674         ctx->after_block = create_empty_block(ctx);
 675
 676         /* Now that we have the subblocks emitted, fix up the branches */
 677
 678         assert(then_block);
 679         assert(else_block);
 680
 681         if (ctx->instruction_count == count_in) {
 682                 /* The else block is empty, so don't emit an exit jump */
 683                 bi_remove_instruction(then_exit);
 684                 then_branch->branch.target = ctx->after_block;
 685         } else {
 686                 then_branch->branch.target = else_block;
 687                 then_exit->branch.target = ctx->after_block;
 688                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 689         }
 690
 691         /* Wire up the successors */
 692
 693         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 694
 695         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 696         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 697 }
 698
 699 static void
 700 emit_loop(bi_context *ctx, nir_loop *nloop)
 701 {
 702         /* Remember where we are */
 703         bi_block *start_block = ctx->current_block;
 704
 705         bi_block *saved_break = ctx->break_block;
 706         bi_block *saved_continue = ctx->continue_block;
 707
 708         ctx->continue_block = create_empty_block(ctx);
 709         ctx->break_block = create_empty_block(ctx);
 710         ctx->after_block = ctx->continue_block;
 711
 712         /* Emit the body itself */
 713         emit_cf_list(ctx, &nloop->body);
 714
 715         /* Branch back to loop back */
 716         bi_instruction *br_back = bi_emit_branch(ctx);
 717         br_back->branch.target = ctx->continue_block;
 718         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 719         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 720
 721         ctx->after_block = ctx->break_block;
 722
 723         /* Pop off */
 724         ctx->break_block = saved_break;
 725         ctx->continue_block = saved_continue;
 726         ++ctx->loop_count;
 727 }
 728
 729 static bi_block *
 730 emit_cf_list(bi_context *ctx, struct exec_list *list)
 731 {
 732         bi_block *start_block = NULL;
 733
 734         foreach_list_typed(nir_cf_node, node, node, list) {
 735                 switch (node->type) {
 736                 case nir_cf_node_block: {
 737                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 738
 739                         if (!start_block)
 740                                 start_block = block;
 741
 742                         break;
 743                 }
 744
 745                 case nir_cf_node_if:
 746                         emit_if(ctx, nir_cf_node_as_if(node));
 747                         break;
 748
 749                 case nir_cf_node_loop:
 750                         emit_loop(ctx, nir_cf_node_as_loop(node));
 751                         break;
 752
 753                 default:
 754                         unreachable("Unknown control flow");
 755                 }
 756         }
 757
 758         return start_block;
 759 }
 760
 761 static int
 762 glsl_type_size(const struct glsl_type *type, bool bindless)
 763 {
 764         return glsl_count_attribute_slots(type, false);
 765 }
 766
 767 static void
 768 bi_optimize_nir(nir_shader *nir)
 769 {
 770         bool progress;
 771         unsigned lower_flrp = 16 | 32 | 64;
 772
 773         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 774         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 775
 776         nir_lower_tex_options lower_tex_options = {
 777                 .lower_txs_lod = true,
 778                 .lower_txp = ~0,
 779                 .lower_tex_without_implicit_lod = true,
 780                 .lower_txd = true,
 781         };
 782
 783         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 784         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 785         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 786
 787         do {
 788                 progress = false;
 789
 790                 NIR_PASS(progress, nir, nir_lower_var_copies);
 791                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 792
 793                 NIR_PASS(progress, nir, nir_copy_prop);
 794                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 795                 NIR_PASS(progress, nir, nir_opt_dce);
 796                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 797                 NIR_PASS(progress, nir, nir_opt_cse);
 798                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 799                 NIR_PASS(progress, nir, nir_opt_algebraic);
 800                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 801
 802                 if (lower_flrp != 0) {
 803                         bool lower_flrp_progress = false;
 804                         NIR_PASS(lower_flrp_progress,
 805                                  nir,
 806                                  nir_lower_flrp,
 807                                  lower_flrp,
 808                                  false /* always_precise */,
 809                                  nir->options->lower_ffma);
 810                         if (lower_flrp_progress) {
 811                                 NIR_PASS(progress, nir,
 812                                          nir_opt_constant_folding);
 813                                 progress = true;
 814                         }
 815
 816                         /* Nothing should rematerialize any flrps, so we only
 817                          * need to do this lowering once.
 818                          */
 819                         lower_flrp = 0;
 820                 }
 821
 822                 NIR_PASS(progress, nir, nir_opt_undef);
 823                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 824                          nir_var_shader_in |
 825                          nir_var_shader_out |
 826                          nir_var_function_temp);
 827         } while (progress);
 828
 829         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 830         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 831         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 832         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 833
 834         /* Take us out of SSA */
 835         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 836         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 837
 838         /* We're a primary scalar architecture but there's enough vector that
 839          * we use a vector IR so let's not also deal with scalar hacks on top
 840          * of the vector hacks */
 841
 842         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 843         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 844         NIR_PASS(progress, nir, nir_opt_dce);
 845 }
 846
 847 static void
 848 bi_insert_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp)
 849 {
 850         bi_instruction move = {
 851                 .type = BI_MOV,
 852                 .dest = parent->dest,
 853                 .dest_type = nir_type_uint32,
 854                 .writemask = (0xF << (4 * comp)),
 855                 .src = { parent->src[0] },
 856                 .src_types = { nir_type_uint32 },
 857                 .swizzle = { { comp } }
 858         };
 859
 860         bi_emit_before(ctx, parent, move);
 861 }
 862
 863 static void
 864 bi_lower_mov(bi_context *ctx, bi_block *block)
 865 {
 866         bi_foreach_instr_in_block_safe(block, ins) {
 867                 if (ins->type != BI_MOV) continue;
 868                 if (util_bitcount(ins->writemask) <= 4) continue;
 869
 870                 for (unsigned i = 0; i < 4; ++i) {
 871                         unsigned quad = (ins->writemask >> (4 * i)) & 0xF;
 872
 873                         if (quad == 0)
 874                                 continue;
 875                         else if (quad == 0xF)
 876                                 bi_insert_mov32(ctx, ins, i);
 877                         else
 878                                 unreachable("TODO: Lowering <32bit moves");
 879                 }
 880
 881                 bi_remove_instruction(ins);
 882         }
 883 }
 884
 885 void
 886 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 887 {
 888         bi_context *ctx = rzalloc(NULL, bi_context);
 889         ctx->nir = nir;
 890         ctx->stage = nir->info.stage;
 891         ctx->quirks = bifrost_get_quirks(product_id);
 892         list_inithead(&ctx->blocks);
 893
 894         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 895          * (so we don't accidentally duplicate the epilogue since mesa/st has
 896          * messed with our I/O quite a bit already) */
 897
 898         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 899
 900         if (ctx->stage == MESA_SHADER_VERTEX) {
 901                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 902                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 903         }
 904
 905         NIR_PASS_V(nir, nir_split_var_copies);
 906         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 907         NIR_PASS_V(nir, nir_lower_var_copies);
 908         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 909         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 910         NIR_PASS_V(nir, nir_lower_ssbo);
 911
 912         bi_optimize_nir(nir);
 913         nir_print_shader(nir, stdout);
 914
 915         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 916         program->sysval_count = ctx->sysvals.sysval_count;
 917         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 918
 919         nir_foreach_function(func, nir) {
 920                 if (!func->impl)
 921                         continue;
 922
 923                 ctx->impl = func->impl;
 924                 emit_cf_list(ctx, &func->impl->body);
 925                 break; /* TODO: Multi-function shaders */
 926         }
 927
 928         bi_foreach_block(ctx, _block) {
 929                 bi_block *block = (bi_block *) _block;
 930                 bi_lower_mov(ctx, block);
 931         }
 932
 933         bool progress = false;
 934
 935         do {
 936                 progress = false;
 937
 938                 bi_foreach_block(ctx, _block) {
 939                         bi_block *block = (bi_block *) _block;
 940                         progress |= bi_opt_dead_code_eliminate(ctx, block);
 941                 }
 942         } while(progress);
 943
 944         bi_print_shader(ctx, stdout);
 945         bi_schedule(ctx);
 946         bi_register_allocate(ctx);
 947         bi_print_shader(ctx, stdout);
 948         bi_pack(ctx, &program->compiled);
 949         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
 950
 951         ralloc_free(ctx);
 952 }