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pan/bi: Handle discard_if in NIR->BIR naively
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
36 #include "compiler.h"
37 #include "bi_quirks.h"
38 #include "bi_print.h"
39
40 static const struct debug_named_value debug_options[] = {
41 {"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
43 DEBUG_NAMED_VALUE_END
44 };
45
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", debug_options, 0)
47
48 int bifrost_debug = 0;
49
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
54
55 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
56 static bi_instruction *bi_emit_branch(bi_context *ctx);
57 static void bi_schedule_barrier(bi_context *ctx);
58
59 static void
60 emit_jump(bi_context *ctx, nir_jump_instr *instr)
61 {
62 bi_instruction *branch = bi_emit_branch(ctx);
63
64 switch (instr->type) {
65 case nir_jump_break:
66 branch->branch_target = ctx->break_block;
67 break;
68 case nir_jump_continue:
69 branch->branch_target = ctx->continue_block;
70 break;
71 default:
72 unreachable("Unhandled jump type");
73 }
74
75 pan_block_add_successor(&ctx->current_block->base, &branch->branch_target->base);
76 }
77
78 static bi_instruction
79 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
80 {
81 bi_instruction load = {
82 .type = T,
83 .vector_channels = instr->num_components,
84 .src = { BIR_INDEX_CONSTANT },
85 .src_types = { nir_type_uint32 },
86 .constant = { .u64 = nir_intrinsic_base(instr) },
87 };
88
89 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
90
91 if (info->has_dest)
92 load.dest = pan_dest_index(&instr->dest);
93
94 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
95 load.dest_type = nir_intrinsic_type(instr);
96
97 nir_src *offset = nir_get_io_offset_src(instr);
98
99 if (nir_src_is_const(*offset))
100 load.constant.u64 += nir_src_as_uint(*offset);
101 else
102 load.src[0] = pan_src_index(offset);
103
104 return load;
105 }
106
107 static void
108 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
109 {
110 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
111 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
112 ins.load_vary.reuse = false; /* TODO */
113 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
114 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
115
116 if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
117 /* Zero it out for direct */
118 ins.src[1] = BIR_INDEX_ZERO;
119 } else {
120 /* R61 contains sample mask stuff, TODO RA XXX */
121 ins.src[1] = BIR_INDEX_REGISTER | 61;
122 }
123
124 bi_emit(ctx, ins);
125 }
126
127 static void
128 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
129 {
130 if (!ctx->emitted_atest) {
131 bi_instruction ins = {
132 .type = BI_ATEST,
133 .src = {
134 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
135 pan_src_index(&instr->src[0])
136 },
137 .src_types = {
138 nir_type_uint32,
139 nir_intrinsic_type(instr)
140 },
141 .swizzle = {
142 { 0 },
143 { 3, 0 } /* swizzle out the alpha */
144 },
145 .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
146 .dest_type = nir_type_uint32,
147 };
148
149 bi_emit(ctx, ins);
150 bi_schedule_barrier(ctx);
151 ctx->emitted_atest = true;
152 }
153
154 bi_instruction blend = {
155 .type = BI_BLEND,
156 .blend_location = nir_intrinsic_base(instr),
157 .src = {
158 pan_src_index(&instr->src[0]),
159 BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
160 },
161 .src_types = {
162 nir_intrinsic_type(instr),
163 nir_type_uint32
164 },
165 .swizzle = {
166 { 0, 1, 2, 3 },
167 { 0 }
168 },
169 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
170 .dest_type = nir_type_uint32,
171 .vector_channels = 4
172 };
173
174 assert(blend.blend_location < BIFROST_MAX_RENDER_TARGET_COUNT);
175 assert(ctx->blend_types);
176 assert(blend.src_types[0]);
177 ctx->blend_types[blend.blend_location] = blend.src_types[0];
178
179 bi_emit(ctx, blend);
180 bi_schedule_barrier(ctx);
181 }
182
183 static bi_instruction
184 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
185 {
186 bi_instruction ld = bi_load(T, instr);
187 ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
188 ld.src[2] = BIR_INDEX_REGISTER | 62;
189 ld.src[3] = 0;
190 ld.src_types[1] = nir_type_uint32;
191 ld.src_types[2] = nir_type_uint32;
192 ld.src_types[3] = nir_intrinsic_type(instr);
193 return ld;
194 }
195
196 static void
197 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
198 {
199 bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
200 address.dest = bi_make_temp(ctx);
201 address.dest_type = nir_type_uint32;
202 address.vector_channels = 3;
203
204 unsigned nr = nir_intrinsic_src_components(instr, 0);
205 assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
206
207 bi_instruction st = {
208 .type = BI_STORE_VAR,
209 .src = {
210 pan_src_index(&instr->src[0]),
211 address.dest, address.dest, address.dest,
212 },
213 .src_types = {
214 nir_type_uint32,
215 nir_type_uint32, nir_type_uint32, nir_type_uint32,
216 },
217 .swizzle = {
218 { 0 },
219 { 0 }, { 1 }, { 2}
220 },
221 .vector_channels = nr,
222 };
223
224 for (unsigned i = 0; i < nr; ++i)
225 st.swizzle[0][i] = i;
226
227 bi_emit(ctx, address);
228 bi_emit(ctx, st);
229 }
230
231 static void
232 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
233 {
234 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
235 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
236
237 /* TODO: Indirect access, since we need to multiply by the element
238 * size. I believe we can get this lowering automatically via
239 * nir_lower_io (as mul instructions) with the proper options, but this
240 * is TODO */
241 assert(ld.src[0] & BIR_INDEX_CONSTANT);
242 ld.constant.u64 += ctx->sysvals.sysval_count;
243 ld.constant.u64 *= 16;
244
245 bi_emit(ctx, ld);
246 }
247
248 static void
249 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
250 unsigned nr_components, unsigned offset)
251 {
252 nir_dest nir_dest;
253
254 /* Figure out which uniform this is */
255 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
256 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
257
258 /* Sysvals are prefix uniforms */
259 unsigned uniform = ((uintptr_t) val) - 1;
260
261 /* Emit the read itself -- this is never indirect */
262
263 bi_instruction load = {
264 .type = BI_LOAD_UNIFORM,
265 .vector_channels = nr_components,
266 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
267 .src_types = { nir_type_uint32, nir_type_uint32 },
268 .constant = { (uniform * 16) + offset },
269 .dest = pan_dest_index(&nir_dest),
270 .dest_type = nir_type_uint32, /* TODO */
271 };
272
273 bi_emit(ctx, load);
274 }
275
276 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
277 * gl_FragCoord.z = ld_vary(fragz)
278 * gl_FragCoord.w = ld_vary(fragw)
279 */
280
281 static void
282 bi_emit_ld_frag_coord(bi_context *ctx, nir_intrinsic_instr *instr)
283 {
284 /* Future proofing for mediump fragcoord at some point.. */
285 nir_alu_type T = nir_type_float32;
286
287 /* First, sketch a combine */
288 bi_instruction combine = {
289 .type = BI_COMBINE,
290 .dest_type = nir_type_uint32,
291 .dest = pan_dest_index(&instr->dest),
292 .src_types = { T, T, T, T },
293 };
294
295 /* Second, handle xy */
296 for (unsigned i = 0; i < 2; ++i) {
297 bi_instruction conv = {
298 .type = BI_CONVERT,
299 .dest_type = T,
300 .dest = bi_make_temp(ctx),
301 .src = {
302 /* TODO: RA XXX */
303 BIR_INDEX_REGISTER | 59
304 },
305 .src_types = { nir_type_uint16 },
306 .swizzle = { { i } }
307 };
308
309 bi_instruction add = {
310 .type = BI_ADD,
311 .dest_type = T,
312 .dest = bi_make_temp(ctx),
313 .src = { conv.dest, BIR_INDEX_CONSTANT },
314 .src_types = { T, T },
315 };
316
317 float half = 0.5;
318 memcpy(&add.constant.u32, &half, sizeof(float));
319
320 bi_emit(ctx, conv);
321 bi_emit(ctx, add);
322
323 combine.src[i] = add.dest;
324 }
325
326 /* Third, zw */
327 for (unsigned i = 0; i < 2; ++i) {
328 bi_instruction load = {
329 .type = BI_LOAD_VAR,
330 .load_vary = {
331 .interp_mode = BIFROST_INTERP_DEFAULT,
332 .reuse = false,
333 .flat = true
334 },
335 .vector_channels = 1,
336 .dest_type = nir_type_float32,
337 .dest = bi_make_temp(ctx),
338 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
339 .src_types = { nir_type_uint32, nir_type_uint32 },
340 .constant = {
341 .u32 = (i == 0) ? BIFROST_FRAGZ : BIFROST_FRAGW
342 }
343 };
344
345 bi_emit(ctx, load);
346
347 combine.src[i + 2] = load.dest;
348 }
349
350 /* Finally, emit the combine */
351 bi_emit(ctx, combine);
352 }
353
354 static void
355 bi_emit_discard_if(bi_context *ctx, nir_intrinsic_instr *instr)
356 {
357 nir_src cond = instr->src[0];
358 nir_alu_type T = nir_type_uint | nir_src_bit_size(cond);
359
360 bi_instruction discard = {
361 .type = BI_DISCARD,
362 .cond = BI_COND_NE,
363 .src_types = { T, T },
364 .src = {
365 pan_src_index(&cond),
366 BIR_INDEX_ZERO
367 },
368 };
369
370 bi_emit(ctx, discard);
371 }
372
373 static void
374 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
375 {
376
377 switch (instr->intrinsic) {
378 case nir_intrinsic_load_barycentric_pixel:
379 /* stub */
380 break;
381 case nir_intrinsic_load_interpolated_input:
382 case nir_intrinsic_load_input:
383 if (ctx->stage == MESA_SHADER_FRAGMENT)
384 bi_emit_ld_vary(ctx, instr);
385 else if (ctx->stage == MESA_SHADER_VERTEX)
386 bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
387 else {
388 unreachable("Unsupported shader stage");
389 }
390 break;
391
392 case nir_intrinsic_store_output:
393 if (ctx->stage == MESA_SHADER_FRAGMENT)
394 bi_emit_frag_out(ctx, instr);
395 else if (ctx->stage == MESA_SHADER_VERTEX)
396 bi_emit_st_vary(ctx, instr);
397 else
398 unreachable("Unsupported shader stage");
399 break;
400
401 case nir_intrinsic_load_uniform:
402 bi_emit_ld_uniform(ctx, instr);
403 break;
404
405 case nir_intrinsic_load_frag_coord:
406 bi_emit_ld_frag_coord(ctx, instr);
407 break;
408
409 case nir_intrinsic_discard_if:
410 bi_emit_discard_if(ctx, instr);
411 break;
412
413 case nir_intrinsic_load_ssbo_address:
414 bi_emit_sysval(ctx, &instr->instr, 1, 0);
415 break;
416
417 case nir_intrinsic_get_buffer_size:
418 bi_emit_sysval(ctx, &instr->instr, 1, 8);
419 break;
420
421 case nir_intrinsic_load_viewport_scale:
422 case nir_intrinsic_load_viewport_offset:
423 case nir_intrinsic_load_num_work_groups:
424 case nir_intrinsic_load_sampler_lod_parameters_pan:
425 bi_emit_sysval(ctx, &instr->instr, 3, 0);
426 break;
427
428 default:
429 unreachable("Unknown intrinsic");
430 break;
431 }
432 }
433
434 static void
435 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
436 {
437 /* Make sure we've been lowered */
438 assert(instr->def.num_components == 1);
439
440 bi_instruction move = {
441 .type = BI_MOV,
442 .dest = pan_ssa_index(&instr->def),
443 .dest_type = instr->def.bit_size | nir_type_uint,
444 .src = {
445 BIR_INDEX_CONSTANT
446 },
447 .src_types = {
448 instr->def.bit_size | nir_type_uint,
449 },
450 .constant = {
451 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
452 }
453 };
454
455 bi_emit(ctx, move);
456 }
457
458 #define BI_CASE_CMP(op) \
459 case op##8: \
460 case op##16: \
461 case op##32: \
462
463 static enum bi_class
464 bi_class_for_nir_alu(nir_op op)
465 {
466 switch (op) {
467 case nir_op_iadd:
468 case nir_op_fadd:
469 case nir_op_fsub:
470 return BI_ADD;
471 case nir_op_isub:
472 return BI_ISUB;
473
474 case nir_op_iand:
475 case nir_op_ior:
476 case nir_op_ixor:
477 return BI_BITWISE;
478
479 BI_CASE_CMP(nir_op_flt)
480 BI_CASE_CMP(nir_op_fge)
481 BI_CASE_CMP(nir_op_feq)
482 BI_CASE_CMP(nir_op_fne)
483 BI_CASE_CMP(nir_op_ilt)
484 BI_CASE_CMP(nir_op_ige)
485 BI_CASE_CMP(nir_op_ieq)
486 BI_CASE_CMP(nir_op_ine)
487 return BI_CMP;
488
489 case nir_op_b8csel:
490 case nir_op_b16csel:
491 case nir_op_b32csel:
492 return BI_CSEL;
493
494 case nir_op_i2i8:
495 case nir_op_i2i16:
496 case nir_op_i2i32:
497 case nir_op_i2i64:
498 case nir_op_u2u8:
499 case nir_op_u2u16:
500 case nir_op_u2u32:
501 case nir_op_u2u64:
502 case nir_op_f2i16:
503 case nir_op_f2i32:
504 case nir_op_f2i64:
505 case nir_op_f2u16:
506 case nir_op_f2u32:
507 case nir_op_f2u64:
508 case nir_op_i2f16:
509 case nir_op_i2f32:
510 case nir_op_i2f64:
511 case nir_op_u2f16:
512 case nir_op_u2f32:
513 case nir_op_u2f64:
514 case nir_op_f2f16:
515 case nir_op_f2f32:
516 case nir_op_f2f64:
517 case nir_op_f2fmp:
518 return BI_CONVERT;
519
520 case nir_op_vec2:
521 case nir_op_vec3:
522 case nir_op_vec4:
523 return BI_COMBINE;
524
525 case nir_op_vec8:
526 case nir_op_vec16:
527 unreachable("should've been lowered");
528
529 case nir_op_ffma:
530 case nir_op_fmul:
531 return BI_FMA;
532
533 case nir_op_imin:
534 case nir_op_imax:
535 case nir_op_umin:
536 case nir_op_umax:
537 case nir_op_fmin:
538 case nir_op_fmax:
539 return BI_MINMAX;
540
541 case nir_op_fsat:
542 case nir_op_fneg:
543 case nir_op_fabs:
544 return BI_FMOV;
545 case nir_op_mov:
546 return BI_MOV;
547
548 case nir_op_fround_even:
549 case nir_op_fceil:
550 case nir_op_ffloor:
551 case nir_op_ftrunc:
552 return BI_ROUND;
553
554 case nir_op_frcp:
555 case nir_op_frsq:
556 return BI_SPECIAL;
557
558 default:
559 unreachable("Unknown ALU op");
560 }
561 }
562
563 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
564 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
565 * optimizations). Otherwise it will bail (when used for primary code
566 * generation). */
567
568 static enum bi_cond
569 bi_cond_for_nir(nir_op op, bool soft)
570 {
571 switch (op) {
572 BI_CASE_CMP(nir_op_flt)
573 BI_CASE_CMP(nir_op_ilt)
574 return BI_COND_LT;
575
576 BI_CASE_CMP(nir_op_fge)
577 BI_CASE_CMP(nir_op_ige)
578 return BI_COND_GE;
579
580 BI_CASE_CMP(nir_op_feq)
581 BI_CASE_CMP(nir_op_ieq)
582 return BI_COND_EQ;
583
584 BI_CASE_CMP(nir_op_fne)
585 BI_CASE_CMP(nir_op_ine)
586 return BI_COND_NE;
587 default:
588 if (soft)
589 return BI_COND_ALWAYS;
590 else
591 unreachable("Invalid compare");
592 }
593 }
594
595 static void
596 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
597 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
598 {
599 unsigned bits = nir_src_bit_size(instr->src[i].src);
600 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
601
602 alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
603 | bits;
604
605 /* Try to inline a constant */
606 if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
607 uint64_t mask = (1ull << dest_bits) - 1;
608 uint64_t cons = nir_src_as_uint(instr->src[i].src);
609
610 /* Try to reuse a constant */
611 for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
612 if (((alu->constant.u64 >> i) & mask) == cons) {
613 alu->src[to] = BIR_INDEX_CONSTANT | i;
614 return;
615 }
616 }
617
618 alu->constant.u64 |= cons << *constant_shift;
619 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
620 --(*constants_left);
621 (*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
622 return;
623 }
624
625 alu->src[to] = pan_src_index(&instr->src[i].src);
626
627 /* Copy swizzle for all vectored components, replicating last component
628 * to fill undersized */
629
630 unsigned vec = alu->type == BI_COMBINE ? 1 :
631 MAX2(1, 32 / dest_bits);
632
633 for (unsigned j = 0; j < vec; ++j)
634 alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
635 }
636
637 static void
638 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
639 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
640 {
641 /* Bail for vector weirdness */
642 if (cond.swizzle[0] != 0)
643 return;
644
645 if (!cond.src.is_ssa)
646 return;
647
648 nir_ssa_def *def = cond.src.ssa;
649 nir_instr *parent = def->parent_instr;
650
651 if (parent->type != nir_instr_type_alu)
652 return;
653
654 nir_alu_instr *alu = nir_instr_as_alu(parent);
655
656 /* Try to match a condition */
657 enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
658
659 if (bcond == BI_COND_ALWAYS)
660 return;
661
662 /* We found one, let's fuse it in */
663 csel->cond = bcond;
664 bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
665 bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
666 }
667
668 static void
669 emit_alu(bi_context *ctx, nir_alu_instr *instr)
670 {
671 /* Try some special functions */
672 switch (instr->op) {
673 case nir_op_fexp2:
674 bi_emit_fexp2(ctx, instr);
675 return;
676 case nir_op_flog2:
677 bi_emit_flog2(ctx, instr);
678 return;
679 default:
680 break;
681 }
682
683 /* Otherwise, assume it's something we can handle normally */
684 bi_instruction alu = {
685 .type = bi_class_for_nir_alu(instr->op),
686 .dest = pan_dest_index(&instr->dest.dest),
687 .dest_type = nir_op_infos[instr->op].output_type
688 | nir_dest_bit_size(instr->dest.dest),
689 };
690
691 /* TODO: Implement lowering of special functions for older Bifrost */
692 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
693
694 unsigned comps = nir_dest_num_components(instr->dest.dest);
695
696 if (alu.type != BI_COMBINE)
697 assert(comps <= MAX2(1, 32 / comps));
698
699 if (!instr->dest.dest.is_ssa) {
700 for (unsigned i = 0; i < comps; ++i)
701 assert(instr->dest.write_mask);
702 }
703
704 /* We inline constants as we go. This tracks how many constants have
705 * been inlined, since we're limited to 64-bits of constants per
706 * instruction */
707
708 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
709 unsigned constants_left = (64 / dest_bits);
710 unsigned constant_shift = 0;
711
712 if (alu.type == BI_COMBINE)
713 constants_left = 0;
714
715 /* Copy sources */
716
717 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
718 assert(num_inputs <= ARRAY_SIZE(alu.src));
719
720 for (unsigned i = 0; i < num_inputs; ++i) {
721 unsigned f = 0;
722
723 if (i && alu.type == BI_CSEL)
724 f++;
725
726 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
727 }
728
729 /* Op-specific fixup */
730 switch (instr->op) {
731 case nir_op_fmul:
732 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
733 alu.src_types[2] = alu.src_types[1];
734 break;
735 case nir_op_fsat:
736 alu.outmod = BIFROST_SAT; /* FMOV */
737 break;
738 case nir_op_fneg:
739 alu.src_neg[0] = true; /* FMOV */
740 break;
741 case nir_op_fabs:
742 alu.src_abs[0] = true; /* FMOV */
743 break;
744 case nir_op_fsub:
745 alu.src_neg[1] = true; /* FADD */
746 break;
747 case nir_op_fmax:
748 case nir_op_imax:
749 case nir_op_umax:
750 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
751 break;
752 case nir_op_frcp:
753 alu.op.special = BI_SPECIAL_FRCP;
754 break;
755 case nir_op_frsq:
756 alu.op.special = BI_SPECIAL_FRSQ;
757 break;
758 BI_CASE_CMP(nir_op_flt)
759 BI_CASE_CMP(nir_op_ilt)
760 BI_CASE_CMP(nir_op_fge)
761 BI_CASE_CMP(nir_op_ige)
762 BI_CASE_CMP(nir_op_feq)
763 BI_CASE_CMP(nir_op_ieq)
764 BI_CASE_CMP(nir_op_fne)
765 BI_CASE_CMP(nir_op_ine)
766 alu.cond = bi_cond_for_nir(instr->op, false);
767 break;
768 case nir_op_fround_even:
769 alu.roundmode = BIFROST_RTE;
770 break;
771 case nir_op_fceil:
772 alu.roundmode = BIFROST_RTP;
773 break;
774 case nir_op_ffloor:
775 alu.roundmode = BIFROST_RTN;
776 break;
777 case nir_op_ftrunc:
778 alu.roundmode = BIFROST_RTZ;
779 break;
780 case nir_op_iand:
781 alu.op.bitwise = BI_BITWISE_AND;
782 break;
783 case nir_op_ior:
784 alu.op.bitwise = BI_BITWISE_OR;
785 break;
786 case nir_op_ixor:
787 alu.op.bitwise = BI_BITWISE_XOR;
788 break;
789 default:
790 break;
791 }
792
793 if (alu.type == BI_CSEL) {
794 /* Default to csel3 */
795 alu.cond = BI_COND_NE;
796 alu.src[1] = BIR_INDEX_ZERO;
797 alu.src_types[1] = alu.src_types[0];
798
799 /* TODO: Reenable cond fusing when we can split up registers
800 * when scheduling */
801 #if 0
802 bi_fuse_csel_cond(&alu, instr->src[0],
803 &constants_left, &constant_shift, comps);
804 #endif
805 } else if (alu.type == BI_BITWISE) {
806 /* Implicit shift argument... at some point we should fold */
807 alu.src[2] = BIR_INDEX_ZERO;
808 alu.src_types[2] = alu.src_types[1];
809 }
810
811 bi_emit(ctx, alu);
812 }
813
814 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
815 * space-efficient and with simpler RA/scheduling requirements*/
816
817 static void
818 emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
819 {
820 bi_instruction tex = {
821 .type = BI_TEX,
822 .op = { .texture = BI_TEX_COMPACT },
823 .texture = {
824 .texture_index = instr->texture_index,
825 .sampler_index = instr->sampler_index,
826 },
827 .dest = pan_dest_index(&instr->dest),
828 .dest_type = instr->dest_type,
829 .src_types = { nir_type_float32, nir_type_float32 },
830 .vector_channels = 4
831 };
832
833 for (unsigned i = 0; i < instr->num_srcs; ++i) {
834 int index = pan_src_index(&instr->src[i].src);
835 assert (instr->src[i].src_type == nir_tex_src_coord);
836
837 tex.src[0] = index;
838 tex.src[1] = index;
839 tex.swizzle[0][0] = 0;
840 tex.swizzle[1][0] = 1;
841 }
842
843 bi_emit(ctx, tex);
844 }
845
846 static void
847 emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
848 {
849 unreachable("stub");
850 }
851
852 static void
853 emit_tex(bi_context *ctx, nir_tex_instr *instr)
854 {
855 nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
856 unsigned sz = nir_dest_bit_size(instr->dest);
857 instr->dest_type = base | sz;
858
859 bool is_normal = instr->op == nir_texop_tex;
860 bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
861 instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
862 bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
863
864 bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
865
866 if (is_compact)
867 emit_tex_compact(ctx, instr);
868 else
869 emit_tex_full(ctx, instr);
870 }
871
872 static void
873 emit_instr(bi_context *ctx, struct nir_instr *instr)
874 {
875 switch (instr->type) {
876 case nir_instr_type_load_const:
877 emit_load_const(ctx, nir_instr_as_load_const(instr));
878 break;
879
880 case nir_instr_type_intrinsic:
881 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
882 break;
883
884 case nir_instr_type_alu:
885 emit_alu(ctx, nir_instr_as_alu(instr));
886 break;
887
888 case nir_instr_type_tex:
889 emit_tex(ctx, nir_instr_as_tex(instr));
890 break;
891
892 case nir_instr_type_jump:
893 emit_jump(ctx, nir_instr_as_jump(instr));
894 break;
895
896 case nir_instr_type_ssa_undef:
897 /* Spurious */
898 break;
899
900 default:
901 unreachable("Unhandled instruction type");
902 break;
903 }
904 }
905
906
907
908 static bi_block *
909 create_empty_block(bi_context *ctx)
910 {
911 bi_block *blk = rzalloc(ctx, bi_block);
912
913 blk->base.predecessors = _mesa_set_create(blk,
914 _mesa_hash_pointer,
915 _mesa_key_pointer_equal);
916
917 blk->base.name = ctx->block_name_count++;
918
919 return blk;
920 }
921
922 static void
923 bi_schedule_barrier(bi_context *ctx)
924 {
925 bi_block *temp = ctx->after_block;
926 ctx->after_block = create_empty_block(ctx);
927 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
928 list_inithead(&ctx->after_block->base.instructions);
929 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
930 ctx->current_block = ctx->after_block;
931 ctx->after_block = temp;
932 }
933
934 static bi_block *
935 emit_block(bi_context *ctx, nir_block *block)
936 {
937 if (ctx->after_block) {
938 ctx->current_block = ctx->after_block;
939 ctx->after_block = NULL;
940 } else {
941 ctx->current_block = create_empty_block(ctx);
942 }
943
944 list_addtail(&ctx->current_block->base.link, &ctx->blocks);
945 list_inithead(&ctx->current_block->base.instructions);
946
947 nir_foreach_instr(instr, block) {
948 emit_instr(ctx, instr);
949 ++ctx->instruction_count;
950 }
951
952 return ctx->current_block;
953 }
954
955 /* Emits an unconditional branch to the end of the current block, returning a
956 * pointer so the user can fill in details */
957
958 static bi_instruction *
959 bi_emit_branch(bi_context *ctx)
960 {
961 bi_instruction branch = {
962 .type = BI_BRANCH,
963 .cond = BI_COND_ALWAYS
964 };
965
966 return bi_emit(ctx, branch);
967 }
968
969 /* Sets a condition for a branch by examing the NIR condition. If we're
970 * familiar with the condition, we unwrap it to fold it into the branch
971 * instruction. Otherwise, we consume the condition directly. We
972 * generally use 1-bit booleans which allows us to use small types for
973 * the conditions.
974 */
975
976 static void
977 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
978 {
979 /* TODO: Try to unwrap instead of always bailing */
980 branch->src[0] = pan_src_index(cond);
981 branch->src[1] = BIR_INDEX_ZERO;
982 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
983 branch->cond = invert ? BI_COND_EQ : BI_COND_NE;
984 }
985
986 static void
987 emit_if(bi_context *ctx, nir_if *nif)
988 {
989 bi_block *before_block = ctx->current_block;
990
991 /* Speculatively emit the branch, but we can't fill it in until later */
992 bi_instruction *then_branch = bi_emit_branch(ctx);
993 bi_set_branch_cond(then_branch, &nif->condition, true);
994
995 /* Emit the two subblocks. */
996 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
997 bi_block *end_then_block = ctx->current_block;
998
999 /* Emit a jump from the end of the then block to the end of the else */
1000 bi_instruction *then_exit = bi_emit_branch(ctx);
1001
1002 /* Emit second block, and check if it's empty */
1003
1004 int count_in = ctx->instruction_count;
1005 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
1006 bi_block *end_else_block = ctx->current_block;
1007 ctx->after_block = create_empty_block(ctx);
1008
1009 /* Now that we have the subblocks emitted, fix up the branches */
1010
1011 assert(then_block);
1012 assert(else_block);
1013
1014 if (ctx->instruction_count == count_in) {
1015 /* The else block is empty, so don't emit an exit jump */
1016 bi_remove_instruction(then_exit);
1017 then_branch->branch_target = ctx->after_block;
1018 } else {
1019 then_branch->branch_target = else_block;
1020 then_exit->branch_target = ctx->after_block;
1021 pan_block_add_successor(&end_then_block->base, &then_exit->branch_target->base);
1022 }
1023
1024 /* Wire up the successors */
1025
1026 pan_block_add_successor(&before_block->base, &then_branch->branch_target->base); /* then_branch */
1027
1028 pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
1029 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
1030 }
1031
1032 static void
1033 emit_loop(bi_context *ctx, nir_loop *nloop)
1034 {
1035 /* Remember where we are */
1036 bi_block *start_block = ctx->current_block;
1037
1038 bi_block *saved_break = ctx->break_block;
1039 bi_block *saved_continue = ctx->continue_block;
1040
1041 ctx->continue_block = create_empty_block(ctx);
1042 ctx->break_block = create_empty_block(ctx);
1043 ctx->after_block = ctx->continue_block;
1044
1045 /* Emit the body itself */
1046 emit_cf_list(ctx, &nloop->body);
1047
1048 /* Branch back to loop back */
1049 bi_instruction *br_back = bi_emit_branch(ctx);
1050 br_back->branch_target = ctx->continue_block;
1051 pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
1052 pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
1053
1054 ctx->after_block = ctx->break_block;
1055
1056 /* Pop off */
1057 ctx->break_block = saved_break;
1058 ctx->continue_block = saved_continue;
1059 ++ctx->loop_count;
1060 }
1061
1062 static bi_block *
1063 emit_cf_list(bi_context *ctx, struct exec_list *list)
1064 {
1065 bi_block *start_block = NULL;
1066
1067 foreach_list_typed(nir_cf_node, node, node, list) {
1068 switch (node->type) {
1069 case nir_cf_node_block: {
1070 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
1071
1072 if (!start_block)
1073 start_block = block;
1074
1075 break;
1076 }
1077
1078 case nir_cf_node_if:
1079 emit_if(ctx, nir_cf_node_as_if(node));
1080 break;
1081
1082 case nir_cf_node_loop:
1083 emit_loop(ctx, nir_cf_node_as_loop(node));
1084 break;
1085
1086 default:
1087 unreachable("Unknown control flow");
1088 }
1089 }
1090
1091 return start_block;
1092 }
1093
1094 static int
1095 glsl_type_size(const struct glsl_type *type, bool bindless)
1096 {
1097 return glsl_count_attribute_slots(type, false);
1098 }
1099
1100 static void
1101 bi_optimize_nir(nir_shader *nir)
1102 {
1103 bool progress;
1104 unsigned lower_flrp = 16 | 32 | 64;
1105
1106 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
1107 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
1108
1109 nir_lower_tex_options lower_tex_options = {
1110 .lower_txs_lod = true,
1111 .lower_txp = ~0,
1112 .lower_tex_without_implicit_lod = true,
1113 .lower_txd = true,
1114 };
1115
1116 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
1117 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1118 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1119
1120 do {
1121 progress = false;
1122
1123 NIR_PASS(progress, nir, nir_lower_var_copies);
1124 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
1125
1126 NIR_PASS(progress, nir, nir_copy_prop);
1127 NIR_PASS(progress, nir, nir_opt_remove_phis);
1128 NIR_PASS(progress, nir, nir_opt_dce);
1129 NIR_PASS(progress, nir, nir_opt_dead_cf);
1130 NIR_PASS(progress, nir, nir_opt_cse);
1131 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
1132 NIR_PASS(progress, nir, nir_opt_algebraic);
1133 NIR_PASS(progress, nir, nir_opt_constant_folding);
1134
1135 if (lower_flrp != 0) {
1136 bool lower_flrp_progress = false;
1137 NIR_PASS(lower_flrp_progress,
1138 nir,
1139 nir_lower_flrp,
1140 lower_flrp,
1141 false /* always_precise */,
1142 nir->options->lower_ffma);
1143 if (lower_flrp_progress) {
1144 NIR_PASS(progress, nir,
1145 nir_opt_constant_folding);
1146 progress = true;
1147 }
1148
1149 /* Nothing should rematerialize any flrps, so we only
1150 * need to do this lowering once.
1151 */
1152 lower_flrp = 0;
1153 }
1154
1155 NIR_PASS(progress, nir, nir_opt_undef);
1156 NIR_PASS(progress, nir, nir_opt_loop_unroll,
1157 nir_var_shader_in |
1158 nir_var_shader_out |
1159 nir_var_function_temp);
1160 } while (progress);
1161
1162 NIR_PASS(progress, nir, nir_opt_algebraic_late);
1163 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
1164 NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
1165 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1166 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1167
1168 /* Take us out of SSA */
1169 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
1170 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
1171 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
1172 }
1173
1174 void
1175 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
1176 {
1177 bifrost_debug = debug_get_option_bifrost_debug();
1178
1179 bi_context *ctx = rzalloc(NULL, bi_context);
1180 ctx->nir = nir;
1181 ctx->stage = nir->info.stage;
1182 ctx->quirks = bifrost_get_quirks(product_id);
1183 list_inithead(&ctx->blocks);
1184
1185 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1186 * (so we don't accidentally duplicate the epilogue since mesa/st has
1187 * messed with our I/O quite a bit already) */
1188
1189 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1190
1191 if (ctx->stage == MESA_SHADER_VERTEX) {
1192 NIR_PASS_V(nir, nir_lower_viewport_transform);
1193 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
1194 }
1195
1196 NIR_PASS_V(nir, nir_split_var_copies);
1197 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1198 NIR_PASS_V(nir, nir_lower_var_copies);
1199 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1200 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
1201 NIR_PASS_V(nir, nir_lower_ssbo);
1202 NIR_PASS_V(nir, nir_lower_mediump_outputs);
1203
1204 bi_optimize_nir(nir);
1205
1206 if (bifrost_debug & BIFROST_DBG_SHADERS) {
1207 nir_print_shader(nir, stdout);
1208 }
1209
1210 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
1211 program->sysval_count = ctx->sysvals.sysval_count;
1212 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
1213 ctx->blend_types = program->blend_types;
1214
1215 nir_foreach_function(func, nir) {
1216 if (!func->impl)
1217 continue;
1218
1219 ctx->impl = func->impl;
1220 emit_cf_list(ctx, &func->impl->body);
1221 break; /* TODO: Multi-function shaders */
1222 }
1223
1224 bi_foreach_block(ctx, _block) {
1225 bi_block *block = (bi_block *) _block;
1226 bi_lower_combine(ctx, block);
1227 }
1228
1229 bool progress = false;
1230
1231 do {
1232 progress = false;
1233
1234 bi_foreach_block(ctx, _block) {
1235 bi_block *block = (bi_block *) _block;
1236 progress |= bi_opt_dead_code_eliminate(ctx, block);
1237 }
1238 } while(progress);
1239
1240 if (bifrost_debug & BIFROST_DBG_SHADERS)
1241 bi_print_shader(ctx, stdout);
1242 bi_schedule(ctx);
1243 bi_register_allocate(ctx);
1244 if (bifrost_debug & BIFROST_DBG_SHADERS)
1245 bi_print_shader(ctx, stdout);
1246 bi_pack(ctx, &program->compiled);
1247
1248 if (bifrost_debug & BIFROST_DBG_SHADERS)
1249 disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1250
1251 ralloc_free(ctx);
1252 }