src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_IMATH,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_REDUCE_FMA,
  72         BI_SELECT,
  73         BI_STORE,
  74         BI_STORE_VAR,
  75         BI_SPECIAL, /* _FAST on supported GPUs */
  76         BI_TABLE,
  77         BI_TEX,
  78         BI_ROUND,
  79         BI_NUM_CLASSES
  80 };
  81
  82 /* Properties of a class... */
  83 extern unsigned bi_class_props[BI_NUM_CLASSES];
  84
  85 /* abs/neg/outmod valid for a float op */
  86 #define BI_MODS (1 << 0)
  87
  88 /* Accepts a bi_cond */
  89 #define BI_CONDITIONAL (1 << 1)
  90
  91 /* Accepts a bifrost_roundmode */
  92 #define BI_ROUNDMODE (1 << 2)
  93
  94 /* Can be scheduled to FMA */
  95 #define BI_SCHED_FMA (1 << 3)
  96
  97 /* Can be scheduled to ADD */
  98 #define BI_SCHED_ADD (1 << 4)
  99
 100 /* Most ALU ops can do either, actually */
 101 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 102
 103 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 104  * nopped out. Used for _FAST operations. */
 105 #define BI_SCHED_SLOW (1 << 5)
 106
 107 /* Swizzling allowed for the 8/16-bit source */
 108 #define BI_SWIZZLABLE (1 << 6)
 109
 110 /* For scheduling purposes this is a high latency instruction and must be at
 111  * the end of a clause. Implies ADD */
 112 #define BI_SCHED_HI_LATENCY (1 << 7)
 113
 114 /* Intrinsic is vectorized and acts with `vector_channels` components */
 115 #define BI_VECTOR (1 << 8)
 116
 117 /* Use a data register for src0/dest respectively, bypassing the usual
 118  * register accessor. Mutually exclusive. */
 119 #define BI_DATA_REG_SRC (1 << 9)
 120 #define BI_DATA_REG_DEST (1 << 10)
 121
 122 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 123 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 124
 125 /* It can't get any worse than csel4... can it? */
 126 #define BIR_SRC_COUNT 4
 127
 128 /* BI_LD_VARY */
 129 struct bi_load_vary {
 130         enum bifrost_interp_mode interp_mode;
 131         bool reuse;
 132         bool flat;
 133 };
 134
 135 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 136  * the target. We forward declare bi_block since this is mildly circular (not
 137  * strictly, but this order of the file makes more sense I think)
 138  *
 139  * We define our own enum of conditions since the conditions in the hardware
 140  * packed in crazy ways that would make manipulation unweildly (meaning changes
 141  * based on port swapping, etc), so we defer dealing with that until emit time.
 142  * Likewise, we expose NIR types instead of the crazy branch types, although
 143  * the restrictions do eventually apply of course. */
 144
 145 struct bi_block;
 146
 147 enum bi_cond {
 148         BI_COND_ALWAYS,
 149         BI_COND_LT,
 150         BI_COND_LE,
 151         BI_COND_GE,
 152         BI_COND_GT,
 153         BI_COND_EQ,
 154         BI_COND_NE,
 155 };
 156
 157 /* Opcodes within a class */
 158 enum bi_minmax_op {
 159         BI_MINMAX_MIN,
 160         BI_MINMAX_MAX
 161 };
 162
 163 enum bi_bitwise_op {
 164         BI_BITWISE_AND,
 165         BI_BITWISE_OR,
 166         BI_BITWISE_XOR
 167 };
 168
 169 enum bi_imath_op {
 170         BI_IMATH_ADD,
 171         BI_IMATH_SUB,
 172 };
 173
 174 enum bi_table_op {
 175         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 176          * CL. In the first argument, takes x. Letting u be such that x =
 177          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 178          * log2(u) / (u - 1). */
 179
 180         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 181 };
 182
 183 enum bi_reduce_op {
 184         /* Takes two fp32 arguments and returns x + frexp(y). Used in
 185          * low-precision log2 argument reduction on newer models. */
 186
 187         BI_REDUCE_ADD_FREXPM,
 188 };
 189
 190 enum bi_frexp_op {
 191         BI_FREXPE_LOG,
 192 };
 193
 194 enum bi_special_op {
 195         BI_SPECIAL_FRCP,
 196         BI_SPECIAL_FRSQ,
 197
 198         /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
 199          * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
 200          * the second, it takes x itself. */
 201         BI_SPECIAL_EXP2_LOW,
 202 };
 203
 204 enum bi_tex_op {
 205         BI_TEX_NORMAL,
 206         BI_TEX_COMPACT,
 207         BI_TEX_DUAL
 208 };
 209
 210 struct bi_bitwise {
 211         bool src_invert[2];
 212         bool rshift; /* false for lshift */
 213 };
 214
 215 struct bi_texture {
 216         /* Constant indices. Indirect would need to be in src[..] like normal,
 217          * we can reserve some sentinels there for that for future. */
 218         unsigned texture_index, sampler_index;
 219 };
 220
 221 typedef struct {
 222         struct list_head link; /* Must be first */
 223         enum bi_class type;
 224
 225         /* Indices, see pan_ssa_index etc. Note zero is special cased
 226          * to "no argument" */
 227         unsigned dest;
 228         unsigned src[BIR_SRC_COUNT];
 229
 230         /* 32-bit word offset for destination, added to the register number in
 231          * RA when lowering combines */
 232         unsigned dest_offset;
 233
 234         /* If one of the sources has BIR_INDEX_CONSTANT */
 235         union {
 236                 uint64_t u64;
 237                 uint32_t u32;
 238                 uint16_t u16[2];
 239                 uint8_t u8[4];
 240         } constant;
 241
 242         /* Floating-point modifiers, type/class permitting. If not
 243          * allowed for the type/class, these are ignored. */
 244         enum bifrost_outmod outmod;
 245         bool src_abs[BIR_SRC_COUNT];
 246         bool src_neg[BIR_SRC_COUNT];
 247
 248         /* Round mode (requires BI_ROUNDMODE) */
 249         enum bifrost_roundmode roundmode;
 250
 251         /* Destination type. Usually the type of the instruction
 252          * itself, but if sources and destination have different
 253          * types, the type of the destination wins (so f2i would be
 254          * int). Zero if there is no destination. Bitsize included */
 255         nir_alu_type dest_type;
 256
 257         /* Source types if required by the class */
 258         nir_alu_type src_types[BIR_SRC_COUNT];
 259
 260         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 261          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 262          * sense. On non-SIMD instructions, it can be used for component
 263          * selection, so we don't have to special case extraction. */
 264         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 265
 266         /* For VECTOR ops, how many channels are written? */
 267         unsigned vector_channels;
 268
 269         /* The comparison op. BI_COND_ALWAYS may not be valid. */
 270         enum bi_cond cond;
 271
 272         /* A class-specific op from which the actual opcode can be derived
 273          * (along with the above information) */
 274
 275         union {
 276                 enum bi_minmax_op minmax;
 277                 enum bi_bitwise_op bitwise;
 278                 enum bi_special_op special;
 279                 enum bi_reduce_op reduce;
 280                 enum bi_table_op table;
 281                 enum bi_frexp_op frexp;
 282                 enum bi_tex_op texture;
 283                 enum bi_imath_op imath;
 284
 285                 /* For FMA/ADD, should we add a biased exponent? */
 286                 bool mscale;
 287         } op;
 288
 289         /* Union for class-specific information */
 290         union {
 291                 enum bifrost_minmax_mode minmax;
 292                 struct bi_load_vary load_vary;
 293                 struct bi_block *branch_target;
 294
 295                 /* For BLEND -- the location 0-7 */
 296                 unsigned blend_location;
 297
 298                 struct bi_bitwise bitwise;
 299                 struct bi_texture texture;
 300         };
 301 } bi_instruction;
 302
 303 /* Represents the assignment of ports for a given bi_bundle */
 304
 305 typedef struct {
 306         /* Register to assign to each port */
 307         unsigned port[4];
 308
 309         /* Read ports can be disabled */
 310         bool enabled[2];
 311
 312         /* Should we write FMA? what about ADD? If only a single port is
 313          * enabled it is in port 2, else ADD/FMA is 2/3 respectively */
 314         bool write_fma, write_add;
 315
 316         /* Should we read with port 3? */
 317         bool read_port3;
 318
 319         /* Packed uniform/constant */
 320         uint8_t uniform_constant;
 321
 322         /* Whether writes are actually for the last instruction */
 323         bool first_instruction;
 324 } bi_registers;
 325
 326 /* A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 327  * leave it NULL; the emitter will fill in a nop. Instructions reference
 328  * registers via ports which are assigned per bundle.
 329  */
 330
 331 typedef struct {
 332         bi_registers regs;
 333         bi_instruction *fma;
 334         bi_instruction *add;
 335 } bi_bundle;
 336
 337 struct bi_block;
 338
 339 typedef struct {
 340         struct list_head link;
 341
 342         /* Link back up for branch calculations */
 343         struct bi_block *block;
 344
 345         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 346          * can be 8 bundles. */
 347
 348         unsigned bundle_count;
 349         bi_bundle bundles[8];
 350
 351         /* For scoreboarding -- the clause ID (this is not globally unique!)
 352          * and its dependencies in terms of other clauses, computed during
 353          * scheduling and used when emitting code. Dependencies expressed as a
 354          * bitfield matching the hardware, except shifted by a clause (the
 355          * shift back to the ISA's off-by-one encoding is worked out when
 356          * emitting clauses) */
 357         unsigned scoreboard_id;
 358         uint8_t dependencies;
 359
 360         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 361          * conditional corresponds to the branch conditional bit except that in
 362          * the emitted code it's always set if back-to-bit is, whereas we use
 363          * the actual value (without back-to-back so to speak) internally */
 364         bool back_to_back;
 365         bool branch_conditional;
 366
 367         /* Assigned data register */
 368         unsigned data_register;
 369
 370         /* Corresponds to the usual bit but shifted by a clause */
 371         bool data_register_write_barrier;
 372
 373         /* Constants read by this clause. ISA limit. Must satisfy:
 374          *
 375          *      constant_count + bundle_count <= 13
 376          *
 377          * Also implicitly constant_count <= bundle_count since a bundle only
 378          * reads a single constant.
 379          */
 380         uint64_t constants[8];
 381         unsigned constant_count;
 382
 383         /* Branches encode a constant offset relative to the program counter
 384          * with some magic flags. By convention, if there is a branch, its
 385          * constant will be last. Set this flag to indicate this is required.
 386          */
 387         bool branch_constant;
 388
 389         /* What type of high latency instruction is here, basically */
 390         unsigned clause_type;
 391 } bi_clause;
 392
 393 typedef struct bi_block {
 394         pan_block base; /* must be first */
 395
 396         /* If true, uses clauses; if false, uses instructions */
 397         bool scheduled;
 398         struct list_head clauses; /* list of bi_clause */
 399 } bi_block;
 400
 401 typedef struct {
 402        nir_shader *nir;
 403        gl_shader_stage stage;
 404        struct list_head blocks; /* list of bi_block */
 405        struct panfrost_sysvals sysvals;
 406        uint32_t quirks;
 407
 408        /* During NIR->BIR */
 409        nir_function_impl *impl;
 410        bi_block *current_block;
 411        bi_block *after_block;
 412        bi_block *break_block;
 413        bi_block *continue_block;
 414        bool emitted_atest;
 415        nir_alu_type *blend_types;
 416
 417        /* For creating temporaries */
 418        unsigned temp_alloc;
 419
 420        /* Analysis results */
 421        bool has_liveness;
 422
 423        /* Stats for shader-db */
 424        unsigned instruction_count;
 425        unsigned loop_count;
 426 } bi_context;
 427
 428 static inline bi_instruction *
 429 bi_emit(bi_context *ctx, bi_instruction ins)
 430 {
 431         bi_instruction *u = rzalloc(ctx, bi_instruction);
 432         memcpy(u, &ins, sizeof(ins));
 433         list_addtail(&u->link, &ctx->current_block->base.instructions);
 434         return u;
 435 }
 436
 437 static inline bi_instruction *
 438 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 439 {
 440         bi_instruction *u = rzalloc(ctx, bi_instruction);
 441         memcpy(u, &ins, sizeof(ins));
 442         list_addtail(&u->link, &tag->link);
 443         return u;
 444 }
 445
 446 static inline void
 447 bi_remove_instruction(bi_instruction *ins)
 448 {
 449         list_del(&ins->link);
 450 }
 451
 452 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 453  * the low bits if necessary.
 454  *
 455  *  Fixed register: do not allocate register, do not collect $200.
 456  *  Uniform: access a uniform register given by low bits.
 457  *  Constant: access the specified constant (specifies a bit offset / shift)
 458  *  Zero: special cased to avoid wasting a constant
 459  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 460  */
 461
 462 #define BIR_INDEX_REGISTER (1 << 31)
 463 #define BIR_INDEX_UNIFORM  (1 << 30)
 464 #define BIR_INDEX_CONSTANT (1 << 29)
 465 #define BIR_INDEX_ZERO     (1 << 28)
 466 #define BIR_INDEX_PASS     (1 << 27)
 467
 468 /* Keep me synced please so we can check src & BIR_SPECIAL */
 469
 470 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 471         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 472
 473 static inline unsigned
 474 bi_max_temp(bi_context *ctx)
 475 {
 476         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 477         return ((alloc + 2 + ctx->temp_alloc) << 1);
 478 }
 479
 480 static inline unsigned
 481 bi_make_temp(bi_context *ctx)
 482 {
 483         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 484 }
 485
 486 static inline unsigned
 487 bi_make_temp_reg(bi_context *ctx)
 488 {
 489         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 490 }
 491
 492 /* Iterators for Bifrost IR */
 493
 494 #define bi_foreach_block(ctx, v) \
 495         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 496
 497 #define bi_foreach_block_from(ctx, from, v) \
 498         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 499
 500 #define bi_foreach_block_from_rev(ctx, from, v) \
 501         list_for_each_entry_from_rev(pan_block, v, from, &ctx->blocks, link)
 502
 503 #define bi_foreach_instr_in_block(block, v) \
 504         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 505
 506 #define bi_foreach_instr_in_block_rev(block, v) \
 507         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 508
 509 #define bi_foreach_instr_in_block_safe(block, v) \
 510         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 511
 512 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 513         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 514
 515 #define bi_foreach_instr_in_block_from(block, v, from) \
 516         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 517
 518 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 519         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 520
 521 #define bi_foreach_clause_in_block(block, v) \
 522         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 523
 524 #define bi_foreach_clause_in_block_from(block, v, from) \
 525         list_for_each_entry_from(bi_clause, v, from, &(block)->clauses, link)
 526
 527 #define bi_foreach_clause_in_block_from_rev(block, v, from) \
 528         list_for_each_entry_from_rev(bi_clause, v, from, &(block)->clauses, link)
 529
 530 #define bi_foreach_instr_global(ctx, v) \
 531         bi_foreach_block(ctx, v_block) \
 532                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 533
 534 #define bi_foreach_instr_global_safe(ctx, v) \
 535         bi_foreach_block(ctx, v_block) \
 536                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 537
 538 /* Based on set_foreach, expanded with automatic type casts */
 539
 540 #define bi_foreach_predecessor(blk, v) \
 541         struct set_entry *_entry_##v; \
 542         bi_block *v; \
 543         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 544                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 545                 _entry_##v != NULL; \
 546                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 547                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 548
 549 #define bi_foreach_src(ins, v) \
 550         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 551
 552 static inline bi_instruction *
 553 bi_prev_op(bi_instruction *ins)
 554 {
 555         return list_last_entry(&(ins->link), bi_instruction, link);
 556 }
 557
 558 static inline bi_instruction *
 559 bi_next_op(bi_instruction *ins)
 560 {
 561         return list_first_entry(&(ins->link), bi_instruction, link);
 562 }
 563
 564 static inline pan_block *
 565 pan_next_block(pan_block *block)
 566 {
 567         return list_first_entry(&(block->link), pan_block, link);
 568 }
 569
 570 /* Special functions */
 571
 572 void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr);
 573 void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr);
 574
 575 /* BIR manipulation */
 576
 577 bool bi_has_outmod(bi_instruction *ins);
 578 bool bi_has_source_mods(bi_instruction *ins);
 579 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 580 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 581 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 582 unsigned bi_get_component_count(bi_instruction *ins, signed s);
 583 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 584 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 585 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 586 unsigned bi_writemask(bi_instruction *ins);
 587
 588 /* BIR passes */
 589
 590 void bi_lower_combine(bi_context *ctx, bi_block *block);
 591 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 592 void bi_schedule(bi_context *ctx);
 593 void bi_register_allocate(bi_context *ctx);
 594
 595 /* Liveness */
 596
 597 void bi_compute_liveness(bi_context *ctx);
 598 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 599 void bi_invalidate_liveness(bi_context *ctx);
 600 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 601
 602 /* Layout */
 603
 604 bool bi_can_insert_bundle(bi_clause *clause, bool constant);
 605 unsigned bi_clause_quadwords(bi_clause *clause);
 606 signed bi_block_offset(bi_context *ctx, bi_clause *start, bi_block *target);
 607
 608 /* Code emit */
 609
 610 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 611
 612 #endif