src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_ISUB,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_REDUCE_FMA,
  72         BI_SELECT,
  73         BI_SHIFT,
  74         BI_STORE,
  75         BI_STORE_VAR,
  76         BI_SPECIAL, /* _FAST on supported GPUs */
  77         BI_TABLE,
  78         BI_TEX,
  79         BI_ROUND,
  80         BI_NUM_CLASSES
  81 };
  82
  83 /* Properties of a class... */
  84 extern unsigned bi_class_props[BI_NUM_CLASSES];
  85
  86 /* abs/neg/outmod valid for a float op */
  87 #define BI_MODS (1 << 0)
  88
  89 /* Generic enough that little class-specific information is required. In other
  90  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  91  * irregular enough to warrant a separate class */
  92 #define BI_GENERIC (1 << 1)
  93
  94 /* Accepts a bifrost_roundmode */
  95 #define BI_ROUNDMODE (1 << 2)
  96
  97 /* Can be scheduled to FMA */
  98 #define BI_SCHED_FMA (1 << 3)
  99
 100 /* Can be scheduled to ADD */
 101 #define BI_SCHED_ADD (1 << 4)
 102
 103 /* Most ALU ops can do either, actually */
 104 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 105
 106 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 107  * nopped out. Used for _FAST operations. */
 108 #define BI_SCHED_SLOW (1 << 5)
 109
 110 /* Swizzling allowed for the 8/16-bit source */
 111 #define BI_SWIZZLABLE (1 << 6)
 112
 113 /* For scheduling purposes this is a high latency instruction and must be at
 114  * the end of a clause. Implies ADD */
 115 #define BI_SCHED_HI_LATENCY (1 << 7)
 116
 117 /* Intrinsic is vectorized and acts with `vector_channels` components */
 118 #define BI_VECTOR (1 << 8)
 119
 120 /* Use a data register for src0/dest respectively, bypassing the usual
 121  * register accessor. Mutually exclusive. */
 122 #define BI_DATA_REG_SRC (1 << 9)
 123 #define BI_DATA_REG_DEST (1 << 10)
 124
 125 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 126 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 127
 128 /* It can't get any worse than csel4... can it? */
 129 #define BIR_SRC_COUNT 4
 130
 131 /* BI_LD_VARY */
 132 struct bi_load_vary {
 133         enum bifrost_interp_mode interp_mode;
 134         bool reuse;
 135         bool flat;
 136 };
 137
 138 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 139  * the target. We forward declare bi_block since this is mildly circular (not
 140  * strictly, but this order of the file makes more sense I think)
 141  *
 142  * We define our own enum of conditions since the conditions in the hardware
 143  * packed in crazy ways that would make manipulation unweildly (meaning changes
 144  * based on port swapping, etc), so we defer dealing with that until emit time.
 145  * Likewise, we expose NIR types instead of the crazy branch types, although
 146  * the restrictions do eventually apply of course. */
 147
 148 struct bi_block;
 149
 150 enum bi_cond {
 151         BI_COND_ALWAYS,
 152         BI_COND_LT,
 153         BI_COND_LE,
 154         BI_COND_GE,
 155         BI_COND_GT,
 156         BI_COND_EQ,
 157         BI_COND_NE,
 158 };
 159
 160 struct bi_branch {
 161         /* Types are specified in src_types and must be compatible (either both
 162          * int, or both float, 16/32, and same size or 32/16 if float. Types
 163          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 164
 165         enum bi_cond cond;
 166         struct bi_block *target;
 167 };
 168
 169 /* Opcodes within a class */
 170 enum bi_minmax_op {
 171         BI_MINMAX_MIN,
 172         BI_MINMAX_MAX
 173 };
 174
 175 enum bi_bitwise_op {
 176         BI_BITWISE_AND,
 177         BI_BITWISE_OR,
 178         BI_BITWISE_XOR
 179 };
 180
 181 enum bi_round_op {
 182         BI_ROUND_MODE, /* use round mode */
 183         BI_ROUND_ROUND /* i.e.: fround() */
 184 };
 185
 186 enum bi_table_op {
 187         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 188          * CL. In the first argument, takes x. Letting u be such that x =
 189          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 190          * log2(u) / (u - 1). */
 191
 192         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 193 };
 194
 195 enum bi_reduce_op {
 196         /* Takes two fp32 arguments and returns x + frexp(y). Used in
 197          * low-precision log2 argument reduction on newer models. */
 198
 199         BI_REDUCE_ADD_FREXPM,
 200 };
 201
 202 enum bi_frexp_op {
 203         BI_FREXPE_LOG,
 204 };
 205
 206 enum bi_special_op {
 207         BI_SPECIAL_FRCP,
 208         BI_SPECIAL_FRSQ,
 209
 210         /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
 211          * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
 212          * the second, it takes x itself. */
 213         BI_SPECIAL_EXP2_LOW,
 214 };
 215
 216 enum bi_tex_op {
 217         BI_TEX_NORMAL,
 218         BI_TEX_COMPACT,
 219         BI_TEX_DUAL
 220 };
 221
 222 typedef struct {
 223         struct list_head link; /* Must be first */
 224         enum bi_class type;
 225
 226         /* Indices, see bir_ssa_index etc. Note zero is special cased
 227          * to "no argument" */
 228         unsigned dest;
 229         unsigned src[BIR_SRC_COUNT];
 230
 231         /* 32-bit word offset for destination, added to the register number in
 232          * RA when lowering combines */
 233         unsigned dest_offset;
 234
 235         /* If one of the sources has BIR_INDEX_CONSTANT */
 236         union {
 237                 uint64_t u64;
 238                 uint32_t u32;
 239                 uint16_t u16[2];
 240                 uint8_t u8[4];
 241         } constant;
 242
 243         /* Floating-point modifiers, type/class permitting. If not
 244          * allowed for the type/class, these are ignored. */
 245         enum bifrost_outmod outmod;
 246         bool src_abs[BIR_SRC_COUNT];
 247         bool src_neg[BIR_SRC_COUNT];
 248
 249         /* Round mode (requires BI_ROUNDMODE) */
 250         enum bifrost_roundmode roundmode;
 251
 252         /* Destination type. Usually the type of the instruction
 253          * itself, but if sources and destination have different
 254          * types, the type of the destination wins (so f2i would be
 255          * int). Zero if there is no destination. Bitsize included */
 256         nir_alu_type dest_type;
 257
 258         /* Source types if required by the class */
 259         nir_alu_type src_types[BIR_SRC_COUNT];
 260
 261         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 262          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 263          * sense. On non-SIMD instructions, it can be used for component
 264          * selection, so we don't have to special case extraction. */
 265         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 266
 267         /* For VECTOR ops, how many channels are written? */
 268         unsigned vector_channels;
 269
 270         /* A class-specific op from which the actual opcode can be derived
 271          * (along with the above information) */
 272
 273         union {
 274                 enum bi_minmax_op minmax;
 275                 enum bi_bitwise_op bitwise;
 276                 enum bi_round_op round;
 277                 enum bi_special_op special;
 278                 enum bi_reduce_op reduce;
 279                 enum bi_table_op table;
 280                 enum bi_frexp_op frexp;
 281                 enum bi_tex_op texture;
 282
 283                 /* For FMA/ADD, should we add a biased exponent? */
 284                 bool mscale;
 285         } op;
 286
 287         /* Union for class-specific information */
 288         union {
 289                 enum bifrost_minmax_mode minmax;
 290                 struct bi_load_vary load_vary;
 291                 struct bi_branch branch;
 292
 293                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 294                  * sense here but you can always just use a move for that */
 295                 enum bi_cond cond;
 296
 297                 /* For BLEND -- the location 0-7 */
 298                 unsigned blend_location;
 299         };
 300 } bi_instruction;
 301
 302 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 303  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 304  * within a clause into FMA/ADD pairs (bi_bundle).
 305  *
 306  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 307  * leave it NULL; the emitter will fill in a nop.
 308  */
 309
 310 typedef struct {
 311         bi_instruction *fma;
 312         bi_instruction *add;
 313 } bi_bundle;
 314
 315 typedef struct {
 316         struct list_head link;
 317
 318         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 319          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 320          * so a clause can have up to 16 bi_instructions. Whether bundles or
 321          * instructions are used depends on where in scheduling we are. */
 322
 323         unsigned instruction_count;
 324         unsigned bundle_count;
 325
 326         union {
 327                 bi_instruction *instructions[16];
 328                 bi_bundle bundles[8];
 329         };
 330
 331         /* For scoreboarding -- the clause ID (this is not globally unique!)
 332          * and its dependencies in terms of other clauses, computed during
 333          * scheduling and used when emitting code. Dependencies expressed as a
 334          * bitfield matching the hardware, except shifted by a clause (the
 335          * shift back to the ISA's off-by-one encoding is worked out when
 336          * emitting clauses) */
 337         unsigned scoreboard_id;
 338         uint8_t dependencies;
 339
 340         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 341          * conditional corresponds to the branch conditional bit except that in
 342          * the emitted code it's always set if back-to-bit is, whereas we use
 343          * the actual value (without back-to-back so to speak) internally */
 344         bool back_to_back;
 345         bool branch_conditional;
 346
 347         /* Assigned data register */
 348         unsigned data_register;
 349
 350         /* Corresponds to the usual bit but shifted by a clause */
 351         bool data_register_write_barrier;
 352
 353         /* Constants read by this clause. ISA limit. */
 354         uint64_t constants[8];
 355         unsigned constant_count;
 356
 357         /* What type of high latency instruction is here, basically */
 358         unsigned clause_type;
 359 } bi_clause;
 360
 361 typedef struct bi_block {
 362         pan_block base; /* must be first */
 363
 364         /* If true, uses clauses; if false, uses instructions */
 365         bool scheduled;
 366         struct list_head clauses; /* list of bi_clause */
 367 } bi_block;
 368
 369 typedef struct {
 370        nir_shader *nir;
 371        gl_shader_stage stage;
 372        struct list_head blocks; /* list of bi_block */
 373        struct panfrost_sysvals sysvals;
 374        uint32_t quirks;
 375
 376        /* During NIR->BIR */
 377        nir_function_impl *impl;
 378        bi_block *current_block;
 379        unsigned block_name_count;
 380        bi_block *after_block;
 381        bi_block *break_block;
 382        bi_block *continue_block;
 383        bool emitted_atest;
 384        nir_alu_type *blend_types;
 385
 386        /* For creating temporaries */
 387        unsigned temp_alloc;
 388
 389        /* Analysis results */
 390        bool has_liveness;
 391
 392        /* Stats for shader-db */
 393        unsigned instruction_count;
 394        unsigned loop_count;
 395 } bi_context;
 396
 397 static inline bi_instruction *
 398 bi_emit(bi_context *ctx, bi_instruction ins)
 399 {
 400         bi_instruction *u = rzalloc(ctx, bi_instruction);
 401         memcpy(u, &ins, sizeof(ins));
 402         list_addtail(&u->link, &ctx->current_block->base.instructions);
 403         return u;
 404 }
 405
 406 static inline bi_instruction *
 407 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 408 {
 409         bi_instruction *u = rzalloc(ctx, bi_instruction);
 410         memcpy(u, &ins, sizeof(ins));
 411         list_addtail(&u->link, &tag->link);
 412         return u;
 413 }
 414
 415 static inline void
 416 bi_remove_instruction(bi_instruction *ins)
 417 {
 418         list_del(&ins->link);
 419 }
 420
 421 /* So we can distinguish between SSA/reg/sentinel quickly */
 422 #define BIR_NO_ARG (0)
 423 #define BIR_IS_REG (1)
 424
 425 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 426  * the low bits if necessary.
 427  *
 428  *  Fixed register: do not allocate register, do not collect $200.
 429  *  Uniform: access a uniform register given by low bits.
 430  *  Constant: access the specified constant (specifies a bit offset / shift)
 431  *  Zero: special cased to avoid wasting a constant
 432  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 433  */
 434
 435 #define BIR_INDEX_REGISTER (1 << 31)
 436 #define BIR_INDEX_UNIFORM  (1 << 30)
 437 #define BIR_INDEX_CONSTANT (1 << 29)
 438 #define BIR_INDEX_ZERO     (1 << 28)
 439 #define BIR_INDEX_PASS     (1 << 27)
 440
 441 /* Keep me synced please so we can check src & BIR_SPECIAL */
 442
 443 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 444         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 445
 446 static inline unsigned
 447 bi_max_temp(bi_context *ctx)
 448 {
 449         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 450         return ((alloc + 2 + ctx->temp_alloc) << 1);
 451 }
 452
 453 static inline unsigned
 454 bi_make_temp(bi_context *ctx)
 455 {
 456         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 457 }
 458
 459 static inline unsigned
 460 bi_make_temp_reg(bi_context *ctx)
 461 {
 462         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
 463 }
 464
 465 static inline unsigned
 466 bir_ssa_index(nir_ssa_def *ssa)
 467 {
 468         /* Off-by-one ensures BIR_NO_ARG is skipped */
 469         return ((ssa->index + 1) << 1) | 0;
 470 }
 471
 472 static inline unsigned
 473 bir_src_index(nir_src *src)
 474 {
 475         if (src->is_ssa)
 476                 return bir_ssa_index(src->ssa);
 477         else {
 478                 assert(!src->reg.indirect);
 479                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 480         }
 481 }
 482
 483 static inline unsigned
 484 bir_dest_index(nir_dest *dst)
 485 {
 486         if (dst->is_ssa)
 487                 return bir_ssa_index(&dst->ssa);
 488         else {
 489                 assert(!dst->reg.indirect);
 490                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 491         }
 492 }
 493
 494 /* Iterators for Bifrost IR */
 495
 496 #define bi_foreach_block(ctx, v) \
 497         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 498
 499 #define bi_foreach_block_from(ctx, from, v) \
 500         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 501
 502 #define bi_foreach_instr_in_block(block, v) \
 503         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 504
 505 #define bi_foreach_instr_in_block_rev(block, v) \
 506         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 507
 508 #define bi_foreach_instr_in_block_safe(block, v) \
 509         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 510
 511 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 512         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 513
 514 #define bi_foreach_instr_in_block_from(block, v, from) \
 515         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 516
 517 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 518         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 519
 520 #define bi_foreach_clause_in_block(block, v) \
 521         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 522
 523 #define bi_foreach_instr_global(ctx, v) \
 524         bi_foreach_block(ctx, v_block) \
 525                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 526
 527 #define bi_foreach_instr_global_safe(ctx, v) \
 528         bi_foreach_block(ctx, v_block) \
 529                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 530
 531 /* Based on set_foreach, expanded with automatic type casts */
 532
 533 #define bi_foreach_predecessor(blk, v) \
 534         struct set_entry *_entry_##v; \
 535         bi_block *v; \
 536         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 537                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 538                 _entry_##v != NULL; \
 539                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 540                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 541
 542 #define bi_foreach_src(ins, v) \
 543         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 544
 545 static inline bi_instruction *
 546 bi_prev_op(bi_instruction *ins)
 547 {
 548         return list_last_entry(&(ins->link), bi_instruction, link);
 549 }
 550
 551 static inline bi_instruction *
 552 bi_next_op(bi_instruction *ins)
 553 {
 554         return list_first_entry(&(ins->link), bi_instruction, link);
 555 }
 556
 557 static inline pan_block *
 558 pan_next_block(pan_block *block)
 559 {
 560         return list_first_entry(&(block->link), pan_block, link);
 561 }
 562
 563 /* Special functions */
 564
 565 void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr);
 566 void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr);
 567
 568 /* BIR manipulation */
 569
 570 bool bi_has_outmod(bi_instruction *ins);
 571 bool bi_has_source_mods(bi_instruction *ins);
 572 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 573 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 574 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 575 unsigned bi_get_component_count(bi_instruction *ins, signed s);
 576 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 577 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 578 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 579 unsigned bi_writemask(bi_instruction *ins);
 580
 581 /* BIR passes */
 582
 583 void bi_lower_combine(bi_context *ctx, bi_block *block);
 584 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 585 void bi_schedule(bi_context *ctx);
 586 void bi_register_allocate(bi_context *ctx);
 587
 588 /* Liveness */
 589
 590 void bi_compute_liveness(bi_context *ctx);
 591 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 592 void bi_invalidate_liveness(bi_context *ctx);
 593 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 594
 595 /* Code emit */
 596
 597 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 598
 599 #endif