2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
76 BI_SPECIAL
, /* _FAST on supported GPUs */
83 /* Properties of a class... */
84 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
86 /* abs/neg/outmod valid for a float op */
87 #define BI_MODS (1 << 0)
89 /* Accepts a bi_cond */
90 #define BI_CONDITIONAL (1 << 1)
92 /* Accepts a bifrost_roundmode */
93 #define BI_ROUNDMODE (1 << 2)
95 /* Can be scheduled to FMA */
96 #define BI_SCHED_FMA (1 << 3)
98 /* Can be scheduled to ADD */
99 #define BI_SCHED_ADD (1 << 4)
101 /* Most ALU ops can do either, actually */
102 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
104 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
105 * nopped out. Used for _FAST operations. */
106 #define BI_SCHED_SLOW (1 << 5)
108 /* Swizzling allowed for the 8/16-bit source */
109 #define BI_SWIZZLABLE (1 << 6)
111 /* For scheduling purposes this is a high latency instruction and must be at
112 * the end of a clause. Implies ADD */
113 #define BI_SCHED_HI_LATENCY (1 << 7)
115 /* Intrinsic is vectorized and acts with `vector_channels` components */
116 #define BI_VECTOR (1 << 8)
118 /* Use a data register for src0/dest respectively, bypassing the usual
119 * register accessor. Mutually exclusive. */
120 #define BI_DATA_REG_SRC (1 << 9)
121 #define BI_DATA_REG_DEST (1 << 10)
123 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
124 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
126 /* It can't get any worse than csel4... can it? */
127 #define BIR_SRC_COUNT 4
130 struct bi_load_vary
{
131 enum bifrost_interp_mode interp_mode
;
136 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
137 * the target. We forward declare bi_block since this is mildly circular (not
138 * strictly, but this order of the file makes more sense I think)
140 * We define our own enum of conditions since the conditions in the hardware
141 * packed in crazy ways that would make manipulation unweildly (meaning changes
142 * based on port swapping, etc), so we defer dealing with that until emit time.
143 * Likewise, we expose NIR types instead of the crazy branch types, although
144 * the restrictions do eventually apply of course. */
158 /* Opcodes within a class */
176 /* fp32 log2() with low precision, suitable for GL or half_log2() in
177 * CL. In the first argument, takes x. Letting u be such that x =
178 * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
179 * log2(u) / (u - 1). */
181 BI_TABLE_LOG2_U_OVER_U_1_LOW
,
185 /* Takes two fp32 arguments and returns x + frexp(y). Used in
186 * low-precision log2 argument reduction on newer models. */
188 BI_REDUCE_ADD_FREXPM
,
199 /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
200 * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
201 * the second, it takes x itself. */
213 bool rshift
; /* false for lshift */
217 /* Constant indices. Indirect would need to be in src[..] like normal,
218 * we can reserve some sentinels there for that for future. */
219 unsigned texture_index
, sampler_index
;
223 struct list_head link
; /* Must be first */
226 /* Indices, see pan_ssa_index etc. Note zero is special cased
227 * to "no argument" */
229 unsigned src
[BIR_SRC_COUNT
];
231 /* 32-bit word offset for destination, added to the register number in
232 * RA when lowering combines */
233 unsigned dest_offset
;
235 /* If one of the sources has BIR_INDEX_CONSTANT */
243 /* Floating-point modifiers, type/class permitting. If not
244 * allowed for the type/class, these are ignored. */
245 enum bifrost_outmod outmod
;
246 bool src_abs
[BIR_SRC_COUNT
];
247 bool src_neg
[BIR_SRC_COUNT
];
249 /* Round mode (requires BI_ROUNDMODE) */
250 enum bifrost_roundmode roundmode
;
252 /* Destination type. Usually the type of the instruction
253 * itself, but if sources and destination have different
254 * types, the type of the destination wins (so f2i would be
255 * int). Zero if there is no destination. Bitsize included */
256 nir_alu_type dest_type
;
258 /* Source types if required by the class */
259 nir_alu_type src_types
[BIR_SRC_COUNT
];
261 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
262 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
263 * sense. On non-SIMD instructions, it can be used for component
264 * selection, so we don't have to special case extraction. */
265 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
267 /* For VECTOR ops, how many channels are written? */
268 unsigned vector_channels
;
270 /* The comparison op. BI_COND_ALWAYS may not be valid. */
273 /* A class-specific op from which the actual opcode can be derived
274 * (along with the above information) */
277 enum bi_minmax_op minmax
;
278 enum bi_bitwise_op bitwise
;
279 enum bi_special_op special
;
280 enum bi_reduce_op reduce
;
281 enum bi_table_op table
;
282 enum bi_frexp_op frexp
;
283 enum bi_tex_op texture
;
284 enum bi_imath_op imath
;
286 /* For FMA/ADD, should we add a biased exponent? */
290 /* Union for class-specific information */
292 enum bifrost_minmax_mode minmax
;
293 struct bi_load_vary load_vary
;
294 struct bi_block
*branch_target
;
296 /* For BLEND -- the location 0-7 */
297 unsigned blend_location
;
299 struct bi_bitwise bitwise
;
300 struct bi_texture texture
;
304 /* Represents the assignment of ports for a given bi_bundle */
306 struct bi_registers
{
307 /* Register to assign to each port */
310 /* Read ports can be disabled */
313 /* Should we write FMA? what about ADD? If only a single port is
314 * enabled it is in port 2, else ADD/FMA is 2/3 respectively */
315 bool write_fma
, write_add
;
317 /* Should we read with port 3? */
320 /* Packed uniform/constant */
321 uint8_t uniform_constant
;
323 /* Whether writes are actually for the last instruction */
324 bool first_instruction
;
327 /* A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
328 * leave it NULL; the emitter will fill in a nop. Instructions reference
329 * registers via ports which are assigned per bundle.
333 struct bi_registers regs
;
339 struct list_head link
;
341 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
342 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
343 * so a clause can have up to 16 bi_instructions. Whether bundles or
344 * instructions are used depends on where in scheduling we are. */
346 unsigned instruction_count
;
347 unsigned bundle_count
;
350 bi_instruction
*instructions
[16];
351 bi_bundle bundles
[8];
354 /* For scoreboarding -- the clause ID (this is not globally unique!)
355 * and its dependencies in terms of other clauses, computed during
356 * scheduling and used when emitting code. Dependencies expressed as a
357 * bitfield matching the hardware, except shifted by a clause (the
358 * shift back to the ISA's off-by-one encoding is worked out when
359 * emitting clauses) */
360 unsigned scoreboard_id
;
361 uint8_t dependencies
;
363 /* Back-to-back corresponds directly to the back-to-back bit. Branch
364 * conditional corresponds to the branch conditional bit except that in
365 * the emitted code it's always set if back-to-bit is, whereas we use
366 * the actual value (without back-to-back so to speak) internally */
368 bool branch_conditional
;
370 /* Assigned data register */
371 unsigned data_register
;
373 /* Corresponds to the usual bit but shifted by a clause */
374 bool data_register_write_barrier
;
376 /* Constants read by this clause. ISA limit. */
377 uint64_t constants
[8];
378 unsigned constant_count
;
380 /* What type of high latency instruction is here, basically */
381 unsigned clause_type
;
384 typedef struct bi_block
{
385 pan_block base
; /* must be first */
387 /* If true, uses clauses; if false, uses instructions */
389 struct list_head clauses
; /* list of bi_clause */
394 gl_shader_stage stage
;
395 struct list_head blocks
; /* list of bi_block */
396 struct panfrost_sysvals sysvals
;
399 /* During NIR->BIR */
400 nir_function_impl
*impl
;
401 bi_block
*current_block
;
402 unsigned block_name_count
;
403 bi_block
*after_block
;
404 bi_block
*break_block
;
405 bi_block
*continue_block
;
407 nir_alu_type
*blend_types
;
409 /* For creating temporaries */
412 /* Analysis results */
415 /* Stats for shader-db */
416 unsigned instruction_count
;
420 static inline bi_instruction
*
421 bi_emit(bi_context
*ctx
, bi_instruction ins
)
423 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
424 memcpy(u
, &ins
, sizeof(ins
));
425 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
429 static inline bi_instruction
*
430 bi_emit_before(bi_context
*ctx
, bi_instruction
*tag
, bi_instruction ins
)
432 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
433 memcpy(u
, &ins
, sizeof(ins
));
434 list_addtail(&u
->link
, &tag
->link
);
439 bi_remove_instruction(bi_instruction
*ins
)
441 list_del(&ins
->link
);
444 /* If high bits are set, instead of SSA/registers, we have specials indexed by
445 * the low bits if necessary.
447 * Fixed register: do not allocate register, do not collect $200.
448 * Uniform: access a uniform register given by low bits.
449 * Constant: access the specified constant (specifies a bit offset / shift)
450 * Zero: special cased to avoid wasting a constant
451 * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
454 #define BIR_INDEX_REGISTER (1 << 31)
455 #define BIR_INDEX_UNIFORM (1 << 30)
456 #define BIR_INDEX_CONSTANT (1 << 29)
457 #define BIR_INDEX_ZERO (1 << 28)
458 #define BIR_INDEX_PASS (1 << 27)
460 /* Keep me synced please so we can check src & BIR_SPECIAL */
462 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
463 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
465 static inline unsigned
466 bi_max_temp(bi_context
*ctx
)
468 unsigned alloc
= MAX2(ctx
->impl
->reg_alloc
, ctx
->impl
->ssa_alloc
);
469 return ((alloc
+ 2 + ctx
->temp_alloc
) << 1);
472 static inline unsigned
473 bi_make_temp(bi_context
*ctx
)
475 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
478 static inline unsigned
479 bi_make_temp_reg(bi_context
*ctx
)
481 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
484 /* Iterators for Bifrost IR */
486 #define bi_foreach_block(ctx, v) \
487 list_for_each_entry(pan_block, v, &ctx->blocks, link)
489 #define bi_foreach_block_from(ctx, from, v) \
490 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
492 #define bi_foreach_instr_in_block(block, v) \
493 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
495 #define bi_foreach_instr_in_block_rev(block, v) \
496 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
498 #define bi_foreach_instr_in_block_safe(block, v) \
499 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
501 #define bi_foreach_instr_in_block_safe_rev(block, v) \
502 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
504 #define bi_foreach_instr_in_block_from(block, v, from) \
505 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
507 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
508 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
510 #define bi_foreach_clause_in_block(block, v) \
511 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
513 #define bi_foreach_instr_global(ctx, v) \
514 bi_foreach_block(ctx, v_block) \
515 bi_foreach_instr_in_block((bi_block *) v_block, v)
517 #define bi_foreach_instr_global_safe(ctx, v) \
518 bi_foreach_block(ctx, v_block) \
519 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
521 /* Based on set_foreach, expanded with automatic type casts */
523 #define bi_foreach_predecessor(blk, v) \
524 struct set_entry *_entry_##v; \
526 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
527 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
528 _entry_##v != NULL; \
529 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
530 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
532 #define bi_foreach_src(ins, v) \
533 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
535 static inline bi_instruction
*
536 bi_prev_op(bi_instruction
*ins
)
538 return list_last_entry(&(ins
->link
), bi_instruction
, link
);
541 static inline bi_instruction
*
542 bi_next_op(bi_instruction
*ins
)
544 return list_first_entry(&(ins
->link
), bi_instruction
, link
);
547 static inline pan_block
*
548 pan_next_block(pan_block
*block
)
550 return list_first_entry(&(block
->link
), pan_block
, link
);
553 /* Special functions */
555 void bi_emit_fexp2(bi_context
*ctx
, nir_alu_instr
*instr
);
556 void bi_emit_flog2(bi_context
*ctx
, nir_alu_instr
*instr
);
558 /* BIR manipulation */
560 bool bi_has_outmod(bi_instruction
*ins
);
561 bool bi_has_source_mods(bi_instruction
*ins
);
562 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
563 bool bi_has_arg(bi_instruction
*ins
, unsigned arg
);
564 uint16_t bi_from_bytemask(uint16_t bytemask
, unsigned bytes
);
565 unsigned bi_get_component_count(bi_instruction
*ins
, signed s
);
566 uint16_t bi_bytemask_of_read_components(bi_instruction
*ins
, unsigned node
);
567 uint64_t bi_get_immediate(bi_instruction
*ins
, unsigned index
);
568 bool bi_writes_component(bi_instruction
*ins
, unsigned comp
);
569 unsigned bi_writemask(bi_instruction
*ins
);
573 void bi_lower_combine(bi_context
*ctx
, bi_block
*block
);
574 bool bi_opt_dead_code_eliminate(bi_context
*ctx
, bi_block
*block
);
575 void bi_schedule(bi_context
*ctx
);
576 void bi_register_allocate(bi_context
*ctx
);
580 void bi_compute_liveness(bi_context
*ctx
);
581 void bi_liveness_ins_update(uint16_t *live
, bi_instruction
*ins
, unsigned max
);
582 void bi_invalidate_liveness(bi_context
*ctx
);
583 bool bi_is_live_after(bi_context
*ctx
, bi_block
*block
, bi_instruction
*start
, int src
);
587 void bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
);