pan/bi: Add register allocator
[mesa.git] / src / panfrost / bifrost / compiler.h
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
29
30 #include "bifrost.h"
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
33
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
44 *
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
47 */
48
49 enum bi_class {
50 BI_ADD,
51 BI_ATEST,
52 BI_BRANCH,
53 BI_CMP,
54 BI_BLEND,
55 BI_BITWISE,
56 BI_CONVERT,
57 BI_CSEL,
58 BI_DISCARD,
59 BI_FMA,
60 BI_FREXP,
61 BI_ISUB,
62 BI_LOAD,
63 BI_LOAD_UNIFORM,
64 BI_LOAD_ATTR,
65 BI_LOAD_VAR,
66 BI_LOAD_VAR_ADDRESS,
67 BI_MINMAX,
68 BI_MOV,
69 BI_SHIFT,
70 BI_STORE,
71 BI_STORE_VAR,
72 BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
73 BI_SWIZZLE,
74 BI_TEX,
75 BI_ROUND,
76 BI_NUM_CLASSES
77 };
78
79 /* Properties of a class... */
80 extern unsigned bi_class_props[BI_NUM_CLASSES];
81
82 /* abs/neg/outmod valid for a float op */
83 #define BI_MODS (1 << 0)
84
85 /* Generic enough that little class-specific information is required. In other
86 * words, it acts as a "normal" ALU op, even if the encoding ends up being
87 * irregular enough to warrant a separate class */
88 #define BI_GENERIC (1 << 1)
89
90 /* Accepts a bifrost_roundmode */
91 #define BI_ROUNDMODE (1 << 2)
92
93 /* Can be scheduled to FMA */
94 #define BI_SCHED_FMA (1 << 3)
95
96 /* Can be scheduled to ADD */
97 #define BI_SCHED_ADD (1 << 4)
98
99 /* Most ALU ops can do either, actually */
100 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
101
102 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
103 * nopped out. Used for _FAST operations. */
104 #define BI_SCHED_SLOW (1 << 5)
105
106 /* Swizzling allowed for the 8/16-bit source */
107 #define BI_SWIZZLABLE (1 << 6)
108
109 /* For scheduling purposes this is a high latency instruction and must be at
110 * the end of a clause. Implies ADD */
111 #define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
112
113 /* Intrinsic is vectorized and should read 4 components regardless of writemask */
114 #define BI_VECTOR (1 << 8)
115
116 /* It can't get any worse than csel4... can it? */
117 #define BIR_SRC_COUNT 4
118
119 /* BI_LD_VARY */
120 struct bi_load_vary {
121 enum bifrost_interp_mode interp_mode;
122 bool reuse;
123 bool flat;
124 };
125
126 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
127 * the target. We forward declare bi_block since this is mildly circular (not
128 * strictly, but this order of the file makes more sense I think)
129 *
130 * We define our own enum of conditions since the conditions in the hardware
131 * packed in crazy ways that would make manipulation unweildly (meaning changes
132 * based on port swapping, etc), so we defer dealing with that until emit time.
133 * Likewise, we expose NIR types instead of the crazy branch types, although
134 * the restrictions do eventually apply of course. */
135
136 struct bi_block;
137
138 enum bi_cond {
139 BI_COND_ALWAYS,
140 BI_COND_LT,
141 BI_COND_LE,
142 BI_COND_GE,
143 BI_COND_GT,
144 BI_COND_EQ,
145 BI_COND_NE,
146 };
147
148 struct bi_branch {
149 /* Types are specified in src_types and must be compatible (either both
150 * int, or both float, 16/32, and same size or 32/16 if float. Types
151 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
152
153 enum bi_cond cond;
154 struct bi_block *target;
155 };
156
157 /* Opcodes within a class */
158 enum bi_minmax_op {
159 BI_MINMAX_MIN,
160 BI_MINMAX_MAX
161 };
162
163 enum bi_bitwise_op {
164 BI_BITWISE_AND,
165 BI_BITWISE_OR,
166 BI_BITWISE_XOR
167 };
168
169 enum bi_round_op {
170 BI_ROUND_MODE, /* use round mode */
171 BI_ROUND_ROUND /* i.e.: fround() */
172 };
173
174 enum bi_special_op {
175 BI_SPECIAL_FRCP,
176 BI_SPECIAL_FRSQ,
177 BI_SPECIAL_FATAN,
178 BI_SPECIAL_FSIN,
179 BI_SPECIAL_FCOS,
180 BI_SPECIAL_FEXP,
181 BI_SPECIAL_FLOG2,
182 BI_SPECIAL_FLOGE
183 };
184
185 typedef struct {
186 struct list_head link; /* Must be first */
187 enum bi_class type;
188
189 /* Indices, see bir_ssa_index etc. Note zero is special cased
190 * to "no argument" */
191 unsigned dest;
192 unsigned src[BIR_SRC_COUNT];
193
194 /* If one of the sources has BIR_INDEX_CONSTANT */
195 union {
196 uint64_t u64;
197 uint32_t u32;
198 uint16_t u16[2];
199 uint8_t u8[4];
200 } constant;
201
202 /* Floating-point modifiers, type/class permitting. If not
203 * allowed for the type/class, these are ignored. */
204 enum bifrost_outmod outmod;
205 bool src_abs[BIR_SRC_COUNT];
206 bool src_neg[BIR_SRC_COUNT];
207
208 /* Round mode (requires BI_ROUNDMODE) */
209 enum bifrost_roundmode roundmode;
210
211 /* Writemask (bit for each affected byte). This is quite restricted --
212 * ALU ops can only write to a single channel (exception: <32 in which
213 * you can write to 32/N contiguous aligned channels). Load/store can
214 * only write to all channels at once, in a sense. But it's still
215 * better to use this generic form than have synthetic ops flying
216 * about, since we're not essentially vector for RA purposes. */
217 uint16_t writemask;
218
219 /* Destination type. Usually the type of the instruction
220 * itself, but if sources and destination have different
221 * types, the type of the destination wins (so f2i would be
222 * int). Zero if there is no destination. Bitsize included */
223 nir_alu_type dest_type;
224
225 /* Source types if required by the class */
226 nir_alu_type src_types[BIR_SRC_COUNT];
227
228 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
229 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
230 * sense. On non-SIMD instructions, it can be used for component
231 * selection, so we don't have to special case extraction. */
232 uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
233
234 /* A class-specific op from which the actual opcode can be derived
235 * (along with the above information) */
236
237 union {
238 enum bi_minmax_op minmax;
239 enum bi_bitwise_op bitwise;
240 enum bi_round_op round;
241 enum bi_special_op special;
242 enum bi_cond compare;
243 } op;
244
245 /* Union for class-specific information */
246 union {
247 enum bifrost_minmax_mode minmax;
248 struct bi_load_vary load_vary;
249 struct bi_branch branch;
250
251 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
252 * sense here but you can always just use a move for that */
253 enum bi_cond csel_cond;
254
255 /* For BLEND -- the location 0-7 */
256 unsigned blend_location;
257 };
258 } bi_instruction;
259
260 /* Scheduling takes place in two steps. Step 1 groups instructions within a
261 * block into distinct clauses (bi_clause). Step 2 schedules instructions
262 * within a clause into FMA/ADD pairs (bi_bundle).
263 *
264 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
265 * leave it NULL; the emitter will fill in a nop.
266 */
267
268 typedef struct {
269 bi_instruction *fma;
270 bi_instruction *add;
271 } bi_bundle;
272
273 typedef struct {
274 struct list_head link;
275
276 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
277 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
278 * so a clause can have up to 16 bi_instructions. Whether bundles or
279 * instructions are used depends on where in scheduling we are. */
280
281 unsigned instruction_count;
282 unsigned bundle_count;
283
284 union {
285 bi_instruction *instructions[16];
286 bi_bundle bundles[8];
287 };
288
289 /* For scoreboarding -- the clause ID (this is not globally unique!)
290 * and its dependencies in terms of other clauses, computed during
291 * scheduling and used when emitting code. Dependencies expressed as a
292 * bitfield matching the hardware, except shifted by a clause (the
293 * shift back to the ISA's off-by-one encoding is worked out when
294 * emitting clauses) */
295 unsigned scoreboard_id;
296 uint8_t dependencies;
297
298 /* Back-to-back corresponds directly to the back-to-back bit. Branch
299 * conditional corresponds to the branch conditional bit except that in
300 * the emitted code it's always set if back-to-bit is, whereas we use
301 * the actual value (without back-to-back so to speak) internally */
302 bool back_to_back;
303 bool branch_conditional;
304
305 /* Corresponds to the usual bit but shifted by a clause */
306 bool data_register_write_barrier;
307
308 /* Constants read by this clause. ISA limit. */
309 uint64_t constants[8];
310 unsigned constant_count;
311 } bi_clause;
312
313 typedef struct bi_block {
314 pan_block base; /* must be first */
315
316 /* If true, uses clauses; if false, uses instructions */
317 bool scheduled;
318 struct list_head clauses; /* list of bi_clause */
319 } bi_block;
320
321 typedef struct {
322 nir_shader *nir;
323 gl_shader_stage stage;
324 struct list_head blocks; /* list of bi_block */
325 struct panfrost_sysvals sysvals;
326 uint32_t quirks;
327
328 /* During NIR->BIR */
329 nir_function_impl *impl;
330 bi_block *current_block;
331 unsigned block_name_count;
332 bi_block *after_block;
333 bi_block *break_block;
334 bi_block *continue_block;
335 bool emitted_atest;
336
337 /* For creating temporaries */
338 unsigned temp_alloc;
339
340 /* Analysis results */
341 bool has_liveness;
342
343 /* Stats for shader-db */
344 unsigned instruction_count;
345 unsigned loop_count;
346 } bi_context;
347
348 static inline bi_instruction *
349 bi_emit(bi_context *ctx, bi_instruction ins)
350 {
351 bi_instruction *u = rzalloc(ctx, bi_instruction);
352 memcpy(u, &ins, sizeof(ins));
353 list_addtail(&u->link, &ctx->current_block->base.instructions);
354 return u;
355 }
356
357 static inline void
358 bi_remove_instruction(bi_instruction *ins)
359 {
360 list_del(&ins->link);
361 }
362
363 /* So we can distinguish between SSA/reg/sentinel quickly */
364 #define BIR_NO_ARG (0)
365 #define BIR_IS_REG (1)
366
367 /* If high bits are set, instead of SSA/registers, we have specials indexed by
368 * the low bits if necessary.
369 *
370 * Fixed register: do not allocate register, do not collect $200.
371 * Uniform: access a uniform register given by low bits.
372 * Constant: access the specified constant
373 * Zero: special cased to avoid wasting a constant
374 */
375
376 #define BIR_INDEX_REGISTER (1 << 31)
377 #define BIR_INDEX_UNIFORM (1 << 30)
378 #define BIR_INDEX_CONSTANT (1 << 29)
379 #define BIR_INDEX_ZERO (1 << 28)
380
381 /* Keep me synced please so we can check src & BIR_SPECIAL */
382
383 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
384 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO))
385
386 static inline unsigned
387 bi_max_temp(bi_context *ctx)
388 {
389 unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
390 return ((alloc + 2 + ctx->temp_alloc) << 1);
391 }
392
393 static inline unsigned
394 bi_make_temp(bi_context *ctx)
395 {
396 return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
397 }
398
399 static inline unsigned
400 bi_make_temp_reg(bi_context *ctx)
401 {
402 return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
403 }
404
405 static inline unsigned
406 bir_ssa_index(nir_ssa_def *ssa)
407 {
408 /* Off-by-one ensures BIR_NO_ARG is skipped */
409 return ((ssa->index + 1) << 1) | 0;
410 }
411
412 static inline unsigned
413 bir_src_index(nir_src *src)
414 {
415 if (src->is_ssa)
416 return bir_ssa_index(src->ssa);
417 else {
418 assert(!src->reg.indirect);
419 return (src->reg.reg->index << 1) | BIR_IS_REG;
420 }
421 }
422
423 static inline unsigned
424 bir_dest_index(nir_dest *dst)
425 {
426 if (dst->is_ssa)
427 return bir_ssa_index(&dst->ssa);
428 else {
429 assert(!dst->reg.indirect);
430 return (dst->reg.reg->index << 1) | BIR_IS_REG;
431 }
432 }
433
434 /* Iterators for Bifrost IR */
435
436 #define bi_foreach_block(ctx, v) \
437 list_for_each_entry(pan_block, v, &ctx->blocks, link)
438
439 #define bi_foreach_block_from(ctx, from, v) \
440 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
441
442 #define bi_foreach_instr_in_block(block, v) \
443 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
444
445 #define bi_foreach_instr_in_block_rev(block, v) \
446 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
447
448 #define bi_foreach_instr_in_block_safe(block, v) \
449 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
450
451 #define bi_foreach_instr_in_block_safe_rev(block, v) \
452 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
453
454 #define bi_foreach_instr_in_block_from(block, v, from) \
455 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
456
457 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
458 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
459
460 #define bi_foreach_clause_in_block(block, v) \
461 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
462
463 #define bi_foreach_instr_global(ctx, v) \
464 bi_foreach_block(ctx, v_block) \
465 bi_foreach_instr_in_block((bi_block *) v_block, v)
466
467 #define bi_foreach_instr_global_safe(ctx, v) \
468 bi_foreach_block(ctx, v_block) \
469 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
470
471 /* Based on set_foreach, expanded with automatic type casts */
472
473 #define bi_foreach_predecessor(blk, v) \
474 struct set_entry *_entry_##v; \
475 bi_block *v; \
476 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
477 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
478 _entry_##v != NULL; \
479 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
480 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
481
482 #define bi_foreach_src(ins, v) \
483 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
484
485 static inline bi_instruction *
486 bi_prev_op(bi_instruction *ins)
487 {
488 return list_last_entry(&(ins->link), bi_instruction, link);
489 }
490
491 static inline bi_instruction *
492 bi_next_op(bi_instruction *ins)
493 {
494 return list_first_entry(&(ins->link), bi_instruction, link);
495 }
496
497 /* BIR manipulation */
498
499 bool bi_has_outmod(bi_instruction *ins);
500 bool bi_has_source_mods(bi_instruction *ins);
501 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
502 bool bi_has_arg(bi_instruction *ins, unsigned arg);
503 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
504 unsigned bi_get_component_count(bi_instruction *ins);
505 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
506
507 /* BIR passes */
508
509 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
510 void bi_schedule(bi_context *ctx);
511 void bi_register_allocate(bi_context *ctx);
512
513 /* Liveness */
514
515 void bi_compute_liveness(bi_context *ctx);
516 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
517 void bi_invalidate_liveness(bi_context *ctx);
518 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
519
520 #endif