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pan/bi: Pretty-print clause types in disassembler
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140
141 if (header.clause_type != 0) {
142 const char *name = bi_clause_type_name(header.clause_type);
143
144 if (name[0] == '?')
145 fprintf(fp, "unk%u ", header.clause_type);
146 else
147 fprintf(fp, "%s ", name);
148 }
149
150 if (header.scoreboard_deps != 0) {
151 fprintf(fp, "next-wait(");
152 bool first = true;
153 for (unsigned i = 0; i < 8; i++) {
154 if (header.scoreboard_deps & (1 << i)) {
155 if (!first) {
156 fprintf(fp, ", ");
157 }
158 fprintf(fp, "%d", i);
159 first = false;
160 }
161 }
162 fprintf(fp, ") ");
163 }
164
165 if (header.datareg_writebarrier)
166 fprintf(fp, "data-reg-barrier ");
167
168 if (!header.no_end_of_shader)
169 fprintf(fp, "eos ");
170
171 if (!header.back_to_back) {
172 fprintf(fp, "nbb ");
173 if (header.branch_cond)
174 fprintf(fp, "branch-cond ");
175 else
176 fprintf(fp, "branch-uncond ");
177 }
178
179 if (header.elide_writes)
180 fprintf(fp, "we ");
181
182 if (header.suppress_inf)
183 fprintf(fp, "suppress-inf ");
184 if (header.suppress_nan)
185 fprintf(fp, "suppress-nan ");
186
187 if (header.unk0)
188 fprintf(fp, "unk0 ");
189 if (header.unk1)
190 fprintf(fp, "unk1 ");
191 if (header.unk2)
192 fprintf(fp, "unk2 ");
193 if (header.unk3)
194 fprintf(fp, "unk3 ");
195 if (header.unk4)
196 fprintf(fp, "unk4 ");
197
198 fprintf(fp, "\n");
199
200 if (verbose) {
201 fprintf(fp, "# clause type %d, next clause type %d\n",
202 header.clause_type, header.next_clause_type);
203 }
204 }
205
206 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
207 {
208 struct bifrost_reg_ctrl decoded = {};
209 unsigned ctrl;
210 if (regs.ctrl == 0) {
211 ctrl = regs.reg1 >> 2;
212 decoded.read_reg0 = !(regs.reg1 & 0x2);
213 decoded.read_reg1 = false;
214 } else {
215 ctrl = regs.ctrl;
216 decoded.read_reg0 = decoded.read_reg1 = true;
217 }
218 switch (ctrl) {
219 case 1:
220 decoded.fma_write_unit = REG_WRITE_TWO;
221 break;
222 case 2:
223 case 3:
224 decoded.fma_write_unit = REG_WRITE_TWO;
225 decoded.read_reg3 = true;
226 break;
227 case 4:
228 decoded.read_reg3 = true;
229 break;
230 case 5:
231 decoded.add_write_unit = REG_WRITE_TWO;
232 break;
233 case 6:
234 decoded.add_write_unit = REG_WRITE_TWO;
235 decoded.read_reg3 = true;
236 break;
237 case 8:
238 decoded.clause_start = true;
239 break;
240 case 9:
241 decoded.fma_write_unit = REG_WRITE_TWO;
242 decoded.clause_start = true;
243 break;
244 case 11:
245 break;
246 case 12:
247 decoded.read_reg3 = true;
248 decoded.clause_start = true;
249 break;
250 case 13:
251 decoded.add_write_unit = REG_WRITE_TWO;
252 decoded.clause_start = true;
253 break;
254
255 case 7:
256 case 15:
257 decoded.fma_write_unit = REG_WRITE_THREE;
258 decoded.add_write_unit = REG_WRITE_TWO;
259 break;
260 default:
261 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
262 }
263
264 return decoded;
265 }
266
267 // Pass in the add_write_unit or fma_write_unit, and this returns which register
268 // the ADD/FMA units are writing to
269 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
270 {
271 switch (unit) {
272 case REG_WRITE_TWO:
273 return regs.reg2;
274 case REG_WRITE_THREE:
275 return regs.reg3;
276 default: /* REG_WRITE_NONE */
277 assert(0);
278 return 0;
279 }
280 }
281
282 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
283 {
284 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
285 fprintf(fp, "# ");
286 if (ctrl.read_reg0)
287 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
288 if (ctrl.read_reg1)
289 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
290
291 if (ctrl.fma_write_unit == REG_WRITE_TWO)
292 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
293 else if (ctrl.add_write_unit == REG_WRITE_TWO)
294 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
295
296 if (ctrl.fma_write_unit == REG_WRITE_THREE)
297 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
298 else if (ctrl.add_write_unit == REG_WRITE_THREE)
299 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
300 else if (ctrl.read_reg3)
301 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
302
303 if (srcs.uniform_const) {
304 if (srcs.uniform_const & 0x80) {
305 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
306 }
307 }
308
309 fprintf(fp, "\n");
310 }
311 static void dump_const_imm(FILE *fp, uint32_t imm)
312 {
313 union {
314 float f;
315 uint32_t i;
316 } fi;
317 fi.i = imm;
318 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
319 }
320
321 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
322 {
323 unsigned low_bits = srcs.uniform_const & 0xf;
324 uint64_t imm;
325 switch (srcs.uniform_const >> 4) {
326 case 4:
327 imm = consts[0];
328 break;
329 case 5:
330 imm = consts[1];
331 break;
332 case 6:
333 imm = consts[2];
334 break;
335 case 7:
336 imm = consts[3];
337 break;
338 case 2:
339 imm = consts[4];
340 break;
341 case 3:
342 imm = consts[5];
343 break;
344 default:
345 assert(0);
346 break;
347 }
348 return imm | low_bits;
349 }
350
351 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
352 {
353 if (srcs.uniform_const & 0x80) {
354 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
355 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
356 } else if (srcs.uniform_const >= 0x20) {
357 uint64_t imm = get_const(consts, srcs);
358 if (high32)
359 dump_const_imm(fp, imm >> 32);
360 else
361 dump_const_imm(fp, imm);
362 } else {
363 switch (srcs.uniform_const) {
364 case 0:
365 fprintf(fp, "0");
366 break;
367 case 5:
368 fprintf(fp, "atest-data");
369 break;
370 case 6:
371 fprintf(fp, "sample-ptr");
372 break;
373 case 8:
374 case 9:
375 case 10:
376 case 11:
377 case 12:
378 case 13:
379 case 14:
380 case 15:
381 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
382 break;
383 default:
384 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
385 break;
386 }
387
388 if (high32)
389 fprintf(fp, ".y");
390 else
391 fprintf(fp, ".x");
392 }
393 }
394
395 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
396 {
397 switch (src) {
398 case 0:
399 fprintf(fp, "R%d", get_reg0(srcs));
400 break;
401 case 1:
402 fprintf(fp, "R%d", get_reg1(srcs));
403 break;
404 case 2:
405 fprintf(fp, "R%d", srcs.reg3);
406 break;
407 case 3:
408 if (isFMA)
409 fprintf(fp, "0");
410 else
411 fprintf(fp, "T"); // i.e. the output of FMA this cycle
412 break;
413 case 4:
414 dump_uniform_const_src(fp, srcs, consts, false);
415 break;
416 case 5:
417 dump_uniform_const_src(fp, srcs, consts, true);
418 break;
419 case 6:
420 fprintf(fp, "T0");
421 break;
422 case 7:
423 fprintf(fp, "T1");
424 break;
425 }
426 }
427
428 static const struct fma_op_info FMAOpInfos[] = {
429 { false, 0x00000, "FMA.f32", FMA_FMA },
430 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
431 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
432 { false, 0x48000, "FCMP.GL", FMA_FCMP },
433 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
434 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
435 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
436 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
437 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
438 { false, 0x58000, "ADD.f32", FMA_FADD },
439 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
440 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
441 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
442 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
443 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
444 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
445 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
446 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
447 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
448 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
449 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
450 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
451 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
452 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
453 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
454 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
455 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
456 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
457 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
458 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
459 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
460 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
461 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
462 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
463 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
464 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
465 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
466 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
467 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
468 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
469 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
470 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
471 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
472 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
473 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
474 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
475 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
476 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
477 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
478 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
479 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
480 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
481 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
482 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
483 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
484 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
485 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
486 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
487 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
488 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
489 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
490 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
491 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
492 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
493 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
494 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
495 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
496 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
497 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
498 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
499 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
500 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
501 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
502 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
503 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
504 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
505 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
506 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
507 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
508 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
509 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
510 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
511 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
512 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
513 { true, 0x0032c, "NOP", FMA_ONE_SRC },
514 { true, 0x0032d, "MOV", FMA_ONE_SRC },
515 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
516 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
517 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
518 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
519 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
520 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
521 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
522 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
523 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
524 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
525 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
526 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
527 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
528 { true, 0x00ec5, "ROUND", FMA_ONE_SRC },
529 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
530 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
531 { true, 0x01805, "ROUNDEVEN", FMA_ONE_SRC },
532 { true, 0x01845, "CEIL", FMA_ONE_SRC },
533 { true, 0x01885, "FLOOR", FMA_ONE_SRC },
534 { true, 0x018c5, "TRUNC", FMA_ONE_SRC },
535 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
536 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
537 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
538 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
539 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
540 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
541 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
542 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
543 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
544 { true, 0x00800, "IMAD", FMA_THREE_SRC },
545 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
546 };
547
548 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
549 {
550 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
551 unsigned opCmp = ~0;
552
553 if (FMAOpInfos[i].extended != extended)
554 continue;
555
556 if (extended)
557 op &= ~0xe0000;
558
559 switch (FMAOpInfos[i].src_type) {
560 case FMA_ONE_SRC:
561 opCmp = op;
562 break;
563 case FMA_TWO_SRC:
564 opCmp = op & ~0x7;
565 break;
566 case FMA_FCMP:
567 case FMA_FCMP16:
568 opCmp = op & ~0x1fff;
569 break;
570 case FMA_THREE_SRC:
571 case FMA_SHIFT_ADD64:
572 opCmp = op & ~0x3f;
573 break;
574 case FMA_FADD:
575 case FMA_FMINMAX:
576 case FMA_FADD16:
577 case FMA_FMINMAX16:
578 opCmp = op & ~0x3fff;
579 break;
580 case FMA_FMA:
581 case FMA_FMA16:
582 opCmp = op & ~0x3ffff;
583 break;
584 case FMA_CSEL4:
585 case FMA_SHIFT:
586 opCmp = op & ~0xfff;
587 break;
588 case FMA_FMA_MSCALE:
589 opCmp = op & ~0x7fff;
590 break;
591 default:
592 opCmp = ~0;
593 break;
594 }
595 if (FMAOpInfos[i].op == opCmp)
596 return FMAOpInfos[i];
597 }
598
599 struct fma_op_info info;
600 snprintf(info.name, sizeof(info.name), "op%04x", op);
601 info.op = op;
602 info.src_type = FMA_THREE_SRC;
603 return info;
604 }
605
606 static void dump_fcmp(FILE *fp, unsigned op)
607 {
608 switch (op) {
609 case 0:
610 fprintf(fp, ".OEQ");
611 break;
612 case 1:
613 fprintf(fp, ".OGT");
614 break;
615 case 2:
616 fprintf(fp, ".OGE");
617 break;
618 case 3:
619 fprintf(fp, ".UNE");
620 break;
621 case 4:
622 fprintf(fp, ".OLT");
623 break;
624 case 5:
625 fprintf(fp, ".OLE");
626 break;
627 default:
628 fprintf(fp, ".unk%d", op);
629 break;
630 }
631 }
632
633 static void dump_16swizzle(FILE *fp, unsigned swiz)
634 {
635 if (swiz == 2)
636 return;
637 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
638 }
639
640 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
641 {
642 switch (ctrl) {
643 case 3:
644 case 4:
645 case 6:
646 fprintf(fp, ".x");
647 break;
648 case 5:
649 case 7:
650 fprintf(fp, ".y");
651 break;
652 case 0:
653 case 1:
654 case 2:
655 break;
656 default:
657 fprintf(fp, ".unk");
658 break;
659 }
660 }
661
662 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
663 {
664 switch (ctrl) {
665 case 1:
666 case 3:
667 fprintf(fp, ".x");
668 break;
669 case 2:
670 case 4:
671 case 5:
672 fprintf(fp, ".y");
673 break;
674 case 0:
675 case 6:
676 case 7:
677 break;
678 default:
679 fprintf(fp, ".unk");
680 break;
681 }
682 }
683
684 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
685 {
686 if (verbose) {
687 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
688 }
689 struct bifrost_fma_inst FMA;
690 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
691 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
692
693 fprintf(fp, "%s", info.name);
694 if (info.src_type == FMA_FADD ||
695 info.src_type == FMA_FMINMAX ||
696 info.src_type == FMA_FMA ||
697 info.src_type == FMA_FADD16 ||
698 info.src_type == FMA_FMINMAX16 ||
699 info.src_type == FMA_FMA16) {
700 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
701 switch (info.src_type) {
702 case FMA_FADD:
703 case FMA_FMA:
704 case FMA_FADD16:
705 case FMA_FMA16:
706 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
707 break;
708 case FMA_FMINMAX:
709 case FMA_FMINMAX16:
710 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
711 break;
712 default:
713 assert(0);
714 }
715 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
716 dump_fcmp(fp, bits(FMA.op, 10, 13));
717 if (info.src_type == FMA_FCMP)
718 fprintf(fp, ".f32");
719 else
720 fprintf(fp, ".v2f16");
721 } else if (info.src_type == FMA_FMA_MSCALE) {
722 if (FMA.op & (1 << 11)) {
723 switch ((FMA.op >> 9) & 0x3) {
724 case 0:
725 /* This mode seems to do a few things:
726 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
727 * since generating a nan would poison the result of
728 * 1/infinity and 1/0.
729 * - Fiddles with which nan is returned in nan * nan,
730 * presumably to make sure that the same exact nan is
731 * returned for 1/nan.
732 */
733 fprintf(fp, ".rcp_mode");
734 break;
735 case 3:
736 /* Similar to the above, but src0 always wins when multiplying
737 * 0 by infinity.
738 */
739 fprintf(fp, ".sqrt_mode");
740 break;
741 default:
742 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
743 }
744 } else {
745 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
746 }
747 } else if (info.src_type == FMA_SHIFT) {
748 struct bifrost_shift_fma shift;
749 memcpy(&shift, &FMA, sizeof(shift));
750
751 if (shift.half == 0x7)
752 fprintf(fp, ".v2i16");
753 else if (shift.half == 0)
754 fprintf(fp, ".i32");
755 else if (shift.half == 0x4)
756 fprintf(fp, ".v4i8");
757 else
758 fprintf(fp, ".unk%u", shift.half);
759
760 if (!shift.unk)
761 fprintf(fp, ".no_unk");
762
763 if (shift.invert_1)
764 fprintf(fp, ".invert_1");
765
766 if (shift.invert_2)
767 fprintf(fp, ".invert_2");
768 }
769
770 fprintf(fp, " ");
771
772 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
773 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
774 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
775 } else {
776 fprintf(fp, "T0, ");
777 }
778
779 switch (info.src_type) {
780 case FMA_ONE_SRC:
781 dump_src(fp, FMA.src0, regs, consts, true);
782 break;
783 case FMA_TWO_SRC:
784 dump_src(fp, FMA.src0, regs, consts, true);
785 fprintf(fp, ", ");
786 dump_src(fp, FMA.op & 0x7, regs, consts, true);
787 break;
788 case FMA_FADD:
789 case FMA_FMINMAX:
790 if (FMA.op & 0x10)
791 fprintf(fp, "-");
792 if (FMA.op & 0x200)
793 fprintf(fp, "abs(");
794 dump_src(fp, FMA.src0, regs, consts, true);
795 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
796 if (FMA.op & 0x200)
797 fprintf(fp, ")");
798 fprintf(fp, ", ");
799 if (FMA.op & 0x20)
800 fprintf(fp, "-");
801 if (FMA.op & 0x8)
802 fprintf(fp, "abs(");
803 dump_src(fp, FMA.op & 0x7, regs, consts, true);
804 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
805 if (FMA.op & 0x8)
806 fprintf(fp, ")");
807 break;
808 case FMA_FADD16:
809 case FMA_FMINMAX16: {
810 bool abs1 = FMA.op & 0x8;
811 bool abs2 = (FMA.op & 0x7) < FMA.src0;
812 if (FMA.op & 0x10)
813 fprintf(fp, "-");
814 if (abs1 || abs2)
815 fprintf(fp, "abs(");
816 dump_src(fp, FMA.src0, regs, consts, true);
817 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
818 if (abs1 || abs2)
819 fprintf(fp, ")");
820 fprintf(fp, ", ");
821 if (FMA.op & 0x20)
822 fprintf(fp, "-");
823 if (abs1 && abs2)
824 fprintf(fp, "abs(");
825 dump_src(fp, FMA.op & 0x7, regs, consts, true);
826 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
827 if (abs1 && abs2)
828 fprintf(fp, ")");
829 break;
830 }
831 case FMA_FCMP:
832 if (FMA.op & 0x200)
833 fprintf(fp, "abs(");
834 dump_src(fp, FMA.src0, regs, consts, true);
835 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
836 if (FMA.op & 0x200)
837 fprintf(fp, ")");
838 fprintf(fp, ", ");
839 if (FMA.op & 0x20)
840 fprintf(fp, "-");
841 if (FMA.op & 0x8)
842 fprintf(fp, "abs(");
843 dump_src(fp, FMA.op & 0x7, regs, consts, true);
844 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
845 if (FMA.op & 0x8)
846 fprintf(fp, ")");
847 break;
848 case FMA_FCMP16:
849 dump_src(fp, FMA.src0, regs, consts, true);
850 // Note: this is kinda a guess, I haven't seen the blob set this to
851 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
852 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
853 fprintf(fp, ", ");
854 dump_src(fp, FMA.op & 0x7, regs, consts, true);
855 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
856 break;
857 case FMA_SHIFT_ADD64:
858 dump_src(fp, FMA.src0, regs, consts, true);
859 fprintf(fp, ", ");
860 dump_src(fp, FMA.op & 0x7, regs, consts, true);
861 fprintf(fp, ", ");
862 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
863 break;
864 case FMA_THREE_SRC:
865 dump_src(fp, FMA.src0, regs, consts, true);
866 fprintf(fp, ", ");
867 dump_src(fp, FMA.op & 0x7, regs, consts, true);
868 fprintf(fp, ", ");
869 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
870 break;
871 case FMA_SHIFT: {
872 struct bifrost_shift_fma shift;
873 memcpy(&shift, &FMA, sizeof(shift));
874
875 dump_src(fp, shift.src0, regs, consts, true);
876 fprintf(fp, ", ");
877 dump_src(fp, shift.src1, regs, consts, true);
878 fprintf(fp, ", ");
879 dump_src(fp, shift.src2, regs, consts, true);
880 break;
881 }
882 case FMA_FMA:
883 if (FMA.op & (1 << 14))
884 fprintf(fp, "-");
885 if (FMA.op & (1 << 9))
886 fprintf(fp, "abs(");
887 dump_src(fp, FMA.src0, regs, consts, true);
888 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
889 if (FMA.op & (1 << 9))
890 fprintf(fp, ")");
891 fprintf(fp, ", ");
892 if (FMA.op & (1 << 16))
893 fprintf(fp, "abs(");
894 dump_src(fp, FMA.op & 0x7, regs, consts, true);
895 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
896 if (FMA.op & (1 << 16))
897 fprintf(fp, ")");
898 fprintf(fp, ", ");
899 if (FMA.op & (1 << 15))
900 fprintf(fp, "-");
901 if (FMA.op & (1 << 17))
902 fprintf(fp, "abs(");
903 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
904 if (FMA.op & (1 << 17))
905 fprintf(fp, ")");
906 break;
907 case FMA_FMA16:
908 if (FMA.op & (1 << 14))
909 fprintf(fp, "-");
910 dump_src(fp, FMA.src0, regs, consts, true);
911 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
912 fprintf(fp, ", ");
913 dump_src(fp, FMA.op & 0x7, regs, consts, true);
914 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
915 fprintf(fp, ", ");
916 if (FMA.op & (1 << 15))
917 fprintf(fp, "-");
918 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
919 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
920 break;
921 case FMA_CSEL4: {
922 struct bifrost_csel4 csel;
923 memcpy(&csel, &FMA, sizeof(csel));
924 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
925
926 dump_src(fp, csel.src0, regs, consts, true);
927 fprintf(fp, ", ");
928 dump_src(fp, csel.src1, regs, consts, true);
929 fprintf(fp, ", ");
930 dump_src(fp, csel.src2, regs, consts, true);
931 fprintf(fp, ", ");
932 dump_src(fp, csel.src3, regs, consts, true);
933 break;
934 }
935 case FMA_FMA_MSCALE:
936 if (FMA.op & (1 << 12))
937 fprintf(fp, "abs(");
938 dump_src(fp, FMA.src0, regs, consts, true);
939 if (FMA.op & (1 << 12))
940 fprintf(fp, ")");
941 fprintf(fp, ", ");
942 if (FMA.op & (1 << 13))
943 fprintf(fp, "-");
944 dump_src(fp, FMA.op & 0x7, regs, consts, true);
945 fprintf(fp, ", ");
946 if (FMA.op & (1 << 14))
947 fprintf(fp, "-");
948 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
949 fprintf(fp, ", ");
950 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
951 break;
952 }
953 fprintf(fp, "\n");
954 }
955
956 static const struct add_op_info add_op_infos[] = {
957 { 0x00000, "MAX.f32", ADD_FMINMAX },
958 { 0x02000, "MIN.f32", ADD_FMINMAX },
959 { 0x04000, "ADD.f32", ADD_FADD },
960 { 0x06000, "FCMP.GL", ADD_FCMP },
961 { 0x07000, "FCMP.D3D", ADD_FCMP },
962 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
963 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
964 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
965 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
966 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
967 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
968 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
969 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
970 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
971 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
972 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
973 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
974 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
975 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
976 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
977 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
978 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
979 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
980 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
981 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
982 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
983 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
984 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
985 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
986 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
987 { 0x07b2c, "NOP", ADD_ONE_SRC },
988 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
989 { 0x07b2d, "MOV", ADD_ONE_SRC },
990 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
991 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
992 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
993 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
994 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
995 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
996 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
997 { 0x07d45, "CEIL", ADD_ONE_SRC },
998 { 0x07d85, "FLOOR", ADD_ONE_SRC },
999 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
1000 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1001 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1002 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1003 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1004 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1005 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1006 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1007 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1008 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1009 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1010 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1011 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1012 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1013 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1014 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1015 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1016 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1017 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1018 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1019 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1020 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1021 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1022 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1023 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1024 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1025 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1026 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1027 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1028 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1029 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1030 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1031 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1032 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1033 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1034 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1035 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1036 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1037 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1038 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1039 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1040 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1041 { 0x0d000, "BRANCH", ADD_BRANCH },
1042 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1043 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1044 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1045 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1046 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1047 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1048 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1049 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1050 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1051 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1052 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1053 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1054 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1055 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1056 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1057 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1058 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1059 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1060 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1061 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1062 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1063 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1064 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1065 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1066 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1067 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1068 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1069 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1070 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1071 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1072 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1073 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1074 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, true },
1075 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
1076 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
1077 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1078 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
1079 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
1080 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1081 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1082 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1083 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1084 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1085 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1086 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1087 { 0x1952c, "BLEND", ADD_BLENDING, true },
1088 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1089 { 0x1ae60, "TEX", ADD_TEX, true },
1090 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1091 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1092 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1093 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1094 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1095 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1096 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1097 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1098 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1099 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1100 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1101 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1102 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1103 };
1104
1105 static struct add_op_info find_add_op_info(unsigned op)
1106 {
1107 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1108 unsigned opCmp = ~0;
1109 switch (add_op_infos[i].src_type) {
1110 case ADD_ONE_SRC:
1111 case ADD_BLENDING:
1112 opCmp = op;
1113 break;
1114 case ADD_TWO_SRC:
1115 opCmp = op & ~0x7;
1116 break;
1117 case ADD_THREE_SRC:
1118 opCmp = op & ~0x3f;
1119 break;
1120 case ADD_SHIFT:
1121 opCmp = op & ~0x3ff;
1122 break;
1123 case ADD_TEX:
1124 opCmp = op & ~0xf;
1125 break;
1126 case ADD_FADD:
1127 case ADD_FMINMAX:
1128 case ADD_FADD16:
1129 opCmp = op & ~0x1fff;
1130 break;
1131 case ADD_FMINMAX16:
1132 case ADD_FADDMscale:
1133 opCmp = op & ~0xfff;
1134 break;
1135 case ADD_FCMP:
1136 case ADD_FCMP16:
1137 opCmp = op & ~0x7ff;
1138 break;
1139 case ADD_TEX_COMPACT:
1140 opCmp = op & ~0x3ff;
1141 break;
1142 case ADD_VARYING_INTERP:
1143 opCmp = op & ~0x7ff;
1144 break;
1145 case ADD_VARYING_ADDRESS:
1146 opCmp = op & ~0xfff;
1147 break;
1148 case ADD_LOAD_ATTR:
1149 case ADD_BRANCH:
1150 opCmp = op & ~0xfff;
1151 break;
1152 default:
1153 opCmp = ~0;
1154 break;
1155 }
1156 if (add_op_infos[i].op == opCmp)
1157 return add_op_infos[i];
1158 }
1159
1160 struct add_op_info info;
1161 snprintf(info.name, sizeof(info.name), "op%04x", op);
1162 info.op = op;
1163 info.src_type = ADD_TWO_SRC;
1164 info.has_data_reg = true;
1165 return info;
1166 }
1167
1168 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1169 struct bifrost_regs next_regs, uint64_t *consts,
1170 unsigned data_reg, unsigned offset, bool verbose)
1171 {
1172 if (verbose) {
1173 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1174 }
1175 struct bifrost_add_inst ADD;
1176 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1177 struct add_op_info info = find_add_op_info(ADD.op);
1178
1179 fprintf(fp, "%s", info.name);
1180
1181 // float16 seems like it doesn't support output modifiers
1182 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1183 // output modifiers
1184 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1185 if (info.src_type == ADD_FADD)
1186 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1187 else
1188 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1189 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1190 dump_fcmp(fp, bits(ADD.op, 3, 6));
1191 if (info.src_type == ADD_FCMP)
1192 fprintf(fp, ".f32");
1193 else
1194 fprintf(fp, ".v2f16");
1195 } else if (info.src_type == ADD_FADDMscale) {
1196 switch ((ADD.op >> 6) & 0x7) {
1197 case 0:
1198 break;
1199 // causes GPU hangs on G71
1200 case 1:
1201 fprintf(fp, ".invalid");
1202 break;
1203 // Same as usual outmod value.
1204 case 2:
1205 fprintf(fp, ".clamp_0_1");
1206 break;
1207 // If src0 is infinite or NaN, flush it to zero so that the other
1208 // source is passed through unmodified.
1209 case 3:
1210 fprintf(fp, ".flush_src0_inf_nan");
1211 break;
1212 // Vice versa.
1213 case 4:
1214 fprintf(fp, ".flush_src1_inf_nan");
1215 break;
1216 // Every other case seems to behave the same as the above?
1217 default:
1218 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1219 break;
1220 }
1221 } else if (info.src_type == ADD_VARYING_INTERP) {
1222 if (ADD.op & 0x200)
1223 fprintf(fp, ".reuse");
1224 if (ADD.op & 0x400)
1225 fprintf(fp, ".flat");
1226 fprintf(fp, "%s", bi_interp_mode_name((ADD.op >> 7) & 0x3));
1227 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1228 } else if (info.src_type == ADD_BRANCH) {
1229 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1230 if (branchCode == BR_ALWAYS) {
1231 // unconditional branch
1232 } else {
1233 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1234 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1235 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1236 // See the comment in branch_bit_size
1237 if (size == BR_SIZE_16YX0)
1238 portSwapped = true;
1239 if (size == BR_SIZE_16YX1)
1240 portSwapped = false;
1241 // These sizes are only for floating point comparisons, so the
1242 // non-floating-point comparisons are reused to encode the flipped
1243 // versions.
1244 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1245 portSwapped = false;
1246 // There's only one argument, so we reuse the extra argument to
1247 // encode this.
1248 if (size == BR_SIZE_ZERO)
1249 portSwapped = !(ADD.op & 1);
1250
1251 switch (cond) {
1252 case BR_COND_LT:
1253 if (portSwapped)
1254 fprintf(fp, ".LT.u");
1255 else
1256 fprintf(fp, ".LT.i");
1257 break;
1258 case BR_COND_LE:
1259 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1260 fprintf(fp, ".UNE.f");
1261 } else {
1262 if (portSwapped)
1263 fprintf(fp, ".LE.u");
1264 else
1265 fprintf(fp, ".LE.i");
1266 }
1267 break;
1268 case BR_COND_GT:
1269 if (portSwapped)
1270 fprintf(fp, ".GT.u");
1271 else
1272 fprintf(fp, ".GT.i");
1273 break;
1274 case BR_COND_GE:
1275 if (portSwapped)
1276 fprintf(fp, ".GE.u");
1277 else
1278 fprintf(fp, ".GE.i");
1279 break;
1280 case BR_COND_EQ:
1281 if (portSwapped)
1282 fprintf(fp, ".NE.i");
1283 else
1284 fprintf(fp, ".EQ.i");
1285 break;
1286 case BR_COND_OEQ:
1287 if (portSwapped)
1288 fprintf(fp, ".UNE.f");
1289 else
1290 fprintf(fp, ".OEQ.f");
1291 break;
1292 case BR_COND_OGT:
1293 if (portSwapped)
1294 fprintf(fp, ".OGT.unk.f");
1295 else
1296 fprintf(fp, ".OGT.f");
1297 break;
1298 case BR_COND_OLT:
1299 if (portSwapped)
1300 fprintf(fp, ".OLT.unk.f");
1301 else
1302 fprintf(fp, ".OLT.f");
1303 break;
1304 }
1305 switch (size) {
1306 case BR_SIZE_32:
1307 case BR_SIZE_32_AND_16X:
1308 case BR_SIZE_32_AND_16Y:
1309 fprintf(fp, "32");
1310 break;
1311 case BR_SIZE_16XX:
1312 case BR_SIZE_16YY:
1313 case BR_SIZE_16YX0:
1314 case BR_SIZE_16YX1:
1315 fprintf(fp, "16");
1316 break;
1317 case BR_SIZE_ZERO: {
1318 unsigned ctrl = (ADD.op >> 1) & 0x3;
1319 if (ctrl == 0)
1320 fprintf(fp, "32.Z");
1321 else
1322 fprintf(fp, "16.Z");
1323 break;
1324 }
1325 }
1326 }
1327 } else if (info.src_type == ADD_SHIFT) {
1328 struct bifrost_shift_add shift;
1329 memcpy(&shift, &ADD, sizeof(ADD));
1330
1331 if (shift.invert_1)
1332 fprintf(fp, ".invert_1");
1333
1334 if (shift.invert_2)
1335 fprintf(fp, ".invert_2");
1336
1337 if (shift.zero)
1338 fprintf(fp, ".unk%u", shift.zero);
1339 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1340 struct bifrost_ld_var_addr ld;
1341 memcpy(&ld, &ADD, sizeof(ADD));
1342 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1343 } else if (info.src_type == ADD_LOAD_ATTR) {
1344 struct bifrost_ld_attr ld;
1345 memcpy(&ld, &ADD, sizeof(ADD));
1346
1347 if (ld.channels)
1348 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1349 else
1350 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1351 }
1352
1353 fprintf(fp, " ");
1354
1355 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1356 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1357 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1358 } else {
1359 fprintf(fp, "T1, ");
1360 }
1361
1362 switch (info.src_type) {
1363 case ADD_BLENDING:
1364 // Note: in this case, regs.uniform_const == location | 0x8
1365 // This probably means we can't load uniforms or immediates in the
1366 // same instruction. This re-uses the encoding that normally means
1367 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1368 // 0x8 or'd in indicates this is happening.
1369 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1370 // fallthrough
1371 case ADD_ONE_SRC:
1372 dump_src(fp, ADD.src0, regs, consts, false);
1373 break;
1374 case ADD_TEX:
1375 case ADD_TEX_COMPACT: {
1376 int tex_index;
1377 int sampler_index;
1378 bool dualTex = false;
1379 if (info.src_type == ADD_TEX_COMPACT) {
1380 tex_index = (ADD.op >> 3) & 0x7;
1381 sampler_index = (ADD.op >> 7) & 0x7;
1382 bool unknown = (ADD.op & 0x40);
1383 // TODO: figure out if the unknown bit is ever 0
1384 if (!unknown)
1385 fprintf(fp, "unknown ");
1386 } else {
1387 uint64_t constVal = get_const(consts, regs);
1388 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1389 struct bifrost_tex_ctrl ctrl;
1390 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1391
1392 // TODO: figure out what actually triggers dual-tex
1393 if (ctrl.result_type == 9) {
1394 struct bifrost_dual_tex_ctrl dualCtrl;
1395 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1396 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1397 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1398 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1399 if (dualCtrl.unk0 != 3)
1400 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1401 dualTex = true;
1402 } else {
1403 if (ctrl.no_merge_index) {
1404 tex_index = ctrl.tex_index;
1405 sampler_index = ctrl.sampler_index;
1406 } else {
1407 tex_index = sampler_index = ctrl.tex_index;
1408 unsigned unk = ctrl.sampler_index >> 2;
1409 if (unk != 3)
1410 fprintf(fp, "unk:%d ", unk);
1411 if (ctrl.sampler_index & 1)
1412 tex_index = -1;
1413 if (ctrl.sampler_index & 2)
1414 sampler_index = -1;
1415 }
1416
1417 if (ctrl.unk0 != 3)
1418 fprintf(fp, "unk0:%d ", ctrl.unk0);
1419 if (ctrl.unk1)
1420 fprintf(fp, "unk1 ");
1421 if (ctrl.unk2 != 0xf)
1422 fprintf(fp, "unk2:%x ", ctrl.unk2);
1423
1424 switch (ctrl.result_type) {
1425 case 0x4:
1426 fprintf(fp, "f32 ");
1427 break;
1428 case 0xe:
1429 fprintf(fp, "i32 ");
1430 break;
1431 case 0xf:
1432 fprintf(fp, "u32 ");
1433 break;
1434 default:
1435 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1436 }
1437
1438 switch (ctrl.tex_type) {
1439 case 0:
1440 fprintf(fp, "cube ");
1441 break;
1442 case 1:
1443 fprintf(fp, "buffer ");
1444 break;
1445 case 2:
1446 fprintf(fp, "2D ");
1447 break;
1448 case 3:
1449 fprintf(fp, "3D ");
1450 break;
1451 }
1452
1453 if (ctrl.is_shadow)
1454 fprintf(fp, "shadow ");
1455 if (ctrl.is_array)
1456 fprintf(fp, "array ");
1457
1458 if (!ctrl.filter) {
1459 if (ctrl.calc_gradients) {
1460 int comp = (controlBits >> 20) & 0x3;
1461 fprintf(fp, "txg comp:%d ", comp);
1462 } else {
1463 fprintf(fp, "txf ");
1464 }
1465 } else {
1466 if (!ctrl.not_supply_lod) {
1467 if (ctrl.compute_lod)
1468 fprintf(fp, "lod_bias ");
1469 else
1470 fprintf(fp, "lod ");
1471 }
1472
1473 if (!ctrl.calc_gradients)
1474 fprintf(fp, "grad ");
1475 }
1476
1477 if (ctrl.texel_offset)
1478 fprintf(fp, "offset ");
1479 }
1480 }
1481
1482 if (!dualTex) {
1483 if (tex_index == -1)
1484 fprintf(fp, "tex:indirect ");
1485 else
1486 fprintf(fp, "tex:%d ", tex_index);
1487
1488 if (sampler_index == -1)
1489 fprintf(fp, "samp:indirect ");
1490 else
1491 fprintf(fp, "samp:%d ", sampler_index);
1492 }
1493 break;
1494 }
1495 case ADD_VARYING_INTERP: {
1496 unsigned addr = ADD.op & 0x1f;
1497 if (addr < 0b10100) {
1498 // direct addr
1499 fprintf(fp, "%d", addr);
1500 } else if (addr < 0b11000) {
1501 if (addr == 22)
1502 fprintf(fp, "fragw");
1503 else if (addr == 23)
1504 fprintf(fp, "fragz");
1505 else
1506 fprintf(fp, "unk%d", addr);
1507 } else {
1508 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1509 }
1510 fprintf(fp, ", ");
1511 dump_src(fp, ADD.src0, regs, consts, false);
1512 break;
1513 }
1514 case ADD_VARYING_ADDRESS: {
1515 dump_src(fp, ADD.src0, regs, consts, false);
1516 fprintf(fp, ", ");
1517 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1518 fprintf(fp, ", ");
1519 unsigned location = (ADD.op >> 3) & 0x1f;
1520 if (location < 16) {
1521 fprintf(fp, "location:%d", location);
1522 } else if (location == 20) {
1523 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1524 } else if (location == 21) {
1525 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1526 } else {
1527 fprintf(fp, "location:%d(unk)", location);
1528 }
1529 break;
1530 }
1531 case ADD_LOAD_ATTR:
1532 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1533 case ADD_TWO_SRC:
1534 dump_src(fp, ADD.src0, regs, consts, false);
1535 fprintf(fp, ", ");
1536 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1537 break;
1538 case ADD_THREE_SRC:
1539 dump_src(fp, ADD.src0, regs, consts, false);
1540 fprintf(fp, ", ");
1541 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1542 fprintf(fp, ", ");
1543 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1544 break;
1545 case ADD_SHIFT: {
1546 struct bifrost_shift_add shift;
1547 memcpy(&shift, &ADD, sizeof(ADD));
1548 dump_src(fp, shift.src0, regs, consts, false);
1549 fprintf(fp, ", ");
1550 dump_src(fp, shift.src1, regs, consts, false);
1551 fprintf(fp, ", ");
1552 dump_src(fp, shift.src2, regs, consts, false);
1553 break;
1554 }
1555 case ADD_FADD:
1556 case ADD_FMINMAX:
1557 if (ADD.op & 0x10)
1558 fprintf(fp, "-");
1559 if (ADD.op & 0x1000)
1560 fprintf(fp, "abs(");
1561 dump_src(fp, ADD.src0, regs, consts, false);
1562 switch ((ADD.op >> 6) & 0x3) {
1563 case 3:
1564 fprintf(fp, ".x");
1565 break;
1566 default:
1567 break;
1568 }
1569 if (ADD.op & 0x1000)
1570 fprintf(fp, ")");
1571 fprintf(fp, ", ");
1572 if (ADD.op & 0x20)
1573 fprintf(fp, "-");
1574 if (ADD.op & 0x8)
1575 fprintf(fp, "abs(");
1576 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1577 switch ((ADD.op >> 6) & 0x3) {
1578 case 1:
1579 case 3:
1580 fprintf(fp, ".x");
1581 break;
1582 case 2:
1583 fprintf(fp, ".y");
1584 break;
1585 case 0:
1586 break;
1587 default:
1588 fprintf(fp, ".unk");
1589 break;
1590 }
1591 if (ADD.op & 0x8)
1592 fprintf(fp, ")");
1593 break;
1594 case ADD_FADD16:
1595 if (ADD.op & 0x10)
1596 fprintf(fp, "-");
1597 if (ADD.op & 0x1000)
1598 fprintf(fp, "abs(");
1599 dump_src(fp, ADD.src0, regs, consts, false);
1600 if (ADD.op & 0x1000)
1601 fprintf(fp, ")");
1602 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1603 fprintf(fp, ", ");
1604 if (ADD.op & 0x20)
1605 fprintf(fp, "-");
1606 if (ADD.op & 0x8)
1607 fprintf(fp, "abs(");
1608 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1609 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1610 if (ADD.op & 0x8)
1611 fprintf(fp, ")");
1612 break;
1613 case ADD_FMINMAX16: {
1614 bool abs1 = ADD.op & 0x8;
1615 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1616 if (ADD.op & 0x10)
1617 fprintf(fp, "-");
1618 if (abs1 || abs2)
1619 fprintf(fp, "abs(");
1620 dump_src(fp, ADD.src0, regs, consts, false);
1621 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1622 if (abs1 || abs2)
1623 fprintf(fp, ")");
1624 fprintf(fp, ", ");
1625 if (ADD.op & 0x20)
1626 fprintf(fp, "-");
1627 if (abs1 && abs2)
1628 fprintf(fp, "abs(");
1629 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1630 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1631 if (abs1 && abs2)
1632 fprintf(fp, ")");
1633 break;
1634 }
1635 case ADD_FADDMscale: {
1636 if (ADD.op & 0x400)
1637 fprintf(fp, "-");
1638 if (ADD.op & 0x200)
1639 fprintf(fp, "abs(");
1640 dump_src(fp, ADD.src0, regs, consts, false);
1641 if (ADD.op & 0x200)
1642 fprintf(fp, ")");
1643
1644 fprintf(fp, ", ");
1645
1646 if (ADD.op & 0x800)
1647 fprintf(fp, "-");
1648 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1649
1650 fprintf(fp, ", ");
1651
1652 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1653 break;
1654 }
1655 case ADD_FCMP:
1656 if (ADD.op & 0x400) {
1657 fprintf(fp, "-");
1658 }
1659 if (ADD.op & 0x100) {
1660 fprintf(fp, "abs(");
1661 }
1662 dump_src(fp, ADD.src0, regs, consts, false);
1663 switch ((ADD.op >> 6) & 0x3) {
1664 case 3:
1665 fprintf(fp, ".x");
1666 break;
1667 default:
1668 break;
1669 }
1670 if (ADD.op & 0x100) {
1671 fprintf(fp, ")");
1672 }
1673 fprintf(fp, ", ");
1674 if (ADD.op & 0x200) {
1675 fprintf(fp, "abs(");
1676 }
1677 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1678 switch ((ADD.op >> 6) & 0x3) {
1679 case 1:
1680 case 3:
1681 fprintf(fp, ".x");
1682 break;
1683 case 2:
1684 fprintf(fp, ".y");
1685 break;
1686 case 0:
1687 break;
1688 default:
1689 fprintf(fp, ".unk");
1690 break;
1691 }
1692 if (ADD.op & 0x200) {
1693 fprintf(fp, ")");
1694 }
1695 break;
1696 case ADD_FCMP16:
1697 dump_src(fp, ADD.src0, regs, consts, false);
1698 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1699 fprintf(fp, ", ");
1700 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1701 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1702 break;
1703 case ADD_BRANCH: {
1704 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1705 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1706 if (code != BR_ALWAYS) {
1707 dump_src(fp, ADD.src0, regs, consts, false);
1708 switch (size) {
1709 case BR_SIZE_16XX:
1710 fprintf(fp, ".x");
1711 break;
1712 case BR_SIZE_16YY:
1713 case BR_SIZE_16YX0:
1714 case BR_SIZE_16YX1:
1715 fprintf(fp, ".y");
1716 break;
1717 case BR_SIZE_ZERO: {
1718 unsigned ctrl = (ADD.op >> 1) & 0x3;
1719 switch (ctrl) {
1720 case 1:
1721 fprintf(fp, ".y");
1722 break;
1723 case 2:
1724 fprintf(fp, ".x");
1725 break;
1726 default:
1727 break;
1728 }
1729 }
1730 default:
1731 break;
1732 }
1733 fprintf(fp, ", ");
1734 }
1735 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1736 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1737 switch (size) {
1738 case BR_SIZE_16XX:
1739 case BR_SIZE_16YX0:
1740 case BR_SIZE_16YX1:
1741 case BR_SIZE_32_AND_16X:
1742 fprintf(fp, ".x");
1743 break;
1744 case BR_SIZE_16YY:
1745 case BR_SIZE_32_AND_16Y:
1746 fprintf(fp, ".y");
1747 break;
1748 default:
1749 break;
1750 }
1751 fprintf(fp, ", ");
1752 }
1753 // I haven't had the chance to test if this actually specifies the
1754 // branch offset, since I couldn't get it to produce values other
1755 // than 5 (uniform/const high), but these three bits are always
1756 // consistent across branch instructions, so it makes sense...
1757 int offsetSrc = (ADD.op >> 3) & 0x7;
1758 if (offsetSrc == 4 || offsetSrc == 5) {
1759 // If the offset is known/constant, we can decode it
1760 uint32_t raw_offset;
1761 if (offsetSrc == 4)
1762 raw_offset = get_const(consts, regs);
1763 else
1764 raw_offset = get_const(consts, regs) >> 32;
1765 // The high 4 bits are flags, while the rest is the
1766 // twos-complement offset in bytes (here we convert to
1767 // clauses).
1768 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1769
1770 // If high4 is the high 4 bits of the last 64-bit constant,
1771 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1772 // offset itself is the last constant. Not sure if this is
1773 // actually used, or just garbage in unused bits, but in any
1774 // case, we can just ignore it here since it's redundant. Note
1775 // that if there is any padding, this will be 4 since the
1776 // padding counts as the last constant.
1777 unsigned flags = raw_offset >> 28;
1778 (void) flags;
1779
1780 // Note: the offset is in bytes, relative to the beginning of the
1781 // current clause, so a zero offset would be a loop back to the
1782 // same clause (annoyingly different from Midgard).
1783 fprintf(fp, "clause_%d", offset + branch_offset);
1784 } else {
1785 dump_src(fp, offsetSrc, regs, consts, false);
1786 }
1787 }
1788 }
1789 if (info.has_data_reg) {
1790 fprintf(fp, ", R%d", data_reg);
1791 }
1792 fprintf(fp, "\n");
1793 }
1794
1795 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1796 struct bifrost_regs next_regs, uint64_t *consts,
1797 unsigned data_reg, unsigned offset, bool verbose)
1798 {
1799 struct bifrost_regs regs;
1800 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1801
1802 if (verbose) {
1803 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1804 dump_regs(fp, regs);
1805 }
1806 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1807 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1808 }
1809
1810 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1811 {
1812 // State for a decoded clause
1813 struct bifrost_alu_inst instrs[8] = {};
1814 uint64_t consts[6] = {};
1815 unsigned num_instrs = 0;
1816 unsigned num_consts = 0;
1817 uint64_t header_bits = 0;
1818 bool stopbit = false;
1819
1820 unsigned i;
1821 for (i = 0; ; i++, words += 4) {
1822 if (verbose) {
1823 fprintf(fp, "# ");
1824 for (int j = 0; j < 4; j++)
1825 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1826 fprintf(fp, "\n");
1827 }
1828 unsigned tag = bits(words[0], 0, 8);
1829
1830 // speculatively decode some things that are common between many formats, so we can share some code
1831 struct bifrost_alu_inst main_instr = {};
1832 // 20 bits
1833 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1834 // 23 bits
1835 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1836 // 35 bits
1837 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1838
1839 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1840 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1841
1842 bool stop = tag & 0x40;
1843
1844 if (verbose) {
1845 fprintf(fp, "# tag: 0x%02x\n", tag);
1846 }
1847 if (tag & 0x80) {
1848 unsigned idx = stop ? 5 : 2;
1849 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1850 instrs[idx + 1] = main_instr;
1851 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1852 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1853 consts[0] = bits(words[3], 17, 32) << 4;
1854 } else {
1855 bool done = false;
1856 switch ((tag >> 3) & 0x7) {
1857 case 0x0:
1858 switch (tag & 0x7) {
1859 case 0x3:
1860 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1861 instrs[1] = main_instr;
1862 num_instrs = 2;
1863 done = stop;
1864 break;
1865 case 0x4:
1866 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1867 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1868 consts[0] = const0;
1869 num_instrs = 3;
1870 num_consts = 1;
1871 done = stop;
1872 break;
1873 case 0x1:
1874 case 0x5:
1875 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1876 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1877 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1878 instrs[3] = main_instr;
1879 if ((tag & 0x7) == 0x5) {
1880 num_instrs = 4;
1881 done = stop;
1882 }
1883 break;
1884 case 0x6:
1885 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1886 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1887 consts[0] = const0;
1888 num_instrs = 6;
1889 num_consts = 1;
1890 done = stop;
1891 break;
1892 case 0x7:
1893 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1894 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1895 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1896 instrs[6] = main_instr;
1897 num_instrs = 7;
1898 done = stop;
1899 break;
1900 default:
1901 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1902 }
1903 break;
1904 case 0x2:
1905 case 0x3: {
1906 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1907 main_instr.add_bits |= (tag & 0x7) << 17;
1908 instrs[idx] = main_instr;
1909 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1910 num_consts = 1;
1911 num_instrs = idx + 1;
1912 done = stop;
1913 break;
1914 }
1915 case 0x4: {
1916 unsigned idx = stop ? 4 : 1;
1917 main_instr.add_bits |= (tag & 0x7) << 17;
1918 instrs[idx] = main_instr;
1919 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1920 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1921 break;
1922 }
1923 case 0x1:
1924 // only constants can come after this
1925 num_instrs = 1;
1926 done = stop;
1927 case 0x5:
1928 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1929 main_instr.add_bits |= (tag & 0x7) << 17;
1930 instrs[0] = main_instr;
1931 break;
1932 case 0x6:
1933 case 0x7: {
1934 unsigned pos = tag & 0xf;
1935 // note that `pos' encodes both the total number of
1936 // instructions and the position in the constant stream,
1937 // presumably because decoded constants and instructions
1938 // share a buffer in the decoder, but we only care about
1939 // the position in the constant stream; the total number of
1940 // instructions is redundant.
1941 unsigned const_idx = 0;
1942 switch (pos) {
1943 case 0:
1944 case 1:
1945 case 2:
1946 case 6:
1947 const_idx = 0;
1948 break;
1949 case 3:
1950 case 4:
1951 case 7:
1952 case 9:
1953 const_idx = 1;
1954 break;
1955 case 5:
1956 case 0xa:
1957 const_idx = 2;
1958 break;
1959 case 8:
1960 case 0xb:
1961 case 0xc:
1962 const_idx = 3;
1963 break;
1964 case 0xd:
1965 const_idx = 4;
1966 break;
1967 default:
1968 fprintf(fp, "# unknown pos 0x%x\n", pos);
1969 break;
1970 }
1971
1972 if (num_consts < const_idx + 2)
1973 num_consts = const_idx + 2;
1974
1975 consts[const_idx] = const0;
1976 consts[const_idx + 1] = const1;
1977 done = stop;
1978 break;
1979 }
1980 default:
1981 break;
1982 }
1983
1984 if (done)
1985 break;
1986 }
1987 }
1988
1989 *size = i + 1;
1990
1991 if (verbose) {
1992 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
1993 }
1994
1995 struct bifrost_header header;
1996 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
1997 dump_header(fp, header, verbose);
1998 if (!header.no_end_of_shader)
1999 stopbit = true;
2000
2001 fprintf(fp, "{\n");
2002 for (i = 0; i < num_instrs; i++) {
2003 struct bifrost_regs next_regs;
2004 if (i + 1 == num_instrs) {
2005 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2006 sizeof(next_regs));
2007 } else {
2008 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2009 sizeof(next_regs));
2010 }
2011
2012 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2013 }
2014 fprintf(fp, "}\n");
2015
2016 if (verbose) {
2017 for (unsigned i = 0; i < num_consts; i++) {
2018 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2019 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2020 }
2021 }
2022 return stopbit;
2023 }
2024
2025 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2026 {
2027 uint32_t *words = (uint32_t *) code;
2028 uint32_t *words_end = words + (size / 4);
2029 // used for displaying branch targets
2030 unsigned offset = 0;
2031 while (words != words_end) {
2032 // we don't know what the program-end bit is quite yet, so for now just
2033 // assume that an all-0 quadword is padding
2034 uint32_t zero[4] = {};
2035 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2036 break;
2037 fprintf(fp, "clause_%d:\n", offset);
2038 unsigned size;
2039 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2040 break;
2041 }
2042 words += size * 4;
2043 offset += size;
2044 }
2045 }
2046