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pan/bi: Add fexp2_fast packing
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140
141 if (header.clause_type != 0) {
142 const char *name = bi_clause_type_name(header.clause_type);
143
144 if (name[0] == '?')
145 fprintf(fp, "unk%u ", header.clause_type);
146 else
147 fprintf(fp, "%s ", name);
148 }
149
150 if (header.scoreboard_deps != 0) {
151 fprintf(fp, "next-wait(");
152 bool first = true;
153 for (unsigned i = 0; i < 8; i++) {
154 if (header.scoreboard_deps & (1 << i)) {
155 if (!first) {
156 fprintf(fp, ", ");
157 }
158 fprintf(fp, "%d", i);
159 first = false;
160 }
161 }
162 fprintf(fp, ") ");
163 }
164
165 if (header.datareg_writebarrier)
166 fprintf(fp, "data-reg-barrier ");
167
168 if (!header.no_end_of_shader)
169 fprintf(fp, "eos ");
170
171 if (!header.back_to_back) {
172 fprintf(fp, "nbb ");
173 if (header.branch_cond)
174 fprintf(fp, "branch-cond ");
175 else
176 fprintf(fp, "branch-uncond ");
177 }
178
179 if (header.elide_writes)
180 fprintf(fp, "we ");
181
182 if (header.suppress_inf)
183 fprintf(fp, "suppress-inf ");
184 if (header.suppress_nan)
185 fprintf(fp, "suppress-nan ");
186
187 if (header.unk0)
188 fprintf(fp, "unk0 ");
189 if (header.unk1)
190 fprintf(fp, "unk1 ");
191 if (header.unk2)
192 fprintf(fp, "unk2 ");
193 if (header.unk3)
194 fprintf(fp, "unk3 ");
195 if (header.unk4)
196 fprintf(fp, "unk4 ");
197
198 fprintf(fp, "\n");
199
200 if (verbose) {
201 fprintf(fp, "# clause type %d, next clause type %d\n",
202 header.clause_type, header.next_clause_type);
203 }
204 }
205
206 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
207 {
208 struct bifrost_reg_ctrl decoded = {};
209 unsigned ctrl;
210 if (regs.ctrl == 0) {
211 ctrl = regs.reg1 >> 2;
212 decoded.read_reg0 = !(regs.reg1 & 0x2);
213 decoded.read_reg1 = false;
214 } else {
215 ctrl = regs.ctrl;
216 decoded.read_reg0 = decoded.read_reg1 = true;
217 }
218 switch (ctrl) {
219 case 1:
220 decoded.fma_write_unit = REG_WRITE_TWO;
221 break;
222 case 2:
223 case 3:
224 decoded.fma_write_unit = REG_WRITE_TWO;
225 decoded.read_reg3 = true;
226 break;
227 case 4:
228 decoded.read_reg3 = true;
229 break;
230 case 5:
231 decoded.add_write_unit = REG_WRITE_TWO;
232 break;
233 case 6:
234 decoded.add_write_unit = REG_WRITE_TWO;
235 decoded.read_reg3 = true;
236 break;
237 case 8:
238 decoded.clause_start = true;
239 break;
240 case 9:
241 decoded.fma_write_unit = REG_WRITE_TWO;
242 decoded.clause_start = true;
243 break;
244 case 11:
245 break;
246 case 12:
247 decoded.read_reg3 = true;
248 decoded.clause_start = true;
249 break;
250 case 13:
251 decoded.add_write_unit = REG_WRITE_TWO;
252 decoded.clause_start = true;
253 break;
254
255 case 7:
256 case 15:
257 decoded.fma_write_unit = REG_WRITE_THREE;
258 decoded.add_write_unit = REG_WRITE_TWO;
259 break;
260 default:
261 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
262 }
263
264 return decoded;
265 }
266
267 // Pass in the add_write_unit or fma_write_unit, and this returns which register
268 // the ADD/FMA units are writing to
269 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
270 {
271 switch (unit) {
272 case REG_WRITE_TWO:
273 return regs.reg2;
274 case REG_WRITE_THREE:
275 return regs.reg3;
276 default: /* REG_WRITE_NONE */
277 assert(0);
278 return 0;
279 }
280 }
281
282 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
283 {
284 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
285 fprintf(fp, "# ");
286 if (ctrl.read_reg0)
287 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
288 if (ctrl.read_reg1)
289 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
290
291 if (ctrl.fma_write_unit == REG_WRITE_TWO)
292 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
293 else if (ctrl.add_write_unit == REG_WRITE_TWO)
294 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
295
296 if (ctrl.fma_write_unit == REG_WRITE_THREE)
297 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
298 else if (ctrl.add_write_unit == REG_WRITE_THREE)
299 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
300 else if (ctrl.read_reg3)
301 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
302
303 if (srcs.uniform_const) {
304 if (srcs.uniform_const & 0x80) {
305 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
306 }
307 }
308
309 fprintf(fp, "\n");
310 }
311 static void dump_const_imm(FILE *fp, uint32_t imm)
312 {
313 union {
314 float f;
315 uint32_t i;
316 } fi;
317 fi.i = imm;
318 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
319 }
320
321 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
322 {
323 unsigned low_bits = srcs.uniform_const & 0xf;
324 uint64_t imm;
325 switch (srcs.uniform_const >> 4) {
326 case 4:
327 imm = consts[0];
328 break;
329 case 5:
330 imm = consts[1];
331 break;
332 case 6:
333 imm = consts[2];
334 break;
335 case 7:
336 imm = consts[3];
337 break;
338 case 2:
339 imm = consts[4];
340 break;
341 case 3:
342 imm = consts[5];
343 break;
344 default:
345 assert(0);
346 break;
347 }
348 return imm | low_bits;
349 }
350
351 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
352 {
353 if (srcs.uniform_const & 0x80) {
354 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
355 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
356 } else if (srcs.uniform_const >= 0x20) {
357 uint64_t imm = get_const(consts, srcs);
358 if (high32)
359 dump_const_imm(fp, imm >> 32);
360 else
361 dump_const_imm(fp, imm);
362 } else {
363 switch (srcs.uniform_const) {
364 case 0:
365 fprintf(fp, "0");
366 break;
367 case 5:
368 fprintf(fp, "atest-data");
369 break;
370 case 6:
371 fprintf(fp, "sample-ptr");
372 break;
373 case 8:
374 case 9:
375 case 10:
376 case 11:
377 case 12:
378 case 13:
379 case 14:
380 case 15:
381 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
382 break;
383 default:
384 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
385 break;
386 }
387
388 if (high32)
389 fprintf(fp, ".y");
390 else
391 fprintf(fp, ".x");
392 }
393 }
394
395 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
396 {
397 switch (src) {
398 case 0:
399 fprintf(fp, "R%d", get_reg0(srcs));
400 break;
401 case 1:
402 fprintf(fp, "R%d", get_reg1(srcs));
403 break;
404 case 2:
405 fprintf(fp, "R%d", srcs.reg3);
406 break;
407 case 3:
408 if (isFMA)
409 fprintf(fp, "0");
410 else
411 fprintf(fp, "T"); // i.e. the output of FMA this cycle
412 break;
413 case 4:
414 dump_uniform_const_src(fp, srcs, consts, false);
415 break;
416 case 5:
417 dump_uniform_const_src(fp, srcs, consts, true);
418 break;
419 case 6:
420 fprintf(fp, "T0");
421 break;
422 case 7:
423 fprintf(fp, "T1");
424 break;
425 }
426 }
427
428 static const struct fma_op_info FMAOpInfos[] = {
429 { false, 0x00000, "FMA.f32", FMA_FMA },
430 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
431 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
432 { false, 0x48000, "FCMP.GL", FMA_FCMP },
433 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
434 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
435 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
436 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
437 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
438 { false, 0x58000, "ADD.f32", FMA_FADD },
439 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
440 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
441 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
442 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
443 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
444 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
445 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
446 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
447 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
448 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
449 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
450 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
451 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
452 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
453 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
454 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
455 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
456 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
457 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
458 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
459 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
460 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
461 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
462 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
463 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
464 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
465 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
466 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
467 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
468 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
469 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
470 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
471 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
472 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
473 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
474 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
475 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
476 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
477 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
478 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
479 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
480 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
481 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
482 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
483
484 /* TODO: Combine to bifrost_fma_f2i_i2f16 */
485 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
486 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
487 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
488 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
489 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
490 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
491 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
492 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
493 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
494 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
495 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
496 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
497 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
498 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
499 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
500 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
501
502 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
503 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
504 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
505 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
506
507 /* TODO: cleanup to use bifrost_fma_int16_to_32 */
508 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
509 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
510 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
511 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
512 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
513 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
514 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
515 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
516
517 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
518 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
519
520 { true, 0x0032c, "NOP", FMA_ONE_SRC },
521 { true, 0x0032d, "MOV", FMA_ONE_SRC },
522 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
523 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
524 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
525 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
526 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
527 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
528 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
529 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
530 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
531 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
532 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
533 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
534 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
535 { true, 0x00ec2, "ROUND.v2f16", FMA_ONE_SRC },
536 { true, 0x00ec5, "ROUND.f32", FMA_ONE_SRC },
537 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
538 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
539 { true, 0x01802, "ROUNDEVEN.v2f16", FMA_ONE_SRC },
540 { true, 0x01805, "ROUNDEVEN.f32", FMA_ONE_SRC },
541 { true, 0x01842, "CEIL.v2f16", FMA_ONE_SRC },
542 { true, 0x01845, "CEIL.f32", FMA_ONE_SRC },
543 { true, 0x01882, "FLOOR.v2f16", FMA_ONE_SRC },
544 { true, 0x01885, "FLOOR.f32", FMA_ONE_SRC },
545 { true, 0x018c2, "TRUNC.v2f16", FMA_ONE_SRC },
546 { true, 0x018c5, "TRUNC.f32", FMA_ONE_SRC },
547 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
548 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
549 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
550 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
551 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
552 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
553 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
554 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
555 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
556 { true, 0x01e80, "ADD_FREXPM.f32", FMA_TWO_SRC },
557 { true, 0x00800, "IMAD", FMA_THREE_SRC },
558 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
559 };
560
561 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
562 {
563 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
564 unsigned opCmp = ~0;
565
566 if (FMAOpInfos[i].extended != extended)
567 continue;
568
569 if (extended)
570 op &= ~0xe0000;
571
572 switch (FMAOpInfos[i].src_type) {
573 case FMA_ONE_SRC:
574 opCmp = op;
575 break;
576 case FMA_TWO_SRC:
577 opCmp = op & ~0x7;
578 break;
579 case FMA_FCMP:
580 case FMA_FCMP16:
581 opCmp = op & ~0x1fff;
582 break;
583 case FMA_THREE_SRC:
584 case FMA_SHIFT_ADD64:
585 opCmp = op & ~0x3f;
586 break;
587 case FMA_FADD:
588 case FMA_FMINMAX:
589 case FMA_FADD16:
590 case FMA_FMINMAX16:
591 opCmp = op & ~0x3fff;
592 break;
593 case FMA_FMA:
594 case FMA_FMA16:
595 opCmp = op & ~0x3ffff;
596 break;
597 case FMA_CSEL4:
598 case FMA_SHIFT:
599 opCmp = op & ~0xfff;
600 break;
601 case FMA_FMA_MSCALE:
602 opCmp = op & ~0x7fff;
603 break;
604 default:
605 opCmp = ~0;
606 break;
607 }
608 if (FMAOpInfos[i].op == opCmp)
609 return FMAOpInfos[i];
610 }
611
612 struct fma_op_info info;
613 snprintf(info.name, sizeof(info.name), "op%04x", op);
614 info.op = op;
615 info.src_type = FMA_THREE_SRC;
616 return info;
617 }
618
619 static void dump_fcmp(FILE *fp, unsigned op)
620 {
621 switch (op) {
622 case 0:
623 fprintf(fp, ".OEQ");
624 break;
625 case 1:
626 fprintf(fp, ".OGT");
627 break;
628 case 2:
629 fprintf(fp, ".OGE");
630 break;
631 case 3:
632 fprintf(fp, ".UNE");
633 break;
634 case 4:
635 fprintf(fp, ".OLT");
636 break;
637 case 5:
638 fprintf(fp, ".OLE");
639 break;
640 default:
641 fprintf(fp, ".unk%d", op);
642 break;
643 }
644 }
645
646 static void dump_16swizzle(FILE *fp, unsigned swiz)
647 {
648 if (swiz == 2)
649 return;
650 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
651 }
652
653 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
654 {
655 switch (ctrl) {
656 case 3:
657 case 4:
658 case 6:
659 fprintf(fp, ".x");
660 break;
661 case 5:
662 case 7:
663 fprintf(fp, ".y");
664 break;
665 case 0:
666 case 1:
667 case 2:
668 break;
669 default:
670 fprintf(fp, ".unk");
671 break;
672 }
673 }
674
675 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
676 {
677 switch (ctrl) {
678 case 1:
679 case 3:
680 fprintf(fp, ".x");
681 break;
682 case 2:
683 case 4:
684 case 5:
685 fprintf(fp, ".y");
686 break;
687 case 0:
688 case 6:
689 case 7:
690 break;
691 default:
692 fprintf(fp, ".unk");
693 break;
694 }
695 }
696
697 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
698 {
699 if (verbose) {
700 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
701 }
702 struct bifrost_fma_inst FMA;
703 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
704 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
705
706 fprintf(fp, "%s", info.name);
707 if (info.src_type == FMA_FADD ||
708 info.src_type == FMA_FMINMAX ||
709 info.src_type == FMA_FMA ||
710 info.src_type == FMA_FADD16 ||
711 info.src_type == FMA_FMINMAX16 ||
712 info.src_type == FMA_FMA16) {
713 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
714 switch (info.src_type) {
715 case FMA_FADD:
716 case FMA_FMA:
717 case FMA_FADD16:
718 case FMA_FMA16:
719 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
720 break;
721 case FMA_FMINMAX:
722 case FMA_FMINMAX16:
723 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
724 break;
725 default:
726 assert(0);
727 }
728 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
729 dump_fcmp(fp, bits(FMA.op, 10, 13));
730 if (info.src_type == FMA_FCMP)
731 fprintf(fp, ".f32");
732 else
733 fprintf(fp, ".v2f16");
734 } else if (info.src_type == FMA_FMA_MSCALE) {
735 if (FMA.op & (1 << 11)) {
736 switch ((FMA.op >> 9) & 0x3) {
737 case 0:
738 /* This mode seems to do a few things:
739 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
740 * since generating a nan would poison the result of
741 * 1/infinity and 1/0.
742 * - Fiddles with which nan is returned in nan * nan,
743 * presumably to make sure that the same exact nan is
744 * returned for 1/nan.
745 */
746 fprintf(fp, ".rcp_mode");
747 break;
748 case 3:
749 /* Similar to the above, but src0 always wins when multiplying
750 * 0 by infinity.
751 */
752 fprintf(fp, ".sqrt_mode");
753 break;
754 default:
755 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
756 }
757 } else {
758 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
759 }
760 } else if (info.src_type == FMA_SHIFT) {
761 struct bifrost_shift_fma shift;
762 memcpy(&shift, &FMA, sizeof(shift));
763
764 if (shift.half == 0x7)
765 fprintf(fp, ".v2i16");
766 else if (shift.half == 0)
767 fprintf(fp, ".i32");
768 else if (shift.half == 0x4)
769 fprintf(fp, ".v4i8");
770 else
771 fprintf(fp, ".unk%u", shift.half);
772
773 if (!shift.unk)
774 fprintf(fp, ".no_unk");
775
776 if (shift.invert_1)
777 fprintf(fp, ".invert_1");
778
779 if (shift.invert_2)
780 fprintf(fp, ".invert_2");
781 }
782
783 fprintf(fp, " ");
784
785 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
786 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
787 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
788 } else {
789 fprintf(fp, "T0, ");
790 }
791
792 switch (info.src_type) {
793 case FMA_ONE_SRC:
794 dump_src(fp, FMA.src0, regs, consts, true);
795 break;
796 case FMA_TWO_SRC:
797 dump_src(fp, FMA.src0, regs, consts, true);
798 fprintf(fp, ", ");
799 dump_src(fp, FMA.op & 0x7, regs, consts, true);
800 break;
801 case FMA_FADD:
802 case FMA_FMINMAX:
803 if (FMA.op & 0x10)
804 fprintf(fp, "-");
805 if (FMA.op & 0x200)
806 fprintf(fp, "abs(");
807 dump_src(fp, FMA.src0, regs, consts, true);
808 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
809 if (FMA.op & 0x200)
810 fprintf(fp, ")");
811 fprintf(fp, ", ");
812 if (FMA.op & 0x20)
813 fprintf(fp, "-");
814 if (FMA.op & 0x8)
815 fprintf(fp, "abs(");
816 dump_src(fp, FMA.op & 0x7, regs, consts, true);
817 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
818 if (FMA.op & 0x8)
819 fprintf(fp, ")");
820 break;
821 case FMA_FADD16:
822 case FMA_FMINMAX16: {
823 bool abs1 = FMA.op & 0x8;
824 bool abs2 = (FMA.op & 0x7) < FMA.src0;
825 if (FMA.op & 0x10)
826 fprintf(fp, "-");
827 if (abs1 || abs2)
828 fprintf(fp, "abs(");
829 dump_src(fp, FMA.src0, regs, consts, true);
830 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
831 if (abs1 || abs2)
832 fprintf(fp, ")");
833 fprintf(fp, ", ");
834 if (FMA.op & 0x20)
835 fprintf(fp, "-");
836 if (abs1 && abs2)
837 fprintf(fp, "abs(");
838 dump_src(fp, FMA.op & 0x7, regs, consts, true);
839 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
840 if (abs1 && abs2)
841 fprintf(fp, ")");
842 break;
843 }
844 case FMA_FCMP:
845 if (FMA.op & 0x200)
846 fprintf(fp, "abs(");
847 dump_src(fp, FMA.src0, regs, consts, true);
848 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
849 if (FMA.op & 0x200)
850 fprintf(fp, ")");
851 fprintf(fp, ", ");
852 if (FMA.op & 0x20)
853 fprintf(fp, "-");
854 if (FMA.op & 0x8)
855 fprintf(fp, "abs(");
856 dump_src(fp, FMA.op & 0x7, regs, consts, true);
857 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
858 if (FMA.op & 0x8)
859 fprintf(fp, ")");
860 break;
861 case FMA_FCMP16:
862 dump_src(fp, FMA.src0, regs, consts, true);
863 // Note: this is kinda a guess, I haven't seen the blob set this to
864 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
865 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
866 fprintf(fp, ", ");
867 dump_src(fp, FMA.op & 0x7, regs, consts, true);
868 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
869 break;
870 case FMA_SHIFT_ADD64:
871 dump_src(fp, FMA.src0, regs, consts, true);
872 fprintf(fp, ", ");
873 dump_src(fp, FMA.op & 0x7, regs, consts, true);
874 fprintf(fp, ", ");
875 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
876 break;
877 case FMA_THREE_SRC:
878 dump_src(fp, FMA.src0, regs, consts, true);
879 fprintf(fp, ", ");
880 dump_src(fp, FMA.op & 0x7, regs, consts, true);
881 fprintf(fp, ", ");
882 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
883 break;
884 case FMA_SHIFT: {
885 struct bifrost_shift_fma shift;
886 memcpy(&shift, &FMA, sizeof(shift));
887
888 dump_src(fp, shift.src0, regs, consts, true);
889 fprintf(fp, ", ");
890 dump_src(fp, shift.src1, regs, consts, true);
891 fprintf(fp, ", ");
892 dump_src(fp, shift.src2, regs, consts, true);
893 break;
894 }
895 case FMA_FMA:
896 if (FMA.op & (1 << 14))
897 fprintf(fp, "-");
898 if (FMA.op & (1 << 9))
899 fprintf(fp, "abs(");
900 dump_src(fp, FMA.src0, regs, consts, true);
901 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
902 if (FMA.op & (1 << 9))
903 fprintf(fp, ")");
904 fprintf(fp, ", ");
905 if (FMA.op & (1 << 16))
906 fprintf(fp, "abs(");
907 dump_src(fp, FMA.op & 0x7, regs, consts, true);
908 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
909 if (FMA.op & (1 << 16))
910 fprintf(fp, ")");
911 fprintf(fp, ", ");
912 if (FMA.op & (1 << 15))
913 fprintf(fp, "-");
914 if (FMA.op & (1 << 17))
915 fprintf(fp, "abs(");
916 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
917 if (FMA.op & (1 << 17))
918 fprintf(fp, ")");
919 break;
920 case FMA_FMA16:
921 if (FMA.op & (1 << 14))
922 fprintf(fp, "-");
923 dump_src(fp, FMA.src0, regs, consts, true);
924 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
925 fprintf(fp, ", ");
926 dump_src(fp, FMA.op & 0x7, regs, consts, true);
927 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
928 fprintf(fp, ", ");
929 if (FMA.op & (1 << 15))
930 fprintf(fp, "-");
931 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
932 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
933 break;
934 case FMA_CSEL4: {
935 struct bifrost_csel4 csel;
936 memcpy(&csel, &FMA, sizeof(csel));
937 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
938
939 dump_src(fp, csel.src0, regs, consts, true);
940 fprintf(fp, ", ");
941 dump_src(fp, csel.src1, regs, consts, true);
942 fprintf(fp, ", ");
943 dump_src(fp, csel.src2, regs, consts, true);
944 fprintf(fp, ", ");
945 dump_src(fp, csel.src3, regs, consts, true);
946 break;
947 }
948 case FMA_FMA_MSCALE:
949 if (FMA.op & (1 << 12))
950 fprintf(fp, "abs(");
951 dump_src(fp, FMA.src0, regs, consts, true);
952 if (FMA.op & (1 << 12))
953 fprintf(fp, ")");
954 fprintf(fp, ", ");
955 if (FMA.op & (1 << 13))
956 fprintf(fp, "-");
957 dump_src(fp, FMA.op & 0x7, regs, consts, true);
958 fprintf(fp, ", ");
959 if (FMA.op & (1 << 14))
960 fprintf(fp, "-");
961 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
962 fprintf(fp, ", ");
963 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
964 break;
965 }
966 fprintf(fp, "\n");
967 }
968
969 static const struct add_op_info add_op_infos[] = {
970 { 0x00000, "MAX.f32", ADD_FMINMAX },
971 { 0x02000, "MIN.f32", ADD_FMINMAX },
972 { 0x04000, "ADD.f32", ADD_FADD },
973 { 0x06000, "FCMP.GL", ADD_FCMP },
974 { 0x07000, "FCMP.D3D", ADD_FCMP },
975 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
976 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
977 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
978 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
979 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
980 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
981 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
982 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
983 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
984 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
985 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
986 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
987 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
988 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
989 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
990 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
991 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
992 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
993 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
994 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
995 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
996 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
997 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
998 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
999 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1000 { 0x07b2c, "NOP", ADD_ONE_SRC },
1001 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1002 { 0x07b2d, "MOV", ADD_ONE_SRC },
1003 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1004 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1005 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1006 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1007 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1008 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1009 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1010 { 0x07d42, "CEIL.v2f16", ADD_ONE_SRC },
1011 { 0x07d45, "CEIL.f32", ADD_ONE_SRC },
1012 { 0x07d82, "FLOOR.v2f16", ADD_ONE_SRC },
1013 { 0x07d85, "FLOOR.f32", ADD_ONE_SRC },
1014 { 0x07dc2, "TRUNC.v2f16", ADD_ONE_SRC },
1015 { 0x07dc5, "TRUNC.f32", ADD_ONE_SRC },
1016 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1017 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1018 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1019 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1020 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1021 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1022 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1023 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1024 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1025 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1026 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1027 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1028 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1029 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1030 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1031 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1032 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1033 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1034 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1035 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1036 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1037 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1038 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1039 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1040 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1041 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1042 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1043 { 0x0cc68, "FLOG2_U.f32", ADD_ONE_SRC },
1044 { 0x0cd58, "FEXP2_FAST.f32", ADD_ONE_SRC },
1045 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1046 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1047 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1048 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1049 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1050 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1051 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1052 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1053 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1054 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1055 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1056 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1057 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1058 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1059 { 0x0d000, "BRANCH", ADD_BRANCH },
1060 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1061 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1062 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1063 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1064 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1065 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1066 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1067 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1068 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1069 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1070 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1071 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1072 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1073 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1074 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1075 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1076 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1077 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1078 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1079 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1080 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1081 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1082 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1083 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1084 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1085 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1086 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1087 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1088 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1089 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1090 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1091 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1092 { 0x17881, "ADD.i8", ADD_TWO_SRC },
1093 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, true },
1094 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
1095 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
1096 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1097 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
1098 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
1099 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1100 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1101 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1102 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1103 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1104 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1105 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1106 { 0x1952c, "BLEND", ADD_BLENDING, true },
1107 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1108 { 0x1ae60, "TEX", ADD_TEX, true },
1109 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1110 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1111 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1112 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1113 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1114 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1115 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1116 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1117 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1118 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1119 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1120 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1121 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1122 };
1123
1124 static struct add_op_info find_add_op_info(unsigned op)
1125 {
1126 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1127 unsigned opCmp = ~0;
1128 switch (add_op_infos[i].src_type) {
1129 case ADD_ONE_SRC:
1130 case ADD_BLENDING:
1131 opCmp = op;
1132 break;
1133 case ADD_TWO_SRC:
1134 opCmp = op & ~0x7;
1135 break;
1136 case ADD_THREE_SRC:
1137 opCmp = op & ~0x3f;
1138 break;
1139 case ADD_SHIFT:
1140 opCmp = op & ~0x3ff;
1141 break;
1142 case ADD_TEX:
1143 opCmp = op & ~0xf;
1144 break;
1145 case ADD_FADD:
1146 case ADD_FMINMAX:
1147 case ADD_FADD16:
1148 opCmp = op & ~0x1fff;
1149 break;
1150 case ADD_FMINMAX16:
1151 case ADD_FADDMscale:
1152 opCmp = op & ~0xfff;
1153 break;
1154 case ADD_FCMP:
1155 case ADD_FCMP16:
1156 opCmp = op & ~0x7ff;
1157 break;
1158 case ADD_TEX_COMPACT:
1159 opCmp = op & ~0x3ff;
1160 break;
1161 case ADD_VARYING_INTERP:
1162 opCmp = op & ~0x7ff;
1163 break;
1164 case ADD_VARYING_ADDRESS:
1165 opCmp = op & ~0xfff;
1166 break;
1167 case ADD_LOAD_ATTR:
1168 case ADD_BRANCH:
1169 opCmp = op & ~0xfff;
1170 break;
1171 default:
1172 opCmp = ~0;
1173 break;
1174 }
1175 if (add_op_infos[i].op == opCmp)
1176 return add_op_infos[i];
1177 }
1178
1179 struct add_op_info info;
1180 snprintf(info.name, sizeof(info.name), "op%04x", op);
1181 info.op = op;
1182 info.src_type = ADD_TWO_SRC;
1183 info.has_data_reg = true;
1184 return info;
1185 }
1186
1187 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1188 struct bifrost_regs next_regs, uint64_t *consts,
1189 unsigned data_reg, unsigned offset, bool verbose)
1190 {
1191 if (verbose) {
1192 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1193 }
1194 struct bifrost_add_inst ADD;
1195 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1196 struct add_op_info info = find_add_op_info(ADD.op);
1197
1198 fprintf(fp, "%s", info.name);
1199
1200 // float16 seems like it doesn't support output modifiers
1201 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1202 // output modifiers
1203 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1204 if (info.src_type == ADD_FADD)
1205 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1206 else
1207 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1208 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1209 dump_fcmp(fp, bits(ADD.op, 3, 6));
1210 if (info.src_type == ADD_FCMP)
1211 fprintf(fp, ".f32");
1212 else
1213 fprintf(fp, ".v2f16");
1214 } else if (info.src_type == ADD_FADDMscale) {
1215 switch ((ADD.op >> 6) & 0x7) {
1216 case 0:
1217 break;
1218 // causes GPU hangs on G71
1219 case 1:
1220 fprintf(fp, ".invalid");
1221 break;
1222 // Same as usual outmod value.
1223 case 2:
1224 fprintf(fp, ".clamp_0_1");
1225 break;
1226 // If src0 is infinite or NaN, flush it to zero so that the other
1227 // source is passed through unmodified.
1228 case 3:
1229 fprintf(fp, ".flush_src0_inf_nan");
1230 break;
1231 // Vice versa.
1232 case 4:
1233 fprintf(fp, ".flush_src1_inf_nan");
1234 break;
1235 // Every other case seems to behave the same as the above?
1236 default:
1237 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1238 break;
1239 }
1240 } else if (info.src_type == ADD_VARYING_INTERP) {
1241 if (ADD.op & 0x200)
1242 fprintf(fp, ".reuse");
1243 if (ADD.op & 0x400)
1244 fprintf(fp, ".flat");
1245 fprintf(fp, "%s", bi_interp_mode_name((ADD.op >> 7) & 0x3));
1246 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1247 } else if (info.src_type == ADD_BRANCH) {
1248 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1249 if (branchCode == BR_ALWAYS) {
1250 // unconditional branch
1251 } else {
1252 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1253 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1254 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1255 // See the comment in branch_bit_size
1256 if (size == BR_SIZE_16YX0)
1257 portSwapped = true;
1258 if (size == BR_SIZE_16YX1)
1259 portSwapped = false;
1260 // These sizes are only for floating point comparisons, so the
1261 // non-floating-point comparisons are reused to encode the flipped
1262 // versions.
1263 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1264 portSwapped = false;
1265 // There's only one argument, so we reuse the extra argument to
1266 // encode this.
1267 if (size == BR_SIZE_ZERO)
1268 portSwapped = !(ADD.op & 1);
1269
1270 switch (cond) {
1271 case BR_COND_LT:
1272 if (portSwapped)
1273 fprintf(fp, ".LT.u");
1274 else
1275 fprintf(fp, ".LT.i");
1276 break;
1277 case BR_COND_LE:
1278 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1279 fprintf(fp, ".UNE.f");
1280 } else {
1281 if (portSwapped)
1282 fprintf(fp, ".LE.u");
1283 else
1284 fprintf(fp, ".LE.i");
1285 }
1286 break;
1287 case BR_COND_GT:
1288 if (portSwapped)
1289 fprintf(fp, ".GT.u");
1290 else
1291 fprintf(fp, ".GT.i");
1292 break;
1293 case BR_COND_GE:
1294 if (portSwapped)
1295 fprintf(fp, ".GE.u");
1296 else
1297 fprintf(fp, ".GE.i");
1298 break;
1299 case BR_COND_EQ:
1300 if (portSwapped)
1301 fprintf(fp, ".NE.i");
1302 else
1303 fprintf(fp, ".EQ.i");
1304 break;
1305 case BR_COND_OEQ:
1306 if (portSwapped)
1307 fprintf(fp, ".UNE.f");
1308 else
1309 fprintf(fp, ".OEQ.f");
1310 break;
1311 case BR_COND_OGT:
1312 if (portSwapped)
1313 fprintf(fp, ".OGT.unk.f");
1314 else
1315 fprintf(fp, ".OGT.f");
1316 break;
1317 case BR_COND_OLT:
1318 if (portSwapped)
1319 fprintf(fp, ".OLT.unk.f");
1320 else
1321 fprintf(fp, ".OLT.f");
1322 break;
1323 }
1324 switch (size) {
1325 case BR_SIZE_32:
1326 case BR_SIZE_32_AND_16X:
1327 case BR_SIZE_32_AND_16Y:
1328 fprintf(fp, "32");
1329 break;
1330 case BR_SIZE_16XX:
1331 case BR_SIZE_16YY:
1332 case BR_SIZE_16YX0:
1333 case BR_SIZE_16YX1:
1334 fprintf(fp, "16");
1335 break;
1336 case BR_SIZE_ZERO: {
1337 unsigned ctrl = (ADD.op >> 1) & 0x3;
1338 if (ctrl == 0)
1339 fprintf(fp, "32.Z");
1340 else
1341 fprintf(fp, "16.Z");
1342 break;
1343 }
1344 }
1345 }
1346 } else if (info.src_type == ADD_SHIFT) {
1347 struct bifrost_shift_add shift;
1348 memcpy(&shift, &ADD, sizeof(ADD));
1349
1350 if (shift.invert_1)
1351 fprintf(fp, ".invert_1");
1352
1353 if (shift.invert_2)
1354 fprintf(fp, ".invert_2");
1355
1356 if (shift.zero)
1357 fprintf(fp, ".unk%u", shift.zero);
1358 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1359 struct bifrost_ld_var_addr ld;
1360 memcpy(&ld, &ADD, sizeof(ADD));
1361 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1362 } else if (info.src_type == ADD_LOAD_ATTR) {
1363 struct bifrost_ld_attr ld;
1364 memcpy(&ld, &ADD, sizeof(ADD));
1365
1366 if (ld.channels)
1367 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1368 else
1369 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1370 }
1371
1372 fprintf(fp, " ");
1373
1374 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1375 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1376 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1377 } else {
1378 fprintf(fp, "T1, ");
1379 }
1380
1381 switch (info.src_type) {
1382 case ADD_BLENDING:
1383 // Note: in this case, regs.uniform_const == location | 0x8
1384 // This probably means we can't load uniforms or immediates in the
1385 // same instruction. This re-uses the encoding that normally means
1386 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1387 // 0x8 or'd in indicates this is happening.
1388 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1389 // fallthrough
1390 case ADD_ONE_SRC:
1391 dump_src(fp, ADD.src0, regs, consts, false);
1392 break;
1393 case ADD_TEX:
1394 case ADD_TEX_COMPACT: {
1395 int tex_index;
1396 int sampler_index;
1397 bool dualTex = false;
1398 if (info.src_type == ADD_TEX_COMPACT) {
1399 tex_index = (ADD.op >> 3) & 0x7;
1400 sampler_index = (ADD.op >> 7) & 0x7;
1401 bool unknown = (ADD.op & 0x40);
1402 // TODO: figure out if the unknown bit is ever 0
1403 if (!unknown)
1404 fprintf(fp, "unknown ");
1405 } else {
1406 uint64_t constVal = get_const(consts, regs);
1407 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1408 struct bifrost_tex_ctrl ctrl;
1409 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1410
1411 // TODO: figure out what actually triggers dual-tex
1412 if (ctrl.result_type == 9) {
1413 struct bifrost_dual_tex_ctrl dualCtrl;
1414 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1415 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1416 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1417 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1418 if (dualCtrl.unk0 != 3)
1419 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1420 dualTex = true;
1421 } else {
1422 if (ctrl.no_merge_index) {
1423 tex_index = ctrl.tex_index;
1424 sampler_index = ctrl.sampler_index;
1425 } else {
1426 tex_index = sampler_index = ctrl.tex_index;
1427 unsigned unk = ctrl.sampler_index >> 2;
1428 if (unk != 3)
1429 fprintf(fp, "unk:%d ", unk);
1430 if (ctrl.sampler_index & 1)
1431 tex_index = -1;
1432 if (ctrl.sampler_index & 2)
1433 sampler_index = -1;
1434 }
1435
1436 if (ctrl.unk0 != 3)
1437 fprintf(fp, "unk0:%d ", ctrl.unk0);
1438 if (ctrl.unk1)
1439 fprintf(fp, "unk1 ");
1440 if (ctrl.unk2 != 0xf)
1441 fprintf(fp, "unk2:%x ", ctrl.unk2);
1442
1443 switch (ctrl.result_type) {
1444 case 0x4:
1445 fprintf(fp, "f32 ");
1446 break;
1447 case 0xe:
1448 fprintf(fp, "i32 ");
1449 break;
1450 case 0xf:
1451 fprintf(fp, "u32 ");
1452 break;
1453 default:
1454 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1455 }
1456
1457 switch (ctrl.tex_type) {
1458 case 0:
1459 fprintf(fp, "cube ");
1460 break;
1461 case 1:
1462 fprintf(fp, "buffer ");
1463 break;
1464 case 2:
1465 fprintf(fp, "2D ");
1466 break;
1467 case 3:
1468 fprintf(fp, "3D ");
1469 break;
1470 }
1471
1472 if (ctrl.is_shadow)
1473 fprintf(fp, "shadow ");
1474 if (ctrl.is_array)
1475 fprintf(fp, "array ");
1476
1477 if (!ctrl.filter) {
1478 if (ctrl.calc_gradients) {
1479 int comp = (controlBits >> 20) & 0x3;
1480 fprintf(fp, "txg comp:%d ", comp);
1481 } else {
1482 fprintf(fp, "txf ");
1483 }
1484 } else {
1485 if (!ctrl.not_supply_lod) {
1486 if (ctrl.compute_lod)
1487 fprintf(fp, "lod_bias ");
1488 else
1489 fprintf(fp, "lod ");
1490 }
1491
1492 if (!ctrl.calc_gradients)
1493 fprintf(fp, "grad ");
1494 }
1495
1496 if (ctrl.texel_offset)
1497 fprintf(fp, "offset ");
1498 }
1499 }
1500
1501 if (!dualTex) {
1502 if (tex_index == -1)
1503 fprintf(fp, "tex:indirect ");
1504 else
1505 fprintf(fp, "tex:%d ", tex_index);
1506
1507 if (sampler_index == -1)
1508 fprintf(fp, "samp:indirect ");
1509 else
1510 fprintf(fp, "samp:%d ", sampler_index);
1511 }
1512 break;
1513 }
1514 case ADD_VARYING_INTERP: {
1515 unsigned addr = ADD.op & 0x1f;
1516 if (addr < 0b10100) {
1517 // direct addr
1518 fprintf(fp, "%d", addr);
1519 } else if (addr < 0b11000) {
1520 if (addr == 22)
1521 fprintf(fp, "fragw");
1522 else if (addr == 23)
1523 fprintf(fp, "fragz");
1524 else
1525 fprintf(fp, "unk%d", addr);
1526 } else {
1527 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1528 }
1529 fprintf(fp, ", ");
1530 dump_src(fp, ADD.src0, regs, consts, false);
1531 break;
1532 }
1533 case ADD_VARYING_ADDRESS: {
1534 dump_src(fp, ADD.src0, regs, consts, false);
1535 fprintf(fp, ", ");
1536 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1537 fprintf(fp, ", ");
1538 unsigned location = (ADD.op >> 3) & 0x1f;
1539 if (location < 16) {
1540 fprintf(fp, "location:%d", location);
1541 } else if (location == 20) {
1542 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1543 } else if (location == 21) {
1544 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1545 } else {
1546 fprintf(fp, "location:%d(unk)", location);
1547 }
1548 break;
1549 }
1550 case ADD_LOAD_ATTR:
1551 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1552 case ADD_TWO_SRC:
1553 dump_src(fp, ADD.src0, regs, consts, false);
1554 fprintf(fp, ", ");
1555 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1556 break;
1557 case ADD_THREE_SRC:
1558 dump_src(fp, ADD.src0, regs, consts, false);
1559 fprintf(fp, ", ");
1560 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1561 fprintf(fp, ", ");
1562 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1563 break;
1564 case ADD_SHIFT: {
1565 struct bifrost_shift_add shift;
1566 memcpy(&shift, &ADD, sizeof(ADD));
1567 dump_src(fp, shift.src0, regs, consts, false);
1568 fprintf(fp, ", ");
1569 dump_src(fp, shift.src1, regs, consts, false);
1570 fprintf(fp, ", ");
1571 dump_src(fp, shift.src2, regs, consts, false);
1572 break;
1573 }
1574 case ADD_FADD:
1575 case ADD_FMINMAX:
1576 if (ADD.op & 0x10)
1577 fprintf(fp, "-");
1578 if (ADD.op & 0x1000)
1579 fprintf(fp, "abs(");
1580 dump_src(fp, ADD.src0, regs, consts, false);
1581 switch ((ADD.op >> 6) & 0x3) {
1582 case 3:
1583 fprintf(fp, ".x");
1584 break;
1585 default:
1586 break;
1587 }
1588 if (ADD.op & 0x1000)
1589 fprintf(fp, ")");
1590 fprintf(fp, ", ");
1591 if (ADD.op & 0x20)
1592 fprintf(fp, "-");
1593 if (ADD.op & 0x8)
1594 fprintf(fp, "abs(");
1595 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1596 switch ((ADD.op >> 6) & 0x3) {
1597 case 1:
1598 case 3:
1599 fprintf(fp, ".x");
1600 break;
1601 case 2:
1602 fprintf(fp, ".y");
1603 break;
1604 case 0:
1605 break;
1606 default:
1607 fprintf(fp, ".unk");
1608 break;
1609 }
1610 if (ADD.op & 0x8)
1611 fprintf(fp, ")");
1612 break;
1613 case ADD_FADD16:
1614 if (ADD.op & 0x10)
1615 fprintf(fp, "-");
1616 if (ADD.op & 0x1000)
1617 fprintf(fp, "abs(");
1618 dump_src(fp, ADD.src0, regs, consts, false);
1619 if (ADD.op & 0x1000)
1620 fprintf(fp, ")");
1621 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1622 fprintf(fp, ", ");
1623 if (ADD.op & 0x20)
1624 fprintf(fp, "-");
1625 if (ADD.op & 0x8)
1626 fprintf(fp, "abs(");
1627 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1628 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1629 if (ADD.op & 0x8)
1630 fprintf(fp, ")");
1631 break;
1632 case ADD_FMINMAX16: {
1633 bool abs1 = ADD.op & 0x8;
1634 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1635 if (ADD.op & 0x10)
1636 fprintf(fp, "-");
1637 if (abs1 || abs2)
1638 fprintf(fp, "abs(");
1639 dump_src(fp, ADD.src0, regs, consts, false);
1640 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1641 if (abs1 || abs2)
1642 fprintf(fp, ")");
1643 fprintf(fp, ", ");
1644 if (ADD.op & 0x20)
1645 fprintf(fp, "-");
1646 if (abs1 && abs2)
1647 fprintf(fp, "abs(");
1648 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1649 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1650 if (abs1 && abs2)
1651 fprintf(fp, ")");
1652 break;
1653 }
1654 case ADD_FADDMscale: {
1655 if (ADD.op & 0x400)
1656 fprintf(fp, "-");
1657 if (ADD.op & 0x200)
1658 fprintf(fp, "abs(");
1659 dump_src(fp, ADD.src0, regs, consts, false);
1660 if (ADD.op & 0x200)
1661 fprintf(fp, ")");
1662
1663 fprintf(fp, ", ");
1664
1665 if (ADD.op & 0x800)
1666 fprintf(fp, "-");
1667 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1668
1669 fprintf(fp, ", ");
1670
1671 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1672 break;
1673 }
1674 case ADD_FCMP:
1675 if (ADD.op & 0x400) {
1676 fprintf(fp, "-");
1677 }
1678 if (ADD.op & 0x100) {
1679 fprintf(fp, "abs(");
1680 }
1681 dump_src(fp, ADD.src0, regs, consts, false);
1682 switch ((ADD.op >> 6) & 0x3) {
1683 case 3:
1684 fprintf(fp, ".x");
1685 break;
1686 default:
1687 break;
1688 }
1689 if (ADD.op & 0x100) {
1690 fprintf(fp, ")");
1691 }
1692 fprintf(fp, ", ");
1693 if (ADD.op & 0x200) {
1694 fprintf(fp, "abs(");
1695 }
1696 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1697 switch ((ADD.op >> 6) & 0x3) {
1698 case 1:
1699 case 3:
1700 fprintf(fp, ".x");
1701 break;
1702 case 2:
1703 fprintf(fp, ".y");
1704 break;
1705 case 0:
1706 break;
1707 default:
1708 fprintf(fp, ".unk");
1709 break;
1710 }
1711 if (ADD.op & 0x200) {
1712 fprintf(fp, ")");
1713 }
1714 break;
1715 case ADD_FCMP16:
1716 dump_src(fp, ADD.src0, regs, consts, false);
1717 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1718 fprintf(fp, ", ");
1719 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1720 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1721 break;
1722 case ADD_BRANCH: {
1723 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1724 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1725 if (code != BR_ALWAYS) {
1726 dump_src(fp, ADD.src0, regs, consts, false);
1727 switch (size) {
1728 case BR_SIZE_16XX:
1729 fprintf(fp, ".x");
1730 break;
1731 case BR_SIZE_16YY:
1732 case BR_SIZE_16YX0:
1733 case BR_SIZE_16YX1:
1734 fprintf(fp, ".y");
1735 break;
1736 case BR_SIZE_ZERO: {
1737 unsigned ctrl = (ADD.op >> 1) & 0x3;
1738 switch (ctrl) {
1739 case 1:
1740 fprintf(fp, ".y");
1741 break;
1742 case 2:
1743 fprintf(fp, ".x");
1744 break;
1745 default:
1746 break;
1747 }
1748 }
1749 default:
1750 break;
1751 }
1752 fprintf(fp, ", ");
1753 }
1754 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1755 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1756 switch (size) {
1757 case BR_SIZE_16XX:
1758 case BR_SIZE_16YX0:
1759 case BR_SIZE_16YX1:
1760 case BR_SIZE_32_AND_16X:
1761 fprintf(fp, ".x");
1762 break;
1763 case BR_SIZE_16YY:
1764 case BR_SIZE_32_AND_16Y:
1765 fprintf(fp, ".y");
1766 break;
1767 default:
1768 break;
1769 }
1770 fprintf(fp, ", ");
1771 }
1772 // I haven't had the chance to test if this actually specifies the
1773 // branch offset, since I couldn't get it to produce values other
1774 // than 5 (uniform/const high), but these three bits are always
1775 // consistent across branch instructions, so it makes sense...
1776 int offsetSrc = (ADD.op >> 3) & 0x7;
1777 if (offsetSrc == 4 || offsetSrc == 5) {
1778 // If the offset is known/constant, we can decode it
1779 uint32_t raw_offset;
1780 if (offsetSrc == 4)
1781 raw_offset = get_const(consts, regs);
1782 else
1783 raw_offset = get_const(consts, regs) >> 32;
1784 // The high 4 bits are flags, while the rest is the
1785 // twos-complement offset in bytes (here we convert to
1786 // clauses).
1787 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1788
1789 // If high4 is the high 4 bits of the last 64-bit constant,
1790 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1791 // offset itself is the last constant. Not sure if this is
1792 // actually used, or just garbage in unused bits, but in any
1793 // case, we can just ignore it here since it's redundant. Note
1794 // that if there is any padding, this will be 4 since the
1795 // padding counts as the last constant.
1796 unsigned flags = raw_offset >> 28;
1797 (void) flags;
1798
1799 // Note: the offset is in bytes, relative to the beginning of the
1800 // current clause, so a zero offset would be a loop back to the
1801 // same clause (annoyingly different from Midgard).
1802 fprintf(fp, "clause_%d", offset + branch_offset);
1803 } else {
1804 dump_src(fp, offsetSrc, regs, consts, false);
1805 }
1806 }
1807 }
1808 if (info.has_data_reg) {
1809 fprintf(fp, ", R%d", data_reg);
1810 }
1811 fprintf(fp, "\n");
1812 }
1813
1814 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1815 struct bifrost_regs next_regs, uint64_t *consts,
1816 unsigned data_reg, unsigned offset, bool verbose)
1817 {
1818 struct bifrost_regs regs;
1819 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1820
1821 if (verbose) {
1822 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1823 dump_regs(fp, regs);
1824 }
1825 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1826 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1827 }
1828
1829 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1830 {
1831 // State for a decoded clause
1832 struct bifrost_alu_inst instrs[8] = {};
1833 uint64_t consts[6] = {};
1834 unsigned num_instrs = 0;
1835 unsigned num_consts = 0;
1836 uint64_t header_bits = 0;
1837 bool stopbit = false;
1838
1839 unsigned i;
1840 for (i = 0; ; i++, words += 4) {
1841 if (verbose) {
1842 fprintf(fp, "# ");
1843 for (int j = 0; j < 4; j++)
1844 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1845 fprintf(fp, "\n");
1846 }
1847 unsigned tag = bits(words[0], 0, 8);
1848
1849 // speculatively decode some things that are common between many formats, so we can share some code
1850 struct bifrost_alu_inst main_instr = {};
1851 // 20 bits
1852 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1853 // 23 bits
1854 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1855 // 35 bits
1856 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1857
1858 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1859 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1860
1861 bool stop = tag & 0x40;
1862
1863 if (verbose) {
1864 fprintf(fp, "# tag: 0x%02x\n", tag);
1865 }
1866 if (tag & 0x80) {
1867 unsigned idx = stop ? 5 : 2;
1868 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1869 instrs[idx + 1] = main_instr;
1870 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1871 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1872 consts[0] = bits(words[3], 17, 32) << 4;
1873 } else {
1874 bool done = false;
1875 switch ((tag >> 3) & 0x7) {
1876 case 0x0:
1877 switch (tag & 0x7) {
1878 case 0x3:
1879 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1880 instrs[1] = main_instr;
1881 num_instrs = 2;
1882 done = stop;
1883 break;
1884 case 0x4:
1885 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1886 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1887 consts[0] = const0;
1888 num_instrs = 3;
1889 num_consts = 1;
1890 done = stop;
1891 break;
1892 case 0x1:
1893 case 0x5:
1894 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1895 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1896 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1897 instrs[3] = main_instr;
1898 if ((tag & 0x7) == 0x5) {
1899 num_instrs = 4;
1900 done = stop;
1901 }
1902 break;
1903 case 0x6:
1904 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1905 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1906 consts[0] = const0;
1907 num_instrs = 6;
1908 num_consts = 1;
1909 done = stop;
1910 break;
1911 case 0x7:
1912 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1913 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1914 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1915 instrs[6] = main_instr;
1916 num_instrs = 7;
1917 done = stop;
1918 break;
1919 default:
1920 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1921 }
1922 break;
1923 case 0x2:
1924 case 0x3: {
1925 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1926 main_instr.add_bits |= (tag & 0x7) << 17;
1927 instrs[idx] = main_instr;
1928 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1929 num_consts = 1;
1930 num_instrs = idx + 1;
1931 done = stop;
1932 break;
1933 }
1934 case 0x4: {
1935 unsigned idx = stop ? 4 : 1;
1936 main_instr.add_bits |= (tag & 0x7) << 17;
1937 instrs[idx] = main_instr;
1938 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1939 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1940 break;
1941 }
1942 case 0x1:
1943 // only constants can come after this
1944 num_instrs = 1;
1945 done = stop;
1946 case 0x5:
1947 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1948 main_instr.add_bits |= (tag & 0x7) << 17;
1949 instrs[0] = main_instr;
1950 break;
1951 case 0x6:
1952 case 0x7: {
1953 unsigned pos = tag & 0xf;
1954 // note that `pos' encodes both the total number of
1955 // instructions and the position in the constant stream,
1956 // presumably because decoded constants and instructions
1957 // share a buffer in the decoder, but we only care about
1958 // the position in the constant stream; the total number of
1959 // instructions is redundant.
1960 unsigned const_idx = 0;
1961 switch (pos) {
1962 case 0:
1963 case 1:
1964 case 2:
1965 case 6:
1966 const_idx = 0;
1967 break;
1968 case 3:
1969 case 4:
1970 case 7:
1971 case 9:
1972 const_idx = 1;
1973 break;
1974 case 5:
1975 case 0xa:
1976 const_idx = 2;
1977 break;
1978 case 8:
1979 case 0xb:
1980 case 0xc:
1981 const_idx = 3;
1982 break;
1983 case 0xd:
1984 const_idx = 4;
1985 break;
1986 default:
1987 fprintf(fp, "# unknown pos 0x%x\n", pos);
1988 break;
1989 }
1990
1991 if (num_consts < const_idx + 2)
1992 num_consts = const_idx + 2;
1993
1994 consts[const_idx] = const0;
1995 consts[const_idx + 1] = const1;
1996 done = stop;
1997 break;
1998 }
1999 default:
2000 break;
2001 }
2002
2003 if (done)
2004 break;
2005 }
2006 }
2007
2008 *size = i + 1;
2009
2010 if (verbose) {
2011 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2012 }
2013
2014 struct bifrost_header header;
2015 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2016 dump_header(fp, header, verbose);
2017 if (!header.no_end_of_shader)
2018 stopbit = true;
2019
2020 fprintf(fp, "{\n");
2021 for (i = 0; i < num_instrs; i++) {
2022 struct bifrost_regs next_regs;
2023 if (i + 1 == num_instrs) {
2024 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2025 sizeof(next_regs));
2026 } else {
2027 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2028 sizeof(next_regs));
2029 }
2030
2031 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2032 }
2033 fprintf(fp, "}\n");
2034
2035 if (verbose) {
2036 for (unsigned i = 0; i < num_consts; i++) {
2037 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2038 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2039 }
2040 }
2041 return stopbit;
2042 }
2043
2044 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2045 {
2046 uint32_t *words = (uint32_t *) code;
2047 uint32_t *words_end = words + (size / 4);
2048 // used for displaying branch targets
2049 unsigned offset = 0;
2050 while (words != words_end) {
2051 // we don't know what the program-end bit is quite yet, so for now just
2052 // assume that an all-0 quadword is padding
2053 uint32_t zero[4] = {};
2054 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2055 break;
2056 fprintf(fp, "clause_%d:\n", offset);
2057 unsigned size;
2058 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2059 break;
2060 }
2061 words += size * 4;
2062 offset += size;
2063 }
2064 }
2065