2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
32 #include <panfrost-misc.h>
37 JOB_TYPE_SET_VALUE
= 2,
38 JOB_TYPE_CACHE_FLUSH
= 3,
41 JOB_TYPE_GEOMETRY
= 6,
44 JOB_TYPE_FRAGMENT
= 9,
51 MALI_LINE_STRIP
= 0x4,
54 MALI_TRIANGLE_STRIP
= 0xA,
55 MALI_TRIANGLE_FAN
= 0xC,
58 MALI_QUAD_STRIP
= 0xF,
60 /* All other modes invalid */
63 /* Applies to tiler_gl_enables */
65 #define MALI_OCCLUSION_QUERY (1 << 3)
66 #define MALI_OCCLUSION_PRECISE (1 << 4)
68 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
69 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
70 * disagree about how to do viewport flipping, so the blob actually sets this
71 * for GL_CW but then has a negative viewport stride */
73 #define MALI_FRONT_CCW_TOP (1 << 5)
75 #define MALI_CULL_FACE_FRONT (1 << 6)
76 #define MALI_CULL_FACE_BACK (1 << 7)
78 /* Used in stencil and depth tests */
85 MALI_FUNC_GREATER
= 4,
86 MALI_FUNC_NOTEQUAL
= 5,
91 /* Same OpenGL, but mixed up. Why? Because forget me, that's why! */
94 MALI_ALT_FUNC_NEVER
= 0,
95 MALI_ALT_FUNC_GREATER
= 1,
96 MALI_ALT_FUNC_EQUAL
= 2,
97 MALI_ALT_FUNC_GEQUAL
= 3,
98 MALI_ALT_FUNC_LESS
= 4,
99 MALI_ALT_FUNC_NOTEQUAL
= 5,
100 MALI_ALT_FUNC_LEQUAL
= 6,
101 MALI_ALT_FUNC_ALWAYS
= 7
104 /* Flags apply to unknown2_3? */
106 #define MALI_HAS_MSAA (1 << 0)
107 #define MALI_CAN_DISCARD (1 << 5)
109 /* Applies on SFBD systems, specifying that programmable blending is in use */
110 #define MALI_HAS_BLEND_SHADER (1 << 6)
112 /* func is mali_func */
113 #define MALI_DEPTH_FUNC(func) (func << 8)
114 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
115 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
117 #define MALI_DEPTH_WRITEMASK (1 << 11)
119 /* Next flags to unknown2_4 */
120 #define MALI_STENCIL_TEST (1 << 0)
123 #define MALI_SAMPLE_ALPHA_TO_COVERAGE_NO_BLEND_SHADER (1 << 1)
125 #define MALI_NO_DITHER (1 << 9)
126 #define MALI_DEPTH_RANGE_A (1 << 12)
127 #define MALI_DEPTH_RANGE_B (1 << 13)
128 #define MALI_NO_MSAA (1 << 14)
130 /* Stencil test state is all encoded in a single u32, just with a lot of
133 enum mali_stencil_op
{
134 MALI_STENCIL_KEEP
= 0,
135 MALI_STENCIL_REPLACE
= 1,
136 MALI_STENCIL_ZERO
= 2,
137 MALI_STENCIL_INVERT
= 3,
138 MALI_STENCIL_INCR_WRAP
= 4,
139 MALI_STENCIL_DECR_WRAP
= 5,
140 MALI_STENCIL_INCR
= 6,
141 MALI_STENCIL_DECR
= 7
144 struct mali_stencil_test
{
147 enum mali_func func
: 3;
148 enum mali_stencil_op sfail
: 3;
149 enum mali_stencil_op dpfail
: 3;
150 enum mali_stencil_op dppass
: 3;
152 } __attribute__((packed
));
154 #define MALI_MASK_R (1 << 0)
155 #define MALI_MASK_G (1 << 1)
156 #define MALI_MASK_B (1 << 2)
157 #define MALI_MASK_A (1 << 3)
159 enum mali_nondominant_mode
{
160 MALI_BLEND_NON_MIRROR
= 0,
161 MALI_BLEND_NON_ZERO
= 1
164 enum mali_dominant_blend
{
165 MALI_BLEND_DOM_SOURCE
= 0,
166 MALI_BLEND_DOM_DESTINATION
= 1
169 enum mali_dominant_factor
{
170 MALI_DOMINANT_UNK0
= 0,
171 MALI_DOMINANT_ZERO
= 1,
172 MALI_DOMINANT_SRC_COLOR
= 2,
173 MALI_DOMINANT_DST_COLOR
= 3,
174 MALI_DOMINANT_UNK4
= 4,
175 MALI_DOMINANT_SRC_ALPHA
= 5,
176 MALI_DOMINANT_DST_ALPHA
= 6,
177 MALI_DOMINANT_CONSTANT
= 7,
180 enum mali_blend_modifier
{
181 MALI_BLEND_MOD_UNK0
= 0,
182 MALI_BLEND_MOD_NORMAL
= 1,
183 MALI_BLEND_MOD_SOURCE_ONE
= 2,
184 MALI_BLEND_MOD_DEST_ONE
= 3,
187 struct mali_blend_mode
{
188 enum mali_blend_modifier clip_modifier
: 2;
189 unsigned unused_0
: 1;
190 unsigned negate_source
: 1;
192 enum mali_dominant_blend dominant
: 1;
194 enum mali_nondominant_mode nondominant_mode
: 1;
196 unsigned unused_1
: 1;
198 unsigned negate_dest
: 1;
200 enum mali_dominant_factor dominant_factor
: 3;
201 unsigned complement_dominant
: 1;
202 } __attribute__((packed
));
204 struct mali_blend_equation
{
205 /* Of type mali_blend_mode */
206 unsigned rgb_mode
: 12;
207 unsigned alpha_mode
: 12;
211 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
213 unsigned color_mask
: 4;
214 } __attribute__((packed
));
216 /* Used with channel swizzling */
218 MALI_CHANNEL_RED
= 0,
219 MALI_CHANNEL_GREEN
= 1,
220 MALI_CHANNEL_BLUE
= 2,
221 MALI_CHANNEL_ALPHA
= 3,
222 MALI_CHANNEL_ZERO
= 4,
223 MALI_CHANNEL_ONE
= 5,
224 MALI_CHANNEL_RESERVED_0
= 6,
225 MALI_CHANNEL_RESERVED_1
= 7,
228 struct mali_channel_swizzle
{
229 enum mali_channel r
: 3;
230 enum mali_channel g
: 3;
231 enum mali_channel b
: 3;
232 enum mali_channel a
: 3;
233 } __attribute__((packed
));
235 /* Compressed per-pixel formats. Each of these formats expands to one to four
236 * floating-point or integer numbers, as defined by the OpenGL specification.
237 * There are various places in OpenGL where the user can specify a compressed
238 * format in memory, which all use the same 8-bit enum in the various
239 * descriptors, although different hardware units support different formats.
242 /* The top 3 bits specify how the bits of each component are interpreted. */
244 /* e.g. R11F_G11F_B10F */
245 #define MALI_FORMAT_SPECIAL (2 << 5)
247 /* signed normalized, e.g. RGBA8_SNORM */
248 #define MALI_FORMAT_SNORM (3 << 5)
251 #define MALI_FORMAT_UINT (4 << 5)
253 /* e.g. RGBA8 and RGBA32F */
254 #define MALI_FORMAT_UNORM (5 << 5)
256 /* e.g. RGBA8I and RGBA16F */
257 #define MALI_FORMAT_SINT (6 << 5)
259 /* These formats seem to largely duplicate the others. They're used at least
260 * for Bifrost framebuffer output.
262 #define MALI_FORMAT_SPECIAL2 (7 << 5)
264 /* If the high 3 bits are 3 to 6 these two bits say how many components
267 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
269 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
270 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
274 #define MALI_CHANNEL_4 2
276 #define MALI_CHANNEL_8 3
278 #define MALI_CHANNEL_16 4
280 #define MALI_CHANNEL_32 5
282 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
283 * MALI_FORMAT_UNORM, it means a 32-bit float.
285 #define MALI_CHANNEL_FLOAT 7
288 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
289 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
290 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
291 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
292 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
293 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
296 MALI_NV12
= MALI_FORMAT_SPECIAL
| 0xc,
298 MALI_Z32_UNORM
= MALI_FORMAT_SPECIAL
| 0xD,
299 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
300 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
301 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
302 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
303 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
304 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
305 /* Only used for varyings, to indicate the transformed gl_Position */
306 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
307 /* Only used for varyings, to indicate that the write should be
310 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
312 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
313 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
314 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
315 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
316 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
317 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
318 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
319 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
320 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
321 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
322 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
323 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
325 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
326 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
327 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
328 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
329 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
330 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
331 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
332 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
333 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
334 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
335 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
336 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
338 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
339 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
340 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
341 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
342 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
343 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
344 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
345 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
346 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
347 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
348 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
349 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
350 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
351 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
352 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
353 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
354 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
356 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
357 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
358 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
359 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
360 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
361 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
362 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
363 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
364 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
365 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
366 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
367 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
368 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
369 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
370 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
371 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
373 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
374 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
375 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
379 /* Alpha coverage is encoded as 4-bits (from a clampf), with inversion
380 * literally performing a bitwise invert. This function produces slightly wrong
381 * results and I'm not sure why; some rounding issue I suppose... */
383 #define MALI_ALPHA_COVERAGE(clampf) ((uint16_t) (int) (clampf * 15.0f))
384 #define MALI_GET_ALPHA_COVERAGE(nibble) ((float) nibble / 15.0f)
386 /* Applies to midgard1.flags */
388 /* Should the hardware perform early-Z testing? Normally should be set
389 * for performance reasons. Clear if you use: discard,
390 * alpha-to-coverage... * It's also possible this disables
391 * forward-pixel kill; we're not quite sure which bit is which yet.
392 * TODO: How does this interact with blending?*/
394 #define MALI_EARLY_Z (1 << 6)
396 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
397 * fragment shader that uses texturing or derivative functions */
399 #define MALI_HELPER_INVOCATIONS (1 << 7)
401 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
402 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
403 * it might read depth/stencil in particular, also set MALI_READS_ZS */
405 #define MALI_READS_ZS (1 << 8)
406 #define MALI_READS_TILEBUFFER (1 << 12)
408 /* The raw Midgard blend payload can either be an equation or a shader
409 * address, depending on the context */
411 union midgard_blend
{
415 struct mali_blend_equation equation
;
420 /* On MRT Midgard systems (using an MFBD), each render target gets its own
421 * blend descriptor */
423 #define MALI_BLEND_SRGB (0x400)
425 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
426 #define MALI_BLEND_NO_DITHER (0x800)
428 struct midgard_blend_rt
{
429 /* Flags base value of 0x200 to enable the render target.
430 * OR with 0x1 for blending (anything other than REPLACE).
431 * OR with 0x2 for programmable blending with 0-2 registers
432 * OR with 0x3 for programmable blending with 2+ registers
433 * OR with MALI_BLEND_SRGB for implicit sRGB
437 union midgard_blend blend
;
438 } __attribute__((packed
));
440 /* On Bifrost systems (all MRT), each render target gets one of these
443 struct bifrost_blend_rt
{
444 /* This is likely an analogue of the flags on
445 * midgard_blend_rt */
447 u16 flags
; // = 0x200
449 /* Single-channel blend constants are encoded in a sort of
450 * fixed-point. Basically, the float is mapped to a byte, becoming
451 * a high byte, and then the lower-byte is added for precision.
452 * For the original float f:
454 * f = (constant_hi / 255) + (constant_lo / 65535)
456 * constant_hi = int(f / 255)
457 * constant_lo = 65535*f - (65535/255) * constant_hi
462 struct mali_blend_equation equation
;
465 * - 0x3 when this slot is unused (everything else is 0 except the index)
466 * - 0x11 when this is the fourth slot (and it's used)
467 + * - 0 when there is a blend shader
470 /* increments from 0 to 3 */
475 /* So far, I've only seen:
476 * - R001 for 1-component formats
477 * - RG01 for 2-component formats
478 * - RGB1 for 3-component formats
479 * - RGBA for 4-component formats
482 enum mali_format format
: 8;
484 /* Type of the shader output variable. Note, this can
485 * be different from the format.
487 * 0: f16 (mediump float)
488 * 1: f32 (highp float)
490 * 3: u32 (highp uint)
491 * 4: i16 (mediump int)
492 * 5: u16 (mediump uint)
498 /* Only the low 32 bits of the blend shader are stored, the
499 * high 32 bits are implicitly the same as the original shader.
500 * According to the kernel driver, the program counter for
501 * shaders is actually only 24 bits, so shaders cannot cross
502 * the 2^24-byte boundary, and neither can the blend shader.
503 * The blob handles this by allocating a 2^24 byte pool for
504 * shaders, and making sure that any blend shaders are stored
505 * in the same pool as the original shader. The kernel will
506 * make sure this allocation is aligned to 2^24 bytes.
510 } __attribute__((packed
));
512 /* Descriptor for the shader. Following this is at least one, up to four blend
513 * descriptors for each active render target */
515 struct mali_shader_meta
{
524 u32 uniform_buffer_count
: 4;
525 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
528 unsigned uniform_buffer_count
: 4;
531 /* Whole number of uniform registers used, times two;
532 * whole number of work registers used (no scale).
534 unsigned work_count
: 5;
535 unsigned uniform_count
: 5;
536 unsigned unknown2
: 6;
540 /* Same as glPolygoOffset() arguments */
549 u8 stencil_mask_front
;
550 u8 stencil_mask_back
;
553 struct mali_stencil_test stencil_front
;
554 struct mali_stencil_test stencil_back
;
559 /* On Bifrost, some system values are preloaded in
560 * registers R55-R62 by the thread dispatcher prior to
561 * the start of shader execution. This is a bitfield
562 * with one entry for each register saying which
563 * registers need to be preloaded. Right now, the known
567 * - R55 : gl_LocalInvocationID.xy
568 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
569 * - R57 : gl_WorkGroupID.x
570 * - R58 : gl_WorkGroupID.y
571 * - R59 : gl_WorkGroupID.z
572 * - R60 : gl_GlobalInvocationID.x
573 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
574 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
577 * - R55 : unknown, never seen (but the bit for this is
579 * - R56 : unknown (bit always unset)
580 * - R57 : gl_PrimitiveID
581 * - R58 : gl_FrontFacing in low bit, potentially other stuff
582 * - R59 : u16 fragment coordinates (used to compute
583 * gl_FragCoord.xy, together with sample positions)
584 * - R60 : gl_SampleMask (used in epilog, so pretty
585 * much always used, but the bit is always 0 -- is
586 * this just always pushed?)
587 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
588 * varying interpolation.
589 * - R62 : unknown (bit always unset).
591 u32 preload_regs
: 8;
592 /* In units of 8 bytes or 64 bits, since the
593 * uniform/const port loads 64 bits at a time.
595 u32 uniform_count
: 7;
596 u32 unk4
: 10; // = 2
603 /* zero on bifrost */
606 /* Blending information for the older non-MRT Midgard HW. Check for
607 * MALI_HAS_BLEND_SHADER to decide how to interpret.
610 union midgard_blend blend
;
611 } __attribute__((packed
));
613 /* This only concerns hardware jobs */
615 /* Possible values for job_descriptor_size */
617 #define MALI_JOB_32 0
618 #define MALI_JOB_64 1
620 struct mali_job_descriptor_header
{
621 u32 exception_status
;
622 u32 first_incomplete_task
;
624 u8 job_descriptor_size
: 1;
625 enum mali_job_type job_type
: 7;
627 u8 unknown_flags
: 7;
629 u16 job_dependency_index_1
;
630 u16 job_dependency_index_2
;
636 } __attribute__((packed
));
638 /* These concern exception_status */
640 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
643 enum mali_exception_access
{
644 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
645 * fault so it's just unused */
646 MALI_EXCEPTION_ACCESS_NONE
= 0,
648 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
649 MALI_EXCEPTION_ACCESS_READ
= 2,
650 MALI_EXCEPTION_ACCESS_WRITE
= 3
653 struct mali_payload_set_value
{
656 } __attribute__((packed
));
658 /* Special attributes have a fixed index */
659 #define MALI_SPECIAL_ATTRIBUTE_BASE 16
660 #define MALI_VERTEX_ID (MALI_SPECIAL_ATTRIBUTE_BASE + 0)
661 #define MALI_INSTANCE_ID (MALI_SPECIAL_ATTRIBUTE_BASE + 1)
666 * This structure lets the attribute unit compute the address of an attribute
667 * given the vertex and instance ID. Unfortunately, the way this works is
668 * rather complicated when instancing is enabled.
670 * To explain this, first we need to explain how compute and vertex threads are
671 * dispatched. This is a guess (although a pretty firm guess!) since the
672 * details are mostly hidden from the driver, except for attribute instancing.
673 * When a quad is dispatched, it receives a single, linear index. However, we
674 * need to translate that index into a (vertex id, instance id) pair, or a
675 * (local id x, local id y, local id z) triple for compute shaders (although
676 * vertex shaders and compute shaders are handled almost identically).
677 * Focusing on vertex shaders, one option would be to do:
679 * vertex_id = linear_id % num_vertices
680 * instance_id = linear_id / num_vertices
682 * but this involves a costly division and modulus by an arbitrary number.
683 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
684 * num_instances threads instead of num_vertices * num_instances, which results
685 * in some "extra" threads with vertex_id >= num_vertices, which we have to
686 * discard. The more we pad num_vertices, the more "wasted" threads we
687 * dispatch, but the division is potentially easier.
689 * One straightforward choice is to pad num_vertices to the next power of two,
690 * which means that the division and modulus are just simple bit shifts and
691 * masking. But the actual algorithm is a bit more complicated. The thread
692 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
693 * to dividing by a power of two. This is possibly using the technique
694 * described in patent US20170010862A1. As a result, padded_num_vertices can be
695 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
696 * since we need less padding.
698 * padded_num_vertices is picked by the hardware. The driver just specifies the
699 * actual number of vertices. At least for Mali G71, the first few cases are
702 * num_vertices | padded_num_vertices
709 * Note that padded_num_vertices is a multiple of four (presumably because
710 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
711 * at least one more than num_vertices, which seems like a quirk of the
712 * hardware. For larger num_vertices, the hardware uses the following
713 * algorithm: using the binary representation of num_vertices, we look at the
714 * most significant set bit as well as the following 3 bits. Let n be the
715 * number of bits after those 4 bits. Then we set padded_num_vertices according
716 * to the following table:
718 * high bits | padded_num_vertices
725 * For example, if num_vertices = 70 is passed to glDraw(), its binary
726 * representation is 1000110, so n = 3 and the high bits are 1000, and
727 * therefore padded_num_vertices = 9 * 2^3 = 72.
729 * The attribute unit works in terms of the original linear_id. if
730 * num_instances = 1, then they are the same, and everything is simple.
731 * However, with instancing things get more complicated. There are four
732 * possible modes, two of them we can group together:
734 * 1. Use the linear_id directly. Only used when there is no instancing.
736 * 2. Use the linear_id modulo a constant. This is used for per-vertex
737 * attributes with instancing enabled by making the constant equal
738 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
739 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
740 * The shift field specifies the power of two, while the extra_flags field
741 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
742 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
743 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
744 * shift = 3. Note that we must exactly follow the hardware algorithm used to
745 * get padded_num_vertices in order to correctly implement per-vertex
748 * 3. Divide the linear_id by a constant. In order to correctly implement
749 * instance divisors, we have to divide linear_id by padded_num_vertices times
750 * to user-specified divisor. So first we compute padded_num_vertices, again
751 * following the exact same algorithm that the hardware uses, then multiply it
752 * by the GL-level divisor to get the hardware-level divisor. This case is
753 * further divided into two more cases. If the hardware-level divisor is a
754 * power of two, then we just need to shift. The shift amount is specified by
755 * the shift field, so that the hardware-level divisor is just 2^shift.
757 * If it isn't a power of two, then we have to divide by an arbitrary integer.
758 * For that, we use the well-known technique of multiplying by an approximation
759 * of the inverse. The driver must compute the magic multiplier and shift
760 * amount, and then the hardware does the multiplication and shift. The
761 * hardware and driver also use the "round-down" optimization as described in
762 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
763 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
764 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
765 * presumably this simplifies the hardware multiplier a little. The hardware
766 * first multiplies linear_id by the multiplier and takes the high 32 bits,
767 * then applies the round-down correction if extra_flags = 1, then finally
768 * shifts right by the shift field.
770 * There are some differences between ridiculousfish's algorithm and the Mali
771 * hardware algorithm, which means that the reference code from ridiculousfish
772 * doesn't always produce the right constants. Mali does not use the pre-shift
773 * optimization, since that would make a hardware implementation slower (it
774 * would have to always do the pre-shift, multiply, and post-shift operations).
775 * It also forces the multplier to be at least 2^31, which means that the
776 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
777 * given the divisor d, the algorithm the driver must follow is:
779 * 1. Set shift = floor(log2(d)).
780 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
781 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
782 * magic_divisor = m - 1 and extra_flags = 1.
783 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
785 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
786 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
787 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
788 * (*NOT the row stride*). Size is set to the size of the image itself.
790 * Special internal varyings (including gl_FrontFacing) could be seen as
791 * IMAGE/INTERNAL as well as LINEAR, setting all fields set to zero and using a
792 * special elements pseudo-pointer.
795 enum mali_attr_mode
{
796 MALI_ATTR_UNUSED
= 0,
797 MALI_ATTR_LINEAR
= 1,
798 MALI_ATTR_POT_DIVIDE
= 2,
799 MALI_ATTR_MODULO
= 3,
800 MALI_ATTR_NPOT_DIVIDE
= 4,
802 MALI_ATTR_INTERNAL
= 6
805 /* Pseudo-address for gl_FrontFacing, used with INTERNAL. Same addres is used
806 * for gl_FragCoord with IMAGE, needing a coordinate flip. Who knows. */
808 #define MALI_VARYING_FRAG_COORD (0x25)
809 #define MALI_VARYING_FRONT_FACING (0x26)
811 /* This magic "pseudo-address" is used as `elements` to implement
812 * gl_PointCoord. When read from a fragment shader, it generates a point
813 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
814 * require an affine transformation in the shader. */
816 #define MALI_VARYING_POINT_COORD (0x61)
818 /* Used for comparison to check if an address is special. Mostly a guess, but
819 * it doesn't really matter. */
821 #define MALI_VARYING_SPECIAL (0x100)
824 /* This is used for actual attributes. */
826 /* The bottom 3 bits are the mode */
827 mali_ptr elements
: 64 - 8;
833 /* The entry after an NPOT_DIVIDE entry has this format. It stores
834 * extra information that wouldn't fit in a normal entry.
837 u32 unk
; /* = 0x20 */
840 /* This is the original, GL-level divisor. */
843 } __attribute__((packed
));
845 struct mali_attr_meta
{
846 /* Vertex buffer index */
849 unsigned unknown1
: 2;
850 unsigned swizzle
: 12;
851 enum mali_format format
: 8;
853 /* Always observed to be zero at the moment */
854 unsigned unknown3
: 2;
856 /* When packing multiple attributes in a buffer, offset addresses by
857 * this value. Obscurely, this is signed. */
859 } __attribute__((packed
));
867 #define FBD_MASK (~0x3f)
869 /* ORed into an MFBD address to specify the fbx section is included */
870 #define MALI_MFBD_TAG_EXTRA (0x2)
872 struct mali_uniform_buffer_meta
{
873 /* This is actually the size minus 1 (MALI_POSITIVE), in units of 16
874 * bytes. This gives a maximum of 2^14 bytes, which just so happens to
875 * be the GL minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
879 /* This is missing the bottom 2 bits and top 8 bits. The top 8 bits
880 * should be 0 for userspace pointers, according to
881 * https://lwn.net/Articles/718895/. By reusing these bits, we can make
882 * each entry in the table only 64 bits.
884 mali_ptr ptr
: 64 - 10;
887 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
888 * They also seem to be the same between Bifrost and Midgard. They're shared in
892 /* Applies to unknown_draw */
894 #define MALI_DRAW_INDEXED_UINT8 (0x10)
895 #define MALI_DRAW_INDEXED_UINT16 (0x20)
896 #define MALI_DRAW_INDEXED_UINT32 (0x30)
897 #define MALI_DRAW_INDEXED_SIZE (0x30)
898 #define MALI_DRAW_INDEXED_SHIFT (4)
900 #define MALI_DRAW_VARYING_SIZE (0x100)
901 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
903 struct mali_vertex_tiler_prefix
{
904 /* This is a dynamic bitfield containing the following things in this order:
906 * - gl_WorkGroupSize.x
907 * - gl_WorkGroupSize.y
908 * - gl_WorkGroupSize.z
909 * - gl_NumWorkGroups.x
910 * - gl_NumWorkGroups.y
911 * - gl_NumWorkGroups.z
913 * The number of bits allocated for each number is based on the *_shift
914 * fields below. For example, workgroups_y_shift gives the bit that
915 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
916 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
917 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
918 * value is one more than the stored value, since if any of the values
919 * are zero, then there would be no invocations (and hence no job). If
920 * there were 0 bits allocated to a given field, then it must be zero,
921 * and hence the real value is one.
923 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
924 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
925 * where vertex count is the number of vertices.
927 u32 invocation_count
;
929 u32 size_y_shift
: 5;
930 u32 size_z_shift
: 5;
931 u32 workgroups_x_shift
: 6;
932 u32 workgroups_y_shift
: 6;
933 u32 workgroups_z_shift
: 6;
934 /* This is max(workgroups_x_shift, 2) in all the cases I've seen. */
935 u32 workgroups_x_shift_2
: 4;
938 u32 unknown_draw
: 22;
940 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
941 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
942 * something to do with how many quads get put in the same execution
943 * engine, which is a balance (you don't want to starve the engine, but
944 * you also want to distribute work evenly).
946 u32 workgroups_x_shift_3
: 6;
949 /* Negative of min_index. This is used to compute
950 * the unbiased index in tiler/fragment shader runs.
952 * The hardware adds offset_bias_correction in each run,
953 * so that absent an index bias, the first vertex processed is
954 * genuinely the first vertex (0). But with an index bias,
955 * the first vertex process is numbered the same as the bias.
957 * To represent this more conviniently:
958 * unbiased_index = lower_bound_index +
960 * offset_bias_correction
962 * This is done since the hardware doesn't accept a index_bias
963 * and this allows it to recover the unbiased index.
965 int32_t offset_bias_correction
;
968 /* Like many other strictly nonzero quantities, index_count is
969 * subtracted by one. For an indexed cube, this is equal to 35 = 6
970 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
971 * for an indexed draw, index_count is the number of actual vertices
972 * rendered whereas invocation_count is the number of unique vertices
973 * rendered (the number of times the vertex shader must be invoked).
974 * For non-indexed draws, this is just equal to invocation_count. */
978 /* No hidden structure; literally just a pointer to an array of uint
979 * indices (width depends on flags). Thanks, guys, for not making my
980 * life insane for once! NULL for non-indexed draws. */
983 } __attribute__((packed
));
985 /* Point size / line width can either be specified as a 32-bit float (for
986 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
987 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
988 * payload, the contents of varying_pointer will be intepreted as an array of
989 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
990 * creating a special MALI_R16F varying writing to varying_pointer. */
992 union midgard_primitive_size
{
997 struct bifrost_vertex_only
{
1003 } __attribute__((packed
));
1005 struct bifrost_tiler_heap_meta
{
1008 /* note: these are just guesses! */
1009 mali_ptr tiler_heap_start
;
1010 mali_ptr tiler_heap_free
;
1011 mali_ptr tiler_heap_end
;
1013 /* hierarchy weights? but they're still 0 after the job has run... */
1015 } __attribute__((packed
));
1017 struct bifrost_tiler_meta
{
1024 mali_ptr tiler_heap_meta
;
1025 /* TODO what is this used for? */
1027 } __attribute__((packed
));
1029 struct bifrost_tiler_only
{
1031 union midgard_primitive_size primitive_size
;
1033 mali_ptr tiler_meta
;
1035 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1040 } __attribute__((packed
));
1042 struct bifrost_scratchpad
{
1044 u32 flags
; // = 0x1f
1045 /* This is a pointer to a CPU-inaccessible buffer, 16 pages, allocated
1046 * during startup. It seems to serve the same purpose as the
1047 * gpu_scratchpad in the SFBD for Midgard, although it's slightly
1050 mali_ptr gpu_scratchpad
;
1051 } __attribute__((packed
));
1053 struct mali_vertex_tiler_postfix
{
1054 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1055 * output from the vertex shader for tiler jobs.
1058 u64 position_varying
;
1060 /* An array of mali_uniform_buffer_meta's. The size is given by the
1063 u64 uniform_buffers
;
1065 /* This is a pointer to an array of pointers to the texture
1066 * descriptors, number of pointers bounded by number of textures. The
1067 * indirection is needed to accomodate varying numbers and sizes of
1068 * texture descriptors */
1069 u64 texture_trampoline
;
1071 /* For OpenGL, from what I've seen, this is intimately connected to
1072 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1073 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1074 * array of sampler descriptors (which are uniform in size) */
1075 u64 sampler_descriptor
;
1079 u64 attributes
; /* struct attribute_buffer[] */
1080 u64 attribute_meta
; /* attribute_meta[] */
1081 u64 varyings
; /* struct attr */
1082 u64 varying_meta
; /* pointer */
1084 u64 occlusion_counter
; /* A single bit as far as I can tell */
1086 /* Note: on Bifrost, this isn't actually the FBD. It points to
1087 * bifrost_scratchpad instead. However, it does point to the same thing
1088 * in vertex and tiler jobs.
1090 mali_ptr framebuffer
;
1091 } __attribute__((packed
));
1093 struct midgard_payload_vertex_tiler
{
1094 struct mali_vertex_tiler_prefix prefix
;
1096 u16 gl_enables
; // 0x5
1098 /* Both zero for non-instanced draws. For instanced draws, a
1099 * decomposition of padded_num_vertices. See the comments about the
1100 * corresponding fields in mali_attr for context. */
1102 unsigned instance_shift
: 5;
1103 unsigned instance_odd
: 3;
1107 /* Offset for first vertex in buffer */
1112 struct mali_vertex_tiler_postfix postfix
;
1114 union midgard_primitive_size primitive_size
;
1115 } __attribute__((packed
));
1117 struct bifrost_payload_vertex
{
1118 struct mali_vertex_tiler_prefix prefix
;
1119 struct bifrost_vertex_only vertex
;
1120 struct mali_vertex_tiler_postfix postfix
;
1121 } __attribute__((packed
));
1123 struct bifrost_payload_tiler
{
1124 struct mali_vertex_tiler_prefix prefix
;
1125 struct bifrost_tiler_only tiler
;
1126 struct mali_vertex_tiler_postfix postfix
;
1127 } __attribute__((packed
));
1129 struct bifrost_payload_fused
{
1130 struct mali_vertex_tiler_prefix prefix
;
1131 struct bifrost_tiler_only tiler
;
1132 struct mali_vertex_tiler_postfix tiler_postfix
;
1133 u64 padding
; /* zero */
1134 struct bifrost_vertex_only vertex
;
1135 struct mali_vertex_tiler_postfix vertex_postfix
;
1136 } __attribute__((packed
));
1138 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1139 * texture is stored as (63, 63) in these fields. This adjusts for that.
1140 * There's an identical pattern in the framebuffer descriptor. Even vertex
1141 * count fields work this way, hence the generic name -- integral fields that
1142 * are strictly positive generally need this adjustment. */
1144 #define MALI_POSITIVE(dim) (dim - 1)
1146 /* Opposite of MALI_POSITIVE, found in the depth_units field */
1148 #define MALI_NEGATIVE(dim) (dim + 1)
1150 /* Used with wrapping. Incomplete (this is a 4-bit field...) */
1152 enum mali_wrap_mode
{
1153 MALI_WRAP_REPEAT
= 0x8,
1154 MALI_WRAP_CLAMP_TO_EDGE
= 0x9,
1155 MALI_WRAP_CLAMP_TO_BORDER
= 0xB,
1156 MALI_WRAP_MIRRORED_REPEAT
= 0xC
1159 /* Shared across both command stream and Midgard, and even with Bifrost */
1161 enum mali_texture_type
{
1162 MALI_TEX_CUBE
= 0x0,
1169 #define MAX_MIP_LEVELS (13)
1171 /* Cubemap bloats everything up */
1172 #define MAX_CUBE_FACES (6)
1174 /* For each pointer, there is an address and optionally also a stride */
1175 #define MAX_ELEMENTS (2)
1177 /* It's not known why there are 4-bits allocated -- this enum is almost
1178 * certainly incomplete */
1180 enum mali_texture_layout
{
1181 /* For a Z/S texture, this is linear */
1182 MALI_TEXTURE_TILED
= 0x1,
1184 /* Z/S textures cannot be tiled */
1185 MALI_TEXTURE_LINEAR
= 0x2,
1188 MALI_TEXTURE_AFBC
= 0xC
1191 /* Corresponds to the type passed to glTexImage2D and so forth */
1193 struct mali_texture_format
{
1194 unsigned swizzle
: 12;
1195 enum mali_format format
: 8;
1198 unsigned unknown1
: 1;
1200 enum mali_texture_type type
: 2;
1201 enum mali_texture_layout layout
: 4;
1204 unsigned unknown2
: 1;
1206 /* Set to allow packing an explicit stride */
1207 unsigned manual_stride
: 1;
1210 } __attribute__((packed
));
1212 struct mali_texture_descriptor
{
1216 uint16_t array_size
;
1218 struct mali_texture_format format
;
1222 /* One for non-mipmapped, zero for mipmapped */
1225 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1228 /* Swizzling is a single 32-bit word, broken up here for convenience.
1229 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1230 * level swizzling, not the internal pixel-level swizzling which is
1231 * below OpenGL's reach */
1233 unsigned swizzle
: 12;
1234 unsigned swizzle_zero
: 20;
1240 mali_ptr payload
[MAX_MIP_LEVELS
* MAX_CUBE_FACES
* MAX_ELEMENTS
];
1241 } __attribute__((packed
));
1245 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1246 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1248 /* TODO: What do these bits mean individually? Only seen set together */
1250 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1251 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1253 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1254 * sampler_t flag. For typical OpenGL textures, this is always set. */
1256 #define MALI_SAMP_NORM_COORDS (1 << 5)
1258 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1259 * be cleaned up a lot. */
1261 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1263 static inline uint16_t
1266 /* Clamp inputs, accounting for float error */
1267 float max_lod
= (32.0 - (1.0 / 512.0));
1269 x
= ((x
> max_lod
) ? max_lod
: ((x
< 0.0) ? 0.0 : x
));
1271 return (int) (x
* 256.0);
1274 struct mali_sampler_descriptor
{
1275 uint32_t filter_mode
;
1277 /* Fixed point. Upper 8-bits is before the decimal point, although it
1278 * caps [0-31]. Lower 8-bits is after the decimal point: int(round(x *
1284 /* All one word in reality, but packed a bit */
1286 enum mali_wrap_mode wrap_s
: 4;
1287 enum mali_wrap_mode wrap_t
: 4;
1288 enum mali_wrap_mode wrap_r
: 4;
1289 enum mali_alt_func compare_func
: 3;
1291 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1292 * ES2, controlling seamless cubemapping */
1293 unsigned seamless_cube_map
: 1;
1298 float border_color
[4];
1299 } __attribute__((packed
));
1301 /* viewport0/viewport1 form the arguments to glViewport. viewport1 is
1302 * modified by MALI_POSITIVE; viewport0 is as-is.
1305 struct mali_viewport
{
1306 /* XY clipping planes */
1312 /* Depth clipping planes */
1318 } __attribute__((packed
));
1320 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1321 * of tile numbers. */
1323 #define MALI_TILE_SHIFT 4
1324 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1326 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1327 * each component. Notice that this provides a theoretical upper bound of (1 <<
1328 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1329 * 65536x65536. Multiplying that together, times another four given that Mali
1330 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1331 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1332 * alone rendering in real-time to such a buffer.
1336 /* From mali_kbase_10969_workaround.c */
1337 #define MALI_X_COORD_MASK 0x00000FFF
1338 #define MALI_Y_COORD_MASK 0x0FFF0000
1340 /* Extract parts of a tile coordinate */
1342 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1343 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1345 /* Helpers to generate tile coordinates based on the boundary coordinates in
1346 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1347 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1348 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1351 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1352 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1353 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1354 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1355 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1357 struct mali_payload_fragment
{
1360 mali_ptr framebuffer
;
1361 } __attribute__((packed
));
1363 /* Single Framebuffer Descriptor */
1365 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1366 * configured for 4x. With MSAA_8, it is configured for 8x. */
1368 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1369 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1370 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1371 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1373 /* Fast/slow based on whether all three buffers are cleared at once */
1375 #define MALI_CLEAR_FAST (1 << 18)
1376 #define MALI_CLEAR_SLOW (1 << 28)
1377 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1379 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1380 * within the larget framebuffer descriptor). Analogous to
1381 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1383 /* See pan_tiler.c for derivation */
1384 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1386 /* Flag disabling the tiler for clear-only jobs */
1387 #define MALI_TILER_DISABLED (1 << 12)
1389 struct midgard_tiler_descriptor
{
1390 /* Size of the entire polygon list; see pan_tiler.c for the
1391 * computation. It's based on hierarchical tiling */
1393 u32 polygon_list_size
;
1395 /* Name known from the replay workaround in the kernel. What exactly is
1396 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1397 * specifies a mask of hierarchy weights, which explains some of the
1398 * performance mysteries around setting it. We also see the bottom bit
1399 * of tiler_flags set in the kernel, but no comment why.
1401 * hierarchy_mask can have the TILER_DISABLED flag */
1406 /* See mali_tiler.c for an explanation */
1407 mali_ptr polygon_list
;
1408 mali_ptr polygon_list_body
;
1410 /* Names based on we see symmetry with replay jobs which name these
1413 mali_ptr heap_start
; /* tiler heap_free_address */
1416 /* Hierarchy weights. We know these are weights based on the kernel,
1417 * but I've never seen them be anything other than zero */
1421 enum mali_block_format
{
1422 MALI_BLOCK_TILED
= 0x0,
1423 MALI_BLOCK_UNKNOWN
= 0x1,
1424 MALI_BLOCK_LINEAR
= 0x2,
1425 MALI_BLOCK_AFBC
= 0x3,
1428 struct mali_sfbd_format
{
1432 /* mali_channel_swizzle */
1433 unsigned swizzle
: 12;
1436 unsigned nr_channels
: 2;
1441 enum mali_block_format block
: 2;
1447 struct mali_single_framebuffer
{
1450 u64 unknown_address_0
;
1454 struct mali_sfbd_format format
;
1459 /* Purposeful off-by-one in these fields should be accounted for by the
1460 * MALI_DIMENSION macro */
1467 u32 checksum_stride
;
1470 /* By default, the framebuffer is upside down from OpenGL's
1471 * perspective. Set framebuffer to the end and negate the stride to
1472 * flip in the Y direction */
1474 mali_ptr framebuffer
;
1479 /* Depth and stencil buffers are interleaved, it appears, as they are
1480 * set to the same address in captures. Both fields set to zero if the
1481 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1482 * get a zero enable despite the buffer being present; that still is
1485 mali_ptr depth_buffer
; // not SAME_VA
1486 u32 depth_stride_zero
: 4;
1487 u32 depth_stride
: 28;
1490 mali_ptr stencil_buffer
; // not SAME_VA
1491 u32 stencil_stride_zero
: 4;
1492 u32 stencil_stride
: 28;
1495 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1496 u32 clear_color_2
; // always equal, but unclear function?
1497 u32 clear_color_3
; // always equal, but unclear function?
1498 u32 clear_color_4
; // always equal, but unclear function?
1500 /* Set to zero if not cleared */
1502 float clear_depth_1
; // float32, ditto
1503 float clear_depth_2
; // float32, ditto
1504 float clear_depth_3
; // float32, ditto
1505 float clear_depth_4
; // float32, ditto
1507 u32 clear_stencil
; // Exactly as it appears in OpenGL
1511 struct midgard_tiler_descriptor tiler
;
1513 /* More below this, maybe */
1514 } __attribute__((packed
));
1516 /* On Midgard, this "framebuffer descriptor" is used for the framebuffer field
1517 * of compute jobs. Superficially resembles a single framebuffer descriptor */
1519 struct mali_compute_fbd
{
1521 } __attribute__((packed
));
1523 /* Format bits for the render target flags */
1525 #define MALI_MFBD_FORMAT_MSAA (1 << 1)
1526 #define MALI_MFBD_FORMAT_SRGB (1 << 2)
1528 struct mali_rt_format
{
1532 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1535 enum mali_block_format block
: 2;
1538 unsigned swizzle
: 12;
1542 /* Disables MFBD preload. When this bit is set, the render target will
1543 * be cleared every frame. When this bit is clear, the hardware will
1544 * automatically wallpaper the render target back from main memory.
1545 * Unfortunately, MFBD preload is very broken on Midgard, so in
1546 * practice, this is a chicken bit that should always be set.
1547 * Discovered by accident, as all good chicken bits are. */
1549 unsigned no_preload
: 1;
1550 } __attribute__((packed
));
1552 struct bifrost_render_target
{
1553 struct mali_rt_format format
;
1558 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1559 * there is an extra metadata buffer that contains 16 bytes per tile.
1560 * The framebuffer needs to be the same size as before, since we don't
1561 * know ahead of time how much space it will take up. The
1562 * framebuffer_stride is set to 0, since the data isn't stored linearly
1565 * When AFBC is disabled, these fields are zero.
1569 u32 stride
; // stride in units of tiles
1570 u32 unk
; // = 0x20000
1573 mali_ptr framebuffer
;
1576 u32 framebuffer_stride
: 28; // in units of bytes
1579 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1580 u32 clear_color_2
; // always equal, but unclear function?
1581 u32 clear_color_3
; // always equal, but unclear function?
1582 u32 clear_color_4
; // always equal, but unclear function?
1583 } __attribute__((packed
));
1585 /* An optional part of bifrost_framebuffer. It comes between the main structure
1586 * and the array of render targets. It must be included if any of these are
1589 * - Transaction Elimination
1591 * - TODO: Anything else?
1594 /* Flags field: note, these are guesses */
1596 #define MALI_EXTRA_PRESENT (0x400)
1597 #define MALI_EXTRA_AFBC (0x20)
1598 #define MALI_EXTRA_AFBC_ZS (0x10)
1599 #define MALI_EXTRA_ZS (0x4)
1601 struct bifrost_fb_extra
{
1603 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1604 u32 checksum_stride
;
1609 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1611 mali_ptr depth_stencil_afbc_metadata
;
1612 u32 depth_stencil_afbc_stride
; // in units of tiles
1615 mali_ptr depth_stencil
;
1621 /* Depth becomes depth/stencil in case of combined D/S */
1623 u32 depth_stride_zero
: 4;
1624 u32 depth_stride
: 28;
1628 u32 stencil_stride_zero
: 4;
1629 u32 stencil_stride
: 28;
1636 } __attribute__((packed
));
1638 /* Flags for mfbd_flags */
1640 /* Enables writing depth results back to main memory (rather than keeping them
1641 * on-chip in the tile buffer and then discarding) */
1643 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1645 /* The MFBD contains the extra bifrost_fb_extra section */
1647 #define MALI_MFBD_EXTRA (1 << 13)
1649 struct bifrost_framebuffer
{
1652 u32 unknown2
; // = 0x1f, same as SFBD
1653 mali_ptr scratchpad
;
1656 mali_ptr sample_locations
;
1659 u16 width1
, height1
;
1661 u16 width2
, height2
;
1662 u32 unk1
: 19; // = 0x01000
1663 u32 rt_count_1
: 2; // off-by-one (use MALI_POSITIVE)
1664 u32 unk2
: 3; // = 0
1665 u32 rt_count_2
: 3; // no off-by-one
1668 u32 clear_stencil
: 8;
1669 u32 mfbd_flags
: 24; // = 0x100
1672 struct midgard_tiler_descriptor tiler
;
1674 /* optional: struct bifrost_fb_extra extra */
1675 /* struct bifrost_render_target rts[] */
1676 } __attribute__((packed
));
1678 #endif /* __PANFROST_JOB_H__ */