2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
41 /* Applies to tiler_gl_enables */
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
51 #define MALI_FRONT_CCW_TOP (1 << 5)
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
56 /* Flags apply to unknown2_3? */
58 #define MALI_HAS_MSAA (1 << 0)
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
83 #define MALI_NO_DITHER (1 << 9)
84 #define MALI_DEPTH_RANGE_A (1 << 12)
85 #define MALI_DEPTH_RANGE_B (1 << 13)
86 #define MALI_NO_MSAA (1 << 14)
88 #define MALI_MASK_R (1 << 0)
89 #define MALI_MASK_G (1 << 1)
90 #define MALI_MASK_B (1 << 2)
91 #define MALI_MASK_A (1 << 3)
93 enum mali_nondominant_mode
{
94 MALI_BLEND_NON_MIRROR
= 0,
95 MALI_BLEND_NON_ZERO
= 1
98 enum mali_dominant_blend
{
99 MALI_BLEND_DOM_SOURCE
= 0,
100 MALI_BLEND_DOM_DESTINATION
= 1
103 enum mali_dominant_factor
{
104 MALI_DOMINANT_UNK0
= 0,
105 MALI_DOMINANT_ZERO
= 1,
106 MALI_DOMINANT_SRC_COLOR
= 2,
107 MALI_DOMINANT_DST_COLOR
= 3,
108 MALI_DOMINANT_UNK4
= 4,
109 MALI_DOMINANT_SRC_ALPHA
= 5,
110 MALI_DOMINANT_DST_ALPHA
= 6,
111 MALI_DOMINANT_CONSTANT
= 7,
114 enum mali_blend_modifier
{
115 MALI_BLEND_MOD_UNK0
= 0,
116 MALI_BLEND_MOD_NORMAL
= 1,
117 MALI_BLEND_MOD_SOURCE_ONE
= 2,
118 MALI_BLEND_MOD_DEST_ONE
= 3,
121 struct mali_blend_mode
{
122 enum mali_blend_modifier clip_modifier
: 2;
123 unsigned unused_0
: 1;
124 unsigned negate_source
: 1;
126 enum mali_dominant_blend dominant
: 1;
128 enum mali_nondominant_mode nondominant_mode
: 1;
130 unsigned unused_1
: 1;
132 unsigned negate_dest
: 1;
134 enum mali_dominant_factor dominant_factor
: 3;
135 unsigned complement_dominant
: 1;
136 } __attribute__((packed
));
138 struct mali_blend_equation
{
139 /* Of type mali_blend_mode */
140 unsigned rgb_mode
: 12;
141 unsigned alpha_mode
: 12;
145 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
147 unsigned color_mask
: 4;
148 } __attribute__((packed
));
150 /* Used with channel swizzling */
152 MALI_CHANNEL_RED
= 0,
153 MALI_CHANNEL_GREEN
= 1,
154 MALI_CHANNEL_BLUE
= 2,
155 MALI_CHANNEL_ALPHA
= 3,
156 MALI_CHANNEL_ZERO
= 4,
157 MALI_CHANNEL_ONE
= 5,
158 MALI_CHANNEL_RESERVED_0
= 6,
159 MALI_CHANNEL_RESERVED_1
= 7,
162 struct mali_channel_swizzle
{
163 enum mali_channel r
: 3;
164 enum mali_channel g
: 3;
165 enum mali_channel b
: 3;
166 enum mali_channel a
: 3;
167 } __attribute__((packed
));
169 /* Compressed per-pixel formats. Each of these formats expands to one to four
170 * floating-point or integer numbers, as defined by the OpenGL specification.
171 * There are various places in OpenGL where the user can specify a compressed
172 * format in memory, which all use the same 8-bit enum in the various
173 * descriptors, although different hardware units support different formats.
176 /* The top 3 bits specify how the bits of each component are interpreted. */
179 #define MALI_FORMAT_COMPRESSED (0 << 5)
181 /* e.g. R11F_G11F_B10F */
182 #define MALI_FORMAT_SPECIAL (2 << 5)
184 /* signed normalized, e.g. RGBA8_SNORM */
185 #define MALI_FORMAT_SNORM (3 << 5)
188 #define MALI_FORMAT_UINT (4 << 5)
190 /* e.g. RGBA8 and RGBA32F */
191 #define MALI_FORMAT_UNORM (5 << 5)
193 /* e.g. RGBA8I and RGBA16F */
194 #define MALI_FORMAT_SINT (6 << 5)
196 /* These formats seem to largely duplicate the others. They're used at least
197 * for Bifrost framebuffer output.
199 #define MALI_FORMAT_SPECIAL2 (7 << 5)
200 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
202 /* If the high 3 bits are 3 to 6 these two bits say how many components
205 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
206 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
208 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
209 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
213 #define MALI_CHANNEL_4 2
215 #define MALI_CHANNEL_8 3
217 #define MALI_CHANNEL_16 4
219 #define MALI_CHANNEL_32 5
221 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
222 * MALI_FORMAT_UNORM, it means a 32-bit float.
224 #define MALI_CHANNEL_FLOAT 7
225 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
228 /* Not all formats are in fact available, need to query dynamically to
229 * check. Factory settings for Juno enables only ETC2 and ASTC, no
234 MALI_ETC2_RGB8
= MALI_FORMAT_COMPRESSED
| 0x1,
235 MALI_ETC2_R11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x2,
236 MALI_ETC2_RGBA8
= MALI_FORMAT_COMPRESSED
| 0x3,
237 MALI_ETC2_RG11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x4,
239 MALI_NXR
= MALI_FORMAT_COMPRESSED
| 0x6, /* Nokia eXtended Range */
240 MALI_BC1_UNORM
= MALI_FORMAT_COMPRESSED
| 0x7, /* DXT1 */
241 MALI_BC2_UNORM
= MALI_FORMAT_COMPRESSED
| 0x8, /* DXT3 */
242 MALI_BC3_UNORM
= MALI_FORMAT_COMPRESSED
| 0x9, /* DXT5 */
243 MALI_BC4_UNORM
= MALI_FORMAT_COMPRESSED
| 0xA, /* RGTC1_UNORM */
244 MALI_BC4_SNORM
= MALI_FORMAT_COMPRESSED
| 0xB, /* RGTC1_SNORM */
245 MALI_BC5_UNORM
= MALI_FORMAT_COMPRESSED
| 0xC, /* RGTC2_UNORM */
246 MALI_BC5_SNORM
= MALI_FORMAT_COMPRESSED
| 0xD, /* RGTC2_SNORM */
247 MALI_BC6H_UF16
= MALI_FORMAT_COMPRESSED
| 0xE,
248 MALI_BC6H_SF16
= MALI_FORMAT_COMPRESSED
| 0xF,
249 MALI_BC7_UNORM
= MALI_FORMAT_COMPRESSED
| 0x10,
250 MALI_ETC2_R11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x11, /* EAC_SNORM */
251 MALI_ETC2_RG11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x12, /* EAC_SNORM */
252 MALI_ETC2_RGB8A1
= MALI_FORMAT_COMPRESSED
| 0x13,
253 MALI_ASTC_3D_LDR
= MALI_FORMAT_COMPRESSED
| 0x14,
254 MALI_ASTC_3D_HDR
= MALI_FORMAT_COMPRESSED
| 0x15,
255 MALI_ASTC_2D_LDR
= MALI_FORMAT_COMPRESSED
| 0x16,
256 MALI_ASTC_2D_HDR
= MALI_FORMAT_COMPRESSED
| 0x17,
258 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
259 MALI_RGB5_X1_UNORM
= MALI_FORMAT_SPECIAL
| 0x1,
260 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
261 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
262 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
263 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
264 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
266 MALI_RGB332_UNORM
= MALI_FORMAT_SPECIAL
| 0xb,
267 MALI_RGB233_UNORM
= MALI_FORMAT_SPECIAL
| 0xc,
269 MALI_Z24X8_UNORM
= MALI_FORMAT_SPECIAL
| 0xd,
270 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
271 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
272 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
273 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
274 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
275 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
276 /* Only used for varyings, to indicate the transformed gl_Position */
277 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
278 /* Only used for varyings, to indicate that the write should be
281 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
283 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
284 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
285 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
286 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
287 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
288 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
289 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
290 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
291 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
292 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
293 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
294 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
296 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
297 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
298 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
299 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
300 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
301 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
302 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
303 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
304 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
305 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
306 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
307 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
309 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
310 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
311 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
312 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
313 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
314 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
315 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
316 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
317 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
318 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
319 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
320 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
321 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
322 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
323 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
324 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
325 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
327 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
328 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
329 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
330 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
331 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
332 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
333 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
334 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
335 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
336 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
337 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
338 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
339 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
340 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
341 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
342 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
344 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
345 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
346 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
350 /* Applies to midgard1.flags_lo */
352 /* Should be set when the fragment shader updates the depth value. */
353 #define MALI_WRITES_Z (1 << 4)
355 /* Should the hardware perform early-Z testing? Set if the shader does not use
356 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
357 * side effects (writes to global memory or images) unless early-z testing is
358 * forced in the shader.
361 #define MALI_EARLY_Z (1 << 6)
363 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
364 * fragment shader that uses texturing or derivative functions */
366 #define MALI_HELPER_INVOCATIONS (1 << 7)
368 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
369 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
370 * it might read depth/stencil in particular, also set MALI_READS_ZS */
372 #define MALI_READS_ZS (1 << 8)
374 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
375 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
376 * incurs a performance penalty. On a fragment shader, this bit implies there
377 * are side effects, hence it interacts with early-z. */
378 #define MALI_WRITES_GLOBAL (1 << 9)
380 #define MALI_READS_TILEBUFFER (1 << 10)
382 /* Applies to midgard1.flags_hi */
384 /* Should be set when the fragment shader updates the stencil value. */
385 #define MALI_WRITES_S (1 << 2)
387 /* Mode to suppress generation of Infinity and NaN values by clamping inf
388 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
390 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
391 * same functionality.
393 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
394 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
396 #define MALI_SUPPRESS_INF_NAN (1 << 3)
398 /* Flags for bifrost1.unk1 */
400 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
401 * allowing for full thread count. If clear, the full [R0, R63] register set is
402 * available at half thread count */
403 #define MALI_BIFROST_FULL_THREAD (1 << 9)
405 /* Enable early-z testing (presumably). This flag may not be set if the shader:
409 * - Writes gl_FragDepth
411 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
412 * blending, although I've begun to suspect that flag does not in fact enable
414 #define MALI_BIFROST_EARLY_Z (1 << 15)
416 /* First clause type is ATEST */
417 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
419 /* The raw Midgard blend payload can either be an equation or a shader
420 * address, depending on the context */
422 union midgard_blend
{
426 struct mali_blend_equation equation
;
431 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
434 #define MALI_BLEND_LOAD_TIB (0x1)
436 /* A blend shader is used to blend this render target */
437 #define MALI_BLEND_MRT_SHADER (0x2)
439 /* On MRT Midgard systems (using an MFBD), each render target gets its own
440 * blend descriptor */
442 #define MALI_BLEND_SRGB (0x400)
444 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
445 #define MALI_BLEND_NO_DITHER (0x800)
447 struct midgard_blend_rt
{
448 /* Flags base value of 0x200 to enable the render target.
449 * OR with 0x1 for blending (anything other than REPLACE).
450 * OR with 0x2 for programmable blending
451 * OR with MALI_BLEND_SRGB for implicit sRGB
455 union midgard_blend blend
;
456 } __attribute__((packed
));
458 /* On Bifrost systems (all MRT), each render target gets one of these
461 enum bifrost_shader_type
{
462 BIFROST_BLEND_F16
= 0,
463 BIFROST_BLEND_F32
= 1,
464 BIFROST_BLEND_I32
= 2,
465 BIFROST_BLEND_U32
= 3,
466 BIFROST_BLEND_I16
= 4,
467 BIFROST_BLEND_U16
= 5,
470 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
472 struct bifrost_blend_rt
{
473 /* This is likely an analogue of the flags on
474 * midgard_blend_rt */
476 u16 flags
; // = 0x200
478 /* Single-channel blend constants are encoded in a sort of
479 * fixed-point. Basically, the float is mapped to a byte, becoming
480 * a high byte, and then the lower-byte is added for precision.
481 * For the original float f:
483 * f = (constant_hi / 255) + (constant_lo / 65535)
485 * constant_hi = int(f / 255)
486 * constant_lo = 65535*f - (65535/255) * constant_hi
490 struct mali_blend_equation equation
;
494 * - 0x3 when this slot is unused (everything else is 0 except the index)
495 * - 0x11 when this is the fourth slot (and it's used)
496 * - 0 when there is a blend shader
500 /* increments from 0 to 3 */
505 /* So far, I've only seen:
506 * - R001 for 1-component formats
507 * - RG01 for 2-component formats
508 * - RGB1 for 3-component formats
509 * - RGBA for 4-component formats
512 enum mali_format format
: 8;
514 /* Type of the shader output variable. Note, this can
515 * be different from the format.
516 * enum bifrost_shader_type
523 /* Only the low 32 bits of the blend shader are stored, the
524 * high 32 bits are implicitly the same as the original shader.
525 * According to the kernel driver, the program counter for
526 * shaders is actually only 24 bits, so shaders cannot cross
527 * the 2^24-byte boundary, and neither can the blend shader.
528 * The blob handles this by allocating a 2^24 byte pool for
529 * shaders, and making sure that any blend shaders are stored
530 * in the same pool as the original shader. The kernel will
531 * make sure this allocation is aligned to 2^24 bytes.
535 } __attribute__((packed
));
537 /* Descriptor for the shader. Following this is at least one, up to four blend
538 * descriptors for each active render target */
540 struct mali_shader_meta
{
549 u32 uniform_buffer_count
: 4;
550 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
553 unsigned uniform_buffer_count
: 4;
554 unsigned flags_lo
: 12;
557 unsigned work_count
: 5;
558 unsigned uniform_count
: 5;
559 unsigned flags_hi
: 6;
563 /* Same as glPolygoOffset() arguments */
569 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
570 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
571 * specification. Only matters when multisampling is enabled. */
576 u8 stencil_mask_front
;
577 u8 stencil_mask_back
;
580 struct mali_stencil_packed stencil_front
;
581 struct mali_stencil_packed stencil_back
;
586 /* On Bifrost, some system values are preloaded in
587 * registers R55-R62 by the thread dispatcher prior to
588 * the start of shader execution. This is a bitfield
589 * with one entry for each register saying which
590 * registers need to be preloaded. Right now, the known
594 * - R55 : gl_LocalInvocationID.xy
595 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
596 * - R57 : gl_WorkGroupID.x
597 * - R58 : gl_WorkGroupID.y
598 * - R59 : gl_WorkGroupID.z
599 * - R60 : gl_GlobalInvocationID.x
600 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
601 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
604 * - R55 : unknown, never seen (but the bit for this is
606 * - R56 : unknown (bit always unset)
607 * - R57 : gl_PrimitiveID
608 * - R58 : gl_FrontFacing in low bit, potentially other stuff
609 * - R59 : u16 fragment coordinates (used to compute
610 * gl_FragCoord.xy, together with sample positions)
611 * - R60 : gl_SampleMask (used in epilog, so pretty
612 * much always used, but the bit is always 0 -- is
613 * this just always pushed?)
614 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
615 * varying interpolation.
616 * - R62 : unknown (bit always unset).
618 * Later GPUs (starting with Mali-G52?) support
619 * preloading float varyings into r0-r7. This is
620 * indicated by setting 0x40. There is no distinction
621 * here between 1 varying and 2.
623 u32 preload_regs
: 8;
624 /* In units of 8 bytes or 64 bits, since the
625 * uniform/const port loads 64 bits at a time.
627 u32 uniform_count
: 7;
628 u32 unk4
: 10; // = 2
637 /* Blending information for the older non-MRT Midgard HW. Check for
638 * MALI_HAS_BLEND_SHADER to decide how to interpret.
641 union midgard_blend blend
;
642 } __attribute__((packed
));
644 /* This only concerns hardware jobs */
646 /* Possible values for job_descriptor_size */
648 #define MALI_JOB_32 0
649 #define MALI_JOB_64 1
651 struct mali_job_descriptor_header
{
652 u32 exception_status
;
653 u32 first_incomplete_task
;
655 u8 job_descriptor_size
: 1;
656 enum mali_job_type job_type
: 7;
658 u8 unknown_flags
: 7;
660 u16 job_dependency_index_1
;
661 u16 job_dependency_index_2
;
663 } __attribute__((packed
));
665 /* These concern exception_status */
667 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
670 enum mali_exception_access
{
671 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
672 * fault so it's just unused */
673 MALI_EXCEPTION_ACCESS_NONE
= 0,
675 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
676 MALI_EXCEPTION_ACCESS_READ
= 2,
677 MALI_EXCEPTION_ACCESS_WRITE
= 3
680 /* Details about write_value from panfrost igt tests which use it as a generic
681 * dword write primitive */
683 #define MALI_WRITE_VALUE_ZERO 3
685 struct mali_payload_write_value
{
687 u32 value_descriptor
;
690 } __attribute__((packed
));
695 * This structure lets the attribute unit compute the address of an attribute
696 * given the vertex and instance ID. Unfortunately, the way this works is
697 * rather complicated when instancing is enabled.
699 * To explain this, first we need to explain how compute and vertex threads are
700 * dispatched. This is a guess (although a pretty firm guess!) since the
701 * details are mostly hidden from the driver, except for attribute instancing.
702 * When a quad is dispatched, it receives a single, linear index. However, we
703 * need to translate that index into a (vertex id, instance id) pair, or a
704 * (local id x, local id y, local id z) triple for compute shaders (although
705 * vertex shaders and compute shaders are handled almost identically).
706 * Focusing on vertex shaders, one option would be to do:
708 * vertex_id = linear_id % num_vertices
709 * instance_id = linear_id / num_vertices
711 * but this involves a costly division and modulus by an arbitrary number.
712 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
713 * num_instances threads instead of num_vertices * num_instances, which results
714 * in some "extra" threads with vertex_id >= num_vertices, which we have to
715 * discard. The more we pad num_vertices, the more "wasted" threads we
716 * dispatch, but the division is potentially easier.
718 * One straightforward choice is to pad num_vertices to the next power of two,
719 * which means that the division and modulus are just simple bit shifts and
720 * masking. But the actual algorithm is a bit more complicated. The thread
721 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
722 * to dividing by a power of two. This is possibly using the technique
723 * described in patent US20170010862A1. As a result, padded_num_vertices can be
724 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
725 * since we need less padding.
727 * padded_num_vertices is picked by the hardware. The driver just specifies the
728 * actual number of vertices. At least for Mali G71, the first few cases are
731 * num_vertices | padded_num_vertices
738 * Note that padded_num_vertices is a multiple of four (presumably because
739 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
740 * at least one more than num_vertices, which seems like a quirk of the
741 * hardware. For larger num_vertices, the hardware uses the following
742 * algorithm: using the binary representation of num_vertices, we look at the
743 * most significant set bit as well as the following 3 bits. Let n be the
744 * number of bits after those 4 bits. Then we set padded_num_vertices according
745 * to the following table:
747 * high bits | padded_num_vertices
754 * For example, if num_vertices = 70 is passed to glDraw(), its binary
755 * representation is 1000110, so n = 3 and the high bits are 1000, and
756 * therefore padded_num_vertices = 9 * 2^3 = 72.
758 * The attribute unit works in terms of the original linear_id. if
759 * num_instances = 1, then they are the same, and everything is simple.
760 * However, with instancing things get more complicated. There are four
761 * possible modes, two of them we can group together:
763 * 1. Use the linear_id directly. Only used when there is no instancing.
765 * 2. Use the linear_id modulo a constant. This is used for per-vertex
766 * attributes with instancing enabled by making the constant equal
767 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
768 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
769 * The shift field specifies the power of two, while the extra_flags field
770 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
771 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
772 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
773 * shift = 3. Note that we must exactly follow the hardware algorithm used to
774 * get padded_num_vertices in order to correctly implement per-vertex
777 * 3. Divide the linear_id by a constant. In order to correctly implement
778 * instance divisors, we have to divide linear_id by padded_num_vertices times
779 * to user-specified divisor. So first we compute padded_num_vertices, again
780 * following the exact same algorithm that the hardware uses, then multiply it
781 * by the GL-level divisor to get the hardware-level divisor. This case is
782 * further divided into two more cases. If the hardware-level divisor is a
783 * power of two, then we just need to shift. The shift amount is specified by
784 * the shift field, so that the hardware-level divisor is just 2^shift.
786 * If it isn't a power of two, then we have to divide by an arbitrary integer.
787 * For that, we use the well-known technique of multiplying by an approximation
788 * of the inverse. The driver must compute the magic multiplier and shift
789 * amount, and then the hardware does the multiplication and shift. The
790 * hardware and driver also use the "round-down" optimization as described in
791 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
792 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
793 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
794 * presumably this simplifies the hardware multiplier a little. The hardware
795 * first multiplies linear_id by the multiplier and takes the high 32 bits,
796 * then applies the round-down correction if extra_flags = 1, then finally
797 * shifts right by the shift field.
799 * There are some differences between ridiculousfish's algorithm and the Mali
800 * hardware algorithm, which means that the reference code from ridiculousfish
801 * doesn't always produce the right constants. Mali does not use the pre-shift
802 * optimization, since that would make a hardware implementation slower (it
803 * would have to always do the pre-shift, multiply, and post-shift operations).
804 * It also forces the multplier to be at least 2^31, which means that the
805 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
806 * given the divisor d, the algorithm the driver must follow is:
808 * 1. Set shift = floor(log2(d)).
809 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
810 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
811 * magic_divisor = m - 1 and extra_flags = 1.
812 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
814 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
815 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
816 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
817 * (*NOT the row stride*). Size is set to the size of the image itself.
819 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
820 * use particular fixed addresses with modified structures.
823 enum mali_attr_mode
{
824 MALI_ATTR_UNUSED
= 0,
825 MALI_ATTR_LINEAR
= 1,
826 MALI_ATTR_POT_DIVIDE
= 2,
827 MALI_ATTR_MODULO
= 3,
828 MALI_ATTR_NPOT_DIVIDE
= 4,
832 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
834 #define MALI_ATTR_VERTEXID (0x22)
835 #define MALI_ATTR_INSTANCEID (0x24)
836 #define MALI_VARYING_FRAG_COORD (0x25)
837 #define MALI_VARYING_FRONT_FACING (0x26)
839 /* This magic "pseudo-address" is used as `elements` to implement
840 * gl_PointCoord. When read from a fragment shader, it generates a point
841 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
842 * require an affine transformation in the shader. */
844 #define MALI_VARYING_POINT_COORD (0x61)
846 /* Used for comparison to check if an address is special. Mostly a guess, but
847 * it doesn't really matter. */
849 #define MALI_RECORD_SPECIAL (0x100)
852 /* This is used for actual attributes. */
854 /* The bottom 3 bits are the mode */
855 mali_ptr elements
: 64 - 8;
861 /* The entry after an NPOT_DIVIDE entry has this format. It stores
862 * extra information that wouldn't fit in a normal entry.
865 u32 unk
; /* = 0x20 */
868 /* This is the original, GL-level divisor. */
871 } __attribute__((packed
));
873 struct mali_attr_meta
{
874 /* Vertex buffer index */
877 unsigned unknown1
: 2;
878 unsigned swizzle
: 12;
879 enum mali_format format
: 8;
881 /* Always observed to be zero at the moment */
882 unsigned unknown3
: 2;
884 /* When packing multiple attributes in a buffer, offset addresses by
885 * this value. Obscurely, this is signed. */
887 } __attribute__((packed
));
889 #define FBD_MASK (~0x3f)
891 /* MFBD, rather than SFBD */
892 #define MALI_MFBD (0x1)
894 /* ORed into an MFBD address to specify the fbx section is included */
895 #define MALI_MFBD_TAG_EXTRA (0x2)
897 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
898 * They also seem to be the same between Bifrost and Midgard. They're shared in
902 /* Applies to unknown_draw */
904 #define MALI_DRAW_INDEXED_UINT8 (0x10)
905 #define MALI_DRAW_INDEXED_UINT16 (0x20)
906 #define MALI_DRAW_INDEXED_UINT32 (0x30)
907 #define MALI_DRAW_INDEXED_SIZE (0x30)
908 #define MALI_DRAW_INDEXED_SHIFT (4)
910 #define MALI_DRAW_VARYING_SIZE (0x100)
912 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
913 * use the last vertex. This is the default in DX and VK, but not in GL. */
915 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
917 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
919 struct mali_vertex_tiler_prefix
{
920 /* This is a dynamic bitfield containing the following things in this order:
922 * - gl_WorkGroupSize.x
923 * - gl_WorkGroupSize.y
924 * - gl_WorkGroupSize.z
925 * - gl_NumWorkGroups.x
926 * - gl_NumWorkGroups.y
927 * - gl_NumWorkGroups.z
929 * The number of bits allocated for each number is based on the *_shift
930 * fields below. For example, workgroups_y_shift gives the bit that
931 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
932 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
933 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
934 * value is one more than the stored value, since if any of the values
935 * are zero, then there would be no invocations (and hence no job). If
936 * there were 0 bits allocated to a given field, then it must be zero,
937 * and hence the real value is one.
939 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
940 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
941 * where vertex count is the number of vertices.
943 u32 invocation_count
;
945 /* Bitfield for shifts:
949 * workgroups_x_shift : 6
950 * workgroups_y_shift : 6
951 * workgroups_z_shift : 6
952 * workgroups_x_shift_2 : 4
954 u32 invocation_shifts
;
957 u32 unknown_draw
: 22;
959 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
960 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
961 * something to do with how many quads get put in the same execution
962 * engine, which is a balance (you don't want to starve the engine, but
963 * you also want to distribute work evenly).
965 u32 workgroups_x_shift_3
: 6;
968 /* Negative of min_index. This is used to compute
969 * the unbiased index in tiler/fragment shader runs.
971 * The hardware adds offset_bias_correction in each run,
972 * so that absent an index bias, the first vertex processed is
973 * genuinely the first vertex (0). But with an index bias,
974 * the first vertex process is numbered the same as the bias.
976 * To represent this more conviniently:
977 * unbiased_index = lower_bound_index +
979 * offset_bias_correction
981 * This is done since the hardware doesn't accept a index_bias
982 * and this allows it to recover the unbiased index.
984 int32_t offset_bias_correction
;
987 /* Like many other strictly nonzero quantities, index_count is
988 * subtracted by one. For an indexed cube, this is equal to 35 = 6
989 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
990 * for an indexed draw, index_count is the number of actual vertices
991 * rendered whereas invocation_count is the number of unique vertices
992 * rendered (the number of times the vertex shader must be invoked).
993 * For non-indexed draws, this is just equal to invocation_count. */
997 /* No hidden structure; literally just a pointer to an array of uint
998 * indices (width depends on flags). Thanks, guys, for not making my
999 * life insane for once! NULL for non-indexed draws. */
1002 } __attribute__((packed
));
1004 /* Point size / line width can either be specified as a 32-bit float (for
1005 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
1006 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1007 * payload, the contents of varying_pointer will be intepreted as an array of
1008 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1009 * creating a special MALI_R16F varying writing to varying_pointer. */
1011 union midgard_primitive_size
{
1016 struct bifrost_tiler_heap_meta
{
1019 /* note: these are just guesses! */
1020 mali_ptr tiler_heap_start
;
1021 mali_ptr tiler_heap_free
;
1022 mali_ptr tiler_heap_end
;
1024 /* hierarchy weights? but they're still 0 after the job has run... */
1028 } __attribute__((packed
));
1030 struct bifrost_tiler_meta
{
1031 u32 tiler_heap_next_start
; /* To be written by the GPU */
1032 u32 used_hierarchy_mask
; /* To be written by the GPU */
1033 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1038 mali_ptr tiler_heap_meta
;
1039 /* TODO what is this used for? */
1041 } __attribute__((packed
));
1043 struct bifrost_tiler_only
{
1045 union midgard_primitive_size primitive_size
;
1047 mali_ptr tiler_meta
;
1049 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1050 } __attribute__((packed
));
1052 struct mali_vertex_tiler_postfix
{
1053 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
1055 /* Both zero for non-instanced draws. For instanced draws, a
1056 * decomposition of padded_num_vertices. See the comments about the
1057 * corresponding fields in mali_attr for context. */
1059 unsigned instance_shift
: 5;
1060 unsigned instance_odd
: 3;
1064 /* Offset for first vertex in buffer */
1069 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1070 * output from the vertex shader for tiler jobs.
1073 u64 position_varying
;
1075 /* An array of mali_uniform_buffer_meta's. The size is given by the
1078 u64 uniform_buffers
;
1080 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1081 * On Midgard, this is a pointer to an array of pointers to the texture
1082 * descriptors, number of pointers bounded by number of textures. The
1083 * indirection is needed to accomodate varying numbers and sizes of
1084 * texture descriptors */
1087 /* For OpenGL, from what I've seen, this is intimately connected to
1088 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1089 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1090 * array of sampler descriptors (which are uniform in size) */
1091 u64 sampler_descriptor
;
1095 u64 attributes
; /* struct attribute_buffer[] */
1096 u64 attribute_meta
; /* attribute_meta[] */
1097 u64 varyings
; /* struct attr */
1098 u64 varying_meta
; /* pointer */
1100 u64 occlusion_counter
; /* A single bit as far as I can tell */
1102 /* On Bifrost, this points directly to a mali_shared_memory structure.
1103 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1104 * tagged), which embeds a mali_shared_memory structure */
1105 mali_ptr shared_memory
;
1106 } __attribute__((packed
));
1108 struct midgard_payload_vertex_tiler
{
1109 struct mali_vertex_tiler_prefix prefix
;
1110 struct mali_vertex_tiler_postfix postfix
;
1112 union midgard_primitive_size primitive_size
;
1113 } __attribute__((packed
));
1115 struct bifrost_payload_vertex
{
1116 struct mali_vertex_tiler_prefix prefix
;
1117 struct mali_vertex_tiler_postfix postfix
;
1118 } __attribute__((packed
));
1120 struct bifrost_payload_tiler
{
1121 struct mali_vertex_tiler_prefix prefix
;
1122 struct bifrost_tiler_only tiler
;
1123 struct mali_vertex_tiler_postfix postfix
;
1124 } __attribute__((packed
));
1126 struct bifrost_payload_fused
{
1127 struct mali_vertex_tiler_prefix prefix
;
1128 struct bifrost_tiler_only tiler
;
1129 struct mali_vertex_tiler_postfix tiler_postfix
;
1130 u64 padding
; /* zero */
1131 struct mali_vertex_tiler_postfix vertex_postfix
;
1132 } __attribute__((packed
));
1134 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1135 * texture is stored as (63, 63) in these fields. This adjusts for that.
1136 * There's an identical pattern in the framebuffer descriptor. Even vertex
1137 * count fields work this way, hence the generic name -- integral fields that
1138 * are strictly positive generally need this adjustment. */
1140 #define MALI_POSITIVE(dim) (dim - 1)
1143 #define MAX_MIP_LEVELS (13)
1145 /* Cubemap bloats everything up */
1146 #define MAX_CUBE_FACES (6)
1148 /* For each pointer, there is an address and optionally also a stride */
1149 #define MAX_ELEMENTS (2)
1151 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1152 * be cleaned up a lot. */
1154 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1156 static inline int16_t
1157 FIXED_16(float x
, bool allow_negative
)
1159 /* Clamp inputs, accounting for float error */
1160 float max_lod
= (32.0 - (1.0 / 512.0));
1161 float min_lod
= allow_negative
? -max_lod
: 0.0;
1163 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
1165 return (int) (x
* 256.0);
1168 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1169 * of tile numbers. */
1171 #define MALI_TILE_SHIFT 4
1172 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1174 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1175 * each component. Notice that this provides a theoretical upper bound of (1 <<
1176 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1177 * 65536x65536. Multiplying that together, times another four given that Mali
1178 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1179 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1180 * alone rendering in real-time to such a buffer.
1184 /* From mali_kbase_10969_workaround.c */
1185 #define MALI_X_COORD_MASK 0x00000FFF
1186 #define MALI_Y_COORD_MASK 0x0FFF0000
1188 /* Extract parts of a tile coordinate */
1190 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1191 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1193 /* Helpers to generate tile coordinates based on the boundary coordinates in
1194 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1195 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1196 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1199 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1200 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1201 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1202 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1203 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1205 struct mali_payload_fragment
{
1208 mali_ptr framebuffer
;
1209 } __attribute__((packed
));
1211 /* Single Framebuffer Descriptor */
1213 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1214 * configured for 4x. With MSAA_8, it is configured for 8x. */
1216 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1217 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1218 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1219 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1221 /* Fast/slow based on whether all three buffers are cleared at once */
1223 #define MALI_CLEAR_FAST (1 << 18)
1224 #define MALI_CLEAR_SLOW (1 << 28)
1225 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1227 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1228 * within the larget framebuffer descriptor). Analogous to
1229 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1231 /* See pan_tiler.c for derivation */
1232 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1234 /* Flag disabling the tiler for clear-only jobs, with
1235 hierarchical tiling */
1236 #define MALI_TILER_DISABLED (1 << 12)
1238 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1239 * hierarhical tiling. */
1240 #define MALI_TILER_USER 0xFFF
1242 /* Absent any geometry, the minimum size of the polygon list header */
1243 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1245 struct midgard_tiler_descriptor
{
1246 /* Size of the entire polygon list; see pan_tiler.c for the
1247 * computation. It's based on hierarchical tiling */
1249 u32 polygon_list_size
;
1251 /* Name known from the replay workaround in the kernel. What exactly is
1252 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1253 * specifies a mask of hierarchy weights, which explains some of the
1254 * performance mysteries around setting it. We also see the bottom bit
1255 * of tiler_flags set in the kernel, but no comment why.
1257 * hierarchy_mask can have the TILER_DISABLED flag */
1262 /* See mali_tiler.c for an explanation */
1263 mali_ptr polygon_list
;
1264 mali_ptr polygon_list_body
;
1266 /* Names based on we see symmetry with replay jobs which name these
1269 mali_ptr heap_start
; /* tiler heap_free_address */
1272 /* Hierarchy weights. We know these are weights based on the kernel,
1273 * but I've never seen them be anything other than zero */
1277 enum mali_block_format
{
1278 MALI_BLOCK_TILED
= 0x0,
1279 MALI_BLOCK_UNKNOWN
= 0x1,
1280 MALI_BLOCK_LINEAR
= 0x2,
1281 MALI_BLOCK_AFBC
= 0x3,
1284 struct mali_sfbd_format
{
1288 /* mali_channel_swizzle */
1289 unsigned swizzle
: 12;
1292 unsigned nr_channels
: 2;
1297 enum mali_block_format block
: 2;
1303 /* Shared structure at the start of framebuffer descriptors, or used bare for
1304 * compute jobs, configuring stack and shared memory */
1306 struct mali_shared_memory
{
1307 u32 stack_shift
: 4;
1310 /* Configuration for shared memory for compute shaders.
1311 * shared_workgroup_count is logarithmic and may be computed for a
1312 * compute shader using shared memory as:
1314 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1316 * For compute shaders that don't use shared memory, or non-compute
1317 * shaders, this is set to ~0
1320 u32 shared_workgroup_count
: 5;
1321 u32 shared_unk1
: 3;
1322 u32 shared_shift
: 4;
1323 u32 shared_zero
: 20;
1325 mali_ptr scratchpad
;
1327 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1328 * fragment shaders on Bifrost, apparently multisampling locations */
1330 mali_ptr shared_memory
;
1332 } __attribute__((packed
));
1334 /* Configures multisampling on Bifrost fragment jobs */
1336 struct bifrost_multisampling
{
1339 mali_ptr sample_locations
;
1341 } __attribute__((packed
));
1343 struct mali_single_framebuffer
{
1344 struct mali_shared_memory shared_memory
;
1345 struct mali_sfbd_format format
;
1350 /* Purposeful off-by-one in these fields should be accounted for by the
1351 * MALI_DIMENSION macro */
1358 u32 checksum_stride
;
1361 /* By default, the framebuffer is upside down from OpenGL's
1362 * perspective. Set framebuffer to the end and negate the stride to
1363 * flip in the Y direction */
1365 mali_ptr framebuffer
;
1370 /* Depth and stencil buffers are interleaved, it appears, as they are
1371 * set to the same address in captures. Both fields set to zero if the
1372 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1373 * get a zero enable despite the buffer being present; that still is
1376 mali_ptr depth_buffer
; // not SAME_VA
1377 u32 depth_stride_zero
: 4;
1378 u32 depth_stride
: 28;
1381 mali_ptr stencil_buffer
; // not SAME_VA
1382 u32 stencil_stride_zero
: 4;
1383 u32 stencil_stride
: 28;
1386 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1387 u32 clear_color_2
; // always equal, but unclear function?
1388 u32 clear_color_3
; // always equal, but unclear function?
1389 u32 clear_color_4
; // always equal, but unclear function?
1391 /* Set to zero if not cleared */
1393 float clear_depth_1
; // float32, ditto
1394 float clear_depth_2
; // float32, ditto
1395 float clear_depth_3
; // float32, ditto
1396 float clear_depth_4
; // float32, ditto
1398 u32 clear_stencil
; // Exactly as it appears in OpenGL
1402 struct midgard_tiler_descriptor tiler
;
1404 /* More below this, maybe */
1405 } __attribute__((packed
));
1408 /* SINGLE to disable multisampling, AVERAGE for
1409 * EXT_multisampled_render_to_texture operation where multiple tilebuffer
1410 * samples are implicitly resolved before writeout, MULTIPLE to write multiple
1411 * samples inline, and LAYERED for ES3-style multisampling with each sample in
1412 * a different buffer.
1415 enum mali_msaa_mode
{
1416 MALI_MSAA_SINGLE
= 0,
1417 MALI_MSAA_AVERAGE
= 1,
1418 MALI_MSAA_MULTIPLE
= 2,
1419 MALI_MSAA_LAYERED
= 3,
1422 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1424 struct mali_rt_format
{
1428 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1432 enum mali_block_format block
: 2;
1433 enum mali_msaa_mode msaa
: 2;
1436 unsigned swizzle
: 12;
1440 /* Disables MFBD preload. When this bit is set, the render target will
1441 * be cleared every frame. When this bit is clear, the hardware will
1442 * automatically wallpaper the render target back from main memory.
1443 * Unfortunately, MFBD preload is very broken on Midgard, so in
1444 * practice, this is a chicken bit that should always be set.
1445 * Discovered by accident, as all good chicken bits are. */
1447 unsigned no_preload
: 1;
1448 } __attribute__((packed
));
1450 /* Flags for afbc.flags and ds_afbc.flags */
1452 #define MALI_AFBC_FLAGS 0x10009
1454 /* Lossless RGB and RGBA colorspace transform */
1455 #define MALI_AFBC_YTR (1 << 17)
1457 struct mali_render_target
{
1458 struct mali_rt_format format
;
1463 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1464 * there is an extra metadata buffer that contains 16 bytes per tile.
1465 * The framebuffer needs to be the same size as before, since we don't
1466 * know ahead of time how much space it will take up. The
1467 * framebuffer_stride is set to 0, since the data isn't stored linearly
1470 * When AFBC is disabled, these fields are zero.
1474 u32 stride
; // stride in units of tiles
1475 u32 flags
; // = 0x20000
1478 mali_ptr framebuffer
;
1481 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1482 u32 layer_stride
; /* For multisample rendering */
1484 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1485 u32 clear_color_2
; // always equal, but unclear function?
1486 u32 clear_color_3
; // always equal, but unclear function?
1487 u32 clear_color_4
; // always equal, but unclear function?
1488 } __attribute__((packed
));
1490 /* An optional part of mali_framebuffer. It comes between the main structure
1491 * and the array of render targets. It must be included if any of these are
1494 * - Transaction Elimination
1496 * - TODO: Anything else?
1500 #define MALI_EXTRA_PRESENT (0x1)
1503 #define MALI_EXTRA_ZS (0x4)
1505 struct mali_framebuffer_extra
{
1507 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1508 u32 checksum_stride
;
1510 unsigned flags_lo
: 4;
1511 enum mali_block_format zs_block
: 2;
1513 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1514 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1515 unsigned zs_samples
: 4;
1516 unsigned flags_hi
: 22;
1519 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1521 mali_ptr depth_stencil_afbc_metadata
;
1522 u32 depth_stencil_afbc_stride
; // in units of tiles
1525 mali_ptr depth_stencil
;
1531 /* Depth becomes depth/stencil in case of combined D/S */
1533 u32 depth_stride_zero
: 4;
1534 u32 depth_stride
: 28;
1535 u32 depth_layer_stride
;
1538 u32 stencil_stride_zero
: 4;
1539 u32 stencil_stride
: 28;
1540 u32 stencil_layer_stride
;
1548 } __attribute__((packed
));
1550 /* Flags for mfbd_flags */
1552 /* Enables writing depth results back to main memory (rather than keeping them
1553 * on-chip in the tile buffer and then discarding) */
1555 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1557 /* The MFBD contains the extra mali_framebuffer_extra section */
1559 #define MALI_MFBD_EXTRA (1 << 13)
1561 struct mali_framebuffer
{
1563 struct mali_shared_memory shared_memory
;
1564 struct bifrost_multisampling msaa
;
1568 u16 width1
, height1
;
1570 u16 width2
, height2
;
1571 u32 unk1
: 19; // = 0x01000
1572 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1573 u32 unk2
: 2; // = 0
1574 u32 rt_count_2
: 3; // no off-by-one
1577 u32 clear_stencil
: 8;
1578 u32 mfbd_flags
: 24; // = 0x100
1582 struct midgard_tiler_descriptor tiler
;
1584 mali_ptr tiler_meta
;
1589 /* optional: struct mali_framebuffer_extra extra */
1590 /* struct mali_render_target rts[] */
1591 } __attribute__((packed
));
1593 #endif /* __PANFROST_JOB_H__ */