2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
41 /* Applies to tiler_gl_enables */
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
51 #define MALI_FRONT_CCW_TOP (1 << 5)
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
56 /* Flags apply to unknown2_3? */
58 #define MALI_HAS_MSAA (1 << 0)
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
83 #define MALI_NO_DITHER (1 << 9)
84 #define MALI_DEPTH_RANGE_A (1 << 12)
85 #define MALI_DEPTH_RANGE_B (1 << 13)
86 #define MALI_NO_MSAA (1 << 14)
88 #define MALI_MASK_R (1 << 0)
89 #define MALI_MASK_G (1 << 1)
90 #define MALI_MASK_B (1 << 2)
91 #define MALI_MASK_A (1 << 3)
93 enum mali_nondominant_mode
{
94 MALI_BLEND_NON_MIRROR
= 0,
95 MALI_BLEND_NON_ZERO
= 1
98 enum mali_dominant_blend
{
99 MALI_BLEND_DOM_SOURCE
= 0,
100 MALI_BLEND_DOM_DESTINATION
= 1
103 enum mali_dominant_factor
{
104 MALI_DOMINANT_UNK0
= 0,
105 MALI_DOMINANT_ZERO
= 1,
106 MALI_DOMINANT_SRC_COLOR
= 2,
107 MALI_DOMINANT_DST_COLOR
= 3,
108 MALI_DOMINANT_UNK4
= 4,
109 MALI_DOMINANT_SRC_ALPHA
= 5,
110 MALI_DOMINANT_DST_ALPHA
= 6,
111 MALI_DOMINANT_CONSTANT
= 7,
114 enum mali_blend_modifier
{
115 MALI_BLEND_MOD_UNK0
= 0,
116 MALI_BLEND_MOD_NORMAL
= 1,
117 MALI_BLEND_MOD_SOURCE_ONE
= 2,
118 MALI_BLEND_MOD_DEST_ONE
= 3,
121 struct mali_blend_mode
{
122 enum mali_blend_modifier clip_modifier
: 2;
123 unsigned unused_0
: 1;
124 unsigned negate_source
: 1;
126 enum mali_dominant_blend dominant
: 1;
128 enum mali_nondominant_mode nondominant_mode
: 1;
130 unsigned unused_1
: 1;
132 unsigned negate_dest
: 1;
134 enum mali_dominant_factor dominant_factor
: 3;
135 unsigned complement_dominant
: 1;
136 } __attribute__((packed
));
138 /* Compressed per-pixel formats. Each of these formats expands to one to four
139 * floating-point or integer numbers, as defined by the OpenGL specification.
140 * There are various places in OpenGL where the user can specify a compressed
141 * format in memory, which all use the same 8-bit enum in the various
142 * descriptors, although different hardware units support different formats.
145 /* The top 3 bits specify how the bits of each component are interpreted. */
148 #define MALI_FORMAT_COMPRESSED (0 << 5)
150 /* e.g. R11F_G11F_B10F */
151 #define MALI_FORMAT_SPECIAL (2 << 5)
153 /* signed normalized, e.g. RGBA8_SNORM */
154 #define MALI_FORMAT_SNORM (3 << 5)
157 #define MALI_FORMAT_UINT (4 << 5)
159 /* e.g. RGBA8 and RGBA32F */
160 #define MALI_FORMAT_UNORM (5 << 5)
162 /* e.g. RGBA8I and RGBA16F */
163 #define MALI_FORMAT_SINT (6 << 5)
165 /* These formats seem to largely duplicate the others. They're used at least
166 * for Bifrost framebuffer output.
168 #define MALI_FORMAT_SPECIAL2 (7 << 5)
169 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
171 /* If the high 3 bits are 3 to 6 these two bits say how many components
174 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
175 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
177 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
178 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
182 #define MALI_CHANNEL_4 2
184 #define MALI_CHANNEL_8 3
186 #define MALI_CHANNEL_16 4
188 #define MALI_CHANNEL_32 5
190 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
191 * MALI_FORMAT_UNORM, it means a 32-bit float.
193 #define MALI_CHANNEL_FLOAT 7
194 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
196 /* Applies to midgard1.flags_lo */
198 /* Should be set when the fragment shader updates the depth value. */
199 #define MALI_WRITES_Z (1 << 4)
201 /* Should the hardware perform early-Z testing? Set if the shader does not use
202 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
203 * side effects (writes to global memory or images) unless early-z testing is
204 * forced in the shader.
207 #define MALI_EARLY_Z (1 << 6)
209 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
210 * fragment shader that uses texturing or derivative functions */
212 #define MALI_HELPER_INVOCATIONS (1 << 7)
214 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
215 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
216 * it might read depth/stencil in particular, also set MALI_READS_ZS */
218 #define MALI_READS_ZS (1 << 8)
220 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
221 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
222 * incurs a performance penalty. On a fragment shader, this bit implies there
223 * are side effects, hence it interacts with early-z. */
224 #define MALI_WRITES_GLOBAL (1 << 9)
226 #define MALI_READS_TILEBUFFER (1 << 10)
228 /* Applies to midgard1.flags_hi */
230 /* Should be set when the fragment shader updates the stencil value. */
231 #define MALI_WRITES_S (1 << 2)
233 /* Mode to suppress generation of Infinity and NaN values by clamping inf
234 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
236 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
237 * same functionality.
239 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
240 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
242 #define MALI_SUPPRESS_INF_NAN (1 << 3)
244 /* Flags for bifrost1.unk1 */
246 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
247 * allowing for full thread count. If clear, the full [R0, R63] register set is
248 * available at half thread count */
249 #define MALI_BIFROST_FULL_THREAD (1 << 9)
251 /* Enable early-z testing (presumably). This flag may not be set if the shader:
255 * - Writes gl_FragDepth
257 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
258 * blending, although I've begun to suspect that flag does not in fact enable
260 #define MALI_BIFROST_EARLY_Z (1 << 15)
262 /* First clause type is ATEST */
263 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
265 /* The raw Midgard blend payload can either be an equation or a shader
266 * address, depending on the context */
268 union midgard_blend
{
272 struct mali_blend_equation_packed equation
;
277 struct midgard_blend_rt
{
278 struct mali_blend_flags_packed flags
;
280 union midgard_blend blend
;
281 } __attribute__((packed
));
283 /* On Bifrost systems (all MRT), each render target gets one of these
286 enum bifrost_shader_type
{
287 BIFROST_BLEND_F16
= 0,
288 BIFROST_BLEND_F32
= 1,
289 BIFROST_BLEND_I32
= 2,
290 BIFROST_BLEND_U32
= 3,
291 BIFROST_BLEND_I16
= 4,
292 BIFROST_BLEND_U16
= 5,
295 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
297 struct bifrost_blend_rt
{
298 /* This is likely an analogue of the flags on
299 * midgard_blend_rt */
301 u16 flags
; // = 0x200
303 /* Single-channel blend constants are encoded in a sort of
304 * fixed-point. Basically, the float is mapped to a byte, becoming
305 * a high byte, and then the lower-byte is added for precision.
306 * For the original float f:
308 * f = (constant_hi / 255) + (constant_lo / 65535)
310 * constant_hi = int(f / 255)
311 * constant_lo = 65535*f - (65535/255) * constant_hi
315 struct mali_blend_equation_packed equation
;
319 * - 0x3 when this slot is unused (everything else is 0 except the index)
320 * - 0x11 when this is the fourth slot (and it's used)
321 * - 0 when there is a blend shader
325 /* increments from 0 to 3 */
330 /* So far, I've only seen:
331 * - R001 for 1-component formats
332 * - RG01 for 2-component formats
333 * - RGB1 for 3-component formats
334 * - RGBA for 4-component formats
337 enum mali_format format
: 8;
339 /* Type of the shader output variable. Note, this can
340 * be different from the format.
341 * enum bifrost_shader_type
348 /* Only the low 32 bits of the blend shader are stored, the
349 * high 32 bits are implicitly the same as the original shader.
350 * According to the kernel driver, the program counter for
351 * shaders is actually only 24 bits, so shaders cannot cross
352 * the 2^24-byte boundary, and neither can the blend shader.
353 * The blob handles this by allocating a 2^24 byte pool for
354 * shaders, and making sure that any blend shaders are stored
355 * in the same pool as the original shader. The kernel will
356 * make sure this allocation is aligned to 2^24 bytes.
360 } __attribute__((packed
));
362 /* Descriptor for the shader. Following this is at least one, up to four blend
363 * descriptors for each active render target */
365 struct mali_shader_meta
{
374 u32 uniform_buffer_count
: 4;
375 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
378 unsigned uniform_buffer_count
: 4;
379 unsigned flags_lo
: 12;
382 unsigned work_count
: 5;
383 unsigned uniform_count
: 5;
384 unsigned flags_hi
: 6;
388 /* Same as glPolygoOffset() arguments */
394 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
395 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
396 * specification. Only matters when multisampling is enabled. */
401 u8 stencil_mask_front
;
402 u8 stencil_mask_back
;
405 struct mali_stencil_packed stencil_front
;
406 struct mali_stencil_packed stencil_back
;
411 /* On Bifrost, some system values are preloaded in
412 * registers R55-R62 by the thread dispatcher prior to
413 * the start of shader execution. This is a bitfield
414 * with one entry for each register saying which
415 * registers need to be preloaded. Right now, the known
419 * - R55 : gl_LocalInvocationID.xy
420 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
421 * - R57 : gl_WorkGroupID.x
422 * - R58 : gl_WorkGroupID.y
423 * - R59 : gl_WorkGroupID.z
424 * - R60 : gl_GlobalInvocationID.x
425 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
426 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
429 * - R55 : unknown, never seen (but the bit for this is
431 * - R56 : unknown (bit always unset)
432 * - R57 : gl_PrimitiveID
433 * - R58 : gl_FrontFacing in low bit, potentially other stuff
434 * - R59 : u16 fragment coordinates (used to compute
435 * gl_FragCoord.xy, together with sample positions)
436 * - R60 : gl_SampleMask (used in epilog, so pretty
437 * much always used, but the bit is always 0 -- is
438 * this just always pushed?)
439 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
440 * varying interpolation.
441 * - R62 : unknown (bit always unset).
443 * Later GPUs (starting with Mali-G52?) support
444 * preloading float varyings into r0-r7. This is
445 * indicated by setting 0x40. There is no distinction
446 * here between 1 varying and 2.
448 u32 preload_regs
: 8;
449 /* In units of 8 bytes or 64 bits, since the
450 * uniform/const port loads 64 bits at a time.
452 u32 uniform_count
: 7;
453 u32 unk4
: 10; // = 2
462 /* Blending information for the older non-MRT Midgard HW. Check for
463 * MALI_HAS_BLEND_SHADER to decide how to interpret.
466 union midgard_blend blend
;
467 } __attribute__((packed
));
469 /* This only concerns hardware jobs */
471 /* Possible values for job_descriptor_size */
473 #define MALI_JOB_32 0
474 #define MALI_JOB_64 1
476 struct mali_job_descriptor_header
{
477 u32 exception_status
;
478 u32 first_incomplete_task
;
480 u8 job_descriptor_size
: 1;
481 enum mali_job_type job_type
: 7;
483 u8 unknown_flags
: 7;
485 u16 job_dependency_index_1
;
486 u16 job_dependency_index_2
;
488 } __attribute__((packed
));
490 /* Details about write_value from panfrost igt tests which use it as a generic
491 * dword write primitive */
493 #define MALI_WRITE_VALUE_ZERO 3
495 struct mali_payload_write_value
{
497 u32 value_descriptor
;
500 } __attribute__((packed
));
505 * This structure lets the attribute unit compute the address of an attribute
506 * given the vertex and instance ID. Unfortunately, the way this works is
507 * rather complicated when instancing is enabled.
509 * To explain this, first we need to explain how compute and vertex threads are
510 * dispatched. This is a guess (although a pretty firm guess!) since the
511 * details are mostly hidden from the driver, except for attribute instancing.
512 * When a quad is dispatched, it receives a single, linear index. However, we
513 * need to translate that index into a (vertex id, instance id) pair, or a
514 * (local id x, local id y, local id z) triple for compute shaders (although
515 * vertex shaders and compute shaders are handled almost identically).
516 * Focusing on vertex shaders, one option would be to do:
518 * vertex_id = linear_id % num_vertices
519 * instance_id = linear_id / num_vertices
521 * but this involves a costly division and modulus by an arbitrary number.
522 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
523 * num_instances threads instead of num_vertices * num_instances, which results
524 * in some "extra" threads with vertex_id >= num_vertices, which we have to
525 * discard. The more we pad num_vertices, the more "wasted" threads we
526 * dispatch, but the division is potentially easier.
528 * One straightforward choice is to pad num_vertices to the next power of two,
529 * which means that the division and modulus are just simple bit shifts and
530 * masking. But the actual algorithm is a bit more complicated. The thread
531 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
532 * to dividing by a power of two. This is possibly using the technique
533 * described in patent US20170010862A1. As a result, padded_num_vertices can be
534 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
535 * since we need less padding.
537 * padded_num_vertices is picked by the hardware. The driver just specifies the
538 * actual number of vertices. At least for Mali G71, the first few cases are
541 * num_vertices | padded_num_vertices
548 * Note that padded_num_vertices is a multiple of four (presumably because
549 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
550 * at least one more than num_vertices, which seems like a quirk of the
551 * hardware. For larger num_vertices, the hardware uses the following
552 * algorithm: using the binary representation of num_vertices, we look at the
553 * most significant set bit as well as the following 3 bits. Let n be the
554 * number of bits after those 4 bits. Then we set padded_num_vertices according
555 * to the following table:
557 * high bits | padded_num_vertices
564 * For example, if num_vertices = 70 is passed to glDraw(), its binary
565 * representation is 1000110, so n = 3 and the high bits are 1000, and
566 * therefore padded_num_vertices = 9 * 2^3 = 72.
568 * The attribute unit works in terms of the original linear_id. if
569 * num_instances = 1, then they are the same, and everything is simple.
570 * However, with instancing things get more complicated. There are four
571 * possible modes, two of them we can group together:
573 * 1. Use the linear_id directly. Only used when there is no instancing.
575 * 2. Use the linear_id modulo a constant. This is used for per-vertex
576 * attributes with instancing enabled by making the constant equal
577 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
578 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
579 * The shift field specifies the power of two, while the extra_flags field
580 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
581 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
582 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
583 * shift = 3. Note that we must exactly follow the hardware algorithm used to
584 * get padded_num_vertices in order to correctly implement per-vertex
587 * 3. Divide the linear_id by a constant. In order to correctly implement
588 * instance divisors, we have to divide linear_id by padded_num_vertices times
589 * to user-specified divisor. So first we compute padded_num_vertices, again
590 * following the exact same algorithm that the hardware uses, then multiply it
591 * by the GL-level divisor to get the hardware-level divisor. This case is
592 * further divided into two more cases. If the hardware-level divisor is a
593 * power of two, then we just need to shift. The shift amount is specified by
594 * the shift field, so that the hardware-level divisor is just 2^shift.
596 * If it isn't a power of two, then we have to divide by an arbitrary integer.
597 * For that, we use the well-known technique of multiplying by an approximation
598 * of the inverse. The driver must compute the magic multiplier and shift
599 * amount, and then the hardware does the multiplication and shift. The
600 * hardware and driver also use the "round-down" optimization as described in
601 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
602 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
603 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
604 * presumably this simplifies the hardware multiplier a little. The hardware
605 * first multiplies linear_id by the multiplier and takes the high 32 bits,
606 * then applies the round-down correction if extra_flags = 1, then finally
607 * shifts right by the shift field.
609 * There are some differences between ridiculousfish's algorithm and the Mali
610 * hardware algorithm, which means that the reference code from ridiculousfish
611 * doesn't always produce the right constants. Mali does not use the pre-shift
612 * optimization, since that would make a hardware implementation slower (it
613 * would have to always do the pre-shift, multiply, and post-shift operations).
614 * It also forces the multplier to be at least 2^31, which means that the
615 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
616 * given the divisor d, the algorithm the driver must follow is:
618 * 1. Set shift = floor(log2(d)).
619 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
620 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
621 * magic_divisor = m - 1 and extra_flags = 1.
622 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
625 #define FBD_MASK (~0x3f)
627 /* MFBD, rather than SFBD */
628 #define MALI_MFBD (0x1)
630 /* ORed into an MFBD address to specify the fbx section is included */
631 #define MALI_MFBD_TAG_EXTRA (0x2)
633 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
634 * They also seem to be the same between Bifrost and Midgard. They're shared in
638 /* Applies to unknown_draw */
640 #define MALI_DRAW_INDEXED_UINT8 (0x10)
641 #define MALI_DRAW_INDEXED_UINT16 (0x20)
642 #define MALI_DRAW_INDEXED_UINT32 (0x30)
643 #define MALI_DRAW_INDEXED_SIZE (0x30)
644 #define MALI_DRAW_INDEXED_SHIFT (4)
646 #define MALI_DRAW_VARYING_SIZE (0x100)
648 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
649 * use the last vertex. This is the default in DX and VK, but not in GL. */
651 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
653 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
655 struct mali_vertex_tiler_prefix
{
656 /* This is a dynamic bitfield containing the following things in this order:
658 * - gl_WorkGroupSize.x
659 * - gl_WorkGroupSize.y
660 * - gl_WorkGroupSize.z
661 * - gl_NumWorkGroups.x
662 * - gl_NumWorkGroups.y
663 * - gl_NumWorkGroups.z
665 * The number of bits allocated for each number is based on the *_shift
666 * fields below. For example, workgroups_y_shift gives the bit that
667 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
668 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
669 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
670 * value is one more than the stored value, since if any of the values
671 * are zero, then there would be no invocations (and hence no job). If
672 * there were 0 bits allocated to a given field, then it must be zero,
673 * and hence the real value is one.
675 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
676 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
677 * where vertex count is the number of vertices.
679 u32 invocation_count
;
681 /* Bitfield for shifts:
685 * workgroups_x_shift : 6
686 * workgroups_y_shift : 6
687 * workgroups_z_shift : 6
688 * workgroups_x_shift_2 : 4
690 u32 invocation_shifts
;
693 u32 unknown_draw
: 22;
695 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
696 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
697 * something to do with how many quads get put in the same execution
698 * engine, which is a balance (you don't want to starve the engine, but
699 * you also want to distribute work evenly).
701 u32 workgroups_x_shift_3
: 6;
704 /* Negative of min_index. This is used to compute
705 * the unbiased index in tiler/fragment shader runs.
707 * The hardware adds offset_bias_correction in each run,
708 * so that absent an index bias, the first vertex processed is
709 * genuinely the first vertex (0). But with an index bias,
710 * the first vertex process is numbered the same as the bias.
712 * To represent this more conviniently:
713 * unbiased_index = lower_bound_index +
715 * offset_bias_correction
717 * This is done since the hardware doesn't accept a index_bias
718 * and this allows it to recover the unbiased index.
720 int32_t offset_bias_correction
;
723 /* Like many other strictly nonzero quantities, index_count is
724 * subtracted by one. For an indexed cube, this is equal to 35 = 6
725 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
726 * for an indexed draw, index_count is the number of actual vertices
727 * rendered whereas invocation_count is the number of unique vertices
728 * rendered (the number of times the vertex shader must be invoked).
729 * For non-indexed draws, this is just equal to invocation_count. */
733 /* No hidden structure; literally just a pointer to an array of uint
734 * indices (width depends on flags). Thanks, guys, for not making my
735 * life insane for once! NULL for non-indexed draws. */
738 } __attribute__((packed
));
740 /* Point size / line width can either be specified as a 32-bit float (for
741 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
742 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
743 * payload, the contents of varying_pointer will be intepreted as an array of
744 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
745 * creating a special MALI_R16F varying writing to varying_pointer. */
747 union midgard_primitive_size
{
752 struct bifrost_tiler_heap_meta
{
755 /* note: these are just guesses! */
756 mali_ptr tiler_heap_start
;
757 mali_ptr tiler_heap_free
;
758 mali_ptr tiler_heap_end
;
760 /* hierarchy weights? but they're still 0 after the job has run... */
764 } __attribute__((packed
));
766 struct bifrost_tiler_meta
{
767 u32 tiler_heap_next_start
; /* To be written by the GPU */
768 u32 used_hierarchy_mask
; /* To be written by the GPU */
769 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
774 mali_ptr tiler_heap_meta
;
775 /* TODO what is this used for? */
777 } __attribute__((packed
));
779 struct bifrost_tiler_only
{
781 union midgard_primitive_size primitive_size
;
785 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
786 } __attribute__((packed
));
788 struct mali_vertex_tiler_postfix
{
789 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
791 /* Both zero for non-instanced draws. For instanced draws, a
792 * decomposition of padded_num_vertices. See the comments about the
793 * corresponding fields in mali_attr for context. */
795 unsigned instance_shift
: 5;
796 unsigned instance_odd
: 3;
800 /* Offset for first vertex in buffer */
805 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
806 * output from the vertex shader for tiler jobs.
809 u64 position_varying
;
811 /* An array of mali_uniform_buffer_meta's. The size is given by the
816 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
817 * On Midgard, this is a pointer to an array of pointers to the texture
818 * descriptors, number of pointers bounded by number of textures. The
819 * indirection is needed to accomodate varying numbers and sizes of
820 * texture descriptors */
823 /* For OpenGL, from what I've seen, this is intimately connected to
824 * texture_meta. cwabbott says this is not the case under Vulkan, hence
825 * why this field is seperate (Midgard is Vulkan capable). Pointer to
826 * array of sampler descriptors (which are uniform in size) */
827 u64 sampler_descriptor
;
831 u64 attributes
; /* struct attribute_buffer[] */
832 u64 attribute_meta
; /* attribute_meta[] */
833 u64 varyings
; /* struct attr */
834 u64 varying_meta
; /* pointer */
836 u64 occlusion_counter
; /* A single bit as far as I can tell */
838 /* On Bifrost, this points directly to a mali_shared_memory structure.
839 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
840 * tagged), which embeds a mali_shared_memory structure */
841 mali_ptr shared_memory
;
842 } __attribute__((packed
));
844 struct midgard_payload_vertex_tiler
{
845 struct mali_vertex_tiler_prefix prefix
;
846 struct mali_vertex_tiler_postfix postfix
;
848 union midgard_primitive_size primitive_size
;
849 } __attribute__((packed
));
851 struct bifrost_payload_vertex
{
852 struct mali_vertex_tiler_prefix prefix
;
853 struct mali_vertex_tiler_postfix postfix
;
854 } __attribute__((packed
));
856 struct bifrost_payload_tiler
{
857 struct mali_vertex_tiler_prefix prefix
;
858 struct bifrost_tiler_only tiler
;
859 struct mali_vertex_tiler_postfix postfix
;
860 } __attribute__((packed
));
862 struct bifrost_payload_fused
{
863 struct mali_vertex_tiler_prefix prefix
;
864 struct bifrost_tiler_only tiler
;
865 struct mali_vertex_tiler_postfix tiler_postfix
;
866 u64 padding
; /* zero */
867 struct mali_vertex_tiler_postfix vertex_postfix
;
868 } __attribute__((packed
));
870 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
871 * texture is stored as (63, 63) in these fields. This adjusts for that.
872 * There's an identical pattern in the framebuffer descriptor. Even vertex
873 * count fields work this way, hence the generic name -- integral fields that
874 * are strictly positive generally need this adjustment. */
876 #define MALI_POSITIVE(dim) (dim - 1)
879 #define MAX_MIP_LEVELS (13)
881 /* Cubemap bloats everything up */
882 #define MAX_CUBE_FACES (6)
884 /* For each pointer, there is an address and optionally also a stride */
885 #define MAX_ELEMENTS (2)
887 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
888 * be cleaned up a lot. */
890 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
892 static inline int16_t
893 FIXED_16(float x
, bool allow_negative
)
895 /* Clamp inputs, accounting for float error */
896 float max_lod
= (32.0 - (1.0 / 512.0));
897 float min_lod
= allow_negative
? -max_lod
: 0.0;
899 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
901 return (int) (x
* 256.0);
904 /* From presentations, 16x16 tiles externally. Use shift for fast computation
905 * of tile numbers. */
907 #define MALI_TILE_SHIFT 4
908 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
910 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
911 * each component. Notice that this provides a theoretical upper bound of (1 <<
912 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
913 * 65536x65536. Multiplying that together, times another four given that Mali
914 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
915 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
916 * alone rendering in real-time to such a buffer.
920 /* From mali_kbase_10969_workaround.c */
921 #define MALI_X_COORD_MASK 0x00000FFF
922 #define MALI_Y_COORD_MASK 0x0FFF0000
924 /* Extract parts of a tile coordinate */
926 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
927 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
929 /* Helpers to generate tile coordinates based on the boundary coordinates in
930 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
931 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
932 * Intentional "off-by-one"; finding the tile number is a form of fencepost
935 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
936 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
937 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
938 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
939 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
941 struct mali_payload_fragment
{
944 mali_ptr framebuffer
;
945 } __attribute__((packed
));
947 /* Single Framebuffer Descriptor */
949 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
950 * configured for 4x. With MSAA_8, it is configured for 8x. */
952 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
953 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
954 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
955 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
957 /* Fast/slow based on whether all three buffers are cleared at once */
959 #define MALI_CLEAR_FAST (1 << 18)
960 #define MALI_CLEAR_SLOW (1 << 28)
961 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
963 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
964 * within the larget framebuffer descriptor). Analogous to
965 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
967 /* See pan_tiler.c for derivation */
968 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
970 /* Flag disabling the tiler for clear-only jobs, with
971 hierarchical tiling */
972 #define MALI_TILER_DISABLED (1 << 12)
974 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
975 * hierarhical tiling. */
976 #define MALI_TILER_USER 0xFFF
978 /* Absent any geometry, the minimum size of the polygon list header */
979 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
981 struct midgard_tiler_descriptor
{
982 /* Size of the entire polygon list; see pan_tiler.c for the
983 * computation. It's based on hierarchical tiling */
985 u32 polygon_list_size
;
987 /* Name known from the replay workaround in the kernel. What exactly is
988 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
989 * specifies a mask of hierarchy weights, which explains some of the
990 * performance mysteries around setting it. We also see the bottom bit
991 * of tiler_flags set in the kernel, but no comment why.
993 * hierarchy_mask can have the TILER_DISABLED flag */
998 /* See mali_tiler.c for an explanation */
999 mali_ptr polygon_list
;
1000 mali_ptr polygon_list_body
;
1002 /* Names based on we see symmetry with replay jobs which name these
1005 mali_ptr heap_start
; /* tiler heap_free_address */
1008 /* Hierarchy weights. We know these are weights based on the kernel,
1009 * but I've never seen them be anything other than zero */
1013 struct mali_sfbd_format
{
1017 /* mali_channel_swizzle */
1018 unsigned swizzle
: 12;
1021 unsigned nr_channels
: 2;
1026 enum mali_block_format block
: 2;
1032 /* Shared structure at the start of framebuffer descriptors, or used bare for
1033 * compute jobs, configuring stack and shared memory */
1035 struct mali_shared_memory
{
1036 u32 stack_shift
: 4;
1039 /* Configuration for shared memory for compute shaders.
1040 * shared_workgroup_count is logarithmic and may be computed for a
1041 * compute shader using shared memory as:
1043 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1045 * For compute shaders that don't use shared memory, or non-compute
1046 * shaders, this is set to ~0
1049 u32 shared_workgroup_count
: 5;
1050 u32 shared_unk1
: 3;
1051 u32 shared_shift
: 4;
1052 u32 shared_zero
: 20;
1054 mali_ptr scratchpad
;
1056 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1057 * fragment shaders on Bifrost, apparently multisampling locations */
1059 mali_ptr shared_memory
;
1061 } __attribute__((packed
));
1063 /* Configures multisampling on Bifrost fragment jobs */
1065 struct bifrost_multisampling
{
1068 mali_ptr sample_locations
;
1070 } __attribute__((packed
));
1072 struct mali_single_framebuffer
{
1073 struct mali_shared_memory shared_memory
;
1074 struct mali_sfbd_format format
;
1079 /* Purposeful off-by-one in these fields should be accounted for by the
1080 * MALI_DIMENSION macro */
1087 u32 checksum_stride
;
1090 /* By default, the framebuffer is upside down from OpenGL's
1091 * perspective. Set framebuffer to the end and negate the stride to
1092 * flip in the Y direction */
1094 mali_ptr framebuffer
;
1099 /* Depth and stencil buffers are interleaved, it appears, as they are
1100 * set to the same address in captures. Both fields set to zero if the
1101 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1102 * get a zero enable despite the buffer being present; that still is
1105 mali_ptr depth_buffer
; // not SAME_VA
1106 u32 depth_stride_zero
: 4;
1107 u32 depth_stride
: 28;
1110 mali_ptr stencil_buffer
; // not SAME_VA
1111 u32 stencil_stride_zero
: 4;
1112 u32 stencil_stride
: 28;
1115 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1116 u32 clear_color_2
; // always equal, but unclear function?
1117 u32 clear_color_3
; // always equal, but unclear function?
1118 u32 clear_color_4
; // always equal, but unclear function?
1120 /* Set to zero if not cleared */
1122 float clear_depth_1
; // float32, ditto
1123 float clear_depth_2
; // float32, ditto
1124 float clear_depth_3
; // float32, ditto
1125 float clear_depth_4
; // float32, ditto
1127 u32 clear_stencil
; // Exactly as it appears in OpenGL
1131 struct midgard_tiler_descriptor tiler
;
1133 /* More below this, maybe */
1134 } __attribute__((packed
));
1137 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1139 struct mali_rt_format
{
1143 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1147 enum mali_block_format block
: 2;
1148 enum mali_msaa msaa
: 2;
1151 unsigned swizzle
: 12;
1155 /* Disables MFBD preload. When this bit is set, the render target will
1156 * be cleared every frame. When this bit is clear, the hardware will
1157 * automatically wallpaper the render target back from main memory.
1158 * Unfortunately, MFBD preload is very broken on Midgard, so in
1159 * practice, this is a chicken bit that should always be set.
1160 * Discovered by accident, as all good chicken bits are. */
1162 unsigned no_preload
: 1;
1163 } __attribute__((packed
));
1165 /* Flags for afbc.flags and ds_afbc.flags */
1167 #define MALI_AFBC_FLAGS 0x10009
1169 /* Lossless RGB and RGBA colorspace transform */
1170 #define MALI_AFBC_YTR (1 << 17)
1172 struct mali_render_target
{
1173 struct mali_rt_format format
;
1178 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1179 * there is an extra metadata buffer that contains 16 bytes per tile.
1180 * The framebuffer needs to be the same size as before, since we don't
1181 * know ahead of time how much space it will take up. The
1182 * framebuffer_stride is set to 0, since the data isn't stored linearly
1185 * When AFBC is disabled, these fields are zero.
1189 u32 stride
; // stride in units of tiles
1190 u32 flags
; // = 0x20000
1193 mali_ptr framebuffer
;
1196 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1197 u32 layer_stride
; /* For multisample rendering */
1199 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1200 u32 clear_color_2
; // always equal, but unclear function?
1201 u32 clear_color_3
; // always equal, but unclear function?
1202 u32 clear_color_4
; // always equal, but unclear function?
1203 } __attribute__((packed
));
1205 /* An optional part of mali_framebuffer. It comes between the main structure
1206 * and the array of render targets. It must be included if any of these are
1209 * - Transaction Elimination
1211 * - TODO: Anything else?
1215 #define MALI_EXTRA_PRESENT (0x1)
1218 #define MALI_EXTRA_ZS (0x4)
1220 struct mali_framebuffer_extra
{
1222 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1223 u32 checksum_stride
;
1225 unsigned flags_lo
: 4;
1226 enum mali_block_format zs_block
: 2;
1228 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1229 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1230 unsigned zs_samples
: 4;
1231 unsigned flags_hi
: 22;
1234 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1236 mali_ptr depth_stencil_afbc_metadata
;
1237 u32 depth_stencil_afbc_stride
; // in units of tiles
1240 mali_ptr depth_stencil
;
1246 /* Depth becomes depth/stencil in case of combined D/S */
1248 u32 depth_stride_zero
: 4;
1249 u32 depth_stride
: 28;
1250 u32 depth_layer_stride
;
1253 u32 stencil_stride_zero
: 4;
1254 u32 stencil_stride
: 28;
1255 u32 stencil_layer_stride
;
1263 } __attribute__((packed
));
1265 /* Flags for mfbd_flags */
1267 /* Enables writing depth results back to main memory (rather than keeping them
1268 * on-chip in the tile buffer and then discarding) */
1270 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1272 /* The MFBD contains the extra mali_framebuffer_extra section */
1274 #define MALI_MFBD_EXTRA (1 << 13)
1276 struct mali_framebuffer
{
1278 struct mali_shared_memory shared_memory
;
1279 struct bifrost_multisampling msaa
;
1283 u16 width1
, height1
;
1285 u16 width2
, height2
;
1286 u32 unk1
: 19; // = 0x01000
1287 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1288 u32 unk2
: 2; // = 0
1289 u32 rt_count_2
: 3; // no off-by-one
1292 u32 clear_stencil
: 8;
1293 u32 mfbd_flags
: 24; // = 0x100
1297 struct midgard_tiler_descriptor tiler
;
1299 mali_ptr tiler_meta
;
1304 /* optional: struct mali_framebuffer_extra extra */
1305 /* struct mali_render_target rts[] */
1306 } __attribute__((packed
));
1308 #endif /* __PANFROST_JOB_H__ */