2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
41 /* Applies to tiler_gl_enables */
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
51 #define MALI_FRONT_CCW_TOP (1 << 5)
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
56 /* Flags apply to unknown2_3? */
58 #define MALI_HAS_MSAA (1 << 0)
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
83 #define MALI_SFBD_ENABLE (1 << 4)
84 #define MALI_SFBD_SRGB (1 << 8)
85 #define MALI_NO_DITHER (1 << 9)
86 #define MALI_DEPTH_RANGE_A (1 << 12)
87 #define MALI_DEPTH_RANGE_B (1 << 13)
88 #define MALI_NO_MSAA (1 << 14)
90 #define MALI_MASK_R (1 << 0)
91 #define MALI_MASK_G (1 << 1)
92 #define MALI_MASK_B (1 << 2)
93 #define MALI_MASK_A (1 << 3)
95 enum mali_nondominant_mode
{
96 MALI_BLEND_NON_MIRROR
= 0,
97 MALI_BLEND_NON_ZERO
= 1
100 enum mali_dominant_blend
{
101 MALI_BLEND_DOM_SOURCE
= 0,
102 MALI_BLEND_DOM_DESTINATION
= 1
105 enum mali_dominant_factor
{
106 MALI_DOMINANT_UNK0
= 0,
107 MALI_DOMINANT_ZERO
= 1,
108 MALI_DOMINANT_SRC_COLOR
= 2,
109 MALI_DOMINANT_DST_COLOR
= 3,
110 MALI_DOMINANT_UNK4
= 4,
111 MALI_DOMINANT_SRC_ALPHA
= 5,
112 MALI_DOMINANT_DST_ALPHA
= 6,
113 MALI_DOMINANT_CONSTANT
= 7,
116 enum mali_blend_modifier
{
117 MALI_BLEND_MOD_UNK0
= 0,
118 MALI_BLEND_MOD_NORMAL
= 1,
119 MALI_BLEND_MOD_SOURCE_ONE
= 2,
120 MALI_BLEND_MOD_DEST_ONE
= 3,
123 struct mali_blend_mode
{
124 enum mali_blend_modifier clip_modifier
: 2;
125 unsigned unused_0
: 1;
126 unsigned negate_source
: 1;
128 enum mali_dominant_blend dominant
: 1;
130 enum mali_nondominant_mode nondominant_mode
: 1;
132 unsigned unused_1
: 1;
134 unsigned negate_dest
: 1;
136 enum mali_dominant_factor dominant_factor
: 3;
137 unsigned complement_dominant
: 1;
138 } __attribute__((packed
));
140 /* Compressed per-pixel formats. Each of these formats expands to one to four
141 * floating-point or integer numbers, as defined by the OpenGL specification.
142 * There are various places in OpenGL where the user can specify a compressed
143 * format in memory, which all use the same 8-bit enum in the various
144 * descriptors, although different hardware units support different formats.
147 /* The top 3 bits specify how the bits of each component are interpreted. */
150 #define MALI_FORMAT_COMPRESSED (0 << 5)
152 /* e.g. R11F_G11F_B10F */
153 #define MALI_FORMAT_SPECIAL (2 << 5)
155 /* signed normalized, e.g. RGBA8_SNORM */
156 #define MALI_FORMAT_SNORM (3 << 5)
159 #define MALI_FORMAT_UINT (4 << 5)
161 /* e.g. RGBA8 and RGBA32F */
162 #define MALI_FORMAT_UNORM (5 << 5)
164 /* e.g. RGBA8I and RGBA16F */
165 #define MALI_FORMAT_SINT (6 << 5)
167 /* These formats seem to largely duplicate the others. They're used at least
168 * for Bifrost framebuffer output.
170 #define MALI_FORMAT_SPECIAL2 (7 << 5)
171 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
173 /* If the high 3 bits are 3 to 6 these two bits say how many components
176 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
177 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
179 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
180 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
184 #define MALI_CHANNEL_4 2
186 #define MALI_CHANNEL_8 3
188 #define MALI_CHANNEL_16 4
190 #define MALI_CHANNEL_32 5
192 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
193 * MALI_FORMAT_UNORM, it means a 32-bit float.
195 #define MALI_CHANNEL_FLOAT 7
196 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
198 /* The raw Midgard blend payload can either be an equation or a shader
199 * address, depending on the context */
201 union midgard_blend
{
205 struct mali_blend_equation_packed equation
;
210 struct midgard_blend_rt
{
211 struct mali_blend_flags_packed flags
;
213 union midgard_blend blend
;
214 } __attribute__((packed
));
216 /* On Bifrost systems (all MRT), each render target gets one of these
219 enum bifrost_shader_type
{
220 BIFROST_BLEND_F16
= 0,
221 BIFROST_BLEND_F32
= 1,
222 BIFROST_BLEND_I32
= 2,
223 BIFROST_BLEND_U32
= 3,
224 BIFROST_BLEND_I16
= 4,
225 BIFROST_BLEND_U16
= 5,
228 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
230 struct bifrost_blend_rt
{
231 /* This is likely an analogue of the flags on
232 * midgard_blend_rt */
234 u16 flags
; // = 0x200
236 /* Single-channel blend constants are encoded in a sort of
237 * fixed-point. Basically, the float is mapped to a byte, becoming
238 * a high byte, and then the lower-byte is added for precision.
239 * For the original float f:
241 * f = (constant_hi / 255) + (constant_lo / 65535)
243 * constant_hi = int(f / 255)
244 * constant_lo = 65535*f - (65535/255) * constant_hi
248 struct mali_blend_equation_packed equation
;
252 * - 0x3 when this slot is unused (everything else is 0 except the index)
253 * - 0x11 when this is the fourth slot (and it's used)
254 * - 0 when there is a blend shader
258 /* increments from 0 to 3 */
263 /* So far, I've only seen:
264 * - R001 for 1-component formats
265 * - RG01 for 2-component formats
266 * - RGB1 for 3-component formats
267 * - RGBA for 4-component formats
270 enum mali_format format
: 8;
272 /* Type of the shader output variable. Note, this can
273 * be different from the format.
274 * enum bifrost_shader_type
281 /* Only the low 32 bits of the blend shader are stored, the
282 * high 32 bits are implicitly the same as the original shader.
283 * According to the kernel driver, the program counter for
284 * shaders is actually only 24 bits, so shaders cannot cross
285 * the 2^24-byte boundary, and neither can the blend shader.
286 * The blob handles this by allocating a 2^24 byte pool for
287 * shaders, and making sure that any blend shaders are stored
288 * in the same pool as the original shader. The kernel will
289 * make sure this allocation is aligned to 2^24 bytes.
293 } __attribute__((packed
));
295 /* Descriptor for the shader. Following this is at least one, up to four blend
296 * descriptors for each active render target */
298 struct mali_shader_meta
{
306 struct mali_bifrost_properties_packed bifrost_props
;
307 struct mali_midgard_properties_packed midgard_props
;
310 /* Same as glPolygoOffset() arguments */
316 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
317 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
318 * specification. Only matters when multisampling is enabled. */
323 u8 stencil_mask_front
;
324 u8 stencil_mask_back
;
327 struct mali_stencil_packed stencil_front
;
328 struct mali_stencil_packed stencil_back
;
331 struct mali_preload_packed bifrost_preload
;
339 /* Blending information for the older non-MRT Midgard HW. Check for
340 * MALI_HAS_BLEND_SHADER to decide how to interpret.
343 union midgard_blend blend
;
344 } __attribute__((packed
));
346 /* This only concerns hardware jobs */
348 /* Possible values for job_descriptor_size */
350 #define MALI_JOB_32 0
351 #define MALI_JOB_64 1
353 struct mali_job_descriptor_header
{
354 u32 exception_status
;
355 u32 first_incomplete_task
;
357 u8 job_descriptor_size
: 1;
358 enum mali_job_type job_type
: 7;
360 u8 unknown_flags
: 7;
362 u16 job_dependency_index_1
;
363 u16 job_dependency_index_2
;
365 } __attribute__((packed
));
367 /* Details about write_value from panfrost igt tests which use it as a generic
368 * dword write primitive */
370 #define MALI_WRITE_VALUE_ZERO 3
372 struct mali_payload_write_value
{
374 u32 value_descriptor
;
377 } __attribute__((packed
));
382 * This structure lets the attribute unit compute the address of an attribute
383 * given the vertex and instance ID. Unfortunately, the way this works is
384 * rather complicated when instancing is enabled.
386 * To explain this, first we need to explain how compute and vertex threads are
387 * dispatched. This is a guess (although a pretty firm guess!) since the
388 * details are mostly hidden from the driver, except for attribute instancing.
389 * When a quad is dispatched, it receives a single, linear index. However, we
390 * need to translate that index into a (vertex id, instance id) pair, or a
391 * (local id x, local id y, local id z) triple for compute shaders (although
392 * vertex shaders and compute shaders are handled almost identically).
393 * Focusing on vertex shaders, one option would be to do:
395 * vertex_id = linear_id % num_vertices
396 * instance_id = linear_id / num_vertices
398 * but this involves a costly division and modulus by an arbitrary number.
399 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
400 * num_instances threads instead of num_vertices * num_instances, which results
401 * in some "extra" threads with vertex_id >= num_vertices, which we have to
402 * discard. The more we pad num_vertices, the more "wasted" threads we
403 * dispatch, but the division is potentially easier.
405 * One straightforward choice is to pad num_vertices to the next power of two,
406 * which means that the division and modulus are just simple bit shifts and
407 * masking. But the actual algorithm is a bit more complicated. The thread
408 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
409 * to dividing by a power of two. This is possibly using the technique
410 * described in patent US20170010862A1. As a result, padded_num_vertices can be
411 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
412 * since we need less padding.
414 * padded_num_vertices is picked by the hardware. The driver just specifies the
415 * actual number of vertices. At least for Mali G71, the first few cases are
418 * num_vertices | padded_num_vertices
425 * Note that padded_num_vertices is a multiple of four (presumably because
426 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
427 * at least one more than num_vertices, which seems like a quirk of the
428 * hardware. For larger num_vertices, the hardware uses the following
429 * algorithm: using the binary representation of num_vertices, we look at the
430 * most significant set bit as well as the following 3 bits. Let n be the
431 * number of bits after those 4 bits. Then we set padded_num_vertices according
432 * to the following table:
434 * high bits | padded_num_vertices
441 * For example, if num_vertices = 70 is passed to glDraw(), its binary
442 * representation is 1000110, so n = 3 and the high bits are 1000, and
443 * therefore padded_num_vertices = 9 * 2^3 = 72.
445 * The attribute unit works in terms of the original linear_id. if
446 * num_instances = 1, then they are the same, and everything is simple.
447 * However, with instancing things get more complicated. There are four
448 * possible modes, two of them we can group together:
450 * 1. Use the linear_id directly. Only used when there is no instancing.
452 * 2. Use the linear_id modulo a constant. This is used for per-vertex
453 * attributes with instancing enabled by making the constant equal
454 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
455 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
456 * The shift field specifies the power of two, while the extra_flags field
457 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
458 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
459 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
460 * shift = 3. Note that we must exactly follow the hardware algorithm used to
461 * get padded_num_vertices in order to correctly implement per-vertex
464 * 3. Divide the linear_id by a constant. In order to correctly implement
465 * instance divisors, we have to divide linear_id by padded_num_vertices times
466 * to user-specified divisor. So first we compute padded_num_vertices, again
467 * following the exact same algorithm that the hardware uses, then multiply it
468 * by the GL-level divisor to get the hardware-level divisor. This case is
469 * further divided into two more cases. If the hardware-level divisor is a
470 * power of two, then we just need to shift. The shift amount is specified by
471 * the shift field, so that the hardware-level divisor is just 2^shift.
473 * If it isn't a power of two, then we have to divide by an arbitrary integer.
474 * For that, we use the well-known technique of multiplying by an approximation
475 * of the inverse. The driver must compute the magic multiplier and shift
476 * amount, and then the hardware does the multiplication and shift. The
477 * hardware and driver also use the "round-down" optimization as described in
478 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
479 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
480 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
481 * presumably this simplifies the hardware multiplier a little. The hardware
482 * first multiplies linear_id by the multiplier and takes the high 32 bits,
483 * then applies the round-down correction if extra_flags = 1, then finally
484 * shifts right by the shift field.
486 * There are some differences between ridiculousfish's algorithm and the Mali
487 * hardware algorithm, which means that the reference code from ridiculousfish
488 * doesn't always produce the right constants. Mali does not use the pre-shift
489 * optimization, since that would make a hardware implementation slower (it
490 * would have to always do the pre-shift, multiply, and post-shift operations).
491 * It also forces the multplier to be at least 2^31, which means that the
492 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
493 * given the divisor d, the algorithm the driver must follow is:
495 * 1. Set shift = floor(log2(d)).
496 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
497 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
498 * magic_divisor = m - 1 and extra_flags = 1.
499 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
502 #define FBD_MASK (~0x3f)
504 /* MFBD, rather than SFBD */
505 #define MALI_MFBD (0x1)
507 /* ORed into an MFBD address to specify the fbx section is included */
508 #define MALI_MFBD_TAG_EXTRA (0x2)
510 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
511 * They also seem to be the same between Bifrost and Midgard. They're shared in
515 /* Applies to unknown_draw */
517 #define MALI_DRAW_INDEXED_UINT8 (0x10)
518 #define MALI_DRAW_INDEXED_UINT16 (0x20)
519 #define MALI_DRAW_INDEXED_UINT32 (0x30)
520 #define MALI_DRAW_INDEXED_SIZE (0x30)
521 #define MALI_DRAW_INDEXED_SHIFT (4)
523 #define MALI_DRAW_VARYING_SIZE (0x100)
525 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
526 * use the last vertex. This is the default in DX and VK, but not in GL. */
528 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
530 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
532 struct mali_vertex_tiler_prefix
{
533 /* This is a dynamic bitfield containing the following things in this order:
535 * - gl_WorkGroupSize.x
536 * - gl_WorkGroupSize.y
537 * - gl_WorkGroupSize.z
538 * - gl_NumWorkGroups.x
539 * - gl_NumWorkGroups.y
540 * - gl_NumWorkGroups.z
542 * The number of bits allocated for each number is based on the *_shift
543 * fields below. For example, workgroups_y_shift gives the bit that
544 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
545 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
546 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
547 * value is one more than the stored value, since if any of the values
548 * are zero, then there would be no invocations (and hence no job). If
549 * there were 0 bits allocated to a given field, then it must be zero,
550 * and hence the real value is one.
552 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
553 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
554 * where vertex count is the number of vertices.
556 u32 invocation_count
;
558 /* Bitfield for shifts:
562 * workgroups_x_shift : 6
563 * workgroups_y_shift : 6
564 * workgroups_z_shift : 6
565 * workgroups_x_shift_2 : 4
567 u32 invocation_shifts
;
570 u32 unknown_draw
: 22;
572 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
573 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
574 * something to do with how many quads get put in the same execution
575 * engine, which is a balance (you don't want to starve the engine, but
576 * you also want to distribute work evenly).
578 u32 workgroups_x_shift_3
: 6;
581 /* Negative of min_index. This is used to compute
582 * the unbiased index in tiler/fragment shader runs.
584 * The hardware adds offset_bias_correction in each run,
585 * so that absent an index bias, the first vertex processed is
586 * genuinely the first vertex (0). But with an index bias,
587 * the first vertex process is numbered the same as the bias.
589 * To represent this more conviniently:
590 * unbiased_index = lower_bound_index +
592 * offset_bias_correction
594 * This is done since the hardware doesn't accept a index_bias
595 * and this allows it to recover the unbiased index.
597 int32_t offset_bias_correction
;
600 /* Like many other strictly nonzero quantities, index_count is
601 * subtracted by one. For an indexed cube, this is equal to 35 = 6
602 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
603 * for an indexed draw, index_count is the number of actual vertices
604 * rendered whereas invocation_count is the number of unique vertices
605 * rendered (the number of times the vertex shader must be invoked).
606 * For non-indexed draws, this is just equal to invocation_count. */
610 /* No hidden structure; literally just a pointer to an array of uint
611 * indices (width depends on flags). Thanks, guys, for not making my
612 * life insane for once! NULL for non-indexed draws. */
615 } __attribute__((packed
));
617 /* Point size / line width can either be specified as a 32-bit float (for
618 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
619 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
620 * payload, the contents of varying_pointer will be intepreted as an array of
621 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
622 * creating a special MALI_R16F varying writing to varying_pointer. */
624 union midgard_primitive_size
{
629 struct bifrost_tiler_heap_meta
{
632 /* note: these are just guesses! */
633 mali_ptr tiler_heap_start
;
634 mali_ptr tiler_heap_free
;
635 mali_ptr tiler_heap_end
;
637 /* hierarchy weights? but they're still 0 after the job has run... */
641 } __attribute__((packed
));
643 struct bifrost_tiler_meta
{
644 u32 tiler_heap_next_start
; /* To be written by the GPU */
645 u32 used_hierarchy_mask
; /* To be written by the GPU */
646 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
651 mali_ptr tiler_heap_meta
;
652 /* TODO what is this used for? */
654 } __attribute__((packed
));
656 struct bifrost_tiler_only
{
658 union midgard_primitive_size primitive_size
;
662 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
663 } __attribute__((packed
));
665 struct mali_vertex_tiler_postfix
{
666 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
668 /* Both zero for non-instanced draws. For instanced draws, a
669 * decomposition of padded_num_vertices. See the comments about the
670 * corresponding fields in mali_attr for context. */
672 unsigned instance_shift
: 5;
673 unsigned instance_odd
: 3;
677 /* Offset for first vertex in buffer */
682 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
683 * output from the vertex shader for tiler jobs.
686 u64 position_varying
;
688 /* An array of mali_uniform_buffer_meta's. The size is given by the
693 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
694 * On Midgard, this is a pointer to an array of pointers to the texture
695 * descriptors, number of pointers bounded by number of textures. The
696 * indirection is needed to accomodate varying numbers and sizes of
697 * texture descriptors */
700 /* For OpenGL, from what I've seen, this is intimately connected to
701 * texture_meta. cwabbott says this is not the case under Vulkan, hence
702 * why this field is seperate (Midgard is Vulkan capable). Pointer to
703 * array of sampler descriptors (which are uniform in size) */
704 u64 sampler_descriptor
;
708 u64 attributes
; /* struct attribute_buffer[] */
709 u64 attribute_meta
; /* attribute_meta[] */
710 u64 varyings
; /* struct attr */
711 u64 varying_meta
; /* pointer */
713 u64 occlusion_counter
; /* A single bit as far as I can tell */
715 /* On Bifrost, this points directly to a mali_shared_memory structure.
716 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
717 * tagged), which embeds a mali_shared_memory structure */
718 mali_ptr shared_memory
;
719 } __attribute__((packed
));
721 struct midgard_payload_vertex_tiler
{
722 struct mali_vertex_tiler_prefix prefix
;
723 struct mali_vertex_tiler_postfix postfix
;
725 union midgard_primitive_size primitive_size
;
726 } __attribute__((packed
));
728 struct bifrost_payload_vertex
{
729 struct mali_vertex_tiler_prefix prefix
;
730 struct mali_vertex_tiler_postfix postfix
;
731 } __attribute__((packed
));
733 struct bifrost_payload_tiler
{
734 struct mali_vertex_tiler_prefix prefix
;
735 struct bifrost_tiler_only tiler
;
736 struct mali_vertex_tiler_postfix postfix
;
737 } __attribute__((packed
));
739 struct bifrost_payload_fused
{
740 struct mali_vertex_tiler_prefix prefix
;
741 struct bifrost_tiler_only tiler
;
742 struct mali_vertex_tiler_postfix tiler_postfix
;
743 u64 padding
; /* zero */
744 struct mali_vertex_tiler_postfix vertex_postfix
;
745 } __attribute__((packed
));
747 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
748 * texture is stored as (63, 63) in these fields. This adjusts for that.
749 * There's an identical pattern in the framebuffer descriptor. Even vertex
750 * count fields work this way, hence the generic name -- integral fields that
751 * are strictly positive generally need this adjustment. */
753 #define MALI_POSITIVE(dim) (dim - 1)
756 #define MAX_MIP_LEVELS (13)
758 /* Cubemap bloats everything up */
759 #define MAX_CUBE_FACES (6)
761 /* For each pointer, there is an address and optionally also a stride */
762 #define MAX_ELEMENTS (2)
764 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
765 * be cleaned up a lot. */
767 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
769 static inline int16_t
770 FIXED_16(float x
, bool allow_negative
)
772 /* Clamp inputs, accounting for float error */
773 float max_lod
= (32.0 - (1.0 / 512.0));
774 float min_lod
= allow_negative
? -max_lod
: 0.0;
776 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
778 return (int) (x
* 256.0);
781 /* From presentations, 16x16 tiles externally. Use shift for fast computation
782 * of tile numbers. */
784 #define MALI_TILE_SHIFT 4
785 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
787 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
788 * each component. Notice that this provides a theoretical upper bound of (1 <<
789 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
790 * 65536x65536. Multiplying that together, times another four given that Mali
791 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
792 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
793 * alone rendering in real-time to such a buffer.
797 /* From mali_kbase_10969_workaround.c */
798 #define MALI_X_COORD_MASK 0x00000FFF
799 #define MALI_Y_COORD_MASK 0x0FFF0000
801 /* Extract parts of a tile coordinate */
803 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
804 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
806 /* Helpers to generate tile coordinates based on the boundary coordinates in
807 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
808 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
809 * Intentional "off-by-one"; finding the tile number is a form of fencepost
812 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
813 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
814 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
815 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
816 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
818 struct mali_payload_fragment
{
821 mali_ptr framebuffer
;
822 } __attribute__((packed
));
824 /* Single Framebuffer Descriptor */
826 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
827 * configured for 4x. With MSAA_8, it is configured for 8x. */
829 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
830 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
831 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
832 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
834 /* Fast/slow based on whether all three buffers are cleared at once */
836 #define MALI_CLEAR_FAST (1 << 18)
837 #define MALI_CLEAR_SLOW (1 << 28)
838 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
840 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
841 * within the larget framebuffer descriptor). Analogous to
842 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
844 /* See pan_tiler.c for derivation */
845 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
847 /* Flag disabling the tiler for clear-only jobs, with
848 hierarchical tiling */
849 #define MALI_TILER_DISABLED (1 << 12)
851 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
852 * hierarhical tiling. */
853 #define MALI_TILER_USER 0xFFF
855 /* Absent any geometry, the minimum size of the polygon list header */
856 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
858 struct midgard_tiler_descriptor
{
859 /* Size of the entire polygon list; see pan_tiler.c for the
860 * computation. It's based on hierarchical tiling */
862 u32 polygon_list_size
;
864 /* Name known from the replay workaround in the kernel. What exactly is
865 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
866 * specifies a mask of hierarchy weights, which explains some of the
867 * performance mysteries around setting it. We also see the bottom bit
868 * of tiler_flags set in the kernel, but no comment why.
870 * hierarchy_mask can have the TILER_DISABLED flag */
875 /* See mali_tiler.c for an explanation */
876 mali_ptr polygon_list
;
877 mali_ptr polygon_list_body
;
879 /* Names based on we see symmetry with replay jobs which name these
882 mali_ptr heap_start
; /* tiler heap_free_address */
885 /* Hierarchy weights. We know these are weights based on the kernel,
886 * but I've never seen them be anything other than zero */
890 struct mali_sfbd_format
{
894 /* mali_channel_swizzle */
895 unsigned swizzle
: 12;
898 unsigned nr_channels
: 2;
903 enum mali_block_format block
: 2;
909 /* Shared structure at the start of framebuffer descriptors, or used bare for
910 * compute jobs, configuring stack and shared memory */
912 struct mali_shared_memory
{
916 /* Configuration for shared memory for compute shaders.
917 * shared_workgroup_count is logarithmic and may be computed for a
918 * compute shader using shared memory as:
920 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
922 * For compute shaders that don't use shared memory, or non-compute
923 * shaders, this is set to ~0
926 u32 shared_workgroup_count
: 5;
928 u32 shared_shift
: 4;
929 u32 shared_zero
: 20;
933 /* For compute shaders, the RAM backing of workgroup-shared memory. For
934 * fragment shaders on Bifrost, apparently multisampling locations */
936 mali_ptr shared_memory
;
938 } __attribute__((packed
));
940 /* Configures multisampling on Bifrost fragment jobs */
942 struct bifrost_multisampling
{
945 mali_ptr sample_locations
;
947 } __attribute__((packed
));
949 struct mali_single_framebuffer
{
950 struct mali_shared_memory shared_memory
;
951 struct mali_sfbd_format format
;
956 /* Purposeful off-by-one in these fields should be accounted for by the
957 * MALI_DIMENSION macro */
967 /* By default, the framebuffer is upside down from OpenGL's
968 * perspective. Set framebuffer to the end and negate the stride to
969 * flip in the Y direction */
971 mali_ptr framebuffer
;
976 /* Depth and stencil buffers are interleaved, it appears, as they are
977 * set to the same address in captures. Both fields set to zero if the
978 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
979 * get a zero enable despite the buffer being present; that still is
982 mali_ptr depth_buffer
; // not SAME_VA
983 u32 depth_stride_zero
: 4;
984 u32 depth_stride
: 28;
987 mali_ptr stencil_buffer
; // not SAME_VA
988 u32 stencil_stride_zero
: 4;
989 u32 stencil_stride
: 28;
992 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
993 u32 clear_color_2
; // always equal, but unclear function?
994 u32 clear_color_3
; // always equal, but unclear function?
995 u32 clear_color_4
; // always equal, but unclear function?
997 /* Set to zero if not cleared */
999 float clear_depth_1
; // float32, ditto
1000 float clear_depth_2
; // float32, ditto
1001 float clear_depth_3
; // float32, ditto
1002 float clear_depth_4
; // float32, ditto
1004 u32 clear_stencil
; // Exactly as it appears in OpenGL
1008 struct midgard_tiler_descriptor tiler
;
1010 /* More below this, maybe */
1011 } __attribute__((packed
));
1014 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1016 struct mali_rt_format
{
1020 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1024 enum mali_block_format block
: 2;
1025 enum mali_msaa msaa
: 2;
1028 unsigned swizzle
: 12;
1032 /* Disables MFBD preload. When this bit is set, the render target will
1033 * be cleared every frame. When this bit is clear, the hardware will
1034 * automatically wallpaper the render target back from main memory.
1035 * Unfortunately, MFBD preload is very broken on Midgard, so in
1036 * practice, this is a chicken bit that should always be set.
1037 * Discovered by accident, as all good chicken bits are. */
1039 unsigned no_preload
: 1;
1040 } __attribute__((packed
));
1042 /* Flags for afbc.flags and ds_afbc.flags */
1044 #define MALI_AFBC_FLAGS 0x10009
1046 /* Lossless RGB and RGBA colorspace transform */
1047 #define MALI_AFBC_YTR (1 << 17)
1049 struct mali_render_target
{
1050 struct mali_rt_format format
;
1055 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1056 * there is an extra metadata buffer that contains 16 bytes per tile.
1057 * The framebuffer needs to be the same size as before, since we don't
1058 * know ahead of time how much space it will take up. The
1059 * framebuffer_stride is set to 0, since the data isn't stored linearly
1062 * When AFBC is disabled, these fields are zero.
1066 u32 stride
; // stride in units of tiles
1067 u32 flags
; // = 0x20000
1070 mali_ptr framebuffer
;
1073 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1074 u32 layer_stride
; /* For multisample rendering */
1076 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1077 u32 clear_color_2
; // always equal, but unclear function?
1078 u32 clear_color_3
; // always equal, but unclear function?
1079 u32 clear_color_4
; // always equal, but unclear function?
1080 } __attribute__((packed
));
1082 /* An optional part of mali_framebuffer. It comes between the main structure
1083 * and the array of render targets. It must be included if any of these are
1086 * - Transaction Elimination
1088 * - TODO: Anything else?
1092 #define MALI_EXTRA_PRESENT (0x1)
1095 #define MALI_EXTRA_ZS (0x4)
1097 struct mali_framebuffer_extra
{
1099 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1100 u32 checksum_stride
;
1102 unsigned flags_lo
: 4;
1103 enum mali_block_format zs_block
: 2;
1105 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1106 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1107 unsigned zs_samples
: 4;
1108 unsigned flags_hi
: 22;
1111 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1113 mali_ptr depth_stencil_afbc_metadata
;
1114 u32 depth_stencil_afbc_stride
; // in units of tiles
1117 mali_ptr depth_stencil
;
1123 /* Depth becomes depth/stencil in case of combined D/S */
1125 u32 depth_stride_zero
: 4;
1126 u32 depth_stride
: 28;
1127 u32 depth_layer_stride
;
1130 u32 stencil_stride_zero
: 4;
1131 u32 stencil_stride
: 28;
1132 u32 stencil_layer_stride
;
1140 } __attribute__((packed
));
1142 /* Flags for mfbd_flags */
1144 /* Enables writing depth results back to main memory (rather than keeping them
1145 * on-chip in the tile buffer and then discarding) */
1147 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1149 /* The MFBD contains the extra mali_framebuffer_extra section */
1151 #define MALI_MFBD_EXTRA (1 << 13)
1153 struct mali_framebuffer
{
1155 struct mali_shared_memory shared_memory
;
1156 struct bifrost_multisampling msaa
;
1160 u16 width1
, height1
;
1162 u16 width2
, height2
;
1163 u32 unk1
: 19; // = 0x01000
1164 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1165 u32 unk2
: 2; // = 0
1166 u32 rt_count_2
: 3; // no off-by-one
1169 u32 clear_stencil
: 8;
1170 u32 mfbd_flags
: 24; // = 0x100
1174 struct midgard_tiler_descriptor tiler
;
1176 mali_ptr tiler_meta
;
1181 /* optional: struct mali_framebuffer_extra extra */
1182 /* struct mali_render_target rts[] */
1183 } __attribute__((packed
));
1185 #endif /* __PANFROST_JOB_H__ */