2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
32 #include <panfrost-misc.h>
37 JOB_TYPE_WRITE_VALUE
= 2,
38 JOB_TYPE_CACHE_FLUSH
= 3,
41 JOB_TYPE_GEOMETRY
= 6,
44 JOB_TYPE_FRAGMENT
= 9,
51 MALI_LINE_STRIP
= 0x4,
54 MALI_TRIANGLE_STRIP
= 0xA,
55 MALI_TRIANGLE_FAN
= 0xC,
58 MALI_QUAD_STRIP
= 0xF,
60 /* All other modes invalid */
63 /* Applies to tiler_gl_enables */
65 #define MALI_OCCLUSION_QUERY (1 << 3)
66 #define MALI_OCCLUSION_PRECISE (1 << 4)
68 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
69 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
70 * disagree about how to do viewport flipping, so the blob actually sets this
71 * for GL_CW but then has a negative viewport stride */
73 #define MALI_FRONT_CCW_TOP (1 << 5)
75 #define MALI_CULL_FACE_FRONT (1 << 6)
76 #define MALI_CULL_FACE_BACK (1 << 7)
78 /* Used in stencil and depth tests */
85 MALI_FUNC_GREATER
= 4,
86 MALI_FUNC_NOTEQUAL
= 5,
91 /* Flags apply to unknown2_3? */
93 #define MALI_HAS_MSAA (1 << 0)
94 #define MALI_CAN_DISCARD (1 << 5)
96 /* Applies on SFBD systems, specifying that programmable blending is in use */
97 #define MALI_HAS_BLEND_SHADER (1 << 6)
99 /* func is mali_func */
100 #define MALI_DEPTH_FUNC(func) (func << 8)
101 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
102 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
104 #define MALI_DEPTH_WRITEMASK (1 << 11)
106 /* Next flags to unknown2_4 */
107 #define MALI_STENCIL_TEST (1 << 0)
110 #define MALI_SAMPLE_ALPHA_TO_COVERAGE_NO_BLEND_SHADER (1 << 1)
112 #define MALI_NO_DITHER (1 << 9)
113 #define MALI_DEPTH_RANGE_A (1 << 12)
114 #define MALI_DEPTH_RANGE_B (1 << 13)
115 #define MALI_NO_MSAA (1 << 14)
117 /* Stencil test state is all encoded in a single u32, just with a lot of
120 enum mali_stencil_op
{
121 MALI_STENCIL_KEEP
= 0,
122 MALI_STENCIL_REPLACE
= 1,
123 MALI_STENCIL_ZERO
= 2,
124 MALI_STENCIL_INVERT
= 3,
125 MALI_STENCIL_INCR_WRAP
= 4,
126 MALI_STENCIL_DECR_WRAP
= 5,
127 MALI_STENCIL_INCR
= 6,
128 MALI_STENCIL_DECR
= 7
131 struct mali_stencil_test
{
134 enum mali_func func
: 3;
135 enum mali_stencil_op sfail
: 3;
136 enum mali_stencil_op dpfail
: 3;
137 enum mali_stencil_op dppass
: 3;
139 } __attribute__((packed
));
141 #define MALI_MASK_R (1 << 0)
142 #define MALI_MASK_G (1 << 1)
143 #define MALI_MASK_B (1 << 2)
144 #define MALI_MASK_A (1 << 3)
146 enum mali_nondominant_mode
{
147 MALI_BLEND_NON_MIRROR
= 0,
148 MALI_BLEND_NON_ZERO
= 1
151 enum mali_dominant_blend
{
152 MALI_BLEND_DOM_SOURCE
= 0,
153 MALI_BLEND_DOM_DESTINATION
= 1
156 enum mali_dominant_factor
{
157 MALI_DOMINANT_UNK0
= 0,
158 MALI_DOMINANT_ZERO
= 1,
159 MALI_DOMINANT_SRC_COLOR
= 2,
160 MALI_DOMINANT_DST_COLOR
= 3,
161 MALI_DOMINANT_UNK4
= 4,
162 MALI_DOMINANT_SRC_ALPHA
= 5,
163 MALI_DOMINANT_DST_ALPHA
= 6,
164 MALI_DOMINANT_CONSTANT
= 7,
167 enum mali_blend_modifier
{
168 MALI_BLEND_MOD_UNK0
= 0,
169 MALI_BLEND_MOD_NORMAL
= 1,
170 MALI_BLEND_MOD_SOURCE_ONE
= 2,
171 MALI_BLEND_MOD_DEST_ONE
= 3,
174 struct mali_blend_mode
{
175 enum mali_blend_modifier clip_modifier
: 2;
176 unsigned unused_0
: 1;
177 unsigned negate_source
: 1;
179 enum mali_dominant_blend dominant
: 1;
181 enum mali_nondominant_mode nondominant_mode
: 1;
183 unsigned unused_1
: 1;
185 unsigned negate_dest
: 1;
187 enum mali_dominant_factor dominant_factor
: 3;
188 unsigned complement_dominant
: 1;
189 } __attribute__((packed
));
191 struct mali_blend_equation
{
192 /* Of type mali_blend_mode */
193 unsigned rgb_mode
: 12;
194 unsigned alpha_mode
: 12;
198 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
200 unsigned color_mask
: 4;
201 } __attribute__((packed
));
203 /* Used with channel swizzling */
205 MALI_CHANNEL_RED
= 0,
206 MALI_CHANNEL_GREEN
= 1,
207 MALI_CHANNEL_BLUE
= 2,
208 MALI_CHANNEL_ALPHA
= 3,
209 MALI_CHANNEL_ZERO
= 4,
210 MALI_CHANNEL_ONE
= 5,
211 MALI_CHANNEL_RESERVED_0
= 6,
212 MALI_CHANNEL_RESERVED_1
= 7,
215 struct mali_channel_swizzle
{
216 enum mali_channel r
: 3;
217 enum mali_channel g
: 3;
218 enum mali_channel b
: 3;
219 enum mali_channel a
: 3;
220 } __attribute__((packed
));
222 /* Compressed per-pixel formats. Each of these formats expands to one to four
223 * floating-point or integer numbers, as defined by the OpenGL specification.
224 * There are various places in OpenGL where the user can specify a compressed
225 * format in memory, which all use the same 8-bit enum in the various
226 * descriptors, although different hardware units support different formats.
229 /* The top 3 bits specify how the bits of each component are interpreted. */
231 /* e.g. R11F_G11F_B10F */
232 #define MALI_FORMAT_SPECIAL (2 << 5)
234 /* signed normalized, e.g. RGBA8_SNORM */
235 #define MALI_FORMAT_SNORM (3 << 5)
238 #define MALI_FORMAT_UINT (4 << 5)
240 /* e.g. RGBA8 and RGBA32F */
241 #define MALI_FORMAT_UNORM (5 << 5)
243 /* e.g. RGBA8I and RGBA16F */
244 #define MALI_FORMAT_SINT (6 << 5)
246 /* These formats seem to largely duplicate the others. They're used at least
247 * for Bifrost framebuffer output.
249 #define MALI_FORMAT_SPECIAL2 (7 << 5)
251 /* If the high 3 bits are 3 to 6 these two bits say how many components
254 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
256 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
257 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
261 #define MALI_CHANNEL_4 2
263 #define MALI_CHANNEL_8 3
265 #define MALI_CHANNEL_16 4
267 #define MALI_CHANNEL_32 5
269 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
270 * MALI_FORMAT_UNORM, it means a 32-bit float.
272 #define MALI_CHANNEL_FLOAT 7
275 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
276 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
277 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
278 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
279 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
280 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
283 MALI_NV12
= MALI_FORMAT_SPECIAL
| 0xc,
285 MALI_Z32_UNORM
= MALI_FORMAT_SPECIAL
| 0xD,
286 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
287 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
288 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
289 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
290 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
291 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
292 /* Only used for varyings, to indicate the transformed gl_Position */
293 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
294 /* Only used for varyings, to indicate that the write should be
297 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
299 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
300 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
301 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
302 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
303 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
304 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
305 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
306 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
307 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
308 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
309 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
310 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
312 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
313 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
314 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
315 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
316 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
317 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
318 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
319 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
320 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
321 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
322 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
323 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
325 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
326 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
327 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
328 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
329 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
330 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
331 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
332 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
333 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
334 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
335 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
336 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
337 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
338 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
339 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
340 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
341 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
343 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
344 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
345 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
346 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
347 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
348 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
349 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
350 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
351 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
352 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
353 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
354 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
355 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
356 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
357 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
358 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
360 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
361 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
362 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
366 /* Alpha coverage is encoded as 4-bits (from a clampf), with inversion
367 * literally performing a bitwise invert. This function produces slightly wrong
368 * results and I'm not sure why; some rounding issue I suppose... */
370 #define MALI_ALPHA_COVERAGE(clampf) ((uint16_t) (int) (clampf * 15.0f))
371 #define MALI_GET_ALPHA_COVERAGE(nibble) ((float) nibble / 15.0f)
373 /* Applies to midgard1.flags */
375 /* Should the hardware perform early-Z testing? Normally should be set
376 * for performance reasons. Clear if you use: discard,
377 * alpha-to-coverage... * It's also possible this disables
378 * forward-pixel kill; we're not quite sure which bit is which yet.
379 * TODO: How does this interact with blending?*/
381 #define MALI_EARLY_Z (1 << 6)
383 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
384 * fragment shader that uses texturing or derivative functions */
386 #define MALI_HELPER_INVOCATIONS (1 << 7)
388 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
389 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
390 * it might read depth/stencil in particular, also set MALI_READS_ZS */
392 #define MALI_READS_ZS (1 << 8)
393 #define MALI_READS_TILEBUFFER (1 << 12)
395 /* The raw Midgard blend payload can either be an equation or a shader
396 * address, depending on the context */
398 union midgard_blend
{
402 struct mali_blend_equation equation
;
407 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
410 #define MALI_BLEND_LOAD_TIB (0x1)
412 /* A blend shader is used to blend this render target */
413 #define MALI_BLEND_MRT_SHADER (0x2)
415 /* On MRT Midgard systems (using an MFBD), each render target gets its own
416 * blend descriptor */
418 #define MALI_BLEND_SRGB (0x400)
420 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
421 #define MALI_BLEND_NO_DITHER (0x800)
423 struct midgard_blend_rt
{
424 /* Flags base value of 0x200 to enable the render target.
425 * OR with 0x1 for blending (anything other than REPLACE).
426 * OR with 0x2 for programmable blending
427 * OR with MALI_BLEND_SRGB for implicit sRGB
431 union midgard_blend blend
;
432 } __attribute__((packed
));
434 /* On Bifrost systems (all MRT), each render target gets one of these
437 struct bifrost_blend_rt
{
438 /* This is likely an analogue of the flags on
439 * midgard_blend_rt */
441 u16 flags
; // = 0x200
443 /* Single-channel blend constants are encoded in a sort of
444 * fixed-point. Basically, the float is mapped to a byte, becoming
445 * a high byte, and then the lower-byte is added for precision.
446 * For the original float f:
448 * f = (constant_hi / 255) + (constant_lo / 65535)
450 * constant_hi = int(f / 255)
451 * constant_lo = 65535*f - (65535/255) * constant_hi
456 struct mali_blend_equation equation
;
459 * - 0x3 when this slot is unused (everything else is 0 except the index)
460 * - 0x11 when this is the fourth slot (and it's used)
461 + * - 0 when there is a blend shader
464 /* increments from 0 to 3 */
469 /* So far, I've only seen:
470 * - R001 for 1-component formats
471 * - RG01 for 2-component formats
472 * - RGB1 for 3-component formats
473 * - RGBA for 4-component formats
476 enum mali_format format
: 8;
478 /* Type of the shader output variable. Note, this can
479 * be different from the format.
481 * 0: f16 (mediump float)
482 * 1: f32 (highp float)
484 * 3: u32 (highp uint)
485 * 4: i16 (mediump int)
486 * 5: u16 (mediump uint)
492 /* Only the low 32 bits of the blend shader are stored, the
493 * high 32 bits are implicitly the same as the original shader.
494 * According to the kernel driver, the program counter for
495 * shaders is actually only 24 bits, so shaders cannot cross
496 * the 2^24-byte boundary, and neither can the blend shader.
497 * The blob handles this by allocating a 2^24 byte pool for
498 * shaders, and making sure that any blend shaders are stored
499 * in the same pool as the original shader. The kernel will
500 * make sure this allocation is aligned to 2^24 bytes.
504 } __attribute__((packed
));
506 /* Descriptor for the shader. Following this is at least one, up to four blend
507 * descriptors for each active render target */
509 struct mali_shader_meta
{
518 u32 uniform_buffer_count
: 4;
519 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
522 unsigned uniform_buffer_count
: 4;
525 /* Whole number of uniform registers used, times two;
526 * whole number of work registers used (no scale).
528 unsigned work_count
: 5;
529 unsigned uniform_count
: 5;
530 unsigned unknown2
: 6;
534 /* Same as glPolygoOffset() arguments */
543 u8 stencil_mask_front
;
544 u8 stencil_mask_back
;
547 struct mali_stencil_test stencil_front
;
548 struct mali_stencil_test stencil_back
;
553 /* On Bifrost, some system values are preloaded in
554 * registers R55-R62 by the thread dispatcher prior to
555 * the start of shader execution. This is a bitfield
556 * with one entry for each register saying which
557 * registers need to be preloaded. Right now, the known
561 * - R55 : gl_LocalInvocationID.xy
562 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
563 * - R57 : gl_WorkGroupID.x
564 * - R58 : gl_WorkGroupID.y
565 * - R59 : gl_WorkGroupID.z
566 * - R60 : gl_GlobalInvocationID.x
567 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
568 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
571 * - R55 : unknown, never seen (but the bit for this is
573 * - R56 : unknown (bit always unset)
574 * - R57 : gl_PrimitiveID
575 * - R58 : gl_FrontFacing in low bit, potentially other stuff
576 * - R59 : u16 fragment coordinates (used to compute
577 * gl_FragCoord.xy, together with sample positions)
578 * - R60 : gl_SampleMask (used in epilog, so pretty
579 * much always used, but the bit is always 0 -- is
580 * this just always pushed?)
581 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
582 * varying interpolation.
583 * - R62 : unknown (bit always unset).
585 u32 preload_regs
: 8;
586 /* In units of 8 bytes or 64 bits, since the
587 * uniform/const port loads 64 bits at a time.
589 u32 uniform_count
: 7;
590 u32 unk4
: 10; // = 2
597 /* zero on bifrost */
600 /* Blending information for the older non-MRT Midgard HW. Check for
601 * MALI_HAS_BLEND_SHADER to decide how to interpret.
604 union midgard_blend blend
;
605 } __attribute__((packed
));
607 /* This only concerns hardware jobs */
609 /* Possible values for job_descriptor_size */
611 #define MALI_JOB_32 0
612 #define MALI_JOB_64 1
614 struct mali_job_descriptor_header
{
615 u32 exception_status
;
616 u32 first_incomplete_task
;
618 u8 job_descriptor_size
: 1;
619 enum mali_job_type job_type
: 7;
621 u8 unknown_flags
: 7;
623 u16 job_dependency_index_1
;
624 u16 job_dependency_index_2
;
630 } __attribute__((packed
));
632 /* These concern exception_status */
634 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
637 enum mali_exception_access
{
638 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
639 * fault so it's just unused */
640 MALI_EXCEPTION_ACCESS_NONE
= 0,
642 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
643 MALI_EXCEPTION_ACCESS_READ
= 2,
644 MALI_EXCEPTION_ACCESS_WRITE
= 3
647 /* Details about write_value from panfrost igt tests which use it as a generic
648 * dword write primitive */
650 #define MALI_WRITE_VALUE_ZERO 3
652 struct mali_payload_write_value
{
654 u32 value_descriptor
;
657 } __attribute__((packed
));
662 * This structure lets the attribute unit compute the address of an attribute
663 * given the vertex and instance ID. Unfortunately, the way this works is
664 * rather complicated when instancing is enabled.
666 * To explain this, first we need to explain how compute and vertex threads are
667 * dispatched. This is a guess (although a pretty firm guess!) since the
668 * details are mostly hidden from the driver, except for attribute instancing.
669 * When a quad is dispatched, it receives a single, linear index. However, we
670 * need to translate that index into a (vertex id, instance id) pair, or a
671 * (local id x, local id y, local id z) triple for compute shaders (although
672 * vertex shaders and compute shaders are handled almost identically).
673 * Focusing on vertex shaders, one option would be to do:
675 * vertex_id = linear_id % num_vertices
676 * instance_id = linear_id / num_vertices
678 * but this involves a costly division and modulus by an arbitrary number.
679 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
680 * num_instances threads instead of num_vertices * num_instances, which results
681 * in some "extra" threads with vertex_id >= num_vertices, which we have to
682 * discard. The more we pad num_vertices, the more "wasted" threads we
683 * dispatch, but the division is potentially easier.
685 * One straightforward choice is to pad num_vertices to the next power of two,
686 * which means that the division and modulus are just simple bit shifts and
687 * masking. But the actual algorithm is a bit more complicated. The thread
688 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
689 * to dividing by a power of two. This is possibly using the technique
690 * described in patent US20170010862A1. As a result, padded_num_vertices can be
691 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
692 * since we need less padding.
694 * padded_num_vertices is picked by the hardware. The driver just specifies the
695 * actual number of vertices. At least for Mali G71, the first few cases are
698 * num_vertices | padded_num_vertices
705 * Note that padded_num_vertices is a multiple of four (presumably because
706 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
707 * at least one more than num_vertices, which seems like a quirk of the
708 * hardware. For larger num_vertices, the hardware uses the following
709 * algorithm: using the binary representation of num_vertices, we look at the
710 * most significant set bit as well as the following 3 bits. Let n be the
711 * number of bits after those 4 bits. Then we set padded_num_vertices according
712 * to the following table:
714 * high bits | padded_num_vertices
721 * For example, if num_vertices = 70 is passed to glDraw(), its binary
722 * representation is 1000110, so n = 3 and the high bits are 1000, and
723 * therefore padded_num_vertices = 9 * 2^3 = 72.
725 * The attribute unit works in terms of the original linear_id. if
726 * num_instances = 1, then they are the same, and everything is simple.
727 * However, with instancing things get more complicated. There are four
728 * possible modes, two of them we can group together:
730 * 1. Use the linear_id directly. Only used when there is no instancing.
732 * 2. Use the linear_id modulo a constant. This is used for per-vertex
733 * attributes with instancing enabled by making the constant equal
734 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
735 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
736 * The shift field specifies the power of two, while the extra_flags field
737 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
738 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
739 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
740 * shift = 3. Note that we must exactly follow the hardware algorithm used to
741 * get padded_num_vertices in order to correctly implement per-vertex
744 * 3. Divide the linear_id by a constant. In order to correctly implement
745 * instance divisors, we have to divide linear_id by padded_num_vertices times
746 * to user-specified divisor. So first we compute padded_num_vertices, again
747 * following the exact same algorithm that the hardware uses, then multiply it
748 * by the GL-level divisor to get the hardware-level divisor. This case is
749 * further divided into two more cases. If the hardware-level divisor is a
750 * power of two, then we just need to shift. The shift amount is specified by
751 * the shift field, so that the hardware-level divisor is just 2^shift.
753 * If it isn't a power of two, then we have to divide by an arbitrary integer.
754 * For that, we use the well-known technique of multiplying by an approximation
755 * of the inverse. The driver must compute the magic multiplier and shift
756 * amount, and then the hardware does the multiplication and shift. The
757 * hardware and driver also use the "round-down" optimization as described in
758 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
759 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
760 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
761 * presumably this simplifies the hardware multiplier a little. The hardware
762 * first multiplies linear_id by the multiplier and takes the high 32 bits,
763 * then applies the round-down correction if extra_flags = 1, then finally
764 * shifts right by the shift field.
766 * There are some differences between ridiculousfish's algorithm and the Mali
767 * hardware algorithm, which means that the reference code from ridiculousfish
768 * doesn't always produce the right constants. Mali does not use the pre-shift
769 * optimization, since that would make a hardware implementation slower (it
770 * would have to always do the pre-shift, multiply, and post-shift operations).
771 * It also forces the multplier to be at least 2^31, which means that the
772 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
773 * given the divisor d, the algorithm the driver must follow is:
775 * 1. Set shift = floor(log2(d)).
776 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
777 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
778 * magic_divisor = m - 1 and extra_flags = 1.
779 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
781 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
782 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
783 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
784 * (*NOT the row stride*). Size is set to the size of the image itself.
786 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
787 * use particular fixed addresses with modified structures.
790 enum mali_attr_mode
{
791 MALI_ATTR_UNUSED
= 0,
792 MALI_ATTR_LINEAR
= 1,
793 MALI_ATTR_POT_DIVIDE
= 2,
794 MALI_ATTR_MODULO
= 3,
795 MALI_ATTR_NPOT_DIVIDE
= 4,
799 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
801 #define MALI_ATTR_VERTEXID (0x22)
802 #define MALI_ATTR_INSTANCEID (0x24)
803 #define MALI_VARYING_FRAG_COORD (0x25)
804 #define MALI_VARYING_FRONT_FACING (0x26)
806 /* This magic "pseudo-address" is used as `elements` to implement
807 * gl_PointCoord. When read from a fragment shader, it generates a point
808 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
809 * require an affine transformation in the shader. */
811 #define MALI_VARYING_POINT_COORD (0x61)
813 /* Used for comparison to check if an address is special. Mostly a guess, but
814 * it doesn't really matter. */
816 #define MALI_RECORD_SPECIAL (0x100)
819 /* This is used for actual attributes. */
821 /* The bottom 3 bits are the mode */
822 mali_ptr elements
: 64 - 8;
828 /* The entry after an NPOT_DIVIDE entry has this format. It stores
829 * extra information that wouldn't fit in a normal entry.
832 u32 unk
; /* = 0x20 */
835 /* This is the original, GL-level divisor. */
838 } __attribute__((packed
));
840 struct mali_attr_meta
{
841 /* Vertex buffer index */
844 unsigned unknown1
: 2;
845 unsigned swizzle
: 12;
846 enum mali_format format
: 8;
848 /* Always observed to be zero at the moment */
849 unsigned unknown3
: 2;
851 /* When packing multiple attributes in a buffer, offset addresses by
852 * this value. Obscurely, this is signed. */
854 } __attribute__((packed
));
856 #define FBD_MASK (~0x3f)
858 /* MFBD, rather than SFBD */
859 #define MALI_MFBD (0x1)
861 /* ORed into an MFBD address to specify the fbx section is included */
862 #define MALI_MFBD_TAG_EXTRA (0x2)
864 struct mali_uniform_buffer_meta
{
865 /* This is actually the size minus 1 (MALI_POSITIVE), in units of 16
866 * bytes. This gives a maximum of 2^14 bytes, which just so happens to
867 * be the GL minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
871 /* This is missing the bottom 2 bits and top 8 bits. The top 8 bits
872 * should be 0 for userspace pointers, according to
873 * https://lwn.net/Articles/718895/. By reusing these bits, we can make
874 * each entry in the table only 64 bits.
876 mali_ptr ptr
: 64 - 10;
879 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
880 * They also seem to be the same between Bifrost and Midgard. They're shared in
884 /* Applies to unknown_draw */
886 #define MALI_DRAW_INDEXED_UINT8 (0x10)
887 #define MALI_DRAW_INDEXED_UINT16 (0x20)
888 #define MALI_DRAW_INDEXED_UINT32 (0x30)
889 #define MALI_DRAW_INDEXED_SIZE (0x30)
890 #define MALI_DRAW_INDEXED_SHIFT (4)
892 #define MALI_DRAW_VARYING_SIZE (0x100)
893 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
895 struct mali_vertex_tiler_prefix
{
896 /* This is a dynamic bitfield containing the following things in this order:
898 * - gl_WorkGroupSize.x
899 * - gl_WorkGroupSize.y
900 * - gl_WorkGroupSize.z
901 * - gl_NumWorkGroups.x
902 * - gl_NumWorkGroups.y
903 * - gl_NumWorkGroups.z
905 * The number of bits allocated for each number is based on the *_shift
906 * fields below. For example, workgroups_y_shift gives the bit that
907 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
908 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
909 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
910 * value is one more than the stored value, since if any of the values
911 * are zero, then there would be no invocations (and hence no job). If
912 * there were 0 bits allocated to a given field, then it must be zero,
913 * and hence the real value is one.
915 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
916 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
917 * where vertex count is the number of vertices.
919 u32 invocation_count
;
921 /* Bitfield for shifts:
925 * workgroups_x_shift : 6
926 * workgroups_y_shift : 6
927 * workgroups_z_shift : 6
928 * workgroups_x_shift_2 : 4
930 u32 invocation_shifts
;
933 u32 unknown_draw
: 22;
935 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
936 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
937 * something to do with how many quads get put in the same execution
938 * engine, which is a balance (you don't want to starve the engine, but
939 * you also want to distribute work evenly).
941 u32 workgroups_x_shift_3
: 6;
944 /* Negative of min_index. This is used to compute
945 * the unbiased index in tiler/fragment shader runs.
947 * The hardware adds offset_bias_correction in each run,
948 * so that absent an index bias, the first vertex processed is
949 * genuinely the first vertex (0). But with an index bias,
950 * the first vertex process is numbered the same as the bias.
952 * To represent this more conviniently:
953 * unbiased_index = lower_bound_index +
955 * offset_bias_correction
957 * This is done since the hardware doesn't accept a index_bias
958 * and this allows it to recover the unbiased index.
960 int32_t offset_bias_correction
;
963 /* Like many other strictly nonzero quantities, index_count is
964 * subtracted by one. For an indexed cube, this is equal to 35 = 6
965 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
966 * for an indexed draw, index_count is the number of actual vertices
967 * rendered whereas invocation_count is the number of unique vertices
968 * rendered (the number of times the vertex shader must be invoked).
969 * For non-indexed draws, this is just equal to invocation_count. */
973 /* No hidden structure; literally just a pointer to an array of uint
974 * indices (width depends on flags). Thanks, guys, for not making my
975 * life insane for once! NULL for non-indexed draws. */
978 } __attribute__((packed
));
980 /* Point size / line width can either be specified as a 32-bit float (for
981 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
982 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
983 * payload, the contents of varying_pointer will be intepreted as an array of
984 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
985 * creating a special MALI_R16F varying writing to varying_pointer. */
987 union midgard_primitive_size
{
992 struct bifrost_vertex_only
{
998 } __attribute__((packed
));
1000 struct bifrost_tiler_heap_meta
{
1003 /* note: these are just guesses! */
1004 mali_ptr tiler_heap_start
;
1005 mali_ptr tiler_heap_free
;
1006 mali_ptr tiler_heap_end
;
1008 /* hierarchy weights? but they're still 0 after the job has run... */
1010 } __attribute__((packed
));
1012 struct bifrost_tiler_meta
{
1019 mali_ptr tiler_heap_meta
;
1020 /* TODO what is this used for? */
1022 } __attribute__((packed
));
1024 struct bifrost_tiler_only
{
1026 union midgard_primitive_size primitive_size
;
1028 mali_ptr tiler_meta
;
1030 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1035 } __attribute__((packed
));
1037 struct bifrost_scratchpad
{
1039 u32 flags
; // = 0x1f
1040 /* This is a pointer to a CPU-inaccessible buffer, 16 pages, allocated
1041 * during startup. It seems to serve the same purpose as the
1042 * gpu_scratchpad in the SFBD for Midgard, although it's slightly
1045 mali_ptr gpu_scratchpad
;
1046 } __attribute__((packed
));
1048 struct mali_vertex_tiler_postfix
{
1049 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1050 * output from the vertex shader for tiler jobs.
1053 u64 position_varying
;
1055 /* An array of mali_uniform_buffer_meta's. The size is given by the
1058 u64 uniform_buffers
;
1060 /* This is a pointer to an array of pointers to the texture
1061 * descriptors, number of pointers bounded by number of textures. The
1062 * indirection is needed to accomodate varying numbers and sizes of
1063 * texture descriptors */
1064 u64 texture_trampoline
;
1066 /* For OpenGL, from what I've seen, this is intimately connected to
1067 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1068 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1069 * array of sampler descriptors (which are uniform in size) */
1070 u64 sampler_descriptor
;
1074 u64 attributes
; /* struct attribute_buffer[] */
1075 u64 attribute_meta
; /* attribute_meta[] */
1076 u64 varyings
; /* struct attr */
1077 u64 varying_meta
; /* pointer */
1079 u64 occlusion_counter
; /* A single bit as far as I can tell */
1081 /* Note: on Bifrost, this isn't actually the FBD. It points to
1082 * bifrost_scratchpad instead. However, it does point to the same thing
1083 * in vertex and tiler jobs.
1085 mali_ptr framebuffer
;
1086 } __attribute__((packed
));
1088 struct midgard_payload_vertex_tiler
{
1089 struct mali_vertex_tiler_prefix prefix
;
1091 u16 gl_enables
; // 0x5
1093 /* Both zero for non-instanced draws. For instanced draws, a
1094 * decomposition of padded_num_vertices. See the comments about the
1095 * corresponding fields in mali_attr for context. */
1097 unsigned instance_shift
: 5;
1098 unsigned instance_odd
: 3;
1102 /* Offset for first vertex in buffer */
1107 struct mali_vertex_tiler_postfix postfix
;
1109 union midgard_primitive_size primitive_size
;
1110 } __attribute__((packed
));
1112 struct bifrost_payload_vertex
{
1113 struct mali_vertex_tiler_prefix prefix
;
1114 struct bifrost_vertex_only vertex
;
1115 struct mali_vertex_tiler_postfix postfix
;
1116 } __attribute__((packed
));
1118 struct bifrost_payload_tiler
{
1119 struct mali_vertex_tiler_prefix prefix
;
1120 struct bifrost_tiler_only tiler
;
1121 struct mali_vertex_tiler_postfix postfix
;
1122 } __attribute__((packed
));
1124 struct bifrost_payload_fused
{
1125 struct mali_vertex_tiler_prefix prefix
;
1126 struct bifrost_tiler_only tiler
;
1127 struct mali_vertex_tiler_postfix tiler_postfix
;
1128 u64 padding
; /* zero */
1129 struct bifrost_vertex_only vertex
;
1130 struct mali_vertex_tiler_postfix vertex_postfix
;
1131 } __attribute__((packed
));
1133 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1134 * texture is stored as (63, 63) in these fields. This adjusts for that.
1135 * There's an identical pattern in the framebuffer descriptor. Even vertex
1136 * count fields work this way, hence the generic name -- integral fields that
1137 * are strictly positive generally need this adjustment. */
1139 #define MALI_POSITIVE(dim) (dim - 1)
1141 /* Used with wrapping. Unclear what top bit conveys */
1143 enum mali_wrap_mode
{
1144 MALI_WRAP_REPEAT
= 0x8 | 0x0,
1145 MALI_WRAP_CLAMP_TO_EDGE
= 0x8 | 0x1,
1146 MALI_WRAP_CLAMP
= 0x8 | 0x2,
1147 MALI_WRAP_CLAMP_TO_BORDER
= 0x8 | 0x3,
1148 MALI_WRAP_MIRRORED_REPEAT
= 0x8 | 0x4 | 0x0,
1149 MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
= 0x8 | 0x4 | 0x1,
1150 MALI_WRAP_MIRRORED_CLAMP
= 0x8 | 0x4 | 0x2,
1151 MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
= 0x8 | 0x4 | 0x3,
1154 /* Shared across both command stream and Midgard, and even with Bifrost */
1156 enum mali_texture_type
{
1157 MALI_TEX_CUBE
= 0x0,
1164 #define MAX_MIP_LEVELS (13)
1166 /* Cubemap bloats everything up */
1167 #define MAX_CUBE_FACES (6)
1169 /* For each pointer, there is an address and optionally also a stride */
1170 #define MAX_ELEMENTS (2)
1172 /* It's not known why there are 4-bits allocated -- this enum is almost
1173 * certainly incomplete */
1175 enum mali_texture_layout
{
1176 /* For a Z/S texture, this is linear */
1177 MALI_TEXTURE_TILED
= 0x1,
1179 /* Z/S textures cannot be tiled */
1180 MALI_TEXTURE_LINEAR
= 0x2,
1183 MALI_TEXTURE_AFBC
= 0xC
1186 /* Corresponds to the type passed to glTexImage2D and so forth */
1188 struct mali_texture_format
{
1189 unsigned swizzle
: 12;
1190 enum mali_format format
: 8;
1193 unsigned unknown1
: 1;
1195 enum mali_texture_type type
: 2;
1196 enum mali_texture_layout layout
: 4;
1199 unsigned unknown2
: 1;
1201 /* Set to allow packing an explicit stride */
1202 unsigned manual_stride
: 1;
1205 } __attribute__((packed
));
1207 struct mali_texture_descriptor
{
1211 uint16_t array_size
;
1213 struct mali_texture_format format
;
1217 /* One for non-mipmapped, zero for mipmapped */
1220 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1223 /* Swizzling is a single 32-bit word, broken up here for convenience.
1224 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1225 * level swizzling, not the internal pixel-level swizzling which is
1226 * below OpenGL's reach */
1228 unsigned swizzle
: 12;
1229 unsigned swizzle_zero
: 20;
1235 mali_ptr payload
[MAX_MIP_LEVELS
* MAX_CUBE_FACES
* MAX_ELEMENTS
];
1236 } __attribute__((packed
));
1240 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1241 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1243 /* TODO: What do these bits mean individually? Only seen set together */
1245 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1246 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1248 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1249 * sampler_t flag. For typical OpenGL textures, this is always set. */
1251 #define MALI_SAMP_NORM_COORDS (1 << 5)
1253 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1254 * be cleaned up a lot. */
1256 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1258 static inline uint16_t
1261 /* Clamp inputs, accounting for float error */
1262 float max_lod
= (32.0 - (1.0 / 512.0));
1264 x
= ((x
> max_lod
) ? max_lod
: ((x
< 0.0) ? 0.0 : x
));
1266 return (int) (x
* 256.0);
1269 struct mali_sampler_descriptor
{
1270 uint16_t filter_mode
;
1272 /* Fixed point. Upper 8-bits is before the decimal point, although it
1273 * caps [0-31]. Lower 8-bits is after the decimal point: int(round(x *
1280 /* All one word in reality, but packed a bit. Comparisons are flipped
1283 enum mali_wrap_mode wrap_s
: 4;
1284 enum mali_wrap_mode wrap_t
: 4;
1285 enum mali_wrap_mode wrap_r
: 4;
1286 enum mali_func compare_func
: 3;
1288 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1289 * ES2, controlling seamless cubemapping */
1290 unsigned seamless_cube_map
: 1;
1295 float border_color
[4];
1296 } __attribute__((packed
));
1298 /* viewport0/viewport1 form the arguments to glViewport. viewport1 is
1299 * modified by MALI_POSITIVE; viewport0 is as-is.
1302 struct mali_viewport
{
1303 /* XY clipping planes */
1309 /* Depth clipping planes */
1315 } __attribute__((packed
));
1317 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1318 * of tile numbers. */
1320 #define MALI_TILE_SHIFT 4
1321 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1323 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1324 * each component. Notice that this provides a theoretical upper bound of (1 <<
1325 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1326 * 65536x65536. Multiplying that together, times another four given that Mali
1327 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1328 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1329 * alone rendering in real-time to such a buffer.
1333 /* From mali_kbase_10969_workaround.c */
1334 #define MALI_X_COORD_MASK 0x00000FFF
1335 #define MALI_Y_COORD_MASK 0x0FFF0000
1337 /* Extract parts of a tile coordinate */
1339 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1340 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1342 /* Helpers to generate tile coordinates based on the boundary coordinates in
1343 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1344 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1345 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1348 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1349 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1350 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1351 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1352 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1354 struct mali_payload_fragment
{
1357 mali_ptr framebuffer
;
1358 } __attribute__((packed
));
1360 /* Single Framebuffer Descriptor */
1362 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1363 * configured for 4x. With MSAA_8, it is configured for 8x. */
1365 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1366 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1367 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1368 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1370 /* Fast/slow based on whether all three buffers are cleared at once */
1372 #define MALI_CLEAR_FAST (1 << 18)
1373 #define MALI_CLEAR_SLOW (1 << 28)
1374 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1376 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1377 * within the larget framebuffer descriptor). Analogous to
1378 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1380 /* See pan_tiler.c for derivation */
1381 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1383 /* Flag disabling the tiler for clear-only jobs, with
1384 hierarchical tiling */
1385 #define MALI_TILER_DISABLED (1 << 12)
1387 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1388 * hierarhical tiling. */
1389 #define MALI_TILER_USER 0xFFF
1391 /* Absent any geometry, the minimum size of the polygon list header */
1392 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1394 struct midgard_tiler_descriptor
{
1395 /* Size of the entire polygon list; see pan_tiler.c for the
1396 * computation. It's based on hierarchical tiling */
1398 u32 polygon_list_size
;
1400 /* Name known from the replay workaround in the kernel. What exactly is
1401 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1402 * specifies a mask of hierarchy weights, which explains some of the
1403 * performance mysteries around setting it. We also see the bottom bit
1404 * of tiler_flags set in the kernel, but no comment why.
1406 * hierarchy_mask can have the TILER_DISABLED flag */
1411 /* See mali_tiler.c for an explanation */
1412 mali_ptr polygon_list
;
1413 mali_ptr polygon_list_body
;
1415 /* Names based on we see symmetry with replay jobs which name these
1418 mali_ptr heap_start
; /* tiler heap_free_address */
1421 /* Hierarchy weights. We know these are weights based on the kernel,
1422 * but I've never seen them be anything other than zero */
1426 enum mali_block_format
{
1427 MALI_BLOCK_TILED
= 0x0,
1428 MALI_BLOCK_UNKNOWN
= 0x1,
1429 MALI_BLOCK_LINEAR
= 0x2,
1430 MALI_BLOCK_AFBC
= 0x3,
1433 struct mali_sfbd_format
{
1437 /* mali_channel_swizzle */
1438 unsigned swizzle
: 12;
1441 unsigned nr_channels
: 2;
1446 enum mali_block_format block
: 2;
1452 struct mali_single_framebuffer
{
1455 mali_ptr scratchpad
;
1460 struct mali_sfbd_format format
;
1465 /* Purposeful off-by-one in these fields should be accounted for by the
1466 * MALI_DIMENSION macro */
1473 u32 checksum_stride
;
1476 /* By default, the framebuffer is upside down from OpenGL's
1477 * perspective. Set framebuffer to the end and negate the stride to
1478 * flip in the Y direction */
1480 mali_ptr framebuffer
;
1485 /* Depth and stencil buffers are interleaved, it appears, as they are
1486 * set to the same address in captures. Both fields set to zero if the
1487 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1488 * get a zero enable despite the buffer being present; that still is
1491 mali_ptr depth_buffer
; // not SAME_VA
1492 u32 depth_stride_zero
: 4;
1493 u32 depth_stride
: 28;
1496 mali_ptr stencil_buffer
; // not SAME_VA
1497 u32 stencil_stride_zero
: 4;
1498 u32 stencil_stride
: 28;
1501 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1502 u32 clear_color_2
; // always equal, but unclear function?
1503 u32 clear_color_3
; // always equal, but unclear function?
1504 u32 clear_color_4
; // always equal, but unclear function?
1506 /* Set to zero if not cleared */
1508 float clear_depth_1
; // float32, ditto
1509 float clear_depth_2
; // float32, ditto
1510 float clear_depth_3
; // float32, ditto
1511 float clear_depth_4
; // float32, ditto
1513 u32 clear_stencil
; // Exactly as it appears in OpenGL
1517 struct midgard_tiler_descriptor tiler
;
1519 /* More below this, maybe */
1520 } __attribute__((packed
));
1522 /* On Midgard, this "framebuffer descriptor" is used for the framebuffer field
1523 * of compute jobs. Superficially resembles a single framebuffer descriptor */
1525 struct mali_compute_fbd
{
1527 } __attribute__((packed
));
1529 /* Format bits for the render target flags */
1531 #define MALI_MFBD_FORMAT_MSAA (1 << 1)
1532 #define MALI_MFBD_FORMAT_SRGB (1 << 2)
1534 struct mali_rt_format
{
1538 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1541 enum mali_block_format block
: 2;
1544 unsigned swizzle
: 12;
1548 /* Disables MFBD preload. When this bit is set, the render target will
1549 * be cleared every frame. When this bit is clear, the hardware will
1550 * automatically wallpaper the render target back from main memory.
1551 * Unfortunately, MFBD preload is very broken on Midgard, so in
1552 * practice, this is a chicken bit that should always be set.
1553 * Discovered by accident, as all good chicken bits are. */
1555 unsigned no_preload
: 1;
1556 } __attribute__((packed
));
1558 struct bifrost_render_target
{
1559 struct mali_rt_format format
;
1564 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1565 * there is an extra metadata buffer that contains 16 bytes per tile.
1566 * The framebuffer needs to be the same size as before, since we don't
1567 * know ahead of time how much space it will take up. The
1568 * framebuffer_stride is set to 0, since the data isn't stored linearly
1571 * When AFBC is disabled, these fields are zero.
1575 u32 stride
; // stride in units of tiles
1576 u32 unk
; // = 0x20000
1579 mali_ptr framebuffer
;
1582 u32 framebuffer_stride
: 28; // in units of bytes
1585 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1586 u32 clear_color_2
; // always equal, but unclear function?
1587 u32 clear_color_3
; // always equal, but unclear function?
1588 u32 clear_color_4
; // always equal, but unclear function?
1589 } __attribute__((packed
));
1591 /* An optional part of bifrost_framebuffer. It comes between the main structure
1592 * and the array of render targets. It must be included if any of these are
1595 * - Transaction Elimination
1597 * - TODO: Anything else?
1600 /* Flags field: note, these are guesses */
1602 #define MALI_EXTRA_PRESENT (0x400)
1603 #define MALI_EXTRA_AFBC (0x20)
1604 #define MALI_EXTRA_AFBC_ZS (0x10)
1605 #define MALI_EXTRA_ZS (0x4)
1607 struct bifrost_fb_extra
{
1609 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1610 u32 checksum_stride
;
1615 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1617 mali_ptr depth_stencil_afbc_metadata
;
1618 u32 depth_stencil_afbc_stride
; // in units of tiles
1621 mali_ptr depth_stencil
;
1627 /* Depth becomes depth/stencil in case of combined D/S */
1629 u32 depth_stride_zero
: 4;
1630 u32 depth_stride
: 28;
1634 u32 stencil_stride_zero
: 4;
1635 u32 stencil_stride
: 28;
1642 } __attribute__((packed
));
1644 /* Flags for mfbd_flags */
1646 /* Enables writing depth results back to main memory (rather than keeping them
1647 * on-chip in the tile buffer and then discarding) */
1649 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1651 /* The MFBD contains the extra bifrost_fb_extra section */
1653 #define MALI_MFBD_EXTRA (1 << 13)
1655 struct bifrost_framebuffer
{
1656 u32 stack_shift
: 4;
1659 u32 unknown2
; // = 0x1f, same as SFBD
1660 mali_ptr scratchpad
;
1663 mali_ptr sample_locations
;
1666 u16 width1
, height1
;
1668 u16 width2
, height2
;
1669 u32 unk1
: 19; // = 0x01000
1670 u32 rt_count_1
: 2; // off-by-one (use MALI_POSITIVE)
1671 u32 unk2
: 3; // = 0
1672 u32 rt_count_2
: 3; // no off-by-one
1675 u32 clear_stencil
: 8;
1676 u32 mfbd_flags
: 24; // = 0x100
1679 struct midgard_tiler_descriptor tiler
;
1681 /* optional: struct bifrost_fb_extra extra */
1682 /* struct bifrost_render_target rts[] */
1683 } __attribute__((packed
));
1685 #endif /* __PANFROST_JOB_H__ */