src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src[3];
  75         int dest;
  76
  77         bool inline_constant;
  78 } ssa_args;
  79
  80 /* Generic in-memory data type repesenting a single logical instruction, rather
  81  * than a single instruction group. This is the preferred form for code gen.
  82  * Multiple midgard_insturctions will later be combined during scheduling,
  83  * though this is not represented in this structure.  Its format bridges
  84  * the low-level binary representation with the higher level semantic meaning.
  85  *
  86  * Notably, it allows registers to be specified as block local SSA, for code
  87  * emitted before the register allocation pass.
  88  */
  89
  90 typedef struct midgard_instruction {
  91         /* Must be first for casting */
  92         struct list_head link;
  93
  94         unsigned type; /* ALU, load/store, texture */
  95
  96         /* If the register allocator has not run yet... */
  97         ssa_args ssa_args;
  98
  99         /* Special fields for an ALU instruction */
 100         midgard_reg_info registers;
 101
 102         /* I.e. (1 << alu_bit) */
 103         int unit;
 104
 105         /* When emitting bundle, should this instruction have a break forced
 106          * before it? Used for r31 writes which are valid only within a single
 107          * bundle and *need* to happen as early as possible... this is a hack,
 108          * TODO remove when we have a scheduler */
 109         bool precede_break;
 110
 111         bool has_constants;
 112         float constants[4];
 113         uint16_t inline_constant;
 114         bool has_blend_constant;
 115
 116         bool compact_branch;
 117         bool writeout;
 118         bool prepacked_branch;
 119
 120         /* Masks in a saneish format. One bit per channel, not packed fancy.
 121          * Use this instead of the op specific ones, and switch over at emit
 122          * time */
 123
 124         uint16_t mask;
 125
 126         /* For ALU ops only: set to true to invert (bitwise NOT) the
 127          * destination of an integer-out op. Not imeplemented in hardware but
 128          * allows more optimizations */
 129
 130         bool invert;
 131
 132         union {
 133                 midgard_load_store_word load_store;
 134                 midgard_vector_alu alu;
 135                 midgard_texture_word texture;
 136                 midgard_branch_extended branch_extended;
 137                 uint16_t br_compact;
 138
 139                 /* General branch, rather than packed br_compact. Higher level
 140                  * than the other components */
 141                 midgard_branch branch;
 142         };
 143 } midgard_instruction;
 144
 145 typedef struct midgard_block {
 146         /* Link to next block. Must be first for mir_get_block */
 147         struct list_head link;
 148
 149         /* List of midgard_instructions emitted for the current block */
 150         struct list_head instructions;
 151
 152         bool is_scheduled;
 153
 154         /* List of midgard_bundles emitted (after the scheduler has run) */
 155         struct util_dynarray bundles;
 156
 157         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 158         unsigned quadword_count;
 159
 160         /* Succeeding blocks. The compiler should not necessarily rely on
 161          * source-order traversal */
 162         struct midgard_block *successors[4];
 163         unsigned nr_successors;
 164
 165         /* The successors pointer form a graph, and in the case of
 166          * complex control flow, this graph has a cycles. To aid
 167          * traversal during liveness analysis, we have a visited?
 168          * boolean for passes to use as they see fit, provided they
 169          * clean up later */
 170         bool visited;
 171 } midgard_block;
 172
 173 typedef struct midgard_bundle {
 174         /* Tag for the overall bundle */
 175         int tag;
 176
 177         /* Instructions contained by the bundle */
 178         int instruction_count;
 179         midgard_instruction *instructions[5];
 180
 181         /* Bundle-wide ALU configuration */
 182         int padding;
 183         int control;
 184         bool has_embedded_constants;
 185         float constants[4];
 186         bool has_blend_constant;
 187 } midgard_bundle;
 188
 189 typedef struct compiler_context {
 190         nir_shader *nir;
 191         gl_shader_stage stage;
 192
 193         /* The screen we correspond to */
 194         struct midgard_screen *screen;
 195
 196         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 197         bool is_blend;
 198
 199         /* Tracking for blend constant patching */
 200         int blend_constant_offset;
 201
 202         /* Number of bytes used for Thread Local Storage */
 203         unsigned tls_size;
 204
 205         /* Count of spills and fills for shaderdb */
 206         unsigned spills;
 207         unsigned fills;
 208
 209         /* Current NIR function */
 210         nir_function *func;
 211
 212         /* Allocated compiler temporary counter */
 213         unsigned temp_alloc;
 214
 215         /* Unordered list of midgard_blocks */
 216         int block_count;
 217         struct list_head blocks;
 218
 219         /* List of midgard_instructions emitted for the current block */
 220         midgard_block *current_block;
 221
 222         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 223         midgard_block *after_block;
 224
 225         /* The current "depth" of the loop, for disambiguating breaks/continues
 226          * when using nested loops */
 227         int current_loop_depth;
 228
 229         /* Total number of loops for shader-db */
 230         unsigned loop_count;
 231
 232         /* Constants which have been loaded, for later inlining */
 233         struct hash_table_u64 *ssa_constants;
 234
 235         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 236         struct hash_table_u64 *hash_to_temp;
 237         int temp_count;
 238         int max_hash;
 239
 240         /* Just the count of the max register used. Higher count => higher
 241          * register pressure */
 242         int work_registers;
 243
 244         /* Used for cont/last hinting. Increase when a tex op is added.
 245          * Decrease when a tex op is removed. */
 246         int texture_op_count;
 247
 248         /* Mapping of texture register -> SSA index for unaliasing */
 249         int texture_index[2];
 250
 251         /* The number of uniforms allowable for the fast path */
 252         int uniform_cutoff;
 253
 254         /* Count of instructions emitted from NIR overall, across all blocks */
 255         int instruction_count;
 256
 257         /* Alpha ref value passed in */
 258         float alpha_ref;
 259
 260         /* The index corresponding to the fragment output */
 261         unsigned fragment_output;
 262
 263         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 264         unsigned sysvals[MAX_SYSVAL_COUNT];
 265         unsigned sysval_count;
 266         struct hash_table_u64 *sysval_to_id;
 267 } compiler_context;
 268
 269 /* Helpers for manipulating the above structures (forming the driver IR) */
 270
 271 /* Append instruction to end of current block */
 272
 273 static inline midgard_instruction *
 274 mir_upload_ins(struct midgard_instruction ins)
 275 {
 276         midgard_instruction *heap = malloc(sizeof(ins));
 277         memcpy(heap, &ins, sizeof(ins));
 278         return heap;
 279 }
 280
 281 static inline void
 282 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 283 {
 284         list_addtail(&(mir_upload_ins(ins))->link, &ctx->current_block->instructions);
 285 }
 286
 287 static inline struct midgard_instruction *
 288 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 289 {
 290         struct midgard_instruction *u = mir_upload_ins(ins);
 291         list_addtail(&u->link, &tag->link);
 292         return u;
 293 }
 294
 295 static inline void
 296 mir_remove_instruction(struct midgard_instruction *ins)
 297 {
 298         list_del(&ins->link);
 299 }
 300
 301 static inline midgard_instruction*
 302 mir_prev_op(struct midgard_instruction *ins)
 303 {
 304         return list_last_entry(&(ins->link), midgard_instruction, link);
 305 }
 306
 307 static inline midgard_instruction*
 308 mir_next_op(struct midgard_instruction *ins)
 309 {
 310         return list_first_entry(&(ins->link), midgard_instruction, link);
 311 }
 312
 313 #define mir_foreach_block(ctx, v) \
 314         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 315
 316 #define mir_foreach_block_from(ctx, from, v) \
 317         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 318
 319 #define mir_foreach_instr(ctx, v) \
 320         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 321
 322 #define mir_foreach_instr_safe(ctx, v) \
 323         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 324
 325 #define mir_foreach_instr_in_block(block, v) \
 326         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 327
 328 #define mir_foreach_instr_in_block_safe(block, v) \
 329         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 330
 331 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 332         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 333
 334 #define mir_foreach_instr_in_block_from(block, v, from) \
 335         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 336
 337 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 338         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 339
 340 #define mir_foreach_bundle_in_block(block, v) \
 341         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 342
 343 #define mir_foreach_instr_global(ctx, v) \
 344         mir_foreach_block(ctx, v_block) \
 345                 mir_foreach_instr_in_block(v_block, v)
 346
 347 #define mir_foreach_instr_global_safe(ctx, v) \
 348         mir_foreach_block(ctx, v_block) \
 349                 mir_foreach_instr_in_block_safe(v_block, v)
 350
 351 static inline midgard_instruction *
 352 mir_last_in_block(struct midgard_block *block)
 353 {
 354         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 355 }
 356
 357 static inline midgard_block *
 358 mir_get_block(compiler_context *ctx, int idx)
 359 {
 360         struct list_head *lst = &ctx->blocks;
 361
 362         while ((idx--) + 1)
 363                 lst = lst->next;
 364
 365         return (struct midgard_block *) lst;
 366 }
 367
 368 static inline bool
 369 mir_is_alu_bundle(midgard_bundle *bundle)
 370 {
 371         return IS_ALU(bundle->tag);
 372 }
 373
 374 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 375
 376 #define IS_REG (1)
 377
 378 static inline unsigned
 379 make_compiler_temp(compiler_context *ctx)
 380 {
 381         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 382 }
 383
 384 static inline unsigned
 385 make_compiler_temp_reg(compiler_context *ctx)
 386 {
 387         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 388 }
 389
 390 static inline unsigned
 391 nir_src_index(compiler_context *ctx, nir_src *src)
 392 {
 393         if (src->is_ssa)
 394                 return (src->ssa->index << 1) | 0;
 395         else {
 396                 assert(!src->reg.indirect);
 397                 return (src->reg.reg->index << 1) | IS_REG;
 398         }
 399 }
 400
 401 static inline unsigned
 402 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 403 {
 404         return nir_src_index(ctx, &src->src);
 405 }
 406
 407 static inline unsigned
 408 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 409 {
 410         if (dst->is_ssa)
 411                 return (dst->ssa.index << 1) | 0;
 412         else {
 413                 assert(!dst->reg.indirect);
 414                 return (dst->reg.reg->index << 1) | IS_REG;
 415         }
 416 }
 417
 418
 419
 420 /* MIR manipulation */
 421
 422 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 423 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 424 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 425 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 426 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 427 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 428 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 429 bool mir_single_use(compiler_context *ctx, unsigned value);
 430 bool mir_special_index(compiler_context *ctx, unsigned idx);
 431 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 432 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 433 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 434
 435 /* MIR printing */
 436
 437 void mir_print_instruction(midgard_instruction *ins);
 438 void mir_print_bundle(midgard_bundle *ctx);
 439 void mir_print_block(midgard_block *block);
 440 void mir_print_shader(compiler_context *ctx);
 441 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 442 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 443 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 444 bool mir_nontrivial_outmod(midgard_instruction *ins);
 445
 446 /* MIR goodies */
 447
 448 static const midgard_vector_alu_src blank_alu_src = {
 449         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 450 };
 451
 452 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 453         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 454 };
 455
 456 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 457         .full = true
 458 };
 459
 460 /* Used for encoding the unused source of 1-op instructions */
 461 static const midgard_vector_alu_src zero_alu_src = { 0 };
 462
 463 /* 'Intrinsic' move for aliasing */
 464
 465 static inline midgard_instruction
 466 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 467 {
 468         midgard_instruction ins = {
 469                 .type = TAG_ALU_4,
 470                 .mask = 0xF,
 471                 .ssa_args = {
 472                         .src = { SSA_UNUSED_1, src, -1 },
 473                         .dest = dest,
 474                 },
 475                 .alu = {
 476                         .op = midgard_alu_op_imov,
 477                         .reg_mode = midgard_reg_mode_32,
 478                         .dest_override = midgard_dest_override_none,
 479                         .outmod = midgard_outmod_int_wrap,
 480                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 481                         .src2 = vector_alu_srco_unsigned(mod)
 482                 },
 483         };
 484
 485         return ins;
 486 }
 487
 488 static inline bool
 489 mir_has_arg(midgard_instruction *ins, unsigned arg)
 490 {
 491         for (unsigned i = 0; i < ARRAY_SIZE(ins->ssa_args.src); ++i) {
 492                 if (ins->ssa_args.src[i] == arg)
 493                         return true;
 494         }
 495
 496         return false;
 497 }
 498
 499 /* Scheduling */
 500
 501 void schedule_program(compiler_context *ctx);
 502
 503 /* Register allocation */
 504
 505 struct ra_graph;
 506
 507 /* Broad types of register classes so we can handle special
 508  * registers */
 509
 510 #define NR_REG_CLASSES 5
 511
 512 #define REG_CLASS_WORK          0
 513 #define REG_CLASS_LDST          1
 514 #define REG_CLASS_LDST27        2
 515 #define REG_CLASS_TEXR          3
 516 #define REG_CLASS_TEXW          4
 517
 518 void mir_lower_special_reads(compiler_context *ctx);
 519 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 520 void install_registers(compiler_context *ctx, struct ra_graph *g);
 521 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 522 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 523
 524 void mir_create_pipeline_registers(compiler_context *ctx);
 525
 526 void
 527 midgard_promote_uniforms(compiler_context *ctx, unsigned pressure);
 528
 529 void
 530 emit_ubo_read(
 531         compiler_context *ctx,
 532         unsigned dest,
 533         unsigned offset,
 534         nir_src *indirect_offset,
 535         unsigned index);
 536
 537 void
 538 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 539
 540 void
 541 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 542
 543 bool mir_op_computes_derivatives(unsigned op);
 544
 545 /* Final emission */
 546
 547 void emit_binary_bundle(
 548         compiler_context *ctx,
 549         midgard_bundle *bundle,
 550         struct util_dynarray *emission,
 551         int next_tag);
 552
 553 /* NIR stuff. TODO: Move? Share? Something? */
 554
 555 bool
 556 nir_undef_to_zero(nir_shader *shader);
 557
 558 void
 559 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 560
 561 /* Optimizations */
 562
 563 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 564 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 565 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 566 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 567 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 568 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 569
 570 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 571 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 572 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 573 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 574
 575 #endif