src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31
  32 #include "util/hash_table.h"
  33 #include "util/u_dynarray.h"
  34 #include "util/set.h"
  35 #include "util/list.h"
  36
  37 #include "main/mtypes.h"
  38 #include "compiler/nir_types.h"
  39 #include "compiler/nir/nir.h"
  40 #include "panfrost/util/pan_ir.h"
  41 #include "panfrost/util/lcra.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Special fields for an ALU instruction */
 101         midgard_reg_info registers;
 102
 103         /* I.e. (1 << alu_bit) */
 104         int unit;
 105
 106         bool has_constants;
 107         midgard_constants constants;
 108         uint16_t inline_constant;
 109         bool has_blend_constant;
 110         bool has_inline_constant;
 111
 112         bool compact_branch;
 113         bool writeout;
 114         bool writeout_depth;
 115         bool writeout_stencil;
 116         bool last_writeout;
 117
 118         /* Masks in a saneish format. One bit per channel, not packed fancy.
 119          * Use this instead of the op specific ones, and switch over at emit
 120          * time */
 121
 122         uint16_t mask;
 123
 124         /* For ALU ops only: set to true to invert (bitwise NOT) the
 125          * destination of an integer-out op. Not implemented in hardware but
 126          * allows more optimizations */
 127
 128         bool invert;
 129
 130         /* Hint for the register allocator not to spill the destination written
 131          * from this instruction (because it is a spill/unspill node itself).
 132          * Bitmask of spilled classes */
 133
 134         unsigned no_spill;
 135
 136         /* Generic hint for intra-pass use */
 137         bool hint;
 138
 139         /* During scheduling, the backwards dependency graph
 140          * (DAG). nr_dependencies is the number of unscheduled
 141          * instructions that must still be scheduled after
 142          * (before) this instruction. dependents are which
 143          * instructions need to be scheduled before (after) this
 144          * instruction. */
 145
 146         unsigned nr_dependencies;
 147         BITSET_WORD *dependents;
 148
 149         /* For load/store ops.. force 64-bit destination */
 150         bool load_64;
 151
 152         union {
 153                 midgard_load_store_word load_store;
 154                 midgard_vector_alu alu;
 155                 midgard_texture_word texture;
 156                 midgard_branch_extended branch_extended;
 157                 uint16_t br_compact;
 158
 159                 /* General branch, rather than packed br_compact. Higher level
 160                  * than the other components */
 161                 midgard_branch branch;
 162         };
 163 } midgard_instruction;
 164
 165 typedef struct midgard_block {
 166         pan_block base;
 167
 168         bool scheduled;
 169
 170         /* List of midgard_bundles emitted (after the scheduler has run) */
 171         struct util_dynarray bundles;
 172
 173         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 174         unsigned quadword_count;
 175
 176         /* Indicates this is a fixed-function fragment epilogue block */
 177         bool epilogue;
 178 } midgard_block;
 179
 180 typedef struct midgard_bundle {
 181         /* Tag for the overall bundle */
 182         int tag;
 183
 184         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 185          * sadd, vadd, smul, vlut, branch) */
 186         int instruction_count;
 187         midgard_instruction *instructions[6];
 188
 189         /* Bundle-wide ALU configuration */
 190         int padding;
 191         int control;
 192         bool has_embedded_constants;
 193         midgard_constants constants;
 194         bool has_blend_constant;
 195         bool last_writeout;
 196 } midgard_bundle;
 197
 198 enum midgard_rt_id {
 199         MIDGARD_COLOR_RT0,
 200         MIDGARD_COLOR_RT1,
 201         MIDGARD_COLOR_RT2,
 202         MIDGARD_COLOR_RT3,
 203         MIDGARD_ZS_RT,
 204         MIDGARD_NUM_RTS,
 205 };
 206
 207 typedef struct compiler_context {
 208         nir_shader *nir;
 209         gl_shader_stage stage;
 210
 211         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 212         bool is_blend;
 213
 214         /* Render target number for a keyed blend shader. Depends on is_blend */
 215         unsigned blend_rt;
 216
 217         /* Tracking for blend constant patching */
 218         int blend_constant_offset;
 219
 220         /* Number of bytes used for Thread Local Storage */
 221         unsigned tls_size;
 222
 223         /* Count of spills and fills for shaderdb */
 224         unsigned spills;
 225         unsigned fills;
 226
 227         /* Current NIR function */
 228         nir_function *func;
 229
 230         /* Allocated compiler temporary counter */
 231         unsigned temp_alloc;
 232
 233         /* Unordered list of midgard_blocks */
 234         int block_count;
 235         struct list_head blocks;
 236
 237         /* TODO merge with block_count? */
 238         unsigned block_source_count;
 239
 240         /* List of midgard_instructions emitted for the current block */
 241         midgard_block *current_block;
 242
 243         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 244         midgard_block *after_block;
 245
 246         /* The current "depth" of the loop, for disambiguating breaks/continues
 247          * when using nested loops */
 248         int current_loop_depth;
 249
 250         /* Total number of loops for shader-db */
 251         unsigned loop_count;
 252
 253         /* Constants which have been loaded, for later inlining */
 254         struct hash_table_u64 *ssa_constants;
 255
 256         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 257         struct hash_table_u64 *hash_to_temp;
 258         int temp_count;
 259         int max_hash;
 260
 261         /* Just the count of the max register used. Higher count => higher
 262          * register pressure */
 263         int work_registers;
 264
 265         /* Used for cont/last hinting. Increase when a tex op is added.
 266          * Decrease when a tex op is removed. */
 267         int texture_op_count;
 268
 269         /* The number of uniforms allowable for the fast path */
 270         int uniform_cutoff;
 271
 272         /* Count of instructions emitted from NIR overall, across all blocks */
 273         int instruction_count;
 274
 275         /* Alpha ref value passed in */
 276         float alpha_ref;
 277
 278         unsigned quadword_count;
 279
 280         /* Bitmask of valid metadata */
 281         unsigned metadata;
 282
 283         /* Model-specific quirk set */
 284         uint32_t quirks;
 285
 286         /* Writeout instructions for each render target */
 287         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 288
 289         struct panfrost_sysvals sysvals;
 290 } compiler_context;
 291
 292 /* Per-block live_in/live_out */
 293 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 294
 295 /* Helpers for manipulating the above structures (forming the driver IR) */
 296
 297 /* Append instruction to end of current block */
 298
 299 static inline midgard_instruction *
 300 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 301 {
 302         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 303         memcpy(heap, &ins, sizeof(ins));
 304         return heap;
 305 }
 306
 307 static inline midgard_instruction *
 308 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 309 {
 310         midgard_instruction *u = mir_upload_ins(ctx, ins);
 311         list_addtail(&u->link, &ctx->current_block->base.instructions);
 312         return u;
 313 }
 314
 315 static inline struct midgard_instruction *
 316 mir_insert_instruction_before(struct compiler_context *ctx,
 317                               struct midgard_instruction *tag,
 318                               struct midgard_instruction ins)
 319 {
 320         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 321         list_addtail(&u->link, &tag->link);
 322         return u;
 323 }
 324
 325 static inline void
 326 mir_remove_instruction(struct midgard_instruction *ins)
 327 {
 328         list_del(&ins->link);
 329 }
 330
 331 static inline midgard_instruction*
 332 mir_prev_op(struct midgard_instruction *ins)
 333 {
 334         return list_last_entry(&(ins->link), midgard_instruction, link);
 335 }
 336
 337 static inline midgard_instruction*
 338 mir_next_op(struct midgard_instruction *ins)
 339 {
 340         return list_first_entry(&(ins->link), midgard_instruction, link);
 341 }
 342
 343 #define mir_foreach_block(ctx, v) \
 344         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 345
 346 #define mir_foreach_block_from(ctx, from, v) \
 347         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 348
 349 #define mir_foreach_instr_in_block(block, v) \
 350         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 351 #define mir_foreach_instr_in_block_rev(block, v) \
 352         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 353
 354 #define mir_foreach_instr_in_block_safe(block, v) \
 355         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 356
 357 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 358         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 359
 360 #define mir_foreach_instr_in_block_from(block, v, from) \
 361         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 362
 363 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 364         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 365
 366 #define mir_foreach_bundle_in_block(block, v) \
 367         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 368
 369 #define mir_foreach_bundle_in_block_rev(block, v) \
 370         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 371
 372 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 373         midgard_instruction* v; \
 374         signed i = 0; \
 375         mir_foreach_bundle_in_block_rev(block, _bundle) \
 376                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 377                                 i >= 0; \
 378                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 379
 380 #define mir_foreach_instr_global(ctx, v) \
 381         mir_foreach_block(ctx, v_block) \
 382                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 383
 384 #define mir_foreach_instr_global_safe(ctx, v) \
 385         mir_foreach_block(ctx, v_block) \
 386                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 387
 388 /* Based on set_foreach, expanded with automatic type casts */
 389
 390 #define mir_foreach_predecessor(blk, v) \
 391         struct set_entry *_entry_##v; \
 392         struct midgard_block *v; \
 393         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 394                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 395                 _entry_##v != NULL; \
 396                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 397                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 398
 399 #define mir_foreach_src(ins, v) \
 400         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 401
 402 static inline midgard_instruction *
 403 mir_last_in_block(struct midgard_block *block)
 404 {
 405         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 406 }
 407
 408 static inline midgard_block *
 409 mir_get_block(compiler_context *ctx, int idx)
 410 {
 411         struct list_head *lst = &ctx->blocks;
 412
 413         while ((idx--) + 1)
 414                 lst = lst->next;
 415
 416         return (struct midgard_block *) lst;
 417 }
 418
 419 static inline bool
 420 mir_is_alu_bundle(midgard_bundle *bundle)
 421 {
 422         return IS_ALU(bundle->tag);
 423 }
 424
 425 static inline unsigned
 426 make_compiler_temp(compiler_context *ctx)
 427 {
 428         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 429 }
 430
 431 static inline unsigned
 432 make_compiler_temp_reg(compiler_context *ctx)
 433 {
 434         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 435 }
 436
 437 static inline unsigned
 438 nir_ssa_index(nir_ssa_def *ssa)
 439 {
 440         return (ssa->index << 1) | 0;
 441 }
 442
 443 static inline unsigned
 444 nir_src_index(compiler_context *ctx, nir_src *src)
 445 {
 446         if (src->is_ssa)
 447                 return nir_ssa_index(src->ssa);
 448         else {
 449                 assert(!src->reg.indirect);
 450                 return (src->reg.reg->index << 1) | PAN_IS_REG;
 451         }
 452 }
 453
 454 static inline unsigned
 455 nir_dest_index(nir_dest *dst)
 456 {
 457         if (dst->is_ssa)
 458                 return (dst->ssa.index << 1) | 0;
 459         else {
 460                 assert(!dst->reg.indirect);
 461                 return (dst->reg.reg->index << 1) | PAN_IS_REG;
 462         }
 463 }
 464
 465
 466
 467 /* MIR manipulation */
 468
 469 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 470 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 471 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 472 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 473 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 474 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 475 bool mir_single_use(compiler_context *ctx, unsigned value);
 476 bool mir_special_index(compiler_context *ctx, unsigned idx);
 477 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 478 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 479 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 480 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 481 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 482 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 483 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 484 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 485 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 486 uint16_t mir_bytemask(midgard_instruction *ins);
 487 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 488 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 489 unsigned mir_upper_override(midgard_instruction *ins);
 490
 491 /* MIR printing */
 492
 493 void mir_print_instruction(midgard_instruction *ins);
 494 void mir_print_bundle(midgard_bundle *ctx);
 495 void mir_print_block(midgard_block *block);
 496 void mir_print_shader(compiler_context *ctx);
 497 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 498 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 499 bool mir_nontrivial_outmod(midgard_instruction *ins);
 500
 501 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 502 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 503 void mir_flip(midgard_instruction *ins);
 504 void mir_compute_temp_count(compiler_context *ctx);
 505
 506 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 507
 508 /* 'Intrinsic' move for aliasing */
 509
 510 static inline midgard_instruction
 511 v_mov(unsigned src, unsigned dest)
 512 {
 513         midgard_instruction ins = {
 514                 .type = TAG_ALU_4,
 515                 .mask = 0xF,
 516                 .src = { ~0, src, ~0, ~0 },
 517                 .swizzle = SWIZZLE_IDENTITY,
 518                 .dest = dest,
 519                 .alu = {
 520                         .op = midgard_alu_op_imov,
 521                         .reg_mode = midgard_reg_mode_32,
 522                         .dest_override = midgard_dest_override_none,
 523                         .outmod = midgard_outmod_int_wrap
 524                 },
 525         };
 526
 527         return ins;
 528 }
 529
 530 /* Broad types of register classes so we can handle special
 531  * registers */
 532
 533 #define REG_CLASS_WORK          0
 534 #define REG_CLASS_LDST          1
 535 #define REG_CLASS_TEXR          3
 536 #define REG_CLASS_TEXW          4
 537
 538 /* Like a move, but to thread local storage! */
 539
 540 static inline midgard_instruction
 541 v_load_store_scratch(
 542                 unsigned srcdest,
 543                 unsigned index,
 544                 bool is_store,
 545                 unsigned mask)
 546 {
 547         /* We index by 32-bit vec4s */
 548         unsigned byte = (index * 4 * 4);
 549
 550         midgard_instruction ins = {
 551                 .type = TAG_LOAD_STORE_4,
 552                 .mask = mask,
 553                 .dest = ~0,
 554                 .src = { ~0, ~0, ~0, ~0 },
 555                 .swizzle = SWIZZLE_IDENTITY_4,
 556                 .load_store = {
 557                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 558
 559                         /* For register spilling - to thread local storage */
 560                         .arg_1 = 0xEA,
 561                         .arg_2 = 0x1E,
 562                 },
 563
 564                 /* If we spill an unspill, RA goes into an infinite loop */
 565                 .no_spill = (1 << REG_CLASS_WORK)
 566         };
 567
 568         ins.constants.u32[0] = byte;
 569
 570         if (is_store) {
 571                 ins.src[0] = srcdest;
 572
 573                 /* Ensure we are tightly swizzled so liveness analysis is
 574                  * correct */
 575
 576                 for (unsigned i = 0; i < 4; ++i) {
 577                         if (!(mask & (1 << i)))
 578                                 ins.swizzle[0][i] = COMPONENT_X;
 579                 }
 580         } else
 581                 ins.dest = srcdest;
 582
 583         return ins;
 584 }
 585
 586 static inline bool
 587 mir_has_arg(midgard_instruction *ins, unsigned arg)
 588 {
 589         if (!ins)
 590                 return false;
 591
 592         mir_foreach_src(ins, i) {
 593                 if (ins->src[i] == arg)
 594                         return true;
 595         }
 596
 597         return false;
 598 }
 599
 600 /* Scheduling */
 601
 602 void midgard_schedule_program(compiler_context *ctx);
 603
 604 void mir_ra(compiler_context *ctx);
 605 void mir_squeeze_index(compiler_context *ctx);
 606 void mir_lower_special_reads(compiler_context *ctx);
 607 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 608 void mir_compute_liveness(compiler_context *ctx);
 609 void mir_invalidate_liveness(compiler_context *ctx);
 610 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 611
 612 void mir_create_pipeline_registers(compiler_context *ctx);
 613 void midgard_promote_uniforms(compiler_context *ctx);
 614
 615 void
 616 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 617
 618 void
 619 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 620
 621 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 622
 623 /* Final emission */
 624
 625 void emit_binary_bundle(
 626         compiler_context *ctx,
 627         midgard_bundle *bundle,
 628         struct util_dynarray *emission,
 629         int next_tag);
 630
 631 bool
 632 nir_undef_to_zero(nir_shader *shader);
 633
 634 void midgard_nir_lod_errata(nir_shader *shader);
 635
 636 /* Optimizations */
 637
 638 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 639 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 640 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 641 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 642 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 643
 644 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 645 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 646 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 647 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 648 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 649 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 650 bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
 651 bool midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block);
 652
 653 #endif