src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31 #include "lcra.h"
  32
  33 #include "util/hash_table.h"
  34 #include "util/u_dynarray.h"
  35 #include "util/set.h"
  36 #include "util/list.h"
  37
  38 #include "main/mtypes.h"
  39 #include "compiler/nir_types.h"
  40 #include "compiler/nir/nir.h"
  41
  42 /* Forward declare */
  43 struct midgard_block;
  44
  45 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  46  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  47  * instruction is actually a discard op. */
  48
  49 #define TARGET_GOTO 0
  50 #define TARGET_BREAK 1
  51 #define TARGET_CONTINUE 2
  52 #define TARGET_DISCARD 3
  53
  54 typedef struct midgard_branch {
  55         /* If conditional, the condition is specified in r31.w */
  56         bool conditional;
  57
  58         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  59         bool invert_conditional;
  60
  61         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  62         unsigned target_type;
  63
  64         /* The actual target */
  65         union {
  66                 int target_block;
  67                 int target_break;
  68                 int target_continue;
  69         };
  70 } midgard_branch;
  71
  72 /* Generic in-memory data type repesenting a single logical instruction, rather
  73  * than a single instruction group. This is the preferred form for code gen.
  74  * Multiple midgard_insturctions will later be combined during scheduling,
  75  * though this is not represented in this structure.  Its format bridges
  76  * the low-level binary representation with the higher level semantic meaning.
  77  *
  78  * Notably, it allows registers to be specified as block local SSA, for code
  79  * emitted before the register allocation pass.
  80  */
  81
  82 #define MIR_SRC_COUNT 4
  83 #define MIR_VEC_COMPONENTS 16
  84
  85 typedef struct midgard_instruction {
  86         /* Must be first for casting */
  87         struct list_head link;
  88
  89         unsigned type; /* ALU, load/store, texture */
  90
  91         /* Instruction arguments represented as block-local SSA
  92          * indices, rather than registers. ~0 means unused. */
  93         unsigned src[MIR_SRC_COUNT];
  94         unsigned dest;
  95
  96         /* vec16 swizzle, unpacked, per source */
  97         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  98
  99         /* Special fields for an ALU instruction */
 100         midgard_reg_info registers;
 101
 102         /* I.e. (1 << alu_bit) */
 103         int unit;
 104
 105         bool has_constants;
 106         midgard_constants constants;
 107         uint16_t inline_constant;
 108         bool has_blend_constant;
 109         bool has_inline_constant;
 110
 111         bool compact_branch;
 112         bool writeout;
 113         bool last_writeout;
 114
 115         /* Kind of a hack, but hint against aggressive DCE */
 116         bool dont_eliminate;
 117
 118         /* Masks in a saneish format. One bit per channel, not packed fancy.
 119          * Use this instead of the op specific ones, and switch over at emit
 120          * time */
 121
 122         uint16_t mask;
 123
 124         /* For ALU ops only: set to true to invert (bitwise NOT) the
 125          * destination of an integer-out op. Not implemented in hardware but
 126          * allows more optimizations */
 127
 128         bool invert;
 129
 130         /* Hint for the register allocator not to spill the destination written
 131          * from this instruction (because it is a spill/unspill node itself).
 132          * Bitmask of spilled classes */
 133
 134         unsigned no_spill;
 135
 136         /* Generic hint for intra-pass use */
 137         bool hint;
 138
 139         /* During scheduling, the backwards dependency graph
 140          * (DAG). nr_dependencies is the number of unscheduled
 141          * instructions that must still be scheduled after
 142          * (before) this instruction. dependents are which
 143          * instructions need to be scheduled before (after) this
 144          * instruction. */
 145
 146         unsigned nr_dependencies;
 147         BITSET_WORD *dependents;
 148
 149         /* For load/store ops.. force 64-bit destination */
 150         bool load_64;
 151
 152         union {
 153                 midgard_load_store_word load_store;
 154                 midgard_vector_alu alu;
 155                 midgard_texture_word texture;
 156                 midgard_branch_extended branch_extended;
 157                 uint16_t br_compact;
 158
 159                 /* General branch, rather than packed br_compact. Higher level
 160                  * than the other components */
 161                 midgard_branch branch;
 162         };
 163 } midgard_instruction;
 164
 165 typedef struct midgard_block {
 166         /* Link to next block. Must be first for mir_get_block */
 167         struct list_head link;
 168
 169         /* List of midgard_instructions emitted for the current block */
 170         struct list_head instructions;
 171
 172         /* Index of the block in source order */
 173         unsigned source_id;
 174
 175         bool is_scheduled;
 176
 177         /* List of midgard_bundles emitted (after the scheduler has run) */
 178         struct util_dynarray bundles;
 179
 180         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 181         unsigned quadword_count;
 182
 183         /* Succeeding blocks. The compiler should not necessarily rely on
 184          * source-order traversal */
 185         struct midgard_block *successors[2];
 186         unsigned nr_successors;
 187
 188         struct set *predecessors;
 189
 190         /* The successors pointer form a graph, and in the case of
 191          * complex control flow, this graph has a cycles. To aid
 192          * traversal during liveness analysis, we have a visited?
 193          * boolean for passes to use as they see fit, provided they
 194          * clean up later */
 195         bool visited;
 196
 197         /* In liveness analysis, these are live masks (per-component) for
 198          * indices for the block. Scalar compilers have the luxury of using
 199          * simple bit fields, but for us, liveness is a vector idea. */
 200         uint16_t *live_in;
 201         uint16_t *live_out;
 202
 203         /* Indicates this is a fixed-function fragment epilogue block */
 204         bool epilogue;
 205 } midgard_block;
 206
 207 typedef struct midgard_bundle {
 208         /* Tag for the overall bundle */
 209         int tag;
 210
 211         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 212          * sadd, vadd, smul, vlut, branch) */
 213         int instruction_count;
 214         midgard_instruction *instructions[6];
 215
 216         /* Bundle-wide ALU configuration */
 217         int padding;
 218         int control;
 219         bool has_embedded_constants;
 220         midgard_constants constants;
 221         bool has_blend_constant;
 222         bool last_writeout;
 223 } midgard_bundle;
 224
 225 typedef struct compiler_context {
 226         nir_shader *nir;
 227         gl_shader_stage stage;
 228
 229         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 230         bool is_blend;
 231
 232         /* Render target number for a keyed blend shader. Depends on is_blend */
 233         unsigned blend_rt;
 234
 235         /* Tracking for blend constant patching */
 236         int blend_constant_offset;
 237
 238         /* Number of bytes used for Thread Local Storage */
 239         unsigned tls_size;
 240
 241         /* Count of spills and fills for shaderdb */
 242         unsigned spills;
 243         unsigned fills;
 244
 245         /* Current NIR function */
 246         nir_function *func;
 247
 248         /* Allocated compiler temporary counter */
 249         unsigned temp_alloc;
 250
 251         /* Unordered list of midgard_blocks */
 252         int block_count;
 253         struct list_head blocks;
 254
 255         /* TODO merge with block_count? */
 256         unsigned block_source_count;
 257
 258         /* List of midgard_instructions emitted for the current block */
 259         midgard_block *current_block;
 260
 261         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 262         midgard_block *after_block;
 263
 264         /* The current "depth" of the loop, for disambiguating breaks/continues
 265          * when using nested loops */
 266         int current_loop_depth;
 267
 268         /* Total number of loops for shader-db */
 269         unsigned loop_count;
 270
 271         /* Constants which have been loaded, for later inlining */
 272         struct hash_table_u64 *ssa_constants;
 273
 274         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 275         struct hash_table_u64 *hash_to_temp;
 276         int temp_count;
 277         int max_hash;
 278
 279         /* Just the count of the max register used. Higher count => higher
 280          * register pressure */
 281         int work_registers;
 282
 283         /* Used for cont/last hinting. Increase when a tex op is added.
 284          * Decrease when a tex op is removed. */
 285         int texture_op_count;
 286
 287         /* The number of uniforms allowable for the fast path */
 288         int uniform_cutoff;
 289
 290         /* Count of instructions emitted from NIR overall, across all blocks */
 291         int instruction_count;
 292
 293         /* Alpha ref value passed in */
 294         float alpha_ref;
 295
 296         unsigned quadword_count;
 297
 298         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 299         unsigned sysvals[MAX_SYSVAL_COUNT];
 300         unsigned sysval_count;
 301         struct hash_table_u64 *sysval_to_id;
 302
 303         /* Bitmask of valid metadata */
 304         unsigned metadata;
 305
 306         /* Model-specific quirk set */
 307         uint32_t quirks;
 308
 309         /* Writeout instructions for each render target */
 310         midgard_instruction *writeout_branch[4];
 311 } compiler_context;
 312
 313 /* Per-block live_in/live_out */
 314 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 315
 316 /* Helpers for manipulating the above structures (forming the driver IR) */
 317
 318 /* Append instruction to end of current block */
 319
 320 static inline midgard_instruction *
 321 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 322 {
 323         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 324         memcpy(heap, &ins, sizeof(ins));
 325         return heap;
 326 }
 327
 328 static inline midgard_instruction *
 329 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 330 {
 331         midgard_instruction *u = mir_upload_ins(ctx, ins);
 332         list_addtail(&u->link, &ctx->current_block->instructions);
 333         return u;
 334 }
 335
 336 static inline struct midgard_instruction *
 337 mir_insert_instruction_before(struct compiler_context *ctx,
 338                               struct midgard_instruction *tag,
 339                               struct midgard_instruction ins)
 340 {
 341         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 342         list_addtail(&u->link, &tag->link);
 343         return u;
 344 }
 345
 346 static inline void
 347 mir_remove_instruction(struct midgard_instruction *ins)
 348 {
 349         list_del(&ins->link);
 350 }
 351
 352 static inline midgard_instruction*
 353 mir_prev_op(struct midgard_instruction *ins)
 354 {
 355         return list_last_entry(&(ins->link), midgard_instruction, link);
 356 }
 357
 358 static inline midgard_instruction*
 359 mir_next_op(struct midgard_instruction *ins)
 360 {
 361         return list_first_entry(&(ins->link), midgard_instruction, link);
 362 }
 363
 364 #define mir_foreach_block(ctx, v) \
 365         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 366
 367 #define mir_foreach_block_from(ctx, from, v) \
 368         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 369
 370 #define mir_foreach_instr(ctx, v) \
 371         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 372
 373 #define mir_foreach_instr_safe(ctx, v) \
 374         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 375
 376 #define mir_foreach_instr_in_block(block, v) \
 377         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 378 #define mir_foreach_instr_in_block_rev(block, v) \
 379         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 380
 381 #define mir_foreach_instr_in_block_safe(block, v) \
 382         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 383
 384 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 385         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 386
 387 #define mir_foreach_instr_in_block_from(block, v, from) \
 388         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 389
 390 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 391         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 392
 393 #define mir_foreach_bundle_in_block(block, v) \
 394         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 395
 396 #define mir_foreach_bundle_in_block_rev(block, v) \
 397         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 398
 399 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 400         midgard_instruction* v; \
 401         signed i = 0; \
 402         mir_foreach_bundle_in_block_rev(block, _bundle) \
 403                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 404                                 i >= 0; \
 405                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 406
 407 #define mir_foreach_instr_global(ctx, v) \
 408         mir_foreach_block(ctx, v_block) \
 409                 mir_foreach_instr_in_block(v_block, v)
 410
 411 #define mir_foreach_instr_global_safe(ctx, v) \
 412         mir_foreach_block(ctx, v_block) \
 413                 mir_foreach_instr_in_block_safe(v_block, v)
 414
 415 #define mir_foreach_successor(blk, v) \
 416         struct midgard_block *v; \
 417         struct midgard_block **_v; \
 418         for (_v = &blk->successors[0], \
 419                 v = *_v; \
 420                 v != NULL && _v < &blk->successors[2]; \
 421                 _v++, v = *_v) \
 422
 423 /* Based on set_foreach, expanded with automatic type casts */
 424
 425 #define mir_foreach_predecessor(blk, v) \
 426         struct set_entry *_entry_##v; \
 427         struct midgard_block *v; \
 428         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 429                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 430                 _entry_##v != NULL; \
 431                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 432                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 433
 434 #define mir_foreach_src(ins, v) \
 435         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 436
 437 static inline midgard_instruction *
 438 mir_last_in_block(struct midgard_block *block)
 439 {
 440         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 441 }
 442
 443 static inline midgard_block *
 444 mir_get_block(compiler_context *ctx, int idx)
 445 {
 446         struct list_head *lst = &ctx->blocks;
 447
 448         while ((idx--) + 1)
 449                 lst = lst->next;
 450
 451         return (struct midgard_block *) lst;
 452 }
 453
 454 static inline midgard_block *
 455 mir_exit_block(struct compiler_context *ctx)
 456 {
 457         midgard_block *last = list_last_entry(&ctx->blocks,
 458                         struct midgard_block, link);
 459
 460         /* The last block must be empty logically but contains branch writeout
 461          * for fragment shaders */
 462
 463         assert(last->nr_successors == 0);
 464
 465         return last;
 466 }
 467
 468 static inline bool
 469 mir_is_alu_bundle(midgard_bundle *bundle)
 470 {
 471         return midgard_word_types[bundle->tag] == midgard_word_type_alu;
 472 }
 473
 474 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 475
 476 #define IS_REG (1)
 477
 478 static inline unsigned
 479 make_compiler_temp(compiler_context *ctx)
 480 {
 481         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 482 }
 483
 484 static inline unsigned
 485 make_compiler_temp_reg(compiler_context *ctx)
 486 {
 487         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 488 }
 489
 490 static inline unsigned
 491 nir_src_index(compiler_context *ctx, nir_src *src)
 492 {
 493         if (src->is_ssa)
 494                 return (src->ssa->index << 1) | 0;
 495         else {
 496                 assert(!src->reg.indirect);
 497                 return (src->reg.reg->index << 1) | IS_REG;
 498         }
 499 }
 500
 501 static inline unsigned
 502 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 503 {
 504         return nir_src_index(ctx, &src->src);
 505 }
 506
 507 static inline unsigned
 508 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 509 {
 510         if (dst->is_ssa)
 511                 return (dst->ssa.index << 1) | 0;
 512         else {
 513                 assert(!dst->reg.indirect);
 514                 return (dst->reg.reg->index << 1) | IS_REG;
 515         }
 516 }
 517
 518
 519
 520 /* MIR manipulation */
 521
 522 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 523 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 524 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 525 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 526 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 527 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 528 bool mir_single_use(compiler_context *ctx, unsigned value);
 529 bool mir_special_index(compiler_context *ctx, unsigned idx);
 530 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 531 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 532 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 533 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 534 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 535 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 536 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 537 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 538 uint16_t mir_to_bytemask(midgard_reg_mode mode, unsigned mask);
 539 uint16_t mir_bytemask(midgard_instruction *ins);
 540 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 541 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 542 unsigned mir_upper_override(midgard_instruction *ins);
 543
 544 /* MIR printing */
 545
 546 void mir_print_instruction(midgard_instruction *ins);
 547 void mir_print_bundle(midgard_bundle *ctx);
 548 void mir_print_block(midgard_block *block);
 549 void mir_print_shader(compiler_context *ctx);
 550 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 551 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 552 bool mir_nontrivial_outmod(midgard_instruction *ins);
 553
 554 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 555 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 556 void mir_flip(midgard_instruction *ins);
 557 void mir_compute_temp_count(compiler_context *ctx);
 558
 559 /* 'Intrinsic' move for aliasing */
 560
 561 static inline midgard_instruction
 562 v_mov(unsigned src, unsigned dest)
 563 {
 564         midgard_instruction ins = {
 565                 .type = TAG_ALU_4,
 566                 .mask = 0xF,
 567                 .src = { ~0, src, ~0, ~0 },
 568                 .swizzle = SWIZZLE_IDENTITY,
 569                 .dest = dest,
 570                 .alu = {
 571                         .op = midgard_alu_op_imov,
 572                         .reg_mode = midgard_reg_mode_32,
 573                         .dest_override = midgard_dest_override_none,
 574                         .outmod = midgard_outmod_int_wrap
 575                 },
 576         };
 577
 578         return ins;
 579 }
 580
 581 /* Broad types of register classes so we can handle special
 582  * registers */
 583
 584 #define REG_CLASS_WORK          0
 585 #define REG_CLASS_LDST          1
 586 #define REG_CLASS_TEXR          3
 587 #define REG_CLASS_TEXW          4
 588
 589 /* Like a move, but to thread local storage! */
 590
 591 static inline midgard_instruction
 592 v_load_store_scratch(
 593                 unsigned srcdest,
 594                 unsigned index,
 595                 bool is_store,
 596                 unsigned mask)
 597 {
 598         /* We index by 32-bit vec4s */
 599         unsigned byte = (index * 4 * 4);
 600
 601         midgard_instruction ins = {
 602                 .type = TAG_LOAD_STORE_4,
 603                 .mask = mask,
 604                 .dest = ~0,
 605                 .src = { ~0, ~0, ~0, ~0 },
 606                 .swizzle = SWIZZLE_IDENTITY_4,
 607                 .load_store = {
 608                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 609
 610                         /* For register spilling - to thread local storage */
 611                         .arg_1 = 0xEA,
 612                         .arg_2 = 0x1E,
 613                 },
 614
 615                 /* If we spill an unspill, RA goes into an infinite loop */
 616                 .no_spill = (1 << REG_CLASS_WORK)
 617         };
 618
 619         ins.constants.u32[0] = byte;
 620
 621         if (is_store) {
 622                 ins.src[0] = srcdest;
 623
 624                 /* Ensure we are tightly swizzled so liveness analysis is
 625                  * correct */
 626
 627                 for (unsigned i = 0; i < 4; ++i) {
 628                         if (!(mask & (1 << i)))
 629                                 ins.swizzle[0][i] = COMPONENT_X;
 630                 }
 631         } else
 632                 ins.dest = srcdest;
 633
 634         return ins;
 635 }
 636
 637 static inline bool
 638 mir_has_arg(midgard_instruction *ins, unsigned arg)
 639 {
 640         if (!ins)
 641                 return false;
 642
 643         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 644                 if (ins->src[i] == arg)
 645                         return true;
 646         }
 647
 648         return false;
 649 }
 650
 651 /* Scheduling */
 652
 653 void midgard_schedule_program(compiler_context *ctx);
 654
 655 void mir_ra(compiler_context *ctx);
 656 void mir_squeeze_index(compiler_context *ctx);
 657 void mir_lower_special_reads(compiler_context *ctx);
 658 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 659 void mir_compute_liveness(compiler_context *ctx);
 660 void mir_invalidate_liveness(compiler_context *ctx);
 661 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 662
 663 void mir_create_pipeline_registers(compiler_context *ctx);
 664 void midgard_promote_uniforms(compiler_context *ctx);
 665
 666 void
 667 emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
 668
 669 void
 670 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 671
 672 void
 673 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 674
 675 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 676
 677 /* Final emission */
 678
 679 void emit_binary_bundle(
 680         compiler_context *ctx,
 681         midgard_bundle *bundle,
 682         struct util_dynarray *emission,
 683         int next_tag);
 684
 685 bool
 686 nir_undef_to_zero(nir_shader *shader);
 687
 688 void midgard_nir_lod_errata(nir_shader *shader);
 689
 690 /* Optimizations */
 691
 692 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 693 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 694 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 695 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 696 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 697
 698 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 699 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 700 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 701 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 702 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 703 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 704 bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
 705 bool midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block);
 706
 707 #endif