src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30 #include "midgard_ops.h"
  31 #include "lcra.h"
  32
  33 #include "util/hash_table.h"
  34 #include "util/u_dynarray.h"
  35 #include "util/set.h"
  36 #include "util/list.h"
  37
  38 #include "main/mtypes.h"
  39 #include "compiler/nir_types.h"
  40 #include "compiler/nir/nir.h"
  41 #include "panfrost/util/pan_ir.h"
  42
  43 /* Forward declare */
  44 struct midgard_block;
  45
  46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  47  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  48  * instruction is actually a discard op. */
  49
  50 #define TARGET_GOTO 0
  51 #define TARGET_BREAK 1
  52 #define TARGET_CONTINUE 2
  53 #define TARGET_DISCARD 3
  54
  55 typedef struct midgard_branch {
  56         /* If conditional, the condition is specified in r31.w */
  57         bool conditional;
  58
  59         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  60         bool invert_conditional;
  61
  62         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  63         unsigned target_type;
  64
  65         /* The actual target */
  66         union {
  67                 int target_block;
  68                 int target_break;
  69                 int target_continue;
  70         };
  71 } midgard_branch;
  72
  73 /* Generic in-memory data type repesenting a single logical instruction, rather
  74  * than a single instruction group. This is the preferred form for code gen.
  75  * Multiple midgard_insturctions will later be combined during scheduling,
  76  * though this is not represented in this structure.  Its format bridges
  77  * the low-level binary representation with the higher level semantic meaning.
  78  *
  79  * Notably, it allows registers to be specified as block local SSA, for code
  80  * emitted before the register allocation pass.
  81  */
  82
  83 #define MIR_SRC_COUNT 4
  84 #define MIR_VEC_COMPONENTS 16
  85
  86 typedef struct midgard_instruction {
  87         /* Must be first for casting */
  88         struct list_head link;
  89
  90         unsigned type; /* ALU, load/store, texture */
  91
  92         /* Instruction arguments represented as block-local SSA
  93          * indices, rather than registers. ~0 means unused. */
  94         unsigned src[MIR_SRC_COUNT];
  95         unsigned dest;
  96
  97         /* vec16 swizzle, unpacked, per source */
  98         unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
  99
 100         /* Special fields for an ALU instruction */
 101         midgard_reg_info registers;
 102
 103         /* I.e. (1 << alu_bit) */
 104         int unit;
 105
 106         bool has_constants;
 107         midgard_constants constants;
 108         uint16_t inline_constant;
 109         bool has_blend_constant;
 110         bool has_inline_constant;
 111
 112         bool compact_branch;
 113         bool writeout;
 114         bool writeout_depth;
 115         bool writeout_stencil;
 116         bool last_writeout;
 117
 118         /* Kind of a hack, but hint against aggressive DCE */
 119         bool dont_eliminate;
 120
 121         /* Masks in a saneish format. One bit per channel, not packed fancy.
 122          * Use this instead of the op specific ones, and switch over at emit
 123          * time */
 124
 125         uint16_t mask;
 126
 127         /* For ALU ops only: set to true to invert (bitwise NOT) the
 128          * destination of an integer-out op. Not implemented in hardware but
 129          * allows more optimizations */
 130
 131         bool invert;
 132
 133         /* Hint for the register allocator not to spill the destination written
 134          * from this instruction (because it is a spill/unspill node itself).
 135          * Bitmask of spilled classes */
 136
 137         unsigned no_spill;
 138
 139         /* Generic hint for intra-pass use */
 140         bool hint;
 141
 142         /* During scheduling, the backwards dependency graph
 143          * (DAG). nr_dependencies is the number of unscheduled
 144          * instructions that must still be scheduled after
 145          * (before) this instruction. dependents are which
 146          * instructions need to be scheduled before (after) this
 147          * instruction. */
 148
 149         unsigned nr_dependencies;
 150         BITSET_WORD *dependents;
 151
 152         /* For load/store ops.. force 64-bit destination */
 153         bool load_64;
 154
 155         union {
 156                 midgard_load_store_word load_store;
 157                 midgard_vector_alu alu;
 158                 midgard_texture_word texture;
 159                 midgard_branch_extended branch_extended;
 160                 uint16_t br_compact;
 161
 162                 /* General branch, rather than packed br_compact. Higher level
 163                  * than the other components */
 164                 midgard_branch branch;
 165         };
 166 } midgard_instruction;
 167
 168 typedef struct pan_block {
 169         /* Link to next block. Must be first for mir_get_block */
 170         struct list_head link;
 171
 172         /* List of instructions emitted for the current block */
 173         struct list_head instructions;
 174
 175         /* Index of the block in source order */
 176         unsigned name;
 177
 178         /* Control flow graph */
 179         struct pan_block *successors[2];
 180         unsigned nr_successors;
 181
 182         struct set *predecessors;
 183
 184         /* In liveness analysis, these are live masks (per-component) for
 185          * indices for the block. Scalar compilers have the luxury of using
 186          * simple bit fields, but for us, liveness is a vector idea. */
 187         uint16_t *live_in;
 188         uint16_t *live_out;
 189 } pan_block;
 190
 191 typedef struct midgard_block {
 192         pan_block base;
 193
 194         bool scheduled;
 195
 196         /* List of midgard_bundles emitted (after the scheduler has run) */
 197         struct util_dynarray bundles;
 198
 199         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 200         unsigned quadword_count;
 201
 202         /* Indicates this is a fixed-function fragment epilogue block */
 203         bool epilogue;
 204 } midgard_block;
 205
 206 typedef struct midgard_bundle {
 207         /* Tag for the overall bundle */
 208         int tag;
 209
 210         /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
 211          * sadd, vadd, smul, vlut, branch) */
 212         int instruction_count;
 213         midgard_instruction *instructions[6];
 214
 215         /* Bundle-wide ALU configuration */
 216         int padding;
 217         int control;
 218         bool has_embedded_constants;
 219         midgard_constants constants;
 220         bool has_blend_constant;
 221         bool last_writeout;
 222 } midgard_bundle;
 223
 224 enum midgard_rt_id {
 225         MIDGARD_COLOR_RT0,
 226         MIDGARD_COLOR_RT1,
 227         MIDGARD_COLOR_RT2,
 228         MIDGARD_COLOR_RT3,
 229         MIDGARD_ZS_RT,
 230         MIDGARD_NUM_RTS,
 231 };
 232
 233 typedef struct compiler_context {
 234         nir_shader *nir;
 235         gl_shader_stage stage;
 236
 237         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 238         bool is_blend;
 239
 240         /* Render target number for a keyed blend shader. Depends on is_blend */
 241         unsigned blend_rt;
 242
 243         /* Tracking for blend constant patching */
 244         int blend_constant_offset;
 245
 246         /* Number of bytes used for Thread Local Storage */
 247         unsigned tls_size;
 248
 249         /* Count of spills and fills for shaderdb */
 250         unsigned spills;
 251         unsigned fills;
 252
 253         /* Current NIR function */
 254         nir_function *func;
 255
 256         /* Allocated compiler temporary counter */
 257         unsigned temp_alloc;
 258
 259         /* Unordered list of midgard_blocks */
 260         int block_count;
 261         struct list_head blocks;
 262
 263         /* TODO merge with block_count? */
 264         unsigned block_source_count;
 265
 266         /* List of midgard_instructions emitted for the current block */
 267         midgard_block *current_block;
 268
 269         /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
 270         midgard_block *after_block;
 271
 272         /* The current "depth" of the loop, for disambiguating breaks/continues
 273          * when using nested loops */
 274         int current_loop_depth;
 275
 276         /* Total number of loops for shader-db */
 277         unsigned loop_count;
 278
 279         /* Constants which have been loaded, for later inlining */
 280         struct hash_table_u64 *ssa_constants;
 281
 282         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 283         struct hash_table_u64 *hash_to_temp;
 284         int temp_count;
 285         int max_hash;
 286
 287         /* Just the count of the max register used. Higher count => higher
 288          * register pressure */
 289         int work_registers;
 290
 291         /* Used for cont/last hinting. Increase when a tex op is added.
 292          * Decrease when a tex op is removed. */
 293         int texture_op_count;
 294
 295         /* The number of uniforms allowable for the fast path */
 296         int uniform_cutoff;
 297
 298         /* Count of instructions emitted from NIR overall, across all blocks */
 299         int instruction_count;
 300
 301         /* Alpha ref value passed in */
 302         float alpha_ref;
 303
 304         unsigned quadword_count;
 305
 306         /* Bitmask of valid metadata */
 307         unsigned metadata;
 308
 309         /* Model-specific quirk set */
 310         uint32_t quirks;
 311
 312         /* Writeout instructions for each render target */
 313         midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
 314
 315         struct panfrost_sysvals sysvals;
 316 } compiler_context;
 317
 318 /* Per-block live_in/live_out */
 319 #define MIDGARD_METADATA_LIVENESS (1 << 0)
 320
 321 /* Helpers for manipulating the above structures (forming the driver IR) */
 322
 323 /* Append instruction to end of current block */
 324
 325 static inline midgard_instruction *
 326 mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
 327 {
 328         midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
 329         memcpy(heap, &ins, sizeof(ins));
 330         return heap;
 331 }
 332
 333 static inline midgard_instruction *
 334 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 335 {
 336         midgard_instruction *u = mir_upload_ins(ctx, ins);
 337         list_addtail(&u->link, &ctx->current_block->base.instructions);
 338         return u;
 339 }
 340
 341 static inline struct midgard_instruction *
 342 mir_insert_instruction_before(struct compiler_context *ctx,
 343                               struct midgard_instruction *tag,
 344                               struct midgard_instruction ins)
 345 {
 346         struct midgard_instruction *u = mir_upload_ins(ctx, ins);
 347         list_addtail(&u->link, &tag->link);
 348         return u;
 349 }
 350
 351 static inline void
 352 mir_remove_instruction(struct midgard_instruction *ins)
 353 {
 354         list_del(&ins->link);
 355 }
 356
 357 static inline midgard_instruction*
 358 mir_prev_op(struct midgard_instruction *ins)
 359 {
 360         return list_last_entry(&(ins->link), midgard_instruction, link);
 361 }
 362
 363 static inline midgard_instruction*
 364 mir_next_op(struct midgard_instruction *ins)
 365 {
 366         return list_first_entry(&(ins->link), midgard_instruction, link);
 367 }
 368
 369 #define mir_foreach_block(ctx, v) \
 370         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 371
 372 #define mir_foreach_block_from(ctx, from, v) \
 373         list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
 374
 375 #define mir_foreach_instr_in_block(block, v) \
 376         list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
 377 #define mir_foreach_instr_in_block_rev(block, v) \
 378         list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
 379
 380 #define pan_foreach_instr_in_block_rev(block, v) \
 381         list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
 382
 383 #define mir_foreach_instr_in_block_safe(block, v) \
 384         list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
 385
 386 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 387         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
 388
 389 #define mir_foreach_instr_in_block_from(block, v, from) \
 390         list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
 391
 392 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 393         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
 394
 395 #define mir_foreach_bundle_in_block(block, v) \
 396         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 397
 398 #define mir_foreach_bundle_in_block_rev(block, v) \
 399         util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
 400
 401 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
 402         midgard_instruction* v; \
 403         signed i = 0; \
 404         mir_foreach_bundle_in_block_rev(block, _bundle) \
 405                 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
 406                                 i >= 0; \
 407                                 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
 408
 409 #define mir_foreach_instr_global(ctx, v) \
 410         mir_foreach_block(ctx, v_block) \
 411                 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
 412
 413 #define mir_foreach_instr_global_safe(ctx, v) \
 414         mir_foreach_block(ctx, v_block) \
 415                 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
 416
 417 #define mir_foreach_successor(blk, v) \
 418         struct midgard_block *v; \
 419         struct midgard_block **_v; \
 420         for (_v = &blk->base.successors[0], \
 421                 v = *_v; \
 422                 v != NULL && _v < &blk->base.successors[2]; \
 423                 _v++, v = *_v) \
 424
 425 #define pan_foreach_successor(blk, v) \
 426         pan_block *v; \
 427         pan_block **_v; \
 428         for (_v = (pan_block **) &blk->successors[0], \
 429                 v = *_v; \
 430                 v != NULL && _v < (pan_block **) &blk->successors[2]; \
 431                 _v++, v = *_v) \
 432
 433 /* Based on set_foreach, expanded with automatic type casts */
 434
 435 #define mir_foreach_predecessor(blk, v) \
 436         struct set_entry *_entry_##v; \
 437         struct midgard_block *v; \
 438         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 439                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 440                 _entry_##v != NULL; \
 441                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 442                 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
 443
 444 #define pan_foreach_predecessor(blk, v) \
 445         struct set_entry *_entry_##v; \
 446         struct pan_block *v; \
 447         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 448                 v = (struct pan_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 449                 _entry_##v != NULL; \
 450                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 451                 v = (struct pan_block *) (_entry_##v ? _entry_##v->key : NULL))
 452
 453 #define mir_foreach_src(ins, v) \
 454         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 455
 456 static inline midgard_instruction *
 457 mir_last_in_block(struct midgard_block *block)
 458 {
 459         return list_last_entry(&block->base.instructions, struct midgard_instruction, link);
 460 }
 461
 462 static inline midgard_block *
 463 mir_get_block(compiler_context *ctx, int idx)
 464 {
 465         struct list_head *lst = &ctx->blocks;
 466
 467         while ((idx--) + 1)
 468                 lst = lst->next;
 469
 470         return (struct midgard_block *) lst;
 471 }
 472
 473 static inline midgard_block *
 474 mir_exit_block(struct compiler_context *ctx)
 475 {
 476         pan_block *last = list_last_entry(&ctx->blocks, pan_block, link);
 477
 478         /* The last block must be empty logically but contains branch writeout
 479          * for fragment shaders */
 480
 481         assert(last->nr_successors == 0);
 482
 483         return (midgard_block *) last;
 484 }
 485
 486 static inline bool
 487 mir_is_alu_bundle(midgard_bundle *bundle)
 488 {
 489         return IS_ALU(bundle->tag);
 490 }
 491
 492 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 493
 494 #define IS_REG (1)
 495
 496 static inline unsigned
 497 make_compiler_temp(compiler_context *ctx)
 498 {
 499         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 500 }
 501
 502 static inline unsigned
 503 make_compiler_temp_reg(compiler_context *ctx)
 504 {
 505         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 506 }
 507
 508 static inline unsigned
 509 nir_ssa_index(nir_ssa_def *ssa)
 510 {
 511         return (ssa->index << 1) | 0;
 512 }
 513
 514 static inline unsigned
 515 nir_src_index(compiler_context *ctx, nir_src *src)
 516 {
 517         if (src->is_ssa)
 518                 return nir_ssa_index(src->ssa);
 519         else {
 520                 assert(!src->reg.indirect);
 521                 return (src->reg.reg->index << 1) | IS_REG;
 522         }
 523 }
 524
 525 static inline unsigned
 526 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 527 {
 528         return nir_src_index(ctx, &src->src);
 529 }
 530
 531 static inline unsigned
 532 nir_dest_index(nir_dest *dst)
 533 {
 534         if (dst->is_ssa)
 535                 return (dst->ssa.index << 1) | 0;
 536         else {
 537                 assert(!dst->reg.indirect);
 538                 return (dst->reg.reg->index << 1) | IS_REG;
 539         }
 540 }
 541
 542
 543
 544 /* MIR manipulation */
 545
 546 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 547 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 548 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 549 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new);
 550 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 551 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 552 bool mir_single_use(compiler_context *ctx, unsigned value);
 553 bool mir_special_index(compiler_context *ctx, unsigned idx);
 554 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 555 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 556 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 557 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 558 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 559 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 560 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 561 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 562 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
 563 uint16_t mir_bytemask(midgard_instruction *ins);
 564 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 565 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 566 unsigned mir_upper_override(midgard_instruction *ins);
 567
 568 /* MIR printing */
 569
 570 void mir_print_instruction(midgard_instruction *ins);
 571 void mir_print_bundle(midgard_bundle *ctx);
 572 void mir_print_block(midgard_block *block);
 573 void mir_print_shader(compiler_context *ctx);
 574 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 575 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 576 bool mir_nontrivial_outmod(midgard_instruction *ins);
 577
 578 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 579 void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
 580 void mir_flip(midgard_instruction *ins);
 581 void mir_compute_temp_count(compiler_context *ctx);
 582
 583 void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
 584
 585 /* 'Intrinsic' move for aliasing */
 586
 587 static inline midgard_instruction
 588 v_mov(unsigned src, unsigned dest)
 589 {
 590         midgard_instruction ins = {
 591                 .type = TAG_ALU_4,
 592                 .mask = 0xF,
 593                 .src = { ~0, src, ~0, ~0 },
 594                 .swizzle = SWIZZLE_IDENTITY,
 595                 .dest = dest,
 596                 .alu = {
 597                         .op = midgard_alu_op_imov,
 598                         .reg_mode = midgard_reg_mode_32,
 599                         .dest_override = midgard_dest_override_none,
 600                         .outmod = midgard_outmod_int_wrap
 601                 },
 602         };
 603
 604         return ins;
 605 }
 606
 607 /* Broad types of register classes so we can handle special
 608  * registers */
 609
 610 #define REG_CLASS_WORK          0
 611 #define REG_CLASS_LDST          1
 612 #define REG_CLASS_TEXR          3
 613 #define REG_CLASS_TEXW          4
 614
 615 /* Like a move, but to thread local storage! */
 616
 617 static inline midgard_instruction
 618 v_load_store_scratch(
 619                 unsigned srcdest,
 620                 unsigned index,
 621                 bool is_store,
 622                 unsigned mask)
 623 {
 624         /* We index by 32-bit vec4s */
 625         unsigned byte = (index * 4 * 4);
 626
 627         midgard_instruction ins = {
 628                 .type = TAG_LOAD_STORE_4,
 629                 .mask = mask,
 630                 .dest = ~0,
 631                 .src = { ~0, ~0, ~0, ~0 },
 632                 .swizzle = SWIZZLE_IDENTITY_4,
 633                 .load_store = {
 634                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 635
 636                         /* For register spilling - to thread local storage */
 637                         .arg_1 = 0xEA,
 638                         .arg_2 = 0x1E,
 639                 },
 640
 641                 /* If we spill an unspill, RA goes into an infinite loop */
 642                 .no_spill = (1 << REG_CLASS_WORK)
 643         };
 644
 645         ins.constants.u32[0] = byte;
 646
 647         if (is_store) {
 648                 ins.src[0] = srcdest;
 649
 650                 /* Ensure we are tightly swizzled so liveness analysis is
 651                  * correct */
 652
 653                 for (unsigned i = 0; i < 4; ++i) {
 654                         if (!(mask & (1 << i)))
 655                                 ins.swizzle[0][i] = COMPONENT_X;
 656                 }
 657         } else
 658                 ins.dest = srcdest;
 659
 660         return ins;
 661 }
 662
 663 static inline bool
 664 mir_has_arg(midgard_instruction *ins, unsigned arg)
 665 {
 666         if (!ins)
 667                 return false;
 668
 669         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 670                 if (ins->src[i] == arg)
 671                         return true;
 672         }
 673
 674         return false;
 675 }
 676
 677 /* Scheduling */
 678
 679 void midgard_schedule_program(compiler_context *ctx);
 680
 681 void mir_ra(compiler_context *ctx);
 682 void mir_squeeze_index(compiler_context *ctx);
 683 void mir_lower_special_reads(compiler_context *ctx);
 684 void mir_liveness_ins_update(uint16_t *live, midgard_instruction *ins, unsigned max);
 685 void mir_compute_liveness(compiler_context *ctx);
 686 void mir_invalidate_liveness(compiler_context *ctx);
 687 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 688
 689 void mir_create_pipeline_registers(compiler_context *ctx);
 690 void midgard_promote_uniforms(compiler_context *ctx);
 691
 692 void
 693 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 694
 695 void
 696 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 697
 698 bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
 699
 700 /* Final emission */
 701
 702 void emit_binary_bundle(
 703         compiler_context *ctx,
 704         midgard_bundle *bundle,
 705         struct util_dynarray *emission,
 706         int next_tag);
 707
 708 bool
 709 nir_undef_to_zero(nir_shader *shader);
 710
 711 void midgard_nir_lod_errata(nir_shader *shader);
 712
 713 /* Optimizations */
 714
 715 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 716 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 717 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 718 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 719 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 720
 721 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 722 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 723 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 724 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 725 bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
 726 bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 727 bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
 728 bool midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block);
 729
 730 #endif